HI-3184PSI-N [HOLTIC]
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| 型号： | HI-3184PSI-N |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | 暂无描述 驱动器 |
| 文件： | 总12页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-3182, HI-3183, HI-3184
HI-3185, HI-3186, HI-3188
March 2008
ARINC 429 Differential Line Driver
GENERAL DESCRIPTION
PIN CONFIGURATION (Top View)
The HI-3182, HI-3183, HI-3184, HI-3185, HI-3186 and HI-3188
bus interface products are silicon gate CMOS devices designed
as a line driver in accordance with the ARINC 429 bus specifica-
tions. In addition to being functional upgrades of Holt's HI-8382
VREF
1
2
3
4
5
6
7
14 V1
GND (See Note * )
13 CLOCK
12 DATA (B)
11 CB
&
HI-8383 products, they are also alternate sources for the
SYNC
DATA (A)
CA
HS-3182 ( Intersil/Harris), the RM3182 (Fairchild /Raytheon)
and a variety of similar line driver products from other manufac-
turers.
10 BOUT
AOUT
9
8
+V
Inputs are provided for clocking and synchronization. These
signals are AND'd with the DATA inputs to enhance system
performance and allow the HI-318X series of products to be
used in a variety of applications. Both logic and synchronization
inputs feature built-in 2,000V minimum ESD input protection as
well asTTLand CMOS compatibility.
-V
GND
HI-3184PS, HI-3185PS & HI-3186PS
14 - PIN PLASTIC SMALL OUTLINE (ESOIC)** NB
The differential outputs of the HI-318X series of products are
programmable to either the high speed or low speedARINC 429
output rise and fall time specifications through the use of two
external capacitors. The output voltage swing is also adjustable
by the application of an external voltage to the VREF input.
Products with 0, 13 or 37.5 ohm resistors in series with each
ARINC output are available. In addition, the HI-3182 and
HI-3184 products also have a fuse in series with each output.
Notes: * Pin 2 may be left floating
** Thermally Enhanced SOIC Package
(See Page 6 for additional package pin configurations)
FUNCTION
The HI-318X series of line drivers are intended for use where
logic signals must be converted to ARINC 429 levels such as
when using an ASIC, the HI-3282/HI-8282A ARINC 429 Serial
Transmitter/Dual Receiver, the HI-6010 ARINC 429 Transmit-
+
_
ter/Receiver or the HI-8783 ARINC Interface Device.
Holt
products are readily available for both industrial and military
applications. Please contact the Holt Sales Department for
additional information.
ARINC 429 DIFFERENTIAL LINE DRIVER
FEATURES
!
!
!
!
!
Low power CMOS
TTL and CMOS compatible inputs
Programmable output voltage swing
Adjustable ARINC rise and fall times
TRUTH TABLE
SYNC CLOCK DATA(A) DATA(B) AOUT BOUT COMMENTS
X
L
L
X
H
H
H
H
X
X
L
X
X
L
0V
0V
0V
0V
0V
0V
NULL
NULL
NULL
LOW
HIGH
NULL
Plastic 14 & 16-pin thermally enhanced SOIC
packages available
!
Pin-for-Pin alternative for Intersil/Fairchild
applications
H
H
H
H
L
H
L
-VREF +VREF
+VREF -VREF
!
!
!
Operates at data rates up to 100 Kbits
Overvoltage protection
H
H
H
0V
0V
Industrial and extended temperature ranges
HOLT INTEGRATED CIRCUITS
www.holtic.com
(Ds3182 Rev. K )
03/09
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
function is not available in the 14 & 16-pin SOIC package
configurations where the pin is internally connected to
ground.
FUNCTIONAL DESCRIPTION
The SYNC and CLOCK inputs establish data synchronization
utilizing two AND gates, one for each data input (figure 2).
Each logic input, including the power enable (STROBE) input,
areTTL/CMOS compatible.
TheARINC outputs of the HI-3182 and HI-3184 are protected
by internal fuses capable of sinking between 800 - 900 mA for
short periods of time (125ms).
Figure 1 illustrates a typical ARINC 429 bus application.
Three power supplies are necessary to operate the HI-3182;
typically +15V, -15V and +5V. The chip also works with 12V
supplies. The +5V supply can also provide a reference
voltage that determines the output voltage swing. The
differential output voltage swing will equal 2VREF. If a value of
VREF other than +5V is needed, a separate +5V power supply
is required for pin V1.
The Vref pin has an internal pull-up resistor to V+, allowing the
use of a simple external zener diode to set the reference
voltage.
POWER SUPPLY SEQUENCING
The power supplies should be controlled to prevent large
currents during supply turn-on and turn-off. The
recommended sequence is +V followed by V1, always
ensuring that +V is the most positive supply. The -V supply
is not critical and can be asserted at any time.
With the DATA(A) input at a logic high and DATA(B) input at a
logic low, AOUT will switch to the +VREF rail and BOUT will
switch to the -VREF rail (ARINC HIGH state). With both data
input signals at a logic low state, the outputs will both switch to
0V (ARINC NULLstate).
+5V
+15V
The driver output impedance, ROUT, is nominally 75, 26 or 0
ohms depending on the option chosen. The rise and fall times
of the outputs can be calibrated through the selection of two
external capacitor values that are connected to the CA and CB
input pins. Typical values for high-speed operation
(100KBPS) are CA = CB = 75pF and for low-speed operation
(12.5 to 14KBPS) CA = CB = 500pF.
V
REF
A
OUT
V
1
SYNC
CLOCK
DATA (A)
INPUTS
DATA (B)
+V
-V
TO ARINC BUS
STROBE
GND
C
B
C
A
B
OUT
The CA and CB pins swing between +5V and ground allowing
the switching of capacitor values with an external single-
supply analog switch.
The ARINC outputs can be put in a tri-state mode by applying
a logic high to the STROBE input pin. If this feature is not
being used, the pin should be tied to ground. The STROBE
-15V
Figure 1. ARINC 429 BUS APPLICATION
Shorted on
HI-3186, HI-3188
A
+V
V
REF
C
A
OUT
DATA (A)
CLOCK
SYNC
LEVEL SHIFTER
AND SLOPE
CONTROL (A)
13W
24.5W
FA
OUTPUT
DRIVER (A)
CL
RL
LEVEL SHIFTER
AND SLOPE
CONTROL (B)
24.5W
13W
FB
DATA (B)
OUTPUT
DRIVER (B)
CURRENT
REGULATOR
Shorted on
HI-3183, HI-3186
HI-3188
Shorted on
HI-3183, HI-3185
HI-3186, HI-3188
V1
STROBE
B
-V
GND
C
B
OUT
Figure 2. FUNCTIONAL BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
PIN DESCRIPTIONS
SYMBOL
FUNCTION
ANALOG
INPUT
DESCRIPTION
VREF
STROBE
SYNC
DATA (A)
CA
Ref. voltage used to determine output voltage swing. Pin sources current to allow use of a zener reference.
A logic high tri-states the ARINC outputs. Not available in the 14-pin SOIC package (tied to GND internally).
INPUT
Synchronizes data inputs
Data input terminal A
Connection for DATA (A) slew-rate capacitor
ARINC output terminal A
-12V to -15V
INPUT
INPUT
AOUT
-V
OUTPUT
POWER
POWER
POWER
OUTPUT
INPUT
GND
+V
0.0V
+12V to +15V
BOUT
CB
ARINC output terminal B
Connection for DATA (B) slew-rate capacitor
Data input terminal B
Synchronizes data inputs
+5V 5ꢀ
DATA (B)
CLOCK
V1
INPUT
INPUT
POWER
ABSOLUTE MAXIMUM RATINGS
All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified)
PARAMETER
Differential Voltage
Supply Voltage
SYMBOL
CONDITIONS
OPERATING RANGE
MAXIMUM
UNIT
VDIF
Voltage between +V and -V terminals
40
V
+V
-V
V1
+10.8 to +16.5
-10.8 to -16.5
+5 5ꢀ
V
V
V
+7
Voltage Reference
VREF
For ARINC 429
For Applications other than ARINC
+5 5ꢀ
1.5 to 6
6
6
V
V
Input Voltage Range
VIN
> GND -0.3
< V1 +0.3
V
V
Output Short-Circuit Duration
Output Overvoltage Protection
Operating Temperature Range
See Note: 1
See Note: 2
TA
Industrial
Extended
-40 to +85
-55 to +125
°C
°C
Storage Temperature Range
TSTG
Ceramic & Plastic
-65 to +150
°C
Lead Temperature
Soldering, 10 seconds
+275
+175
°C
°C
Junction Temperature
TJ
Note 1. Heatsinking may be required for continuous Output Short Circuit at +125°C and for 100KBPS at +125°C.
Note 2. The fuses used for Output Overvoltage Protection may be blown by the presence of a voltage at either output that is greater
than 12.0V with respect to GND. (HI-3182 & 3184 only)
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HOLT INTEGRATED CIRCUITS
3
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
DC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Supply Current +V (Operating)
SYMBOL
CONDITION
(0 - 100KBPS)
MIN TYP MAX UNITS
ICCOP (+V)
ICCOP (-V)
ICCOP (V1)
No Load
No Load
No Load
+16
mA
mA
µA
mA
mA
mA
mA
mA
µA
µA
V
Supply Current -V (Operating)
(0 - 100KBPS)
(0 - 100KBPS)
-16
-1.0
-150
+80
Supply Current V1 (Operating)
Reference Pin Current VREF (Operating)
Supply Current +V (During Short Circuit Test)
Supply Current -V (During Short Circuit Test)
Output Short Circuit Current (Output High)
Output Short Circuit Current (Output Low)
Input Current (Input High)
500
-0.15
150
ICCOP (VREF) No Load, VREF = 5V (0 - 100KBPS)
-0.4
ISC (+V)
ISC (-V)
IOHSC
IOLSC
IIH
Short to Ground (See Note: 1)
Short to Ground (See Note: 1)
Short to Ground VMIN=0 (See Note: 2)
Short to Ground VMIN=0 (See Note: 2)
-80
1.0
Input Current (Input Low)
IIL
-1.0
2.0
Input Voltage High
VIH
Input Voltage Low
VIL
0.5
V
Output Voltage High (Output to Ground)
VOH
No Load
No Load
(0 -100KBPS)
(0 -100KBPS)
(0-100KBPS)
+VREF
-.25
+VREF
+.25
V
Output Voltage Low (Output to Ground)
VOL
-VREF
-.25
-VREF
+.25
V
Output Voltage Null
Input Capacitance
VNULL
CIN
No Load
-250
+250
mV
pF
See Note 1
15
Note 1. Not tested, but characterized at initial device design and after major process and/or design change which affects this parameter.
Note 2. Interchangeability of force and sense is acceptable.
AC ELECTRICAL CHARACTERISTICS
+V = +15V, -V = -15V, V1 = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Rise Time (AOUT, BOUT)
SYMBOL
tR
CONDITION
MIN TYP MAX UNITS
CA = CB = 75pF
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
1.0
1.0
2.0
2.0
3.0
3.0
µs
µs
µs
µs
Fall Time (AOUT, BOUT)
tF
CA = CB = 75pF
CA = CB = 75pF
CA = CB = 75pF
Propagtion Delay Input to Output
Propagtion Delay Input to Output
tPLH
tPHL
2.0V
50ꢀ
0.5V
2.0V
0.5V
DATA (A) 0V
50ꢀ
DATA (B) 0V
ADJUST
BY CA
VREF
+4.75V to +5.25V
AOUT 0V
ADJUST
BY CA
-VREF
+VREF
-4.75V to -5.25V
+4.75V to +5.25V
ADJUST
BY CB
tPHL
50ꢀ
tPLH
BOUT 0V
ADJUST
BY CB
50ꢀ
-4.75V to -5.25V
+9.5V to +10.5V
-VREF
HIGH
2VREF
tR
NULL
LOW
DIFFERENTIAL
OUTPUT 0V
(AOUT - BOUT)
-9.5V to -10.5V
-2VREF
tF
NOTE: OUTPUTS UNLOADED
Figure 3. SWITCHING WAVEFORMS
HOLT INTEGRATED CIRCUITS
4
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
HI-318X PACKAGE THERMAL CHARACTERISTICS
MAXIMUM ARINC LOAD 3, 6, 7
JUNCTION TEMPERATURE, Tj
TA = 25°C TA = 85°C TA = 125°C
ØJA
(°C/W)
PACKAGE STYLE1
HEAT SINK
SUPPLY CURRENT2
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
Unsoldered
Soldered
82
65
20 mA
20 mA
57°C
51°C
117°C
111°C
157°C
151°C
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
Unsoldered
Soldered
51
28
20 mA
20 mA
45°C
36°C
105°C
96°C
145°C
136°C
28-pin Plastic
N/A
70
25 mA
56°C
110°C
150°C
AOUT and BOUT Shorted to Ground 3, 4, 5, 6, 7
JUNCTION TEMPERATURE, Tj
TA = 25°C TA = 85°C TA = 125°C
ØJA
(°C/W)
PACKAGE STYLE1
HEAT SINK
SUPPLY CURRENT2
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
Unsoldered
Soldered
82
36 mA
36 mA
57°C
78°C
147°C
138°C
187°C
178°C
65
14-pin Thermally
Enhanced Plastic
SOIC (ESOIC)
Unsoldered
Soldered
51
28
40 mA
40 mA
64°C
53°C
124°C
113°C
164°C
153°C
28-pin Plastic
N/A
70
63 mA
100°C
150°C
182°C
Notes:
1. All data taken in still air on devices soldered to a single layer copper PCB (3" X 4.5" X .062").
2. At 100ꢀ duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8.
3. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF
as this is considered unrealistic for high speed operation.
4. Similar results would be obtained with AOUT shorted to BOUT.
5. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
6. Data will vary depending on air flow and the method of heat sinking employed.
7. Current values listed are for each of the +V and -V supplies.
HEAT SINK - ESOIC PACKAGES
Both the 14-pin and 16-pin thermally enhanced SOIC dissipation. The heat sink is electrically isolated from the
packages are used for HI-318X products. These ESOIC chip and can be soldered to any ground or power plane.
packages include a metal heat sink located on the bottom However, since the chip’s substrate is at +V, connecting
surface of the device. This heat sink should be soldered the heat sink to this power plane is recommended to avoid
down to the printed circuit board for optimum thermal coupling noise into the circuit.
HOLT INTEGRATED CIRCUITS
5
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
ADDITIONAL PIN CONFIGURATIONS (See page 1 for 14-Pin Small Outline SOIC)
HI-3182PS, HI-3183PS, HI-3188PS
VREF - 1
GND (See Note * ) - 2
SYNC - 3
16 - V1
4
3 2 1 28 27 26
15 - N/C
14 - CLOCK
13 - DATA(B)
12 - CB
25
24
5
6
N/C
DATA (A)
N/C
CLOCK
N/C
HI-3182PJ 23
HI-3183PJ
7
DATA (B)
CB
DATA(A) - 4
CA - 5
22
N/C
8
21
CA
9
N/C
AOUT - 6
11 - BOUT
10 - N/C
9 - +V
20
19
N/C
10
11
N/C
-V - 7
N/C
N/C
GND - 8
12 13 14 15 16 17 18
Notes: * Pin 2 may be left floating
** Thermally Enhanced SOIC package
16 - PIN PLASTIC SMALL OUTLINE (ESOIC)**
28 - PIN PLASTIC PLCC
4
3
2
1 28 27 26
29 28 27 26 25 24 23 22 21
N/C
DATA (A)
N/C
5
6
7
8
9
25 CLOCK
24 N/C
CLOCK
30
20
19
18
17
16
15
14
N/C
N/C
+V
V1 31
N/C 32
23 DATA (B)
22 CB
HI-3182CJ
HI-3183CJ
HI-3182CL
HI-3183CL
VREF
1
2
3
4
GND
N/C
-V
N/C
STROBE
SYNC
N/C
CA
21 N/C
N/C 10
N/C 11
20
19
N/C
N/C
N/C
5
6
7
8 9 10 11 12 13
12 13 14 15 16 17 18
32 - PIN CERQUAD
28 - PIN CERAMIC LCC
VREF 1
16 V1
VREF 1
16 V1
STROBE 2
15 N/C
STROBE 2
15 N/C
HI-3182CD
HI-3183CD
HI-3182CR
HI-3183CR
SYNC 3
DATA(A) 4
CA 5
14 CLOCK
13 DATA(B)
12 CB
SYNC 3
DATA(A) 4
CA 5
14 CLOCK
13 DATA(B)
12 CB
16 - PIN
CERAMIC
SIDE BRAZED
DIP
16 - PIN
CERDIP
AOUT 6
-V 7
11 BOUT
10 N/C
AOUT 6
-V 7
11 BOUT
10 N/C
GND 8
9 +V
GND 8
9 +V
HOLT INTEGRATED CIRCUITS
6
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
ORDERING INFORMATION
HI - 318x x x - xx (Ceramic)
PART
NUMBER
TEMPERATURE
RANGE
BURN
IN
FLOW
I
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
I
No
No
T
M
T
M
Yes
PART PACKAGE
NUMBER DESCRIPTION
LEAD
FINISH (Note 1)
CD
CJ
16 PIN CERAMIC SIDE BRAZED DIP (16C)
Gold (’M’ Flow: Solder)
Solder
32 PIN J-LEAD CERQUAD (32U) not available with ‘M’ flow
28 PIN CERAMIC LEADLESS CHIP CARRIER (LCC) (28S)
16 PIN CERDIP (16D) not available with ‘M’ flow
CL
CR
Gold (’M’ Flow: Solder)
Solder
PART
OUTPUT SERIES
NUMBER RESISTANCE
FUSE
Yes
3182
3183
37.5 Ohms
13 Ohms
No
HI - 318xxx x x (Plastic)
PART
NUMBER
LEAD
FINISH
Blank
F
Tin / Lead (Sn / Pb) Solder
100ꢀ Matte Tin (Pb-free, RoHS compliant)
PART
NUMBER
TEMPERATURE
RANGE
BURN
FLOW
IN
No
No
Yes
I
T
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
I
T
M
M (Note 2)
PART
PACKAGE
OUTPUT SERIES
NUMBER DESCRIPTION
RESISTANCE
37.5 Ohms
37.5 Ohms
13 Ohms
FUSE
Yes
Yes
No
3182PJ
3182PS
3183PJ
3183PS
3184PS
3185PS
3186PS
3188PS
28 PIN PLASTIC J-LEAD PLCC (28J)
16 PIN PLASTIC SMALL OUTLINE - WB ESOIC (16HWE)
28 PIN PLASTIC J-LEAD PLCC (28J)
16 PIN PLASTIC SMALL OUTLINE - WB ESOIC (16HWE)
14 PIN PLASTIC SMALL OUTLINE - NB ESOIC (14HNE)
14 PIN PLASTIC SMALL OUTLINE - NB ESOIC (14HNE)
14 PIN PLASTIC SMALL OUTLINE - NB ESOIC (14HNE)
16 PIN PLASTIC SMALL OUTLINE - NB ESOIC (16HNE)
13 Ohms
No
37.5 Ohms
37.5 Ohms
0 Ohms
Yes
No
No
0 Ohms
No
Legend: ESOIC
NB
WB
-
-
-
Thermally Enhanced Small Outline Package (SOIC with built-in heat sink)
Narrow Body
Wide Body
(1) Gold terminal finish is Pb-Free, RoHS compliant.
(2) Only available with ‘3182PJ’.
HOLT INTEGRATED CIRCUITS
7
HI-3182, HI-3183, HI-3184, HI-3185, HI-3186, HI-3188
REVISION HISTORY
Revision
Date
Description of Change
DS3182, Rev. K
03/19/09 Clarified the temperature ranges, and Note (2) in the Ordering Information.
HOLT INTEGRATED CIRCUITS
8
HI-318X PACKAGE DIMENSIONS
14-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB
(Narrow Body, Thermally Enhanced)
inches (millimeters)
Package Type: 14HNE
.0085 .001
(.220 .029)
.270
(6.86)
.341 .004
(8.65 .10)
typ
.236 .008
.153 .003
Top View
.100
(2.54)
Bottom
View
typ
(6.00 .20)
(3.87 .06)
See Detail A
.0165 .003
(.419 .089)
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
.055 .005
(1.397 .13)
.050
(1.27)
BSC
0° to 8°
.0025 .0015
(.0635 .04)
.033 .017
(.838 .43)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
16-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB
(Narrow Body, Thermally Enhanced)
inches (millimeters)
Package Type: 16HNE
.0086
.0015
.270
typ
.390 .004
(9.90 .10)
(6.86)
Bottom
View
.10
(2.54)
.236 ±.008
(5.99 ±.20)
.1525 .003
(2.87 .06)
Top View
typ
See Detail A
.0165 .003
(.419 .09)
.061 .007
(1.55 .18)
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
.050
(1.27)
BSC
0° to 8°
.0025 .0015
(.0635 .04)
Detail A
.033 .017
(.838 .43)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
9
HI-318X PACKAGE DIMENSIONS
16-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB
(Wide Body, Thermally Enhanced)
inches (millimeters)
Package Type: 16HWE
.0105 .0015
(.2667 .038)
.240
typ
.405 .008
(10.287 .20)
(6.10)
.407 .013
(10.34 .32)
.295 .004
(7.49 .10)
.190
(4.83)
Bottom
View
Top View
typ
See Detail A
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
.090 .010
(2.286 .254)
.050
BSC
(1.27)
.0165 .003
(.419 .089)
0° to 8°
.0025 .002
(.064 .038)
.033 .017
(.838 .432)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
16-PIN CERAMIC SIDE-BRAZED DIP
inches (millimeters)
Package Type: 16C
.810
(20.574)
max
.295 ±.010
(7.493 ±.254)
.050 ±.005
(1.270 ±.127)
PIN 1
max
.200
.035 .010
(.889 ±.254)
(5.080)
BASE
PLANE
.125
(3.175)
min
.010 ±.002
(.254 ±.051)
SEATING
PLANE
.018 .002
(.457 ±.051)
.100
(2.54)
.300 .010
(7.620 ±.254)
BSC
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
10
HI-318X PACKAGE DIMENSIONS
inches (millimeters)
16-PIN CERDIP
Package Type: 16D
.050 max
(1.27 max)
.790 max
(20.006 max)
.005 min
(.127 min)
.288 ±.005
(7.315 ±.125)
.100
(2.54)
BSC
.056 typ
(1.422 typ)
.310 ±.010
(7.874 ±.254)
.180 max
(4.572 max)
.200 max
(5.080 max)
.015 min
(.381 min)
0° to 15°
.010 ±.002
(.254 ±.051)
.018 ±.003
(.457 ±.760)
.125 min
(3.175 min)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
28-PIN PLASTIC PLCC
inches (millimeters)
Package Type: 28J
PIN NO. 1 IDENT
PIN NO. 1
.050
(1.27)
BSC
.045 x 45°
.045 x 45°
.453 ± .003
(11.506 ±.076)
SQ.
.490 ± .005
(12.446 ±.127)
SQ.
.031 ±.005
(.787 ±.127)
.017 ±.004
(.432 ±.102)
See Detail A
.010 .001
(.254 .03)
.173 ±.008
(4.394 ±.203)
.020
(.508)
min
.410 ±.020
(10.414 ±.508)
DETAILA
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.035
.889
R
HOLT INTEGRATED CIRCUITS
11
HI-318X PACKAGE DIMENSIONS
28-PIN CERAMIC LEADLESS CHIP CARRIER
inches (millimeters)
Package Type: 28S
.080 ±.020
(2.032 ±.508)
.020
(.508)
INDEX
PIN 1
PIN 1
.050 ±.005
(1.270 ±.127)
.451 ±.009
(11.455 ±.229)
SQ.
.050
(1.270)
BSC
.008R .006
(.203R ±.152)
.025 ±.003
(.635 ±.076)
.040 x 45° 3PLS
(1.016 x 45° 3PLS)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
32-PIN J-LEAD CERQUAD
inches (millimeters)
Package Type: 32U
31
32
1
.450 ±.008
(11.430 ±.203)
.420 ±.012
(10.668 ±.305)
.488 ±.008
(12.395 ±.203)
2
.588 ±.008
(14.935 ±.203)
.550 ± .009
(13.970 ± .229)
.190
(4.826)
max
.040
(1.016)
typ
.083 ±.009
(2.108 ±.229)
.050
(1.270)
.019 ± .003
(.483 ± .076)
BSC
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.520 ±.012
(13.208 ±.305)
HOLT INTEGRATED CIRCUITS
12
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