HT83XXX [HOLTEK]
Q-Voice; Q-语音
| 型号： | HT83XXX |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Q-Voice |
| 文件： | 总21页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT83XXX
Q-VoiceTM
Preliminary
Features
·
·
·
·
Operating voltage: 2.4V~5.0V
Watchdog Timer
·
4-level subroutine nesting
Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)
system clock
HALT function and wake-up feature reduce power
consumption
·
System clock: 4MHz~8MHz (2.4V)
·
·
·
PWM circuit direct drive speaker or output by
transistor
RC oscillator for system clock
·
Eight I/O pins
32-pin DIP package
·
2K´14-bit program ROM
·
80´8-bit RAM
·
Two 8-bit programmable timer counter with 8-stage
prescaler and one time base counter
Applications
·
·
Intelligent educational leisure products
Sound effect generators
·
Alert and warning systems
General Description
The HT83XXX series are 8-bit high performance
microcontroller with voice synthesizer and tone genera-
tor. The HT83XXX is designed for applications on multi-
ple I/Os with sound effects, such as voice and melody. It
can provide various sampling rates and beats, tone lev-
els, tempos for speech synthesizer and melody genera-
tor.
The HT83XXX is excellent for versatile voice and sound
effect product applications. The efficient MCU instruc-
tions allow users to program the powerful custom appli-
cations. The system frequency of HT83XXX can be up
to 8MHz under 2.4V and include a HALT function to re-
duce power consumption.
Selection Table
Body
HT83003
64K-bit
3 sec
HT83006
128K-bit
6 sec
HT83009
192K-bit
9 sec
HT83018
384K-bit
18 sec
HT83036
768K-bit
36 sec
HT83048
1024K-bit
48 sec
HT83072
1536K-bit
72 sec
Voice ROM Size
Voice Length
Rev. 0.10
1
August 25, 2003
Preliminary
HT83XXX
Block Diagram
S
T
A
C
K
K
0
I
n
t
e
r
r
u
p
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M
R
0
8
-
s
t
a
g
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P
r
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c
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S
Y
S
C
L
K
C
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r
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i
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S
S
S
T
T
T
A
A
A
C
C
C
1
2
3
K
P
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-
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g
e
P
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e
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c
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M
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8
-
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e
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C
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/
1
0
2
4
S
Y
S
C
L
K
/
4
M
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P
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P
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~
P
A
7
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n
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P
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D
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S
M
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S
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1
A
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¸
2
5
6
W
D
T
P
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r
X
R
E
S
S
Y
S
C
L
K
/
4
V
V
D
D
H
A
L
T
E
N
/
D
I
S
S
S
S
P
P
Y
W
W
S
C
L
K
L
V
D
/
L
V
R
P
W
M
M
M
1
2
Pin Assignment
N
N
N
N
N
N
N
N
N
N
C
C
C
C
C
C
C
C
C
C
N
C
C
C
C
C
C
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
1
2
3
4
N
N
N
N
5
6
7
8
9
N
P
W
M
M
2
1
P
W
V
D
D
D
A
V
D
1
1
0
1
P
P
P
P
P
P
A
A
A
A
A
A
0
1
2
3
4
5
V
S
S
S
S
V
A
1
1
2
3
O
S
C
1
R
E
S
1
1
1
4
5
6
P
P
A
A
7
6
H
T
8
3
0
0
3
/
H
T
8
3
0
0
6
/
H
T
8
3
0
0
9
/
H
T
8
3
0
1
8
H
T
8
3
0
3
6
/
H
T
8
3
0
4
8
/
H
T
8
3
0
7
2
3
2
D
I
P
-
A
Rev. 0.10
2
August 25, 2003
Preliminary
HT83XXX
Pad Assignment
HT83003/HT83006/HT83009
(
0
,
0
)
1
1
6
5
P
W
M
M
2
1
P
V
W
D
1
4
D
A
1
1
1
2
1
3
2
7
1
3
5
6
8
9
4
1
0
Chip size: 2220 ´ 1355 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
HT83018/HT83036
(
0
,
0
)
1
6
P
W
M
M
2
1
1
5
P
V
W
D
1
4
D
A
1
1
1
2
1
3
1
2
3
4
5
6
7
8
9
1
0
Chip size: 2220 ´ 1660 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 0.10
3
August 25, 2003
Preliminary
HT83XXX
HT83048/HT83072
(
0
,
0
)
1
6
P
W
M
M
2
1
1
5
P
V
W
D
D
A
1
4
1
1
1
2
1
3
1
2
3
4
5
6
7
8
9
Chip size: 2220 ´ 2335 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates
HT83003/HT83006/HT83009
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
-982.145
-876.845
-766.245
-666.245
-555.645
-455.645
-345.045
-245.045
-508.050
-508.050
-508.050
-508.050
-508.050
-508.050
-508.050
-508.050
-135.205
-31.229
758.645
858.645
958.645
841.895
841.895
841.895
-508.050
-508.050
-490.400
-490.400
-490.400
-345.550
-224.050
-85.450
10
11
12
13
14
15
16
HT83018/HT83036
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
-982.145
-876.845
-766.245
-666.245
-555.645
-455.645
-345.045
-245.045
-660.550
-660.550
-660.550
-660.550
-660.550
-660.550
-660.550
-660.550
-135.205
-31.229
758.645
858.645
958.645
841.895
841.895
841.895
-660.550
-660.550
-642.900
-642.900
-642.900
-498.050
-376.550
-237.950
10
11
12
13
14
15
16
Rev. 0.10
4
August 25, 2003
Preliminary
HT83XXX
HT83048/HT83072
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
-982.145
-876.845
-766.245
-666.245
-555.645
-455.645
-345.045
-245.045
-998.050
-998.050
-998.050
-998.050
-998.050
-998.050
-998.050
-998.050
-135.205
-31.229
758.645
858.645
958.645
841.895
841.895
841.895
-998.050
-998.050
-980.400
-980.400
-980.400
-835.550
-714.050
-575.450
10
11
12
13
14
15
16
Pad Description
Pad Name
I/O
Mask Option
Description
Wake-up,
Pull-high
or None
Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input
by mask option. Software instructions determine the CMOS output or
Schmitt trigger input with or without pull-high resistor (mask option).
PA0~PA7
I/O
VSS
Negative power supply, ground
¾
¾
¾
¾
I
¾
¾
¾
¾
¾
RC
¾
VDD
Positive power supply
VSSA
PWM negative power supply, ground
VDDA
RES
PWM positive power supply, ground
Schmitt trigger reset input, active low
OSC1
PWM1, PWM2
OSC1 is connected to an RC network for the internal system clock.
PWM output for driving a external transistor or speaker
¾
O
Absolute Maximum Ratings
Supply Voltage ..........................VSS+2.4V to VSS+5.2V
Storage Temperature ...........................-50°C to 125°C
Operating Temperature ..........................-20°C to 70°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Test Conditions
Symbol
Parameter
Operating Voltage
Min.
Typ.
Max.
Unit
VDD
¾
Conditions
¾
VDD
ISTB
IDD
IOL
2.4
¾
5.2
¾
V
¾
1
Standby Current
3V
3V
3V
3V
3V
3V
3V
3V
No load, system HALT
No load, fSYS=4MHz
VOL=0.3V
mA
mA
mA
mA
mA
mA
V
Operating Current
1.2
¾
1.5
¾
¾
I/O Port Sink Current
I/O Port Source Current
PWM Source Current
PWM Source Current
Input Low Voltage (RES)
Input High Voltage (RES)
17
IOH
IO
VOH=2.7V
-12
121
-81
¾
¾
¾
VOL=0.3V
¾
¾
IO
VOH=2.7V
¾
¾
VIL1
VIH1
1.5
2.2
4.0
8.0
¾
¾
¾
V
¾
¾
3.7
7.4
4.5
8.6
ROSC=100kW
ROSC=62kW
fSYS
System Frequency
3V
MHz
Rev. 0.10
5
August 25, 2003
Preliminary
HT83XXX
A.C. Characteristics
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
fSYS
System Clock (RC OSC)
Timer Input Frequency
Watchdog Oscillator
3V
3V
3V
4
0
8
8
MHz
MHz
¾
¾
¾
¾
¾
90
23
¾
fTIMER
tWDTOSC
tWDT
45
12
1
180
45
¾
ms
ms
ms
Watchdog Time-out Period (RC) 3V Without WDT prescaler
tRES
External Reset Low Pulse Width
System Start-up Timer Period
¾
¾
¾
Power-up or wake-up from
HALT
tSST
tSYS
1024
¾
¾
Characteristics Curves
R vs. F Characteristics Curve
H
T
8
3
X
X
X
R
v
s
.
F
C
h
a
r
t
9
8
7
6
5
4
3
4
.
5
V
3
.
0
V
6
2
7
2
8
2
9
2
1
0
2
R
(
k
W
)
Rev. 0.10
6
August 25, 2003
Preliminary
HT83XXX
V vs. F Characteristics Curve
H
T
8
3
X
X
X
V
v
s
.
F
C
h
a
r
t
(
F
o
r
3
.
0
V
)
1
0
8
6
4
2
8
M
H
z
/
6
3
k
6
M
H
z
/
7
8
k
4
M
H
z
/
1
0
4
k
2
.
4
2
.
6
2
.
8
3
3
.
2
3
.
4
3
.
6
3
.
8
4
4
.
2
4
.
4
4
.
5
4
.
6
4
.
8
5
5
.
2
V
D
D
H
T
8
3
X
X
X
V
v
s
.
F
C
h
a
r
t
(
F
o
r
4
.
5
V
)
1
0
8
6
4
2
4
M
H
z
/
1
1
3
k
6
M
H
z
/
8
3
k
8
M
H
z
/
6
7
k
2
.
4
2
.
6
2
.
8
3
3
.
2
3
.
4
3
.
6
3
.
8
4
4
.
2
4
.
4
4
.
5
4
.
6
4
.
8
5
5
.
2
V
D
D
Rev. 0.10
7
August 25, 2003
Preliminary
HT83XXX
Functional Description
Execution Flow
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
The system clock for the HT83XXX series is derived
from RC oscillator. It is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt or return from subroutine, the PC
manipulates the program transfer by loading the ad-
dress corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle takes its place while the correct instruction is ob-
tained.
Program Counter - PC
The lower byte of the program counter (PCL) is a
read/write register (06H). Moving data into the PCL per-
forms a short jump. The destination must be within 256
locations.
The 11-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
When a control transfer takes place, an additional
dummy cycle is required.
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
P
C
P
C
+
1
P
C
+
2
P
C
F
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
-
1
)
F
e
t
c
h
I
N
S
T
(
P
C
+
1
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
)
F
e
t
c
h
I
N
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution Flow
Program Counter
Mode
*10
0
*9
0
*8
0
*7
0
*6
0
*5
0
*4
0
*3
0
*2
0
*1
0
*0
0
Initial Reset
Time Base Overflow
0
0
0
0
0
0
0
0
1
0
0
Timer Counter 0 Overflow
Timer Counter 1 Overflow
Skip
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
PC+2
@5
#5
S5
Loading PCL
*10
*9
*8
#8
S8
@7
#7
@6
#6
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, Call Branch
Return from Subroutine
#10
S10
#9
S9
S7
S6
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program counter bits
#10~#0: Instruction code bits
S10~S0: Stack register bits
@7~@0: PCL bits
Rev. 0.10
8
August 25, 2003
Preliminary
HT83XXX
Table Location
Program Memory - ROM
Any location in the ROM space can be used as look up
tables. The instructions TABRDC [m] (used for any
bank) and TABRDL [m] (only used for last page of pro-
gram ROM) transfer the contents of the lower-order byte
to the specified data memory [m], and the higher-order
byte to TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined. The
higher-order bytes of the table word are transferred to
the TBLH. The table higher-order byte register (TBLH)
is read only.
The program memory stores the program instructions
that are to be executed. It also includes data, table and
interrupt entries, addressed by the program counter
along with the table pointer. The program memory size
for HT83XXX is 2048´14 bits. Certain locations in the
program memory are reserved for special usage:
·
Location 000H
This area is reserved for program initialization. The
program always begins execution at location 000H
each time the system is reset.
The table pointer (TBLP) is a read/write register, which
indicates the table location.
·
Location 004H
This area is reserved for the time base interrupt ser-
vice program. If the ETBI (intc.1) is activated, and the
interrupt is enabled and the stack is not full, the pro-
gram will jump to location 004H and begins execution.
Stack Register - Stack
The stack register is a special part of the memory used
to save the contents of the program counter (PC). This
stack is organized into four levels. It is neither part of the
data nor part of the program space, and cannot be read
or written to. Its activated level is indexed by a stack
pointer (SP) and cannot be read or written to. At a sub-
routine call or interrupt acknowledgment, the contents of
the program counter are pushed onto the stack.
·
Location 008H
This area is reserved for the 8-bit timer counter 0 inter-
rupt service program. If a timer interrupt results from a
timer counter 0 overflow, and if the interrupt is enabled
and the stack is not full, the program will jump to loca-
tion 008H and begins execution.
·
The program counter is restored to its previous value
from the stack at the end of subroutine or interrupt rou-
tine, which is signaled by return instruction (RET or
RETI). After a chip resets, SP will point to the top of the
stack.
Location 00CH
This area is reserved for the 8-bit timer counter 1 inter-
rupt service program. If a timer interrupt results from a
timer counter 1 overflow, and if the interrupt is enabled
and the stack is not full, the program will jump to loca-
tion 00CH and begins execution.
The interrupt request flag will be recorded but the ac-
knowledgment will be inhibited when the stack is full and
a non-masked interrupt takes place. After the stack
pointer is decremented (by RET or RETI), the interrupt
request will be serviced. This feature prevents stack
overflow and allows programmers to use the structure
more easily. In a similar case, if the stack is full and a
²CALL² is subsequently executed, stack overflow oc-
curs and the first entry is lost.
0
0
0
0
H
I
n
i
t
i
a
l
A
d
d
r
e
s
s
0
0
0
4
H
T
i
m
e
B
a
s
e
I
n
t
e
r
r
u
p
t
S
u
b
r
o
u
t
i
n
e
0
0
0
8
H
T
i
m
e
r
0
I
n
t
e
r
r
u
p
t
S
u
b
r
o
u
t
i
n
e
P
R
r
o
g
r
a
m
0
0
0
C
H
H
O
M
T
i
m
e
r
1
I
n
t
e
r
r
u
p
t
S
u
b
r
o
u
t
i
n
e
0
0
1
5
0
7
F
F
H
Program Memory
Table Location
Instruction
*10
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
P10
1
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table Location
@7~@0: Write @7~@0 to TBLP pointer register
Note: *10~*0: Current program ROM table
P10~P8: Bits of current program counter
Rev. 0.10
9
August 25, 2003
Preliminary
HT83XXX
Data Memory - RAM
0
0
0
0
1
2
H
H
H
R
0
M
P
0
The data memory is designed with 80´8 bits. The data
memory is further divided into two functional groups,
namely, special function registers (00H~2AH) and gen-
eral purpose user data memory (30H~7FH). Although
most of them can be read or be written to, some are read
only.
0
0
3
4
H
H
0
0
0
0
0
5
6
7
8
9
H
H
H
H
H
A
C
C
P
C
L
T
B
L
P
T
B
L
H
The special function registers include an indirect ad-
dressing register (R0:00H), memory pointer register
(MP0:01H), accumulator (ACC:05H), program counter
lower-order byte register (PCL:06H), table pointer
(TBLP:07H), table higher-order byte register
(TBLH:08H), status register (STATUS:0AH), interrupt
control register 0 (INTC:0BH), timer counter 0
(TMR0:0DH), timer counter 0 control register
(TMR0C:0EH), timer counter 1 (TMR1L:10H), timer
counter 1 control register (TMR1C:11H), I/O registers
(PA:12H), I/O control registers (PAC:13H), voice ROM
address latch0[21:0] (LATCH0H:18H, LATCH0M:19H,
LATCH0L:1AH), time base control bit EBTI (INTC.1),
PWM control register (PWMCR:26H), PWM output
(PWMD:28H), voice ROM latch data register
(LATCHD:2AH).
W
D
T
S
0
A
H
S
T
A
T
U
S
0
B
H
I
N
T
C
0
C
H
0
D
H
T
M
R
0
0
E
H
T
M
R
0
C
0
F
H
1
0
H
T
M
R
1
1
1
H
T
M
R
1
C
1
2
H
P
A
1
3
H
P
A
C
1
1
1
1
1
1
4
5
6
7
8
9
H
H
H
H
H
H
S
p
e
c
i
a
l
P
u
r
p
o
s
e
L
A
T
C
H
0
H
D
A
T
A
M
E
M
O
R
Y
L
A
T
C
H
0
M
1
1
A
B
H
H
L
A
T
C
H
0
L
The general purpose data memory, addressed from
30H~7FH, is used for data and control information un-
der instruction commands.
1
1
C
D
H
H
1
E
H
The areas in the RAM can directly handle the arithmetic,
logic, increment, decrement and rotate operations. Ex-
cept some dedicated bits, each bit in the RAM can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through the Memory Pointer
register 0 (MP0:01H).
1
F
H
2
2
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
P
W
M
C
R
P
W
M
D
2
2
A
B
H
H
:
U
n
u
s
e
d
.
L
A
T
C
H
D
R
e
a
d
a
s
"
0
"
2
F
H
H
3
0
G
e
n
e
r
a
l
P
u
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p
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s
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D
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t
a
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e
m
o
r
y
7
F
H
RAM Mapping
Description
Address RAM Mapping
Read/Write
R/W
00H
01H
05H
06H
07H
08H
09H
R0
Indirect addressing register 0
Memory pointer 0
MP0
ACC
PCL
R/W
R/W
Accumulator
R/W
Program counter lower-order byte address
Table pointer lower-order byte register
Table higher-order byte content register
Watchdog Timer option setting register
TBLP
TBLH
WDTS
R/W
R
R/W
Rev. 0.10
10
August 25, 2003
Preliminary
HT83XXX
Address RAM Mapping
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
0AH
0BH
0DH
0EH
10H
11H
12H
13H
18H
19H
1AH
26H
28H
2AH
STATUS
INTC
Status register
Interrupt control register 0
Timer counter 0 register
TMR0
TMR0C
TMR1
Timer counter 0 control register
Timer counter 1 register
TMR1C
PA
Timer counter 1 control register
Port A I/O data register
PAC
Port A I/O control register
LATCH0H
LATCH0M
LATCH0L
PWMCR
PWMD
LATCHD
Voice ROM address latch 0 [A17, A16]
Voice ROM address latch 0 [A15~A8]
Voice ROM address latch 0 [A7~A0]
PWM control register
PWM output data D7~D0
Voice ROM data register
2BH~2FH Unused
30H~7FH User data RAM
R/W
User data RAM
Note: R: Read only
W: Write only
R/W: Read/Write
Indirect Addressing Register
Status Register - STATUS (0AH)
Location 00H is indirect addressing registers that are
not physically implemented. Any read/write operation of
[00H] accesses the RAM pointed to by MP0 (01H) re-
spectively. Reading location 00H indirectly returns the
result 00H. While, writing it indirectly leads to no opera-
tion.
This 8-bit STATUS register (0AH) consists of a zero flag
(Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
Except the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
however, may yield different results from those in-
tended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruc-
tion. The Z, OV, AC, and C flags reflect the status of the
latest operations.
Accumulator - ACC (05H)
The accumulator (ACC) is related to the ALU opera-
tions. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
·
Logic operations (AND, OR, XOR, CPL)
·
Rotation (RL, RR, RLC, RRC)
·
Increment and Decrement (INC, DEC)
·
Branch decision (SZ, SNZ, SIZ, SDZ etc)
Rev. 0.10
11
August 25, 2003
Preliminary
HT83XXX
Labels
Bits
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
0
C
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by ex-
ecuting the ²HALT² instruction.
4
PDF
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
5
TO
set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Status Register
Interrupts
T1F bit is set, a subroutine call to location 0CH will oc-
cur. The related interrupt request flag (T1F) will be reset
The HT83XXX provides two 8-bit programmable timer
interrupts, and a time base interrupt. The Interrupt Con-
trol registers (INTC:0BH) contain the interrupt control
bits to set to enable/disable and the interrupt request
flags.
and the EMI bit cleared to disable further interrupts.
Time Base Interrupt is triggered by set INTC.1 (ETBI)
which sets the related interrupt request flag (TBF:bit 4 of
INTC). When the interrupt is enabled, and the stack is
not full and the external interrupt is active, a subroutine
call to location 04H will occur. The interrupt request flag
(TBF) and EMI bits will be cleared to disable other inter-
rupts.
Once an interrupt subroutine is serviced, all other inter-
rupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain in-
terrupt needs servicing within the service routine, the
EMI bit and the corresponding INTC bit may be set to al-
low interrupt nesting. If the stack is full, the interrupt re-
quest will not be acknowledged, even if the related
interrupt is enabled, until the SP is decremented. If im-
mediate service is desired, the stack must be prevented
from becoming full.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgment are held until the RETI instruc-
tion is executed or the EMI bit and the related interrupt
control bit are set to 1 (of course, if the stack is not full).
To return from the interrupt subroutine, the RET or RETI
instruction may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at the specified location(s) in
the program memory. Only the program counter is
pushed onto the stack. The programmer must save the
contents of the register or status register (STATUS) in
advance if they are altered by an interrupt service pro-
gram which corrupts the desired control sequence.
The timer counter 0/1 interrupt request flag (T0F/T1F)
which enables timer counter 0/1 control bit (ET0I/ET1I),
the time base interrupt request flag (TBF) which enables
time base control bit (ETTBI) from the interrupt control
register (INTC:0BH) EMI, ETBI, ET0I, ET1I are used to
control the enabling/disabling of interrupts. These bits
prevent the requested interrupt begin serviced. Once
the interrupt request flags (T0F, T1F, TBF) are set, they
will remain in the INTC register until the interrupts are
serviced or cleared by a software instruction.
The Internal Timer Counter 0 Interrupt is initialized by
setting the timer counter 0 interrupt request flag (T0F:bit
5 of INTC), caused by a timer counter 0 overflow. When
the interrupt is enabled, and the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
The Internal Timer Counter 1 Interrupt is initialized by
setting the timer counter 1 interrupt request flag (T1F:bit
6 of INTC), caused by a timer counter 1 overflow. When
the interrupt is enabled, and the stack is not full and the
It is recommended that application programs do not use
CALL subroutines within an interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
Rev. 0.10
12
August 25, 2003
Preliminary
HT83XXX
one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt subrou-
tine will corrupt the original control sequence.
Register Bit No.
Label
EMI
ETBI
ET0I
ET1I
TBF
T0F
T1F
¾
Function
Controls the master (global) interrupt (1= enabled; 0= disabled)
Controls the time base interrupt (1= enabled; 0= disabled)
Controls the timer 0 interrupt (1= enabled; 0= disabled)
Controls the timer 1 interrupt (1= enabled; 0= disabled)
Time base interrupt request flag (1= active; 0= inactive)
Timer 0 request flag (1= active; 0= inactive)
0
1
2
3
INTC
(0BH)
4
5
6
7
Timer 1 request flag (1= active; 0= inactive)
Unused bit, read as ²0²
INTC0 register
Interrupt Source
Time Base Interrupt
Priority
Vector
04H
1
2
3
Timer Counter 0 Overflow
Timer Counter 1 Overflow
08H
0CH
Oscillator Configuration
Watchdog Timer - WDT
The HT83XXX provides RC oscillator circuit for the sys-
tem clock. The signal is used for the system clock. The
HALT mode stops the system oscillator to conserve
power. If the RC oscillator is used, an external resistor
between OSC1 and VSS is required, and the range of
the resistance should be from 62kW to 100kW. The sys-
tem clock, divided by 4. The RC oscillator provides the
most cost effective solution. However, the frequency of
the oscillation may vary with VDD, temperature, and the
chip itself due to process variations. It is therefore not
suitable for timing sensitive operations where accurate
oscillator frequency is desired.
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by mask options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The Watchdog Timer can be disabled
by mask option. If the Watchdog Timer is disabled, all
the executions related to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with pe-
riod 78ms normally) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approxi-
mately 20ms. This time-out period may vary with tem-
perature, VDD and process variations. By invoking the
WDT prescaler, longer time-out period can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of
WDTS(09H)) can give different time-out period.
O
S
C
1
If WS2, WS1, WS0 all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.6 sec-
onds.
R
C
O
s
c
i
l
l
a
t
o
r
System Oscillator
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
Rev. 0.10
13
August 25, 2003
Preliminary
HT83XXX
S
y
s
t
e
m
C
l
o
c
k
/
4
W
D
T
P
r
e
s
c
a
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r
M
a
s
k
8
-
b
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t
C
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r
7
-
b
i
t
C
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r
O
p
t
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c
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W
D
T
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S
C
8
-
t
o
-
1
M
U
X
W
S
0
~
W
S
2
W
D
T
T
i
m
e
-
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u
t
Watchdog Timer
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². Whereas in
the HALT mode, the overflow will initialize a ²warm re -
set² only the PC and SP are reset to zero. To clear the
contents of the WDT (including the WDT prescaler),
three methods are adopted; external reset (external re-
set (a low level to RES), software instructions, or a
HALT instruction. The software instruction is ²CLR
WDT² and execution of the ²CLR WDT² instruction will
clear the WDT.
WS7
¾
WS6
¾
WS5
¾
WS4
¾
WS3
¾
WS2
WS1
WS0
Division Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
¾
¾
¾
¾
¾
1:4
¾
¾
¾
¾
¾
1:8
¾
¾
¾
¾
¾
1:16
1:32
1:64
1:128
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
WDTS Register
Power Down - HALT
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled by the stack is full, the program
will resume execution at the next instruction. If the inter-
rupt is enabled and the stack is not full, the regular inter-
rupt response takes place.
The HALT mode is initialized by a HALT instruction and
results in the following:
·
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
·
The contents of the on chip RAM and registers remain
unchanged.
·
WDT and WDT prescaler will be cleared and recount
again.
·
All I/O ports maintain their original status.
Once a wake-up event occurs, it takes 1024 system
clock period to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be dis-
abled. To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT
status.
·
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². By examining the TO and PDF
flags, the reason for the chip reset can be determined.
The PDF flag is cleared when the system powers-up or
executes the ²CLR WDT² instruction, and is set when
the ²HALT² instruction is executed. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the PC and SP. The other maintain their original
status.
Rev. 0.10
14
August 25, 2003
Preliminary
HT83XXX
Reset
H
A
L
T
W
a
r
m
R
e
s
e
t
W
T
D
T
e
There are 3 ways in which a reset can occur:
W
D
T
i
m
-
o
u
t
·
RES reset during normal operation
R
e
s
e
t
·
RES reset during HALT
R
E
S
·
WDT time-out reset during normal operation
C
o
l
d
S
S
T
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the PC and SP, leaving the other cir-
cuits in their original state. Some registers remain un-
changed during any other reset conditions. Most
registers are reset to their ²initial condition² when the re-
set conditions are met. By examining the PDF flag and
TO flag, the program can distinguish between different
²chip resets².
R
e
s
e
1
0
-
s
t
a
g
e
O
S
C
I
R
i
p
p
l
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C
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r
P
o
w
e
r
-
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n
D
e
t
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c
t
i
n
g
Reset Configuration
The functional unit chip reset status are shown below.
PC
000H
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
Interrupt
Prescaler
Disable
Clear
0
u
0
1
1
0
u
1
u
1
Clear. After master reset,
WDT begins counting
WDT
WDT time-out during normal operation
WDT wake-up HALT
Timer counter
Input/output ports
SP
Off
Input mode
Note: ²u² stands for ²unchanged²
Points to the top of the stack
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses after a system
power up or when awakening from a HALT state.
Timer Counter 0/1
The TMR0/TMR1 is internal clock source only, i.e. (TM1,
TM0)=(1,0). There is a 3-bit prescaler (TMRS2, TMRS1,
TMRS0) which defines different division ratio of
TMR0/TMR1¢s clock source.
When a system power up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
Label Bits
Function
Defines the operating clock source
(TMRS2, TMRS1, TMRS0)
000: clock source/2
V
D
D
R
E
S
001: clock source/4
t
S S T
TMRS2,
010: clock source/8
S
S
T
T
i
m
e
-
o
u
t
TMRS1, 0~2
TMRS0
011: clock source/16
100: clock source/32
C
h
i
p
R
e
s
e
t
101: clock source/64
Reset Timing Chart
110: clock source/128
111: clock source/256
V
D
D
Defines the TMR0/TMR1 active edge
of timer counter
TE
3
Enable/disable timer counting
(0=disabled; 1=enabled)
TON
4
5
R
E
S
¾
Unused bit, read as ²0²
TM0,
TM1
6
7
Defines the operating mode
(TM1, TM0)
TMR0C/TMR1C Register
Reset Circuit
Note:
TMR0C/TMR1C bit 3 always write ²0²
TMR0C/TMR1C bit 5 always write ²0²
TMR0C/TMR1C bit 6 always write ²1²
TMR0C/TMR1C bit 7 always write ²0²
Rev. 0.10
15
August 25, 2003
Preliminary
HT83XXX
The TMR0C is the timer counter 0 control register, which
defines the timer counter 0 options. The timer counter 1
has the same options as the timer counter 0 and is de-
fined by TMR1C.
The TMR0/1 is internal clock source only. There is a
3-bit prescaler (TMRS2, TMRS1, TMRS0) which de-
fines different division ratio of TMR0/1¢s clock source.
Time Base
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to 1. The
overflow of the timer counter is one of the wake-up
sources. No matter what the operation mode is, writing a
0 to ET0I/ET1I can disable the corresponding interrupt
service.
The time base enables the counting operation by
INTC.1 (ETBI) bit. The overflow to interrupt as set
INTC.1. The time base is internal clock source only.
Time base of 1ms to overflow as system clock is 4MHz.
Time base of 0.5ms to overflow as system clock is
8MHz.
(
T
M
R
S
2
,
T
M
R
S
1
,
T
M
R
S
0
)
D
R
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t
l
a
B
u
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a
d
8
-
S
t
a
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e
T
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r
C
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r
0
/
1
S
y
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C
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C
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r
0
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t
o
I
n
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e
r
r
u
p
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Timer Counter 0/1
O
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S
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C
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/
4
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1
0
2
4
t
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r
r
u
p
t
Time Base
The registers states are summarized in the following table.
WDT Time-out RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)
Register Reset (Power On)
PC
0000H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0111
--00 xxxx
-000 0000
xxxx xxxx
00-0 1---
0000H
0000H
0000H
0000H
MP0
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--1u uuuu
-000 0000
uuuu uuuu
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--uu uuuu
-000 0000
uuuu uuuu
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0111
--01 uuuu
-000 0000
uuuu uuuu
00-0 1---
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uu-u u---
ACC
TBLP
TBLH
WDTS
STATUS
INTC
TMR0
TMR0C
TMR1
xxxx xxxx
00-0 1---
uuuu uuuu
00-0 1---
uuuu uuuu
00-0 1---
uuuu uuuu
00-0 1---
uuuu uuuu
uu-u u---
TMR1C
LATCH0H
LATCH0M
LATCH0L
PA
---- --xx
---- --uu
---- --uu
---- --uu
---- --uu
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
-00- 00-0
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
-uu- uu-u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
-uu- uu-u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
1111 1111
-uu- uu-u
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uu- uu-u
uuuu uuuu
uuuu uuuu
PAC
PWMCR
PWMD
LATCHD
Note:
²u² means ²unchanged²; ²x² means ²unknown²; ²-² means ²undefined²
Rev. 0.10
16
August 25, 2003
Preliminary
HT83XXX
Input/Output Ports
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H.
There are 8 bidirectional input/output lines in the
microcontroller, labeled from PA, which are mapped to
the data memory of [12H] respectively. All of these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
²MOV A, [m]² (m=12H). For output operation, all the
data is latched and remains unchanged until the output
latch is rewritten.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H) instruc-
tions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC) to con-
trol the input/output configuration. With this control reg-
ister, CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured
dynamically under software control. To function as an in-
put, the corresponding latch of the control register must
write ²1². The input source also depends on the control
register. If the control register bit is ²1², the input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the ²read-modify-write² instruction.
Each line of port A has the capability of waking-up the
device. The wake-up capability of port A is determined
by mask option. There is a pull-high option available for
all I/O lines. Once the pull-high option is selected, all I/O
lines have pull-high resistors. Otherwise, the pull-high
resistors are absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
V
D
D
D
C
Q
D
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t
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B
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P
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Input/Output Ports
Rev. 0.10
17
August 25, 2003
Preliminary
HT83XXX
Audio Output - PWMD (28H)
The HT83XXX provides one 8-bit PWM interface for driving an external 8W speaker. The programmer must write the
voice data to register PWMD (28H)
Pulse Width Modulation Control Register - PWMCR (26H)
Bit 7
Bit 6 (R/W) Bit 5 (R/W)
P1 P0
Bit 4
Bit 3 (R/W) Bit 2 (R/W)
Single_PWM VROMC
Bit 1
Bit 0 (R/W)
PWMC
¾
¾
¾
PWMC: Start bit of PWM output
PWM2 and the PWM1 will get a GND level voltage after
setting start bit to 1.
·
PWM start counter: 0 to 1
·
PWM ½ output Initial low level , and stop in low level
PWM stop counter: 1 to 0
After waiting one cycle end , stop the PWM counter and
keep in low signal
If PWMC from low to high then start PWM output and
5kHz/6kHz/8kHz latch new data , if no update then keep
the old value.
VROMC: Enable voice ROM power circuit (1=enable;
0=disable)
If PWMC from high to low, in duty end, stop PWM output
and stop the counter.
Single_PWM: Driving PWM signal only by PWM1 port.
(1=enable; 0=disable)
Voice ROM Data Address Latch Counter
The HT83xxx provides an 8-bit (bit 7 is a sign bit, if Sin-
gle_PWM = 0) PWM interface. The PWM provides two
pad outputs: PWM1, PWM2 which can directly drive a
piezo or a 8W speaker without adding any external ele-
ment (green mode), or using only port PWM1 (Set Sin-
gle_PWM = 1) to drive piezo or a 8W speaker with
external element.
The voice ROM data address latch counter is the hand-
shaking between the microcontroller and voice ROM,
where the voice codes are stored. One 8-bit of voice
ROM data will be addressed by setting 18-bit address
latch counter LATCH0H/LATCH0M/LATCH0L. After the
8-bit voice ROM data is addressed, a few instruction cy-
cles (4ms at least) will be generated to latch the voice
ROM data, then the microcontroller can read the voice
data from LATCHD (2AH).
When Setting Single_PWM = 1, choose voice
data7~data1 as the output data (no sign bit on it).
Setting data to P0 and P1 can generate various sam-
pling rates (5kHz/6kHz/8kHz):
Example: Read an 8-bit voice ROM data which is lo-
cated at address 000007H by address latch 0
set
[26H].2
A, 07H
; Enable voice ROM circuit
;
Sampling Carrier Preload PWM Code
P1 P0
Rate
5kHz
6kHz
8kHz
X
frequency Times
Range
1~127
1~127
1~124
X
mov
mov
mov
mov
mov
mov
call
0
0
0
1
30kHz
30kHz
32kHz
X
6
5
4
X
LATCH0L, A ; Set LATCH0L to 07H
A, 00H
LATCH0M, A ; Set LATCH0M to 00H
A, 00H
;
1
0
;
¾
¾
LATCH0H, A ; Set LATCH0H to 00H
If the sign bit is 0, then the signal is output to PWM1and
the PWM2 will get a GND level voltage after setting start
bit to 1. If the sign bit is 1, then the signal is output to
Delay Time ; Delay a short period of time
A, LATCHD ; Get voice data at 000007H
mov
D
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B
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B
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0
F
1
D
C
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B
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P
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2
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P
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2
f
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P
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A
K
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R
PWM
18
Rev. 0.10
August 25, 2003
Preliminary
HT83XXX
Mask Option
Mask Option
Description
PA Wake-up
Enable or disable PA wake-up function
Enable or disable WDT function
Watchdog Timer (WDT)
PA Pull-high
WDT clock source is from WDTOSC or T1
Enable or disable PA pull-high
fOSC - ROSC Table (VDD=5V)
fOSC
ROSC
4MHz 10%
6MHz 10%
8MHz 10%
100k
75k
62k
Application Circuits
V
D
D
V
D
D
O
S
C
1
V
S
S
R
(
1
0
0
k
W
~
6
2
W
k )
V
D
D
V
D
D
A
4
m
7 F
R
P
E
S
V
S
S
A
m
0 . 1 F
C
A
0
~
P
A
7
S
(
p
e
a
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r
P
W
M
M
1
P
W
2
8
/
1
6
)
H
T
8
3
X
X
X
Single PWM Mode
V
D
D
V
D
D
O
S
C
1
V
S
S
R
W
W
V
D
D
V
D
D
A
V
D
D
4
m
7 F
R
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S
V
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A
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(
p
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m
0 . 1 F
C
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1
6
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P
A
0
~
P
A
7
Q
2
P
W
M
M
1
N
P
N
B
C
E
P
W
2
H
T
8
3
X
X
X
Note:
* For normal application, a capacitor C is not necessary. However, if you want to extend the reset time , a 0.1 F
capacitor can be placed on the RES pin.
Rev. 0.10
19
August 25, 2003
Preliminary
HT83XXX
Package Information
32-pin DIP (600mil) Outline Dimensions
A
3
2
1
7
B
1
1
6
H
C
D
I
a
E
F
G
Dimensions in mil
Nom.
Symbol
Min.
1635
535
145
125
16
Max.
A
B
C
D
E
F
G
H
I
1665
555
155
145
20
¾
¾
¾
¾
¾
50
70
¾
100
¾
¾
¾
595
635
0°
615
670
15°
¾
a
¾
Rev. 0.10
20
August 25, 2003
Preliminary
HT83XXX
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 0.10
21
August 25, 2003
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