HT83XXX_07 [HOLTEK]
Q-Voice; Q-语音
| 型号： | HT83XXX_07 |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Q-Voice |
| 文件： | 总39页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT83XXX
Q-VoiceTM
Technical Document
·
·
·
Tools Information
FAQs
Application Note
Features
·
·
·
Operating voltage: 2.4V~5.2V
Two 8-bit programmable timer counter with 8-stage
prescaler and one time base counter
Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)
system clock
·
·
·
Watchdog Timer
·
·
·
·
·
4-level subroutine nesting
System clock: 4MHz~8MHz (2.4V)
Crystal or RC oscillator for system clock
12 I/O pins
HALT function and wake-up feature reduce power
consumption
·
·
PWM circuit direct drive speaker or output by
transistor
2K´15 program ROM
80´8 RAM
28-pin SOP package
Applications
·
·
·
Intelligent educational leisure products
Alert and warning systems
Sound effect generators
General Description
The HT83XXX is 8-bit high performance microcontroller
with voice synthesizer and tone generator. The
HT83XXX is designed for applications on multiple I/Os
with sound effects, such as voice and melody. It can pro-
vide various sampling rates and beats, tone levels, tem-
pos for speech synthesizer and melody generator.
The HT83XXX is excellent for versatile voice and sound
effect product applications. The efficient MCU instruc-
tions allow users to program the powerful custom appli-
cations. The system frequency of HT83XXX can be up
to 8MHz under 2.4V and include a HALT function to re-
duce power consumption.
Selection Table
Body
HT83004
64K-bit
3 sec
HT83007
128K-bit
6 sec
HT83010
192K-bit
9 sec
HT83020
384K-bit
18 sec
HT83038
768K-bit
36 sec
HT83050
1024K-bit
48 sec
HT83074
1536K-bit
72 sec
Voice ROM Size
Voice Length
Rev. 1.20
1
May 17, 2007
HT83XXX
Block Diagram
S
S
T
T
A
A
C
C
K
K
0
1
I
n
t
e
r
r
u
p
t
T
M
R
0
8
-
s
t
a
g
e
P
r
e
s
c
a
l
e
r
S
Y
S
C
L
K
C
i
r
c
u
i
t
S
T
A
C
K
2
P
r
o
g
r
a
m
T
M
R
0
C
S
T
A
C
K
3
8
-
b
i
t
C
o
u
n
t
e
r
P
r
o
g
r
a
m
I
N
T
C
R
O
M
T
M
R
1
8
-
s
t
a
g
e
P
r
e
s
c
a
l
e
r
S
Y
S
C
L
K
I
n
s
t
r
u
c
s
t
t
i
e
o
n
T
M
R
1
C
M
P
0
R
e
g
i
r
M
8
-
b
i
t
D
a
t
a
U
M
e
m
o
r
y
X
T
i
m
e
B
a
s
e
S
Y
S
C
L
K
/
1
0
2
4
S
Y
S
C
L
K
/
4
M
U
X
I
n
s
t
r
u
c
t
i
o
n
P
A
C
P
O
R
T
A
P
A
0
~
P
A
7
D
e
c
o
d
e
r
P
A
S
T
A
T
U
S
A
L
U
P
B
C
T
i
m
i
n
g
P
O
R
T
B
S
h
i
f
t
e
r
P
B
0
~
P
B
3
G
e
n
e
r
a
t
i
o
n
P
B
W
D
T
R
C
W
D
T
S
M
O
S
C
O
S
C
2
O
S
C
1
A
C
C
U
¸
2
5
6
W
D
T
P
r
e
s
c
a
l
e
r
X
R
E
S
S
Y
S
C
L
K
/
4
V
D
D
V
S
S
S
P
P
Y
W
W
S
C
L
K
P
W
M
M
M
1
2
Pin Assignment
N
N
N
C
C
C
N
C
C
C
1
2
3
4
5
6
7
8
9
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
N
N
P
A
0
P
W
W
D
D
S
S
M
M
2
1
P
A
1
P
P
A
2
V
D
D
A
P
A
3
V
P
A
4
V
S
S
P
A
5
V
A
P
A
6
O
O
R
N
P
S
S
C
C
1
2
0
1
2
3
4
P
P
A
B
7
0
E
C
S
P
B
1
P
B
2
B
3
H
T
8
3
0
0
4
/
H
T
8
3
0
0
7
/
H
T
8
3
0
1
0
/
H
T
8
3
0
2
0
/
H
T
8
3
0
3
8
/
H
T
8
3
0
5
0
/
H
T
8
3
0
7
4
2
8
S
O
P
-
A
Rev. 1.20
2
May 17, 2007
HT83XXX
Pad Assignment
HT83004/HT83007/HT83010
P
A
0
1
2
3
4
5
6
7
8
2
1
P
P
W
W
M
M
2
1
P
A
1
P
A
2
2
1
0
9
(
0
,
0
)
P
A
3
V
V
V
V
D
D
S
S
D
D
A
P
A
4
1
8
P
A
5
1
7
S
S
A
P
P
A
A
6
7
1
6
1
1
5
4
O
O
S
S
C
C
1
2
9
1
0
1
1
1
2
1
3
Chip size: 2280´1475 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
HT83020/HT83038
P
P
A
A
0
1
1
2
2
2
1
0
P
W
M
2
(
0
,
0
)
P
P
A
A
2
3
3
4
P
W
M
1
1
9
V
V
D
D
D
A
P
P
A
A
4
5
5
6
7
8
1
8
D
1
7
V
V
S
S
S
A
P
P
A
A
6
7
1
1
6
5
S
O
O
S
C
1
1
4
S
C
2
1
1
1 2
3
1
0
9
1
Chip size: 2180´1720 (mm)2
* The IC substrate should be connected to in the PCB layout artwork.
Rev. 1.20
3
May 17, 2007
HT83XXX
HT83050/HT83074
(
0
,
0
)
P
A
0
1
2
3
4
2
1
P
P
W
W
M
M
2
1
P
A
1
P
P
A
A
2
3
2
0
1
9
V
V
D
D
S
S
D
A
P
P
A
A
4
5
5
6
1
8
D
1
1
1
1
7
6
5
4
V
S
A
P
P
A
A
6
7
7
8
V
S
O
O
S
C
1
S
C
2
9
1
0
1
1
1 2
1 3
Chip size: 2180´2075 (mm)2
* The IC substrate should be connected to in the PCB layout artwork.
Pad Coordinates
HT83004/HT83007/HT83010
Pad No.
X
Y
Pad No.
X
Y
1
2
307.150
212.150
109.150
14.150
12
13
14
15
16
17
18
19
20
21
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-947.200
-852.200
-749.200
-654.200
-551.200
940.400
940.400
940.600
940.600
896.250
904.900
904.900
904.900
-587.900
-587.900
-571.200
-476.200
-368.500
-273.000
-165.350
-63.250
56.300
3
4
5
-88.850
-183.850
-286.850
-381.850
-587.900
-587.900
-587.900
6
7
8
9
10
11
266.800
HT83020/HT83038
Pad No.
X
Y
Pad No.
X
Y
1
2
184.650
89.650
12
13
14
15
16
17
18
19
20
21
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-947.200
-852.200
-749.200
-654.200
-551.200
940.400
940.400
940.600
940.600
896.250
904.900
904.900
904.900
-710.400
-710.400
-693.700
-598.700
-491.000
-395.500
-285.750
-185.750
-66.200
3
-13.350
4
-108.350
-211.350
-306.350
-409.350
-504.350
-710.400
-710.400
-710.400
5
6
7
8
9
10
11
144.300
Rev. 1.20
4
May 17, 2007
HT83XXX
HT83050/HT83074
Pad No.
X
Y
Pad No.
X
Y
1
2
7.150
12
13
14
15
16
17
18
19
20
21
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-940.400
-947.200
-852.200
-749.200
-654.200
-551.200
940.400
940.400
940.600
940.600
896.250
904.900
904.900
904.900
-887.900
-887.900
-871.200
-776.200
-668.500
-573.000
-463.250
-363.250
-243.700
-33.200
-87.850
3
-190.850
-285.850
-388.850
-483.850
-586.850
-681.850
-887.900
-887.900
-887.900
4
5
6
7
8
9
10
11
Pad Description
Pad Name I/O Mask Option
Description
Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input by
Wake-up,
PA0~PA7
PB0~PB3
I/O
I/O
Pull-high
or None
mask option. Software instructions determine the
output or Schmitt trig-
ger input with or without pull-high resistor (mask option).
Pull-high
or None
Bidirectional 4-bit I/O port. Software instructions determine the CMOS output or
Schmitt trigger input (pull-high resistor depending on mask option).
Negative power supply, ground
Positive power supply
¾
¾
¾
¾
I
¾
¾
¾
¾
¾
PWM negative power supply, ground
PWM positive power supply, ground
Schmitt trigger reset input, active low
RES
OSC1 and OSC2 are connected to an RC network or crystal (by mask option)
for the internal system clock. In the case of RC operation, OSC2 is the output
terminal for 1/4 system clock. The system clock may came form the crystal, the
two pins cannot be floating.
OSC1,
OSC2
RC or
¾
Crystal
PWM1,
PWM2
O
PWM output for driving a external transistor or speaker
¾
Absolute Maximum Ratings
Supply Voltage ..........................VSS+2.4V to VSS+5.5V
Storage Temperature ...........................-50°C to 125°C
Operating Temperature ..........................-20°C to 70°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
5
May 17, 2007
HT83XXX
D.C. Characteristics
Test Conditions
Conditions
Symbol
VDD
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
fSYS=4MHz/8MHz
Operating Voltage
2.4
¾
5.2
1
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
1
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
ISTB1
Standby Current (Watchdog Off)
No load, system HALT
No load, system HALT
No load, fSYS=4MHz
2
¾
2
¾
ISTB2
Standby Current (Watchdog On)
Operating Current
4
¾
2
¾
IDD
5
¾
7
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
100
50
IOL1
IOH1
IOL2
IOH2
VIL1
VIH1
VIL2
VIH2
fSYS
RPH
V
V
V
V
OL=0.1VDD
I/O Port Sink Current
15
-3.5
-8
50
100
-14.5
-26
¾
OH=0.9VDD
I/O Port Source Current
PWM1/PWM2 Sink Current
PWM1/PWM2 Source Current
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Reset Low Voltage (RES)
Reset High Voltage (RES)
System Frequency
OL=0.1VDD
OH=0.9VDD
¾
¾
¾
¾
2
V
¾
2
V
¾
3.2
1.5
2.5
2.1
3.5
4.0
8.0
60
30
V
¾
V
¾
V
¾
V
¾
V
¾
MHz
MHz
kW
kW
RTYPICAL=275kW
¾
3V
R
TYPICAL=144kW
¾
3V
5V
20
10
Pull-high Resistance
¾
Rev. 1.20
6
May 17, 2007
HT83XXX
A.C. Characteristics
Test Conditions
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
¾
fSYS1
fSYS2
fTIMER
System Clock (RC OSC)
System Clock (Crystal OSC)
Timer Input Frequency
2.4V~5.2V
4
4
0
8
8
8
MHz
MHz
MHz
¾
¾
¾
2.4V~5.2V
2.4V~5.2V
¾
¾
3V
5V
3V
5V
50 100 200
ms
ms
tWDTOSC
Watchdog Oscillator Period
¾
37
12
8
74 148
23
17
46
33
ms
ms
Watchdog Time-out Period
(WDT OSC)
tWDT1
Without WDT prescaler
Without WDT prescaler
Watchdog Time-out Period
(System Clock)
tWDT2
tSYS
1024
¾
¾
¾
tRES
tSST
tINT
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
1
¾
1
¾
¾
¾
¾
¾
¾
¾
1024
¾
¾
¾
¾
¾
¾
ms
tSYS
Power-up or Wake-up from HALT
¾
¾
ms
ms
ms
tDRT
tDRR
Data ROM Access Timer
Data ROM enable Read
5
¾
Read after data ROM enable
30
¾
Characteristics Curves
R vs. F Characteristics Curve
H
T
8
3
X
X
X
R
v
s
.
F
C
h
a
r
t
1
0
8
6
4
2
3
V
4
.
5
V
0
1
4
4
1
8
8
2
7
5
5
6
0
R
(
k
W
)
Rev. 1.20
7
May 17, 2007
HT83XXX
V vs. F Characteristics Curve
H
T
8
3
X
X
X
V
v
s
.
F
C
h
a
r
t
(
F
o
r
3
.
0
V
)
1
0
8
6
8
6
M
M
H
H
z
z
/
/
1
1
4
8
4
8
k
k
W
W
4
4
M
H
z
/
2
7
5
k
2
2
.
5
2
.
7
3
.
0
3
.
5
4
.
0
4
.
5
5
.
2
5
.
5
V
D
D
H
T
8
3
X
X
X
V
v
s
.
F
C
h
a
r
t
(
F
o
r
4
.
5
V
)
1
0
8
6
4
2
8
M
H
z
/
1
3
9
k
6
M
H
z
/
1
8
4
k
4
M
H
z
/
2
7
4
k
2
.
5
2
.
7
3
.
0
3
.
5
4
.
0
4
.
5
5
.
2
5
.
5
V
D
D
Rev. 1.20
8
May 17, 2007
HT83XXX
Functional Description
Execution Flow
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
The system clock for the HT83XXX is derived from ei-
ther a crystal or RC oscillator. It is internally divided into
four non-overlapping clocks. One instruction cycle con-
sists of four system clock cycles.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt or return from subroutine, the PC
manipulates the program transfer by loading the ad-
dress corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the Program Counter, two cycles are
required to complete the instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle takes its place while the correct instruction is ob-
tained.
Program Counter - PC
The lower byte of the program counter (PCL) is a
read/write register (06H). Moving data into the PCL per-
forms a short jump. The destination must be within 256
locations.
The 11-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
When a control transfer takes place, an additional
dummy cycle is required.
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
P
C
P
C
+
1
P
C
+
2
P
C
F
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
-
1
)
F
e
t
c
h
I
N
S
T
(
P
C
+
1
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
)
F
e
t
c
h
I
N
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution Flow
Program Counter
Mode
*10
0
*9
0
*8
0
*7
0
*6
0
*5
0
*4
0
*3
0
*2
0
*1
0
*0
0
Initial Reset
Time Base Overflow
0
0
0
0
0
0
0
0
1
0
0
Timer Counter 0 Overflow
Timer Counter 1 Overflow
Skip
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Program Counter+2
Loading PCL
*10
*9
*8
#8
S8
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, Call Branch
Return from Subroutine
#10
S10
#9
S9
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program counter bits
#10~#0: Instruction code bits
S10~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.20
9
May 17, 2007
HT83XXX
Table Location
Program Memory - ROM
Any location in the ROM space can be used as look up
tables. The instructions ²TABRDC [m]² (used for any
bank) and ²TABRDL [m]² (only used for last page of pro-
gram ROM) transfer the contents of the lower-order byte
to the specified data memory [m], and the higher-order
byte to TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined. The
higher-order bytes of the table word are transferred to
the TBLH. The table higher-order byte register (TBLH)
is read only.
The program memory stores the program instructions
that are to be executed. It also includes data, table and
interrupt entries, addressed by the program counter
along with the table pointer. The program memory size
for HT83XXX is 2048´15 bits. Certain locations in the
program memory are reserved for special usage:
·
Location 000H
This area is reserved for program initialization. The
program always begins execution at location 000H
each time the system is reset.
The table pointer (TBLP) is a read/write register, which
indicates the table location.
·
Location 004H
This area is reserved for the time base interrupt ser-
vice program. If the ETBI (intc.1) is activated, and the
interrupt is enabled and the stack is not full, the pro-
gram will jump to location 004H and begins execution.
Stack Register - Stack
The stack register is a special part of the memory used
to save the contents of the Program Counter. This stack
is organized into four levels. It is neither part of the data
nor part of the program space, and cannot be read or
written to. Its activated level is indexed by a stack
pointer (SP) and cannot be read or written to. At a sub-
routine call or interrupt acknowledgment, the contents of
the program counter are pushed onto the stack.
·
·
Location 008H
This area is reserved for the 8-bit Timer Counter 0 in-
terrupt service program. If a timer interrupt results
from a Timer Counter 0 overflow, and if the interrupt is
enabled and the stack is not full, the program will jump
to location 008H and begins execution.
Location 00CH
The program counter is restored to its previous value
from the stack at the end of subroutine or interrupt rou-
tine, which is signaled by return instruction (RET or
RETI). After a chip resets, SP will point to the top of the
stack.
This area is reserved for the 8-bit Timer Counter 1 in-
terrupt service program. If a timer interrupt results
from a Timer Counter 1 overflow, and if the interrupt is
enabled and the stack is not full, the program will jump
to location 00CH and begins execution.
The interrupt request flag will be recorded but the ac-
knowledgment will be inhibited when the stack is full and
a non-masked interrupt takes place. After the stack
pointer is decremented (by RET or RETI), the interrupt
request will be serviced. This feature prevents stack
overflow and allows programmers to use the structure
more easily. In a similar case, if the stack is full and a
²CALL² is subsequently executed, stack overflow oc-
curs and the first entry is lost.
0
0
0
0
0
0
0
0
0
0
4
8
H
H
H
I
n
i
t
i
a
l
A
d
d
r
e
s
s
T
i
m
e
B
a
s
e
I
n
t
e
r
r
u
p
t
S
u
b
r
o
u
t
i
n
e
T
i
m
e
r
0
I
n
t
e
r
r
u
p
t
S
u
b
r
o
u
t
i
n
e
P
R
r
o
g
r
a
m
0
0
0
C
H
O
M
T
i
m
e
r
1
I
n
t
e
r
r
u
p
t
S
u
b
r
o
u
t
i
n
e
0
0
1
5
H
0
7
F
F
H
Program Memory
Table Location
Instruction
*10
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
P10
1
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table Location
@7~@0: Write @7~@0 to TBLP pointer register
Note: *10~*0: Current program ROM table
P10~P8: Bits of current program counter
Rev. 1.20
10
May 17, 2007
HT83XXX
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Data Memory - RAM
The data memory is designed with 80´8 bits. The data
memory is further divided into two functional groups,
namely, special function registers (00H~2AH) and general
purpose user data memory (30H~7FH). Although most of
them can be read or be written to, some are read only.
The general purpose data memory, addressed from
30H~7FH, is used for data and control information un-
der instruction commands.
0
0
0
0
1
2
H
H
H
I
A
R
0
M
P
0
The areas in the RAM can directly handle the arithmetic,
logic, increment, decrement and rotate operations. Ex-
cept some dedicated bits, each bit in the RAM can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through the Memory Pointer
register 0 (MP0:01H).
0
0
3
4
H
H
0
0
0
0
0
5
6
7
8
9
H
H
H
H
H
A
C
C
P
C
L
T
B
L
P
T
B
L
H
W
D
T
S
0
A
H
Indirect Addressing Register
S
T
A
T
U
S
0
B
H
I
N
T
C
Location 00H is indirect addressing registers that are not
physically implemented. Any read/write operation of
[00H] accesses the RAM pointed to by MP0 (01H) re-
spectively. Reading location 00H indirectly returns the re-
sult 00H. While, writing it indirectly leads to no operation.
0
C
H
0
D
H
T
M
R
0
0
E
H
T
M
R
0
C
0
F
H
1
0
H
T
M
R
1
1
1
H
T
M
R
1
C
Accumulator - ACC (05H)
1
2
H
P
A
The accumulator (ACC) is related to the ALU opera-
tions. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
1
3
H
P
A
C
1
1
1
1
4
5
6
7
H
H
H
H
P
B
P
B
C
S
p
e
c
i
a
l
P
u
r
p
o
s
e
1
8
H
H
L
A
T
C
H
0
H
Arithmetic and Logic Unit - ALU
D
a
t
a
M
e
m
o
r
y
1
9
L
A
T
C
H
0
M
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
1
1
A
B
H
H
H
H
L
A
T
C
H
0
L
1
1
C
D
·
·
·
·
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
1
E
H
1
F
H
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ etc)
2
0
H
2
1
H
2
2
H
Status Register - STATUS (0AH)
2
3
H
2
4
H
This 8-bit STATUS register (0AH) consists of a zero flag
(Z), carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF), watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
2
5
H
2
6
H
P
W
M
C
R
2
2
7
8
H
H
P
W
M
L
P
W
M
H
2
9
H
V
o
l
u
m
e
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
(
V
O
L
)
Except the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
however, may yield different results from those in-
tended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruc-
tion. The Z, OV, AC, and C flags reflect the status of the
latest operations.
2
2
A
B
H
H
L
A
T
C
H
D
:
U
n
u
s
e
d
,
2
F
H
r
e
a
d
a
s
"
0
"
3
0
H
G
e
n
e
r
a
l
P
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p
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D
a
t
a
M
e
m
o
r
y
7
F
H
RAM Mapping
Rev. 1.20
11
May 17, 2007
HT83XXX
Address RAM Mapping
Read/Write
R/W
R/W
R/W
R/W
R/W
R
Description
Indirect Addressing Register 0
00H
01H
05H
06H
07H
08H
09H
0AH
0BH
0DH
0EH
10H
11H
12H
13H
14H
15H
18H
19H
1AH
26H
IAR0
MP0
Memory Pointer 0
ACC
Accumulator
PCL
Program counter lower-order byte address
Table pointer lower-order byte register
Table higher-order byte content register
Watchdog Timer option setting register
Status register
TBLP
TBLH
WDTS
STATUS
INTC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt control register 0
TMR0
TMR0C
TMR1
TMR1C
PA
Timer Counter 0 register
Timer Counter 0 control register
Timer Counter 1 register
Timer Counter 1 control register
Port A I/O data register
PAC
Port A I/O control register
PB
Port B I/O data register
PBC
Port B I/O control register
LATCH0H
LATCH0M
LATCH0L
PWMCR
Voice ROM address latch 0 [A17, A16]
Voice ROM address latch 0 [A15~A8]
Voice ROM address latch 0 [A7~A0]
PWM control register
R/W, higher-nibble
available only
27H
28H
29H
2AH
PWML
PWMH
VOL
PWM output data P3~P0 to PWML7~PWML4
PWM output data P11~P4 to PWMH7~PWMH0
R/W
R/W, higher-nibble
available only
Volume control register and volume controlled by VOL8~VOL4
Voice ROM data register
LATCHD
R
2BH~2FH Unused
30H~7FH User data RAM
R/W
User data RAM
Note: R: Read only
W: Write only
R/W: Read/Write
Interrupts
low interrupt nesting. If the stack is full, the interrupt re-
quest will not be acknowledged, even if the related
The HT83XXX provides two 8-bit programmable timer
interrupts, and a time base interrupt. The Interrupt Con-
trol registers (INTC:0BH) contain the interrupt control
bits to set to enable/disable and the interrupt request
flags.
interrupt is enabled, until the Stack Pointer is decre-
mented. If immediate service is desired, the stack must
be prevented from becoming full.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at the specified location(s) in
the program memory. Only the program counter is
pushed onto the stack. The programmer must save the
contents of the register or status register (STATUS) in
advance if they are altered by an interrupt service pro-
gram which corrupts the desired control sequence.
Once an interrupt subroutine is serviced, all other inter-
rupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain in-
terrupt needs servicing within the service routine, the
EMI bit and the corresponding INTC bit may be set to al-
Rev. 1.20
12
May 17, 2007
HT83XXX
Bit No.
Label
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
0
C
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared by system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
4
PDF
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
5
TO
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
The Internal Timer Counter 0 Interrupt is initialized by
setting the Timer Counter 0 interrupt request flag (T0F:bit
5 of INTC), caused by a Timer Counter 0 overflow. When
the interrupt is enabled, and the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
the time base interrupt request flag (TBF) which enables
time base control bit (ETBI) from the interrupt control reg-
ister (INTC:0BH) EMI, ETBI, ET0I, ET1I are used to con-
trol the enabling/disabling of interrupts. These bits
prevent the requested interrupt begin serviced. Once the
interrupt request flags (T0F, T1F, TBF) are set, they will
remain in the INTC register until the interrupts are ser-
viced or cleared by a software instruction.
The Internal Timer Counter 1 Interrupt is initialized by
setting the Timer Counter 1 interrupt request flag (T1F:bit
6 of INTC), caused by a Timer Counter 1 overflow. When
the interrupt is enabled, and the stack is not full and the
T1F bit is set, a subroutine call to location 0CH will occur.
The related interrupt request flag (T1F) will be reset and
the EMI bit cleared to disable further interrupts.
It is recommended that application programs do not use
CALL subroutines within an interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and the interrupt enable is not well con-
trolled, once a CALL subroutine if used in the interrupt
subroutine will corrupt the original control sequence.
Time Base Interrupt is triggered by set INTC.1 (ETBI)
which sets the related interrupt request flag (TBF:bit 4 of
INTC). When the interrupt is enabled, and the stack is not
full and the external interrupt is active, a subroutine call to
location 04H will occur. The interrupt request flag (TBF)
and EMI bits will be cleared to disable other interrupts.
Bit No. Label
Function
Controls the master (global) interrupt
(1= enabled; 0= disabled)
0
1
2
3
4
5
EMI
ETBI
ET0I
ET1I
TBF
T0F
Controls the time base interrupt
(1= enabled; 0= disabled)
During the execution of an interrupt subroutine, other in-
terrupt acknowledgment are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to ²1² (of course, if the stack
is not full). To return from the interrupt subroutine, the
²RET² or ²RETI² instruction may be invoked. RETI will
set the EMI bit to enable an interrupt service, but RET
will not.
Controls the timer 0 interrupt
(1= enabled; 0= disabled)
Controls the timer 1 interrupt
(1= enabled; 0= disabled)
Time base interrupt request flag
(1= active; 0= inactive)
Timer 0 request flag
(1= active; 0= inactive)
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Timer 1 request flag
6
7
T1F
(1= active; 0= inactive)
¾
Unused bit, read as ²0²
INTC (0BH) Register
The Timer Counter 0/1 interrupt request flag (T0F/T1F)
which enables Timer Counter 0/1 control bit (ET0I/ ET1I),
Rev. 1.20
13
May 17, 2007
HT83XXX
Interrupt Source
Time Base Interrupt
Priority Vector
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by mask options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The Watchdog Timer can be disabled
by mask option. If the Watchdog Timer is disabled, all
the executions related to the WDT result in no operation.
1
2
3
04H
08H
0CH
Timer Counter 0 Overflow
Timer Counter 1 Overflow
Oscillator Configuration
The HT83XXX provides two oscillator circuits for system
clock, i.e., RC oscillator and Crystal oscillator. No matter
what type of oscillator.. The signal is used for the system
clock. The HALT mode stops the system oscillator to
conserve power. If the RC oscillator is used, an external
resistor between OSC1 and VSS is required, and the
range of the resistance should be from 144kW to 275kW.
The system clock, divided by 4. The RC oscillator pro-
vides the most cost effective solution. However, the fre-
quency of the oscillation may vary with VDD,
temperature, and the chip itself due to process varia-
tions. It is therefore not suitable for timing sensitive op-
erations where accurate oscillator frequency is desired.
Once the internal WDT oscillator (RC oscillator with pe-
riod 78ms normally) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approxi-
mately 20ms. This time-out period may vary with tem-
perature, VDD and process variations. By invoking the
WDT prescaler, longer time-out period can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of
WDTS(09H)) can give different time-out period.
If WS2, WS1, WS0 all equal to 1, the division ratio is up to
1:128, and the maximum time-out period is 2.6 seconds.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors in OSC1 and OSC2 are required.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². Whereas in
the HALT mode, the overflow will initialize a ²warm re -
set² only the Program Counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset
(external reset (a low level to RES), software instruc-
tions, or a ²HALT² instruction. The software instruction
is ²CLR WDT² and execution of the ²CLR WDT² instruc-
tion will clear the WDT.
O
S
C
1
O
S
C
1
V
D
D
f
S
Y
S
/
4
O
S
C
2
O
S
C
2
R
C
O
s
c
i
l
l
a
t
o
r
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
o
r
System Oscillator
WS7
¾
WS6
¾
WS5
¾
WS4
¾
WS3
¾
WS2
WS1
WS0
Division Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
¾
¾
¾
¾
¾
1:4
¾
¾
¾
¾
¾
1:8
¾
¾
¾
¾
¾
1:16
1:32
1:64
1:128
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
WDTS (09H) Register
Rev. 1.20
14
May 17, 2007
HT83XXX
S
y
s
t
e
m
C
l
o
c
k
/
4
W
D
T
P
r
e
s
c
a
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e
r
M
a
s
k
8
-
b
i
t
C
o
u
n
t
e
r
7
-
b
i
t
C
o
u
n
t
e
r
O
p
t
i
o
n
S
e
l
e
c
t
W
D
T
O
S
C
8
-
t
o
-
1
M
U
X
W
S
0
~
W
S
2
W
D
T
T
i
m
e
-
o
u
t
Watchdog Timer
Power Down - HALT
abled. To minimize power consumption, all I/O pins
should be carefully managed before entering the HALT
status.
The HALT mode is initialized by a ²HALT² instruction
and results in the following:
·
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
Reset
There are 3 ways in which a reset can occur:
·
·
·
RES reset during normal operation
RES reset during HALT
·
·
The contents of the on chip RAM and registers remain
unchanged.
WDT time-out reset during normal operation
WDT and WDT prescaler will be cleared and recount
again.
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the Program Counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during any other reset
conditions. Most registers are reset to their ²initial condi-
tion² when the reset conditions are met. By examining
the PDF flag and TO flag, the program can distinguish
between different ²chip resets².
·
·
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². By examining the TO and PDF
flags, the reason for the chip reset can be determined.
The PDF flag is cleared when the system powers-up or
executes the ²CLR WDT² instruction, and is set when
the ²HALT² instruction is executed. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and Stack Pointer. The
other maintain their original status.
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
0
u
0
1
1
0
u
1
u
1
WDT time-out during normal operation
WDT wake-up HALT
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port
stimulus, the program will resume execution of the next
instruction. If awakening from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled by the stack is full, the program
will resume execution at the next instruction. If the inter-
rupt is enabled and the stack is not full, the regular inter-
rupt response takes place.
Note: ²u² stands for ²unchanged²
V
D
D
R
E
S
Once a wake-up event occurs, it takes 1024 system
clock period to resume normal operation. In other
words, a dummy cycle period will be inserted after a
wake-up. If the wake-up results from an interrupt ac-
knowledge, the actual interrupt subroutine will be de-
layed by one more cycle. If the wake-up results in next
instruction execution, this will be executed immediately
after a dummy period is finished. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be dis-
Reset Circuit
V
D
D
R
E
S
t
S S T
S
S
T
T
i
m
e
-
o
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t
C
h
i
p
R
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s
e
t
Reset Timing Chart
Rev. 1.20
15
May 17, 2007
HT83XXX
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses after a system
power up or when awakening from a HALT state.
The functional unit chip reset status are shown below.
Program Counter
Interrupt
000H
Disable
Clear
Prescaler
When a system power up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
Clear. After master reset,
WDT begins counting
WDT
Timer Counter
Input/Output Ports
Stack Pointer
Off
H
A
L
T
W
a
r
m
R
e
s
e
t
Input mode
W
T
D
T
e
W
D
T
Points to the top of the stack
i
m
-
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t
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-
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Reset Configuration
Timer Counter 0/1
The TMR0/TMR1 is internal clock source only, i.e. (TM1, TM0) = (0, 1). There is a 3-bit prescaler (TMRS2, TMRS1,
TMRS0) which defines different division ratio of TMR0/TMR1¢s clock source.
Bit No.
Label
Function
Defines the operating clock source (TMRS2, TMRS1, TMRS0)
000: clock source/2
001: clock source/4
TMRS2, 010: clock source/8
TMRS1, 011: clock source/16
TMRS0 100: clock source/32
101: clock source/64
0~2
110: clock source/128
111: clock source/256
3
4
5
TE
TON
¾
Defines the TMR0/TMR1 active edge of Timer Counter
Enable/disable timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
6
7
TM0,
TM1
Defines the operating mode (TM1, TM0)
TMR0C (0EH)/TMR1C (11H) Register
Note:
TMR0C/TMR1C bit 3 always write ²0²
TMR0C/TMR1C bit 5 always write ²0²
TMR0C/TMR1C bit 6 always write ²1²
TMR0C/TMR1C bit 7 always write ²0²
(
T
M
R
S
2
,
T
M
R
S
1
,
T
M
R
S
0
)
D
R
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B
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8
-
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T
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0
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1
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C
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r
0
/
1
t
o
I
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r
r
u
p
t
Timer Counter 0/1
Rev. 1.20
16
May 17, 2007
HT83XXX
The TMR0C is the Timer Counter 0 control register,
which defines the Timer Counter 0 options. The Timer
Counter 1 has the same options as the Timer Counter 0
and is defined by TMR1C.
Time Base
The time base enables the counting operation by
INTC.1 (ETBI) bit. The overflow to interrupt as set
INTC.4. The time base is internal clock source only.
Time base of 1ms to overflow as system clock is 4MHz.
Time base of 0.5ms to overflow as system clock is
8MHz.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C/TMR1C) should be set to ²1². The
overflow of the timer counter is one of the wake-up
sources. No matter what the operation mode is, writing a
0 to ET0I/ET1I can disable the corresponding interrupt
service.
O
v
e
r
f
l
o
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S
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s
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m
C
l
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c
k
/
4
¸
1
0
2
4
t
o
I
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e
r
r
u
p
t
Time Base
The TMR0/1 is internal clock source only. There is a
3-bit prescaler (TMRS2, TMRS1, TMRS0) which de-
fines different division ratio of TMR0/1¢s clock source.
The registers states are summarized in the following table.
WDT Time-out RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)
Register Reset (Power-on)
MP0
ACC
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
0000H
0000H
0000H
0000H
0000H
xxxx xxxx
xxxx xxxx
0000 0111
--00 xxxx
-000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
---- 1111
---- 1111
---- --xx
uuuu uuuu
uuuu uuuu
0000 0111
--1u uuuu
-000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
---- 1111
uuuu uuuu
uuuu uuuu
0000 0111
--uu uuuu
-000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
---- 1111
uuuu uuuu
uuuu uuuu
0000 0111
--01 uuuu
-000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
---- 1111
---- 1111
---- --uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--11 uuuu
-uuu uuuu
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
---- uuuu
TBLH
WDTS
STATUS
INTC
TMR0
TMR0C
TMR1
TMR1C
PA
PAC
PB
PBC
---- 1111
---- 1111
---- uuuu
LATCH0H
LATCH0M
LATCH0L
PWMCR
PWML
PWMH
VOL
---- --uu
---- --uu
---- --uu
xxxx xxxx
xxxx xxxx
0--- 00-0
xxxx ----
uuuu uuuu
uuuu uuuu
u--- uu-u
uuuu uuuu
uuuu uuuu
u--- uu-u
uuuu uuuu
uuuu uuuu
u--- uu-u
uuuu ----
uuuu
uuuu uuuu
uuuu uuuu
u--- uu-u
uuuu ----
uuuu ----
uuuu ----
xxxx xxxx
xxxx ----
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu ----
uuuu ----
uuuu uuuu
LATCHD
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note:
²u² means ²unchanged²
²x² means ²unknown²
²-² means ²undefined²
Rev. 1.20
17
May 17, 2007
HT83XXX
Input/Output Ports
These control registers are mapped to locations 13Hm
15H.
There are 12 bidirectional input/output lines in the
microcontroller, labeled from PA to PB, which are
mapped to the data memory of [12H], [14H] respec-
tively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A, [m]² (m=12H, 14H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H) in-
structions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC, PBC) to
control the input/output configuration. With this control
register, CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured
dynamically under software control. To function as an in-
put, the corresponding latch of the control register must
write ²1². The input source also depends on the control
register. If the control register bit is ²1², the input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the ²read-modify-write² instruction.
Each line of port A has the capability of waking-up the
device. The wake-up capability of port A is determined
by mask option. There is a pull-high option available for
all I/O lines. Once the pull-high option is selected, all I/O
lines have pull-high resistors. Otherwise, the pull-high
resistors are absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
For output function, CMOS is the only configuration.
V
D
D
D
a
t
a
B
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s
D
C
Q
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V
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P
A
0
~
P
A
7
P
B
0
~
P
B
3
D
C
Q
W
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I
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Q
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P
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M
a
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O
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n
Input/Output Ports
Rev. 1.20
18
May 17, 2007
HT83XXX
Pulse Width Modulation Output - PWML/PWMH (27H/28H)
The HT83XXX provide one 12-bit PWM interface for driving an external 8W speaker. The programmer must write the
voice data to register PWML/PWMH (27H/28H)
Pulse Width Modulation Control Register - PWMCR (26H)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 (R/W)
Bit 2 (R/W)
Bit 1
Bit 0 (R/W)
MSB_SIGN
Single_PWM
VROMC
PWMC
¾
¾
¾
¾
Voice ROM Data Address Latch Counter
PWMC: Start bit of PWM output
The voice ROM data address latch counter is the hand-
shaking between the microcontroller and voice ROM,
where the voice codes are stored. One 8-bit of voice
ROM data will be addressed by setting 18-bit address
latch counter LATCH0H/LATCH0M/LATCH0L. After the
8-bit voice ROM data is addressed, a few instruction cy-
cles (4ms at least) will be generated to latch the voice
ROM data, then the microcontroller can read the voice
data from LATCHD (2AH).
·
·
PWM start counter: 0 to 1
PWM stop counter: 1 to 0
After waiting one cycle end , stop the PWM counter and
keep in low signal
VROMC: Enable voice ROM power circuit
(1=enable; 0=disable)
Single_PWM: Driving PWM signal by PWM1 output.
(1=PWM1 output; 0=PWM1/PWM2 output)
Example: Read an 8-bit voice ROM data which is lo-
cated at address 000007H by address latch 0
The HT83XXX provide an 12-bit (bit 7 is a sign bit, if Sin-
gle_PWM = 0) PWM interface. The PWM provides two
pad outputs: PWM1, PWM2 which can directly drive a
piezo or an 8W speaker without adding any external ele-
ment (green mode), or using only port PWM1 (Set Sin-
gle_PWM = 1) to drive piezo or an 8W speaker with
external element.
set
[26H].2
A, 07H
; Enable voice ROM circuit
;
mov
mov
mov
mov
mov
mov
call
LATCH0L, A ; Set LATCH0L to 07H
A, 00H
LATCH0M, A ; Set LATCH0M to 00H
A, 00H
;
When Setting Single_PWM= 1, choose voice data7~
data1 as the output data (no sign bit on it).
;
LATCH0H, A ; Set LATCH0H to 00H
If the sign bit is 0, then the signal is output to PWM1and
the PWM2 will get a GND level voltage after setting start
bit to 1. If the sign bit is 1, then the signal is output to
PWM2 and the PWM1 will get a GND level voltage after
setting start bit to 1.
Delay Time ; Delay a short period of time
A, LATCHD ; Get voice data at 000007H
mov
PWM output Initial low level , and stop in low level
If PWMC from low to high then start PWM output latch
new data , if no update then keep the old value.
If PWMC from high to low, in duty end, stop PWM output
and stop the counter.
D
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a
B
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B
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7
(
s
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b
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P
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(
2
8
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)
V
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7
B
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~
B
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2
6
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2
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S
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PWM
Rev. 1.20
19
May 17, 2007
HT83XXX
Mask Option
Mask Option
Description
PA Wake-up
Enable or disable PA wake-up function
Enable or disable WDT function
Watchdog Timer (WDT)
WDT clock source is from WDTOSC or T1
PA Pull-high
PB Pull-high
OSC Option
Enable or disable PA pull-high
Enable or disable PB pull-high
Crystal or Resistor type
fOSC - RTYPICAL Table (VDD=3V)
fOSC
RTYPICAL
4MHz±10%
6MHz±10%
8MHz±10%
275kW
188kW
144kW
Application Circuits
V
D
D
V
D
D
V
S
S
O
S
C
1
R
O
S
C
V
D
D
V
D
D
V
D
D
P
1
0
0
k
4
m
7 F
V
S
S
P
R
E
S
m
0 . 1 F
C
S
(
p
e
a
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r
P
P
A
0
~
P
A
7
P
W
M
M
1
B
0
~
P
B
3
P
W
2
8
W
W
H
T
8
3
X
X
X
Single PWM Mode
V
D
D
O
S
C
2
V
D
D
4
M
H
z
~
8
M
H
z
V
S
S
O
S
C
1
V
D
D
V
D
D
V
D
D
P
1
0
0
k
V
D
D
4
m
7 F
V
S
S
P
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S
S
p
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a
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r
m
0 . 1 F
C
W
W
Q
2
P
P
A
0
~
P
A
7
P
W
M
1
N
P
N
B
C
E
B
0
~
P
B
3
H
T
8
3
X
X
X
Rev. 1.20
20
May 17, 2007
HT83XXX
Instruction Set Summary
Mnemonic
Instruction
Cycle
Flag
Affected
Description
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
Add data memory to ACC
1
1(1)
1
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
Add ACC to data memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add data memory to ACC with carry
1
1(1)
Add ACC to data memory with carry
Subtract immediate data from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Subtract data memory from ACC
1
1(1)
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1(1)
Logic Operation
AND A,[m]
OR A,[m]
AND data memory to ACC
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
OR data memory to ACC
XOR A,[m]
ANDM A,[m]
ORM A,[m]
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
1
1(1)
1(1)
1(1)
1
XORM A,[m] Exclusive-OR ACC to data memory
AND A,x
OR A,x
AND immediate data to ACC
OR immediate data to ACC
1
XOR A,x
CPL [m]
CPLA [m]
Exclusive-OR immediate data to ACC
Complement data memory
1
1(1)
Complement data memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment data memory with result in ACC
1
Z
Z
Z
Z
Increment data memory
1(1)
DECA [m]
DEC [m]
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
Rotate
RRA [m]
RR [m]
Rotate data memory right with result in ACC
Rotate data memory right
1
1(1)
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
1(1)
C
1
None
None
C
1(1)
1
RLCA [m]
RLC [m]
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1(1)
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Rev. 1.20
21
May 17, 2007
HT83XXX
Instruction
Cycle
Flag
Affected
Mnemonic
Branch
Description
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if data memory is zero
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
Miscellaneous
NOP
No operation
1
1(1)
1(1)
1
None
None
CLR [m]
Clear data memory
SET [m]
Set data memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1
1(1)
1
None
1
TO,PDF
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(1) and (2)
(3)
:
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
Rev. 1.20
22
May 17, 2007
HT83XXX
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
Rev. 1.20
23
May 17, 2007
HT83XXX
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
Operation
The contents of the specified data memory are cleared to 0.
[m] ¬ 00H
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.20
24
May 17, 2007
HT83XXX
CLR [m].i
Clear bit of data memory
Description
Operation
The bit i of the specified data memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
0
PDF
0
OV
Z
AC
C
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
0*
PDF
0*
OV
Z
AC
C
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
0*
PDF
0*
OV
Z
AC
C
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.20
25
May 17, 2007
HT83XXX
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Operation
Data in the specified data memory is decremented by 1.
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.20
26
May 17, 2007
HT83XXX
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
0
PDF
1
OV
Z
AC
C
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Operation
Data in the specified data memory is incremented by 1
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Description
Operation
Move data memory to the accumulator
The contents of the specified data memory are copied to the accumulator.
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.20
27
May 17, 2007
HT83XXX
MOV A,x
Move immediate data to the accumulator
Description
Operation
The 8-bit data specified by the code is loaded into the accumulator.
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
Program Counter ¬ Program Counter+1
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.20
28
May 17, 2007
HT83XXX
RET
Return from subroutine
Description
Operation
Affected flag(s)
The program counter is restored from the stack. This is a 2-cycle instruction.
Program Counter ¬ Stack
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
Operation
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.20
29
May 17, 2007
HT83XXX
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
Operation
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
Rev. 1.20
30
May 17, 2007
HT83XXX
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.20
31
May 17, 2007
HT83XXX
SET [m]
Set data memory
Description
Operation
Each bit of the specified data memory is set to 1.
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Operation
Bit i of the specified data memory is set to 1.
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.20
32
May 17, 2007
HT83XXX
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.20
33
May 17, 2007
HT83XXX
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.20
34
May 17, 2007
HT83XXX
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.20
35
May 17, 2007
HT83XXX
Package Information
28-pin SOP (300mil) Outline Dimensions
2
8
1
5
A
B
1
1
4
C
C
'
G
H
D
a
E
F
Dimensions in mil
Nom.
Symbol
Min.
394
290
14
697
92
¾
Max.
A
B
C
C¢
D
E
F
419
300
20
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
713
104
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.20
36
May 17, 2007
HT83XXX
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
330±1
A
B
Reel Outer Diameter
Reel Inner Diameter
62±1.5
13+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
Rev. 1.20
37
May 17, 2007
HT83XXX
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
24±0.3
W
P
Carrier Tape Width
Cavity Pitch
12±0.1
E
Perforation Position
1.75±0.1
11.5±0.1
1.5+0.1
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K0
t
1.5+0.25
4±0.1
Cavity to Perforation (Length Direction)
Cavity Length
2±0.1
10.85±0.1
18.34±0.1
2.97±0.1
0.35±0.01
21.3
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
Rev. 1.20
38
May 17, 2007
HT83XXX
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
39
May 17, 2007
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