概述
数据手册HM62W8511HJPI-15 概述
4M High Speed SRAM (512-kword x 8-bit) 4M高速SRAM （ 512千字×8位）
HM62W8511HJPI-15 数据手册
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PDF下载HM62W8511HI Series
4M High Speed SRAM (512-kword × 8-bit)
ADE-203-1036A(Z)
Rev. 1.0
Apr. 15, 1999
Description
The HM62W8511HI is a 4-Mbit high speed static RAM organized 512-kword × 8-bit. It has realized high
speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed
circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged
in 400-mil 36-pin SOJ.
Features
•
•
•
Single supply : 3.3 V ± 0.3 V
Access time 15 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
•
•
All inputs and outputs
•
•
•
•
•
Operating current : 130 mA (max)
TTL standby current : 50 mA (max)
CMOS standby current : 5 mA (max)
Center VCC and VSS type pinout
Temperature range: –40 to 85°C
HM62W8511HI Series
Ordering Information
Type No.
Access time
Package
HM62W8511HJPI-15
15 ns
400-mil 36-pin plastic SOJ (CP-36D)
Pin Arrangement
HM62W8511HJPI Series
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A0
A1
2
A18
A17
A16
A15
OE
I/O8
I/O7
VSS
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
3
A2
4
A3
5
A4
6
CS
I/O1
I/O2
VCC
VSS
I/O3
I/O4
WE
A5
7
8
9
10
11
12
13
14
15
16
17
18
A6
A7
A8
A9
(Top View)
2
HM62W8511HI Series
Pin Description
Pin name
A0 to A18
I/O1 to I/O8
CS
Function
Address input
Data input/output
Chip select
OE
Output enable
Write enable
Power supply
Ground
WE
VCC
VSS
NC
No connection
Block Diagram
(LSB)
A1
VCC
VSS
A17
A7
A11
A16
A2
Memory matrix
256 rows × 8 columns ×
256 blocks × 8 bit
(4,194,304 bits)
Row
decoder
A6
A5
(MSB)
CS
Column I/O
I/O1
.
Input
data
control
Column decoder
CS
.
.
I/O8
A10 A8 A9 A12 A13 A14 A0 A18 A15 A3 A4
(LSB)
(MSB)
WE
CS
OE
CS
3
HM62W8511HI Series
Operation Table
CS
H
L
OE
×
WE
×
Mode
VCC current
I/O
Ref. cycle
—
Standby
Output disable
Read
ISB, ISB1
ICC
High-Z
High-Z
Dout
Din
H
L
H
H
L
—
L
ICC
Read cycle (1) to (3)
Write cycle (1)
Write cycle (2)
L
H
L
Write
ICC
L
L
Write
ICC
Din
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
VCC
–0.5 to +4.6
–0.5*1 to VCC+0.5*2
V
VT
V
PT
1.0
W
°C
°C
°C
Operating temperature
Storage temperature
Topr
Tstg
Tbias
–40 to +85
–55 to +125
–40 to +85
Storage temperature under bias
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
2. VT (max) = VCC+2.0 V for pulse width (over shoot)≤ 8 ns
Recommended DC Operating Conditions (Ta = –40 to +85°C)
Parameter
Symbol
VCC*3
VSS*4
VIH
Min
3.0
Typ
3.3
0
Max
Unit
V
Supply voltage
3.6
0
0
V
Input voltage
2.2
—
VCC + 0.5*2
V
VIL
–0.5*1
—
0.8
V
Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
2. VIH (max) = VCC+2.0 V for pulse width (over shoot)≤ 8 ns
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all VSS pins must be on the same level.
4
HM62W8511HI Series
DC Characteristics (Ta = –40 to +85°C, VCC = 3.3 V ± 0.3 V, VSS = 0V)
Parameter
Symbol Min
Typ*1
—
Max
2
Unit
µA
Test conditions
Vin = VSS to VCC
Vin = VSS to VCC
Input leakage current
Output leakage current
IILII
—
—
—
IILOI
—
2
µA
Operation power
supply current
15 ns cycle ICC
—
130
mA
Min cycle
CS = VIL, lout = 0 mA
Other inputs = VIH/VIL
Standby power supply 15 ns cycle ISB
current
—
—
—
50
5
mA
mA
Min cycle
CS = VIH,
Other inputs = VIH/VIL
ISB1
0.05
f = 0 MHz
V
CC ≥ CS ≥ VCC - 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC - 0.2 V
Output voltage
VOL
VOH
—
—
—
0.4
—
V
V
IOL = 8 mA
2.4
IOH = –4 mA
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol Min
Typ
—
Max
6
Unit
pF
Test conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
Cin
CI/O
—
—
—
8
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
5
HM62W8511HI Series
AC Characteristics (Ta = –40 to +85°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
3.3 V
1.5 V
319Ω
Dout
353Ω
RL=50 Ω
5 pF
Dout
Zo=50 Ω
Output load (A)
Output load (B)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW
)
Read Cycle
HM62W8511HI
-15
Parameter
Symbol
tRC
Min
15
—
—
—
3
Max
—
15
15
7
Unit
Notes
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select access time
tAA
tACS
tOE
Output enable to outpput valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
tOH
—
—
—
7
tCLZ
3
1
1
1
1
tOLZ
tCHZ
tOHZ
0
—
—
7
6
HM62W8511HI Series
Write Cycle
HM62W8511HI
-15
Min
15
10
10
10
0
Parameter
Symbol
tWC
Max
—
—
—
—
—
—
—
—
—
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Address valid to end of write
Chip select to end of write
Write pulse width
tAW
tCW
9
8
6
7
tWP
Address setup time
tAS
Write recovery time
tWR
0
Data to write time overlap
Data hold from write time
Write disable to output in low-Z
Output disable to output in high-Z
Write enable to output in high-Z
tDW
7
tDH
0
tOW
3
1
1
1
tOHZ
tWHZ
—
—
7
Note: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. Address should be valid prior to or coincident with CS transition low.
3. WE and/or CS must be high during address transition time.
4. if CS and OE are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
output remains a high impedance state.
6. tAS is measured from the latest address transition to the later of CS or WE going low.
7. tWR is measured from the earlier of CS or WE going high to the first address transition.
8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low. A write ends at the earliest transition among CS going
high and WE going high. tWP is measured from the beginnig of write to the end of write.
9. tCW is measured from the later of CS going low to the the end of write.
7
HM62W8511HI Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tAA
tOH
tCHZ
tACS
CS
OE
tOE
tOHZ
tOLZ
tCLZ
High Impedance
Dout
Valid data
Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)
tRC
Address
Dout
Valid address
tAA
tOH
tOH
Valid data
8
HM62W8511HI Series
Read Timing Waveform (3) (WE = VIH, CS = VIL, OE = VIL)*2
tRC
CS
tACS
tCHZ
tCLZ
High
Dout
High
Impedance
Valid data
Impedance
Write Timing Waveform (1) (WE Controlled)
tWC
Valid address
tAW
Address
tWR
OE
tCW
CS*3
tAS
tWP
WE*3
Dout
Din
tOHZ
High impedance*5
tDW
tDH
4
4
*
*
Valid data
9
HM62W8511HI Series
Write Timing Waveform (2) (CS Controlled)
tWC
Valid address
tCW
Address
tWR
CS *3
tAW
tWP
WE *3
tAS
tWHZ
tOW
High impedance*5
Dout
Din
tDW
tDH
4
4
*
*
Valid data
10
HM62W8511HI Series
Package Dimensions
HM62W8511HJPI Series (CP-36D)
Unit: mm
23.25
23.62 Max
36
19
18
1
0.74
1.30 Max
9.40 ± 0.25
1.27
0.10
0.43 ± 0.10
0.41 ± 0.08
Hitachi Code
JEDEC
CP-36D
Conforms
Conforms
Weight (reference value) 1.4 g
EIAJ
Dimension including the plating thickness
Base material dimension
11
HM62W8511HI Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
12
HM62W8511HI Series
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
1.0
Apr. 15, 1999
Initial issue
13
HM62W8511HJPI-15 相关器件
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| HM62W8512ALFP-8 | RENESAS | 512KX8 STANDARD SRAM, 85ns, PDSO32, 0.525 INCH, PLASTIC, SOP-32 | 获取价格 |
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| HM62W8512ALFP-8SL | RENESAS | 512KX8 STANDARD SRAM, 85ns, PDSO32, 0.525 INCH, PLASTIC, SOP-32 | 获取价格 |
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| HM62W8512ALRR-8 | RENESAS | 512KX8 STANDARD SRAM, 85ns, PDSO32, 0.400 INCH, PLASTIC, REVERSE, TSOP2-32 | 获取价格 |
|
| HM62W8512ALRR-8SL | RENESAS | 512KX8 STANDARD SRAM, 85ns, PDSO32, 0.400 INCH, PLASTIC, REVERSE, TSOP2-32 | 获取价格 |
|
| HM62W8512ALTT-8 | RENESAS | 512KX8 STANDARD SRAM, 85ns, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32 | 获取价格 |
|
| HM62W8512ALTT-8SL | RENESAS | 512KX8 STANDARD SRAM, 85ns, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32 | 获取价格 |
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