HM5164805TT-5 [HITACHI]
EDO DRAM, 8MX8, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32;
| 型号： | HM5164805TT-5 |
| 厂家： | 
HITACHI SEMICONDUCTOR |
| 描述： | EDO DRAM, 8MX8, 50ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总35页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM5164805 Series
HM5165805 Series
64 M EDO DRAM (8-Mword × 8-bit)
8 k Refresh/4 k Refresh
ADE-203-808B (Z)
Rev. 1.0
Feb. 27, 1998
Description
The Hitachi HM5164805 Series, HM5165805 Series are 64M-bit dynamic RAMs organized as 8,388,608-
word × 8-bit. They have realized high performance and low power by employing CMOS process
technology. HM5164805 Series, HM5165805 Series offer Extended Data Out (EDO) Page Mode as a
high speed access mode. They have the package variation of standard 32-pin plastic SOJ and standard
32-pin plastic TSOPII.
Features
•
•
•
Single 3.3 V supply: 3.3 V ± 0.3 V
Access time: 50 ns/60 ns (max)
Power dissipation
Active: 414 mW/378 mW (max) (HM5164805 Series)
: 486 mW/414 mW (max) (HM5165805 Series)
Standby : 1.8 mW (max) (CMOS interface)
: 0.54 mW (max) (L-version)
EDO page mode capability
•
•
Refresh cycles
-only refresh
8192 cycles
/128 ms (HM5164805L) (L-version)
4096 cycles /64 ms (HM5165805)
/128 ms (HM5165805L) (L-version)
/64 ms (HM5164805)
HM5164805 Series, HM5165805 Series
CBR/Hidden refresh
4096 cycles
/64 ms (HM5164805, HM5165805)
/128 ms (HM5164805L, HM5165805L) (L-version)
4 variations of refresh
•
•
-only refresh
-before-
refresh
Hidden refresh
Self refresh (L-version)
Battery backup operation (L-version)
Ordering Information
Type No.
Access time
Package
HM5164805J-5
HM5164805J-6
50 ns
60 ns
400-mil 32-pin plastic SOJ
(CP-32DC)
HM5164805LJ-5
HM5164805LJ-6
50 ns
60 ns
HM5165805J-5
HM5165805J-6
50 ns
60 ns
HM5165805LJ-5
HM5165805LJ-6
50 ns
60 ns
HM5164805TT-5
HM5164805TT-6
50 ns
60 ns
400-mil 32-pin plastic TSOP II
(TTP-32DC)
HM5164805LTT-5
HM5164805LTT-6
50 ns
60 ns
HM5165805TT-5
HM5165805TT-6
50 ns
60 ns
HM5165805LTT-5
HM5165805LTT-6
50 ns
60 ns
2
HM5164805 Series, HM5165805 Series
Pin Arrangement
(HM5164805 Series)
32-pin SOJ
32-pin TSOP
V
V
V
SS
V
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SS
CC
CC
I/O0
I/O1
I/O2
I/O3
NC
I/O7
I/O6
I/O5
I/O4
I/O7
I/O6
I/O5
I/O4
I/O0
I/O1
I/O2
I/O3
NC
3
3
4
4
5
5
V
V
6
6
SS
SS
V
CAS
OE
A12
A11
A10
A9
CAS
OE
A12
A11
A10
A9
V
7
7
CC
CC
WE
RAS
A0
WE
RAS
A0
8
8
9
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
A1
A1
A2
A2
A3
A8
A8
A3
A4
A7
A7
A4
A5
A6
A6
A5
V
V
V
V
SS
CC
SS
CC
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A12
Address input
•
•
Row/Refresh address
Column address
A0 to A12
A0 to A9
I/O0 to I/O7
Data input/output
Row address strobe
Column address strobe
Write enable
Output enable
Power supply
VCC
VSS
NC
Ground
No connection
3
HM5164805 Series, HM5165805 Series
Pin Arrangement
(HM5165805 Series)
32-pin SOJ
32-pin TSOP
V
V
SS
V
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SS
CC
CC
I/O7
I/O6
I/O5
I/O4
I/O7
I/O6
I/O5
I/O4
I/O0
I/O1
I/O2
I/O3
NC
I/O0
I/O1
I/O2
I/O3
NC
3
4
5
V
V
6
SS
SS
CAS
OE
NC
A11
A10
A9
CAS
OE
NC
A11
A10
A9
V
7
V
CC
CC
WE
RAS
A0
8
WE
RAS
A0
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
A1
A1
A2
A2
A8
A8
A3
A3
A7
A7
A4
A4
A6
A6
A5
A5
V
V
V
V
SS
SS
CC
CC
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A11
Address input
•
•
Row/Refresh address
Column address
A0 to A11
A0 to A10
I/O0 to I/O7
Data input/output
Row address strobe
Column address strobe
Write enable
Output enable
Power supply
VCC
VSS
NC
Ground
No connection
4
HM5164805 Series, HM5165805 Series
Block Diagram
(HM5164805 Series)
RAS
CAS
WE
OE
Timing and control
A0
Column decoder
Column
address
buffers
A1
8M array
8M array
8M array
8M array
8M array
8M array
8M array
8M array
•
•
•
to
A9
I/O0
to
I/O buffers
•
•
•
I/O7
Row
address
buffers
A10
to
A12
5
HM5164805 Series, HM5165805 Series
Block Diagram
(HM5165805 Series)
RAS
CAS
WE
OE
Timing and control
A0
Column decoder
Column
address
buffers
A1
8M array
8M array
8M array
8M array
8M array
8M array
8M array
8M array
•
•
•
to
A10
I/O0
to
I/O buffers
•
•
•
I/O7
Row
address
buffers
A11
6
HM5164805 Series, HM5165805 Series
Operation Table
I/O 0 to I/O 7
High-Z
Dout
Operation
H
×
L
L
L
L
H
L
×
×
Standby
L
H
L
Read cycle
L
L*2
L*2
H to L
×
×
Din
Early write cycle
Delayed write cycle
Read-modify-write cycle
-only refresh cycle
L
H
Din
L
L to H
Dout/Din
High-Z
High-Z
L
×
×
H to L
H
-before-
refresh cycle or
Self refresh cycle (L-version)
L
L
H
H
High-Z
Read cycle (Output disabled)
Notes: 1. H: VIH (inactive), L: VIL (active), ×: VIH or VIL
2. tWCS ≥ 0 ns: Early write cycle
tWCS < 0 ns: Delayed write cycle
Absolute Maximum Ratings
Parameter
Symbol
Value
–0.5 to VCC + 0.5 (≤ 4.6 V (max))
Unit
Terminal voltage on any pin relative to VSS VT
V
Power supply voltage relative to VSS
Short circuit output current
Power dissipation
VCC
–0.5 to +4.6
50
V
Iout
PT
mA
W
1.0
Storage temperature
Tstg
–55 to +125
°C
DC Operating Conditions
Parameter
Symbol
VCC
Min
3.0
0
Typ
3.3
0
Max
3.6
Unit
V
Notes
Supply voltage
1, 2
2
VSS
0
V
Input high voltage
VIH
2.0
–0.3
0
—
VCC + 0.3
0.8
V
1
Input low voltage
VIL
—
V
1
Ambient temperature range
Notes: 1. All voltage referred to VSS.
Ta
—
70
_C
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS
pins must be on the same level.
7
HM5164805 Series, HM5165805 Series
DC Characteristics (HM5164805 Series)
HM5164805
-5
-6
Parameter
Operating current*1, *2
Symbol Min
Max
115
2
Min
—
Max
105
2
Unit Test conditions
ICC1
ICC2
—
—
mA
mA
tRC = min
Standby current
—
TTL interface
,
= VIH
Dout = High-Z
—
—
0.5
—
—
0.5
mA
µA
CMOS interface
,
≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
150
150
CMOS interface
,
≥ VCC – 0.2 V
Dout = High-Z
-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
115
5
—
—
105
5
mA
mA
tRC = min
= VIH,
= VIL
Dout = enable
-before-
current
EDO page mode current*1, *3
refresh
ICC6
ICC7
ICC10
—
—
—
115
110
500
—
—
—
105
100
500
mA
mA
µA
tRC = min
= VIL ,
tHPC = tHPC min
cycle,
Battery backup current*4
(Standby with CBR refresh)
(L-version)
CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3
µs
t
RAS ≥ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
400
—
400
µA
CMOS interface
,
≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–5
–5
5
5
–5
–5
5
5
µA
µA
0 V ≤ Vin ≤ VCC + 0.3 V
ILO
0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while
= VIL.
3. Measured with one sequential address change per EDO cycle, tHPC
.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
8
HM5164805 Series, HM5165805 Series
DC Characteristics
(HM5165805 Series)
HM5165805
-5
-6
Parameter
Operating current*1, *2
Symbol Min
Max
Min
—
Max
115
2
Unit Test conditions
ICC1
ICC2
—
—
135
2
mA
mA
tRC = min
Standby current
—
TTL interface
,
= VIH
Dout = High-Z
—
—
0.5
—
—
0.5
mA
µA
CMOS interface
,
≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
150
150
CMOS interface
,
≥ VCC – 0.2 V
Dout = High-Z
-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
135
5
—
—
115
5
mA
mA
tRC = min
= VIH,
= VIL
Dout = enable
-before-
current
EDO page mode current*1, *3
refresh
ICC6
ICC7
ICC10
—
—
—
135
110
500
—
—
—
115
100
500
mA
mA
µA
tRC = min
= VIL ,
tHPC = tHPC min
cycle,
Battery backup current*4
(Standby with CBR refresh)
(L-version)
CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3
µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
400
—
400
µA
CMOS interface
,
≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–5
–5
5
5
–5
–5
5
5
µA
µA
0 V ≤ Vin ≤ VCC + 0.3 V
ILO
0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while
= VIL.
3. Measured with one sequential address change per EDO cycle, tHPC
.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
9
HM5164805 Series, HM5165805 Series
Capacitance (Ta = 25_C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. and = VIH to disable Dout.
10
HM5164805 Series, HM5165805 Series
1,
2,
19
AC Characteristics
(Ta = 0 to +70_C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) * * *
Test Conditions
•
•
•
•
•
Input rise and fall time: 2 ns
Input pulse levels: VIL = 0 V, VIH = 3.0 V
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164805/HM5165805
-5
Min
84
30
8
-6
Parameter
Symbol
tRC
Max
—
Min
104
40
Max
—
Unit
ns
Notes
Random read or write cycle time
precharge time
tRP
—
—
ns
precharge time
tCP
—
10
—
ns
pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
50
8
10000 60
10000 10
10000 ns
10000 ns
pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
0
—
—
—
—
37
25
—
—
—
—
—
—
50
0
—
—
—
—
45
30
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
10
0
0
8
10
14
12
15
40
5
to
delay time
12
10
13
35
5
3
4
to column address delay time
hold time
hold time
to
precharge time
to Din delay time
delay time from Din
13
0
15
0
5
6
6
7
delay time from Din
0
0
Transition time (rise and fall)
2
2
11
HM5164805 Series, HM5165805 Series
Read Cycle
HM5164805/HM5165805
-5
Min
—
—
—
—
0
-6
Min
—
—
—
—
0
Parameter
Symbol
tRAC
tCAC
tAA
Max
50
13
25
13
—
—
—
—
—
—
—
—
—
13
13
—
—
13
13
—
—
Max
60
15
30
15
—
—
—
—
—
—
—
—
—
15
15
—
—
15
15
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
8, 9
Access time from
Access time from
9, 10, 17
9, 11, 17
9
Access time from address
Access time from
tOEA
tRCS
tRCH
tRCHR
tRRH
tRAL
Read command setup time
Read command hold time to
Read command hold time from
Read command hold time to
0
0
12
12
50
0
60
0
Column address to
Column address to
to output in low-Z
lead time
lead time
25
15
0
30
18
0
tCAL
tCLZ
Output data hold time
tOH
3
3
21
Output data hold time from
Output buffer turn-off time
Output buffer turn-off to
to Din delay time
tOHO
tOFF
3
3
—
—
13
3
—
—
15
3
13, 21
13
tOEZ
tCDD
tOHR
tOFR
tWEZ
tWED
tRDD
5
Output data hold time from
Output buffer turn-off to
Output buffer turn-off to
to Din delay time
21
—
—
13
13
—
—
15
15
13, 21
13
to Din delay time
12
HM5164805 Series, HM5165805 Series
Write Cycle
HM5164805/HM5165805
-5
Min
0
-6
Parameter
Symbol
tWCS
tWCH
tWP
Max
—
Min
0
Max
—
Unit
ns
Notes
Write command setup time
Write command hold time
Write command pulse width
14
8
—
10
10
15
10
0
—
ns
8
—
—
ns
Write command to
Write command to
Data-in setup time
Data-in hold time
lead time
lead time
tRWL
13
8
—
—
ns
tCWL
—
—
ns
tDS
0
—
—
ns
15
15
tDH
8
—
10
—
ns
Read-Modify-Write Cycle
HM5164805/HM5165805
-5
-6
Parameter
Symbol
tRWC
Min
116
67
Max
—
Min
140
79
Max
—
Unit
ns
Notes
Read-modify-write cycle time
to
to
delay time
delay time
tRWD
—
—
ns
14
14
14
tCWD
30
—
34
—
ns
Column address to
hold time from
delay time
tAWD
42
—
49
—
ns
tOEH
13
—
15
—
ns
Refresh Cycle
HM5164805/HM5165805
-5
Min
5
-6
Min
5
Parameter
Symbol
Max
—
Max
—
Unit
ns
Notes
setup time (CBR refresh cycle) tCSR
hold time (CBR refresh cycle)
setup time (CBR refresh cycle)
hold time (CBR refresh cycle)
tCHR
tWRP
tWRH
tRPC
8
—
10
0
—
ns
0
—
—
ns
8
—
10
5
—
ns
precharge to
hold time
5
—
—
ns
13
HM5164805 Series, HM5165805 Series
EDO Page Mode Cycle
HM5164805/HM5165805
-5
Min
20
—
—
28
3
-6
Parameter
Symbol
tHPC
Max
Min
25
Max
Unit
Notes
20
EDO page mode cycle time
—
—
ns
EDO page mode
Access time from
hold time from
pulse width
tRASP
tCPA
tCPRH
tDOH
100000 —
100000 ns
16
precharge
precharge
28
—
—
—
—
—
—
35
3
35
—
—
—
—
—
ns
ns
ns
ns
ns
ns
9, 17
Output data hold time from
hold time referred
low
9, 22
tCOL
8
10
5
to
setup time
tCOP
5
Read command hold time from
precharge
tRCHC
28
35
Write pulse width during
precharge
tWPE
tOEP
8
8
—
—
10
10
—
—
ns
ns
precharge time
EDO Page Mode Read-Modify-Write Cycle
HM5164805/HM5165805
-5
-6
Parameter
Symbol
Min
57
Max
Min
68
Max
Unit
Notes
EDO page mode read-modify-write
cycle time
tHPRWC
—
—
ns
delay time from
precharge tCPW
45
—
54
—
ns
14
Refresh (HM5164805 Series)
Parameter
Symbol
tREF
tREF
Max
Unit
ms
Notes
Refresh period
64
8192 cycles
8192 cycles
Refresh period (L-version)
128
ms
Refresh (HM5165805 Series)
Parameter
Symbol
tREF
Max
64
Unit
ms
Notes
Refresh period
4096 cycles
4096 cycles
Refresh period (L-version)
tREF
128
ms
14
HM5164805 Series, HM5165805 Series
Self Refresh Mode (L-version)
HM5164805L/HM5165805L
-5
-6
Parameter
Symbol
tRASS
Min
100
90
Max
—
Min
100
110
–50
Max
—
Unit
µs
Notes
26
pulse width (self refresh)
precharge time (self refresh)
hold time (self refresh)
tRPS
—
—
ns
26
tCHS
–50
—
—
ns
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing -only refresh or -before- refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, than the access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW
CPW (min), the cycle is a read-modify-write and the data output will contain data read from the
≥
t
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15. tDS and tDH are referred to
leading edge in early write cycles and to
leading edge in
delayed write or read-modify-write cycles.
16. tRASP defines
pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. In delayed write or read-modify-write cycles,
data to the device.
must disable output buffer prior to applying
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
15
HM5164805 Series, HM5165805 Series
20. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode
cycle (EDO
page mode mix cycle (1), (2)), minimum value of
than the specified tHPC (min) value. The value of
shown in EDO page mode mix cycle (1) and (2).
cycle (tCAS + tCP + 2 tT) becomes greater
cycle time of mixed EDO page mode is
21. Data output turns off and becomes high impedance from later rising edge of
Hold time and turn off time are specified by the timing specifications of later rising edge of
and between tOHR and tOH and between tOFR and tOFF
and
.
.
22. tDOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms period on the condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at
equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6µs after exiting from self refresh mode.
24. In case of entering from
-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
25. For L-version, it is available to apply each 128 ms and 31.2 µs instead of 64 ms and 15.6 µs at
note 23.
26 At tRASS > 100 µs, self refresh mode is activated, and not activated at tRASS < 10 µs. It is
undefined within the range of 10 µs ≤ tRASS ≤ 100 µs. For tRASS ≥ 10 µs, it is necessary to satisfy
tRPS
.
27. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
16
HM5164805 Series, HM5165805 Series
Timing Waveforms*27
Read Cycle
tRC
tRAS
tRP
RAS
CAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
tRAD
tRAL
tCAL
tCAH
tASR
tASC
tRAH
Address
Column
Row
tRRH
tRCHR
tRCS
tRCH
WE
tWED
tDZC
tCDD
tRDD
High-Z
tOEA
Din
tDZO
tOED
OE
tOEZ
tOHO
tOFF
tOH
tOFR
tOHR
tCAC
tAA
tRAC
tCLZ
tWEZ
Dout
Dout
17
HM5164805 Series, HM5165805 Series
Early Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tASR tRAH
tASC
tCAH
Row
Column
Address
tWCS
tWCH
WE
tDS
tDH
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
18
HM5164805 Series, HM5165805 Series
Delayed Write Cycle*18
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tRAH
tASC
tASR
tCAH
Row
Column
Address
tCWL
tRWL
tWP
tRCS
WE
tDS
tDH
tDZC
High-Z
Din
Din
tOED
tDZO
tOEH
tOEP
OE
tOEZ
tCLZ
High-Z
Dout
Invalid Dout
19
HM5164805 Series, HM5165805 Series
Read-Modify-Write Cycle*18
tRWC
tRAS
tRP
RAS
tT
tRCD
tCAS
tCRP
CAS
tRAD
tASC
tRAH
tCAH
tASR
Address
Row
Column
tCWL
tCWD
tAWD
tRWD
tRCS
tRWL
tWP
WE
Din
OE
tDZC
tDH
tDS
High-Z
Din
tOED
tOEH
tDZO
tOEA
tOEP
tCAC
tAA
tOEZ
tOHO
tRAC
High-Z
Dout
Dout
tCLZ
20
HM5164805 Series, HM5165805 Series
-Only Refresh Cycle
tRC
tRAS
tRP
RAS
CAS
tT
tRPC
tCRP
tCRP
tASR
tRAH
Row
Address
tOFR
tOFF
High-Z
Dout
21
HM5164805 Series, HM5165805 Series
-Before-
Refresh Cycle
tRC
tRC
tRP
tRP
tRAS
tRAS
tRP
RAS
tT
tCSR
tRPC
tRPC
tCP
tCRP
tCP
tCHR
tCSR
tCHR
CAS
WE
tWRP tWRH
tWRP
tWRH
Address
tOFR
tOFF
High-Z
Dout
22
HM5164805 Series, HM5165805 Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
CAS
t
t
RAL
RAD
t
t
t
t
CAH
RAH
ASR
ASC
Address
Row
Column
t
RRH
t
RCS
t
RCH
WE
t
WED
t
DZC
t
CDD
t
RDD
High-Z
Din
t
t
DZO
OED
t
OEA
OE
t
t
OEZ
CAC
t
WEZ
OHO
t
AA
t
t
t
OFF
RAC
t
CLZ
t
OH
Dout
Dout
t
OFR
t
OHR
23
HM5164805 Series, HM5165805 Series
EDO Page Mode Read Cycle (1)
t
RP
t
t
HPC
t
RASP
RAS
t
t
t
CRP
HPC
HPC
t
CPRH
CP
t
t
T
CSH
t
CP
t
t
CP
t
RSH
t
t
t
CAS
CAS
WE
CAS
CAS
CAS
t
RCHC
t
RCHR
tRCS
t
t
RRH
RCH
tRCS
tRCH
tWPE
t
RAL
t
t
CAH
t
tCAH
tCAH
WED
tASC
tASC
tCAH
tRAH
ASC
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
CAL
Column 4
t
t
CAL
CAL
CAL
t
t
RDD
CDD
t
DZC
High-Z
Din
t
t
t
DZO
COP
COL
t
OED
t
t
OEP
OEP
OE
t
t
OFR
CPA
t
CPA
t
OEA
t
t
t
CPA
AA
t
OHR
OEZ
AA
t
t
OEZ
AA
t
t
CAC
t
CAC
t
OEZ
t
t
t
OHO
CAC
AA
t
t
t
t
t
CAC
WEZ
OHO
OFF
OH
tOEA
t
t
RAC
OEA
t
DOH
t
OHO
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
24
HM5164805 Series, HM5165805 Series
EDO Page Mode Read Cycle (2)
t
RP
t
RASP
RAS
t
t
t
t
HPC
HPC
t
CRP
HPC
t
t
t
T
CSH
t
CP
t
t
CP
CP
t
RSH
t
t
CAS
CAS
CAS
WE
CAS
CAS
t
RCHC
t
t
tRCS
RRH
RCH
t
RAL
t
WED
t
CAH
tASC
tCAH
t
tCAH
tCAH
tASC
tRAH ASC
tASC
tASR
Address
Row
Column 1
Column 2
Column 3
t
CAL
Column 4
t
t
CAL
CAL
t
t
RDD
t
CAL
t
DZC
CDD
High-Z
Din
t
t
t
DZO
COP
COL
t
OED
t
OEP
t
OEP
OE
t
t
t
CPA
OFR
t
CPA
AA
CPA
t
OEA
t
t
t
t
t
OHR
OEZ
AA
t
t
OEZ
AA
t
CAC
t
CAC
CAC
t
OEZ
t
t
OHO
AA
t
t
t
t
CAC
OHO
OFF
OH
t
t
OEA
DOH
t
DOH
t
t
OEA
RAC
t
OHO
Dout
Dout 1
Dout 2
Dout 2
Dout 4
Dout 3
25
HM5164805 Series, HM5165805 Series
EDO Page Mode Early Write Cycle
tRASP
tRP
RAS
tT
tCSH
tHPC
tRSH
tCAS
tCP
tCAS
tCP
tCRP
tCAS
tRCD
CAS
tRAH
tASR
tASC tCAH
Column 1
tASC
tCAH
tCAH
tASC
Row
Column 2
Column N
Address
tWCH
tWCH
tWCS
tWCS
tWCS tWCH
WE
tDS
tDH
tDS
tDH
tDS
tDH
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
26
HM5164805 Series, HM5165805 Series
EDO Page Mode Delayed Write Cycle*18
tRASP
tRP
RAS
tCRP
tT
tCP
tCP
tCSH
tHPC
tCAS
tRSH
tCAS
tRCD
tCAS
CAS
tRAD
tRAH
Row
tASR
tASC
tCAH
tASC
tASC
tCAH
tCAH
Column 1
Column 2
Column N
Address
tCWL
tCWL
tRCS
tCWL
tRWL
tRCS
tRCS
WE
tWP
tWP
tDZC tDS
tWP
tDS
tDZC tDS
tDZC
tDH
Din
tDH
Din
tDH
Din
Din
1
2
N
tOED
tDZO
tDZO
tDZO
tOED
tOEP
tOEH
tOED
OEP
tOEP
tOEH
t
tOEH
OE
tCLZ
tCLZ
tCLZ
tOEZ
tOEZ
tOEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
27
HM5164805 Series, HM5165805 Series
EDO Page Mode Read-Modify-Write Cycle*18
t
RASP
t
RP
RAS
t
t
T
HPRWC
t
t
RSH
CAS
t
t
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
CAS
t
RAD
t
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
CWL
RWD
AWD
CWL
CPW
AWD
CWL
CPW
AWD
t
RCS
t
t
RWL
RCS
t
t
t
CWD
CWD
CWD
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEP
OEP
OEP
t
t
t
OEH
OEH
OEH
OE
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
OEZ
t
t
OEZ
t
t
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
28
HM5164805 Series, HM5165805 Series
EDO Page Mode Mix Cycle (1)*20
t
RP
t
RASP
RAS
t
CRP
t
T
t
t
t
CP
CP
CP
t
t
t
t
CAS
CAS
CAS
CAS
CAS
t
CSH
t
RSH
tRCD
t
t
tRCS
RRH
RCH
tWCS
tRCS
tWCH
t
t
CPW
AWD
tWP
WE
t
RAL
tCAH
tASC
tRAH
tASC
t
tASC tCAH
tCAH
CAH
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
Column 4
CAL
t
RDD
t
CAL
t
t
CDD
DH
t
t
DH
DS
t
DS
High-Z
Din
Din 1
Din 3
t
OED
t
OEP
t
WED
OE
t
t
OFR
WEZ
t
CPA
CPA
t
t
t
t
CPA
t
AA
t
AA
t
OEZ
OEZ
t
t
t
OEA
AA
CAC
OHO
t
CAC
tOHO
Dout 3
t
t
OEA
CAC
t
t
OFF
OH
t
DOH
Dout
Dout 2
Dout 4
29
HM5164805 Series, HM5165805 Series
EDO Page Mode Mix Cycle (2) *20
t
RP
t
RASP
RAS
t
CRP
t
t
T
t
CSH
t
CP
t
CP
CP
t
t
t
t
CAS
CAS
CAS
CAS
CAS
WE
tRCD
tRCS
tRCHR
t
RSH
t
RCS
t
RRH
tWCS
tWCH
t
RCS
tRCH
t
RCH
tWP
t
CPW
t
RAL
tASC
tRAH
t
CAH
tASC
tASC tCAH
tCAH
tCAH
tASC
tASR
Address
Row
Column 1
Column 2
t
Column 3
t
Column 4
t
t
CAL
CAL
CAL
CAL
t
DS
t
t
RDD
CDD
t
t
t
DH
DS
DH
High-Z
Din
Din 2
OEP
Din 3
t
t
OEP
t
t
OED
t
OED
COP
t
WED
t
COL
OE
t
OFR
WEZ
t
t
OEA
t
t
t
t
CPA
t
AA
t
CPA
t
OEA
AA
OEZ
t
t
OEZ
AA
t
CAC
t
t
CAC
OEZ
OHO
t
t
RAC
CAC
t
OEA
t
t
t
OFF
OH
t
OHO
OHO
Dout
Dout 1
Dout 3
Dout 4
30
HM5164805 Series, HM5165805 Series
Self Refresh Cycle (L-version)*23, 24, 25, 26
tRASS
tRP
tRPS
RAS
tT
tRPC
tCRP
tCHS
tCSR
tCP
CAS
WE
tWRP
tWRH
tOFR
tOFF
High-Z
Dout
31
HM5164805 Series, HM5165805 Series
Package Dimensions
HM5164805J/ LJ Series
HM5165805J/ LJ Series (CP-32DC)
Unit: mm
20.95
21.38 Max
32
17
16
1
0.74
1.165 Max
9.40 ± 0.25
1.27
0.43 ± 0.10
0.41 ± 0.08
0.10
Hitachi Code
JEDEC
EIAJ
CP-32DC
—
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.2 g
32
HM5164805 Series, HM5165805 Series
HM5164805TT/LTT Series
HM5165805TT/LTT Series (TTP-32DC)
Unit: mm
20.95
21.35 Max
32
17
16
1
1.27
0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32DC
Conforms
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
33
HM5164805 Series, HM5165805 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part
of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the
examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party
or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Tel: 415-589-8300
Fax: 535-1533
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Berkshire SL6 8YA
United Kingdom
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 0628-585000
Fax: 0628-778322
Tel: 27359218
Fax: 27306071
34
HM5164805 Series, HM5165805 Series
Revision Record
Rev. Date
Contents of Modification
Initial issue
Drawn by
J. Miyake
J. Miyake
Approved by
M. Saeki
0.0
0.1
Jul. 23, 1997
Nov. 1997
Change of Subtitle
Y. Takahashi
Timing waveforms
Correct eroors of EDO mix cycle (1)
1.0
Feb. 27, 1998
Deletion of Preliminary
35
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