HM5165160AJ-7 [ETC]
x16 Fast Page Mode DRAM ; X16快速页模式DRAM\n
| 型号： | HM5165160AJ-7 |
| 厂家： | 
ETC |
| 描述： | x16 Fast Page Mode DRAM
|
| 文件： | 总34页 (文件大小：398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM5164160A Series
HM5165160A Series
64M FP DRAM (4-Mword × 16-bit)
8k refresh/4k refresh
ADE-203-596B (Z)
Rev. 2.0
Nov. 25, 1997
Description
The Hitachi HM5164160A Series, HM5165160A Series are CMOS dynamic RAMs organized as
4,194,304-word × 16-bit. They employ the most advanced CMOS technology for high performance and
low power. The HM5164160A Series, HM5165160A Series offer Fast Page Mode as a high speed access
mode. They have the package variations of standard 400-mil 50-pin plastic SOJ and standard 400-mil 50-
pin plastic TSOPII.
Features
•
•
•
Single 3.3 V (±0.3 V)
Access time: 60 ns/70 ns (max)
Power dissipation
Active mode : 432 mW/360 mW (max) (HM5164160A Series)
: 630 mW/540 mW (max) (HM5165160A Series)
Standby mode : 7.2 mW (max)
: 1.08 mW (L-version)
•
•
Fast page mode capability
Refresh cycles
RAS-only refresh
8192 cycles /64 ms (HM5164160A)
4096 cycles /64 ms (HM5165160A)
/128 ms (HM5165160AL) (L-version)
CBR/Hidden refresh
4096 cycles /64 ms (HM5164160A, HM5165160A)
/128 ms (HM5165160AL) (L-version)
4 variations of refresh
•
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
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HM5164160A Series, HM5165160A Series
Self refresh (L-version)
•
•
2CAS-byte control
Battery backup operation (L-version)
Ordering Information
Type No.
Access time
Package
HM5164160AJ-6
HM5164160AJ-7
60 ns
70 ns
400-mil 50-pin plastic SOJ (CP-50DA)
HM5165160AJ-6
HM5165160AJ-7
60 ns
70 ns
HM5164160ATT-6
HM5164160ATT-7
60 ns
70 ns
400-mil 50-pin plastic TSOP II (TTP-50DB)
HM5165160ATT-6
HM5165160ATT-7
60 ns
70 ns
HM5165160ALTT-6
60 ns
2
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HM5164160A Series, HM5165160A Series
Pin Arrangement
HM5164160AJ Series
HM5164160ATT Series
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
VCC
WE
RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
VCC
WE
RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
I/O15
I/O14
I/O13
I/O12
I/O15
I/O14
I/O13
I/O12
V
V
SS
SS
I/O11
I/O10
I/O9
I/O8
NC
VSS
LCAS
UCAS
OE
NC
NC
A12
A11
A10
A9
I/O11
I/O10
I/O9
I/O8
NC
VSS
LCAS
UCAS
OE
NC
NC
A12
A11
A10
A9
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A8
A7
A6
VSS
A8
A7
A6
VSS
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A12
Address input
— Row/Refresh address A0 to A12
— Column address
Data input/Data output
Row address strobe
A0 to A8
I/O0 to I/O15
RAS
UCAS, LCAS Column address strobe
WE
OE
VCC
VSS
NC
Read/Write enable
Output enable
Power supply
Ground
No connection
3
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HM5164160A Series, HM5165160A Series
Pin Arrangement
HM5165160AJ Series
HM5165160ATT/ALTT Series
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
VCC
WE
RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
VCC
WE
RAS
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
VCC
I/O15
I/O14
I/O13
I/O12
I/O15
I/O14
I/O13
I/O12
V
V
SS
SS
I/O11
I/O10
I/O9
I/O8
NC
VSS
LCAS
UCAS
OE
NC
NC
NC
A11
A10
A9
A8
A7
I/O11
I/O10
I/O9
I/O8
NC
VSS
LCAS
UCAS
OE
NC
NC
NC
A11
A10
A9
A8
A7
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A6
VSS
A6
VSS
(Top view)
(Top view)
Pin Description
Pin name
Function
A0 to A11
Address input
— Row/Refresh address A0 to A11
— Column address
Data input/Data output
Row address strobe
A0 to A9
I/O0 to I/O15
RAS
UCAS, LCAS Column address strobe
WE
OE
VCC
VSS
NC
Read/Write enable
Output enable
Power supply
Ground
No connection
4
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HM5164160A Series, HM5165160A Series
Block Diagram (HM5164160A Series)
RAS UCAS LCAS
WE
OE
Timing and control
A0
A1
to
Column decoder
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
Column
address
buffers
•
•
•
A8
I/O0
to
I/O buffers
•
•
•
I/O15
Row
address
buffers
A9
to
A12
5
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HM5164160A Series, HM5165160A Series
Block Diagram (HM5165160A Series)
RAS UCAS LCAS
WE
OE
Timing and control
Column decoder
A0
A1
to
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
4M array
Column
address
buffers
•
•
•
A9
I/O0
to
I/O buffers
•
•
•
I/O15
Row
address
buffers
A10
A11
Truth Table
RAS
H
L
LCAS
UCAS
WE
D
OE
Output
Operation
Standby
D
L
D
H
L
D
Open
H
L
Valid
Valid
Valid
Open
Open
Open
Lower byte Read cycle
Upper byte
L
H
L
H
L
L
L
H
L*2
L*2
L*2
L
Word
L
L
H
L
D
Lower byte Early write cycle
Upper byte
L
H
L
D
L
L
D
Word
L
L
H
L
L*2
L*2
L*2
H
Undefined Lower byte Delayed write cycle
Undefined Upper byte
L
H
L
H
L
L
H
Undefined Word
L
L
H
L
H to L
H to L
H to L
L to H
L to H
L to H
Valid
Valid
Valid
Lower byte Read-modify-write cycle
L
H
L
Upper byte
Word
L
L
6
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HM5164160A Series, HM5165160A Series
L
H
H
L
H
L
D
H
H
H
H
D
D
D
D
H
Open
Open
Open
Open
Open
Word
Word
Word
Word
RAS-only refresh cycle
H to L
H to L
H to L
L
CAS-before-RAS refresh cycle or
Self refresh cycle (L-version)
H
L
L
L
L
Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. tWCS ≥ 0 ns: Early write cycle
tWCS < 0 ns: Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.)
However write OPERATION and output High-Z control are done independently by each UCAS,
LCAS.
ex. if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Absolute Maximum Ratings
Parameter
Symbol
VT
Value
Unit
V
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
–0.5 to VCC + 0.5 (≤ 4.6 V (max))
VCC
–0.5 to +4.6
50
V
Iout
PT
mA
W
1.0
Operating temperature
Storage temperature
Topr
Tstg
0 to +70
–55 to +125
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
3.0
Typ
3.3
—
Max
Unit
V
Notes
Supply voltage
3.6
1, 2
1
Input high voltage
Input low voltage
VIH
2.0
VCC + 0.3
0.8
V
VIL
–0.3
—
V
1
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS
pins must be on the same level.
7
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HM5164160A Series, HM5165160A Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5164160A Series)
HM5164160A
-6
-7
Parameter
Operating current*1, *2
Symbol Min
Max
120
2
Min
—
Max
100
2
Unit Test conditions
mA tRC = min
ICC1
ICC2
—
—
Standby current
—
mA TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
—
1
—
—
1
mA CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
TBD
TBD
µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
120
5
—
—
100
5
mA tRC = min
mA RAS = VIH
UCAS, LCAS = VIL
Dout = enable
CAS-before-RAS refresh
current
ICC6
—
140
—
120
mA tRC = min
Fast page mode current*1, *3 ICC7
—
—
100
—
—
90
mA tPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10
TBD
TBD
µA
µA
CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
TBD
—
TBD
CMOS interface
RAS, UCAS, LCAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10
–10
10
10
–10
–10
10
10
µA
µA
0 V ≤ Vin ≤ VCC + 0.3 V
ILO
0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less within one page mode cycle tPC.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
8
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HM5164160A Series, HM5165160A Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM5165160A Series)
HM5165160A
-6
-7
Parameter
Operating current*1, *2
Symbol Min
Max
175
2
Min
—
Max
150
2
Unit Test conditions
mA tRC = min
ICC1
ICC2
—
—
Standby current
—
mA TTL interface
RAS, UCAS, LCAS = VIH
Dout = High-Z
—
—
1
—
—
1
mA CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
Standby current
(L-version)
ICC2
300
300
µA
CMOS interface
RAS, UCAS,
LCAS ≥ VCC – 0.2 V
Dout = High-Z
RAS-only refresh current*2
Standby current*1
ICC3
ICC5
—
—
175
5
—
—
150
5
mA tRC = min
mA RAS = VIH
UCAS, LCAS = VIL
Dout = enable
CAS-before-RAS refresh
current
ICC6
—
140
—
120
mA tRC = min
Fast page mode current*1, *3 ICC7
—
—
120
650
—
—
110
650
mA tPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10
µA
µA
CMOS interface
Dout = High-Z
CBR refresh: tRC = 31.3 µs
t
RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
ICC11
—
500
—
500
CMOS interface
RAS, UCAS, LCAS ≤ 0.2 V
Dout = High-Z
Input leakage current
Output leakage current
ILI
–10
–10
10
10
–10
–10
10
10
µA
µA
0 V ≤ Vin ≤ VCC + 0.3 V
ILO
0 V ≤ Vout ≤ VCC
Dout = disable
Output high voltage
Output low voltage
VOH
VOL
2.4
0
VCC
0.4
2.4
0
VCC
0.4
V
V
High Iout = –2 mA
Low Iout = 2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less within one page mode cycle tPC.
4. VIH ≥ VCC – 0.2 V, 0 V ≤ VIL ≤ 0.2 V.
9
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HM5164160A Series, HM5165160A Series
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
CI1
Typ
—
Max
Unit
pF
Notes
Input capacitance (Address)
Input capacitance (Clocks)
Output capacitance (Data-in, Data-out)
5
7
7
1
CI2
—
pF
1
CI/O
—
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. RAS, UCAS and LCAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18, *19
Test Conditions
•
•
•
•
Input rise and fall time: 5 ns
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
10
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HM5164160A Series, HM5165160A Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164160A/HM5165160A
-6
-7
Parameter
Symbol Min
Max
—
Min
130
50
10
70
18
0
Max
—
Unit Notes
Random read or write cycle time
RAS precharge time
CAS precharge time
RAS pulse width
tRC
110
40
10
60
15
0
ns
ns
ns
ns
ns
ns
ns
tRP
—
—
tCP
—
—
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
10000
10000
—
10000
10000
—
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
10
0
—
10
0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
21
21
3
10
20
15
15
60
5
—
15
20
15
18
70
5
—
45
52
RAS to column address delay time tRAD
30
35
4
RAS hold time
tRSH
tCSH
tCRP
tOED
tDZO
tDZC
tT
—
—
CAS hold time
—
—
CAS to RAS precharge time
OE to Din delay time
OE delay time from Din
CAS delay time from Din
Transition time (rise and fall)
—
—
22
5
15
0
—
18
0
—
—
—
6
0
—
0
—
6
3
50
3
50
7
11
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HM5164160A Series, HM5165160A Series
Read Cycle
HM5164160A/HM5165160A
-6
-7
Min
—
—
—
—
0
Parameter
Symbol Min
Max
60
15
30
15
—
Max
70
18
35
18
—
–
Unit Notes
Access time from RAS
tRAC
tCAC
tAA
—
—
—
—
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8, 9
Access time from CAS
9, 10, 17
9, 11, 17
9, 25
21
Access time from address
Access time from OE
tOEA
tRCS
tRCH
tRRH
tRAL
tCAL
tCLZ
tOH
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Column address to RAS lead time
Column address to CAS lead time
CAS to output in low-Z
0
—
0
12, 22
12
5
—
5
—
—
—
—
—
—
15
15
—
30
30
0
—
35
35
0
—
—
Output data hold time
3
—
3
Output data hold time from OE
Output buffer turn-off time
Output buffer turn-off to OE
CAS to Din delay time
tOHO
tOFF
tOEZ
tCDD
3
—
3
—
—
15
15
15
—
—
—
18
13
13
5
Write Cycle
HM5164160A/HM5165160A
-6
Symbol Min
-7
Parameter
Max
—
Min
0
Max
—
Unit Notes
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
tWCS
tWCH
tWP
0
ns
ns
ns
ns
ns
ns
ns
14, 21
21
10
10
15
15
0
—
15
10
18
18
0
—
—
—
tRWL
tCWL
tDS
—
—
—
—
23
—
—
15, 23
15, 23
Data-in hold time
tDH
10
—
15
—
12
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HM5164160A Series, HM5165160A Series
Read-Modify-Write Cycle
HM5164160A/HM5165160A
-6
-7
Parameter
Symbol Min
Max
—
Min
181
98
Max
—
Unit Notes
Read-modify-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
OE hold time from WE
tRWC
tRWD
tCWD
tAWD
tOEH
155
85
40
55
15
ns
—
—
ns
ns
ns
ns
14
14
14
—
46
—
—
63
—
—
18
—
Refresh Cycle
HM5164160A/HM5165160A
-6
Symbol Min
-7
Min
5
Parameter
Max
—
Max
—
Unit Notes
CAS setup time (CBR refresh cycle) tCSR
CAS hold time (CBR refresh cycle) tCHR
WE setup time (CBR refresh cycle) tWRP
5
ns
ns
ns
ns
ns
21
22
10
0
—
10
0
—
—
—
WE hold time (CBR refresh cycle)
RAS precharge to CAS hold time
tWRH
tRPC
10
0
—
10
0
—
—
—
21
Fast Page Mode Cycle
HM5164160A/HM5165160A
-6
Symbol Min
-7
Parameter
Max
—
Min
45
—
Max
—
Unit Notes
Fast page mode cycle time
Fast page mode RAS pulse width
Access time from CAS precharge
tPC
40
—
—
35
ns
tRASP
tCPA
100000
35
100000
40
ns
ns
ns
16
—
9, 17, 22
RAS hold time from CAS precharge tCPRH
—
40
—
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HM5164160A Series, HM5165160A Series
Fast Page Mode Read-Modify-Write Cycle
HM5164160A/HM5165160A
-6
-7
Parameter
Symbol Min
Max
Min
96
Max
Unit Notes
Fast page mode read-modify-write tPRWC
cycle time
85
—
—
ns
WE delay time from CAS precharge tCPW
60
—
68
—
ns
14, 22
Refresh (HM5164160A Series)
Parameter
Symbol
tREF
tREF
Max
Unit
ms
Note
Refresh period
64
8192 cycles
8192 cycles
Refresh period (L-version)
TBD
ms
Refresh (HM5165160A Series)
Parameter
Symbol
tREF
Max
64
Unit
ms
Note
Refresh period
4096 cycles
4096 cycles
Refresh period (L-version)
tREF
128
ms
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HM5164160A Series, HM5165160A Series
Self Refresh Mode (L-version)
HM5165160AL
-6
-7
Parameter
Symbol Min
Max
—
Min
100
130
–50
Max
—
Unit Notes
RAS pulse width (Self refresh)
RAS precharge time (Self refresh)
CAS hold time (Self refresh)
tRASS
tRPS
tCHS
100
110
–50
µs
ns
ns
26
—
—
—
—
23
Notes: 1. AC measurements assume tT = 5 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW
tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
≥
15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE
leading edge in delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in fast page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.
UCAS and LCAS cannot be staggered within the same write/read cycles.
19. All the VCC and VSS pins shall be supplied with the same voltages.
20. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS.
22. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the later rising edge of UCAS or LCAS.
23. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS.
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HM5164160A Series, HM5165160A Series
24. tCP is determined by the time that both UCAS and LCAS are high.
25. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
26. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If tRASS ≥ 100 µs, then RAS
precharge time should use tRPS instead of tRP.
27. CBR burst refresh or 4096 cycles of distributed CBR refresh with 15.6 µs interval should be
executed within 64 ms immediately after exiting from and before entering into the self refresh
mode.
28. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
29. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ V ≤ VIL (max))
IN
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. However skew between
UCAS/LCAS are allowed under the following conditions.
1. Each of the UCAS/LCAS should satisfy the timing specifications individually.
2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS
Delayed write
UCAS
Early write
LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is
satisfied, fast page mode can be performed.
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HM5164160A Series, HM5165160A Series
RAS
UCAS
LCAS
t
UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
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HM5164160A Series, HM5165160A Series
Timing Waveforms*29
Read Cycle
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
UCAS
LCAS
tRAD
tRAL
tCAL
tCAH
tASR
tASC
tRAH
Row
Column
Address
tRRH
tRCS
tRCH
WE
tDZC
tCDD
High-Z
tOEA
Din
tDZO
tOED
OE
tOEZ
tOHO
tCAC
tAA
tOFF
tOH
tRAC
tCLZ
Dout
Dout
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HM5164160A Series, HM5165160A Series
Early Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
UCAS
LCAS
tASR tRAH
tASC
tCAH
Row
Column
Address
tWCS
tWCH
WE
tDS
tDH
Din
Din
High-Z*
Dout
t
t
(min)
WCS
WCS
*
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HM5164160A Series, HM5165160A Series
Delayed Write Cycle*20
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
UCAS
LCAS
tRAH
tASC
tASR
tCAH
Row
Column
Address
tCWL
tRWL
tWP
tRCS
WE
tDS
tDH
tDZC
High-Z
Din
Din
tOED
tDZO
tOEH
OE
tOEZ
tCLZ
High-Z
Dout
Invalid Dout
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HM5164160A Series, HM5165160A Series
Read-Modify-Write Cycle*20
tRWC
tRAS
tRP
RAS
tT
tRCD
tCAS
tCRP
UCAS
LCAS
tRAD
tRAH
tASC
tCAH
tASR
Address
Row
Column
tCWL
tCWD
tAWD
tRWD
tRCS
tRWL
tWP
WE
Din
OE
tDZC
tDH
tDS
High-Z
Din
tOED
tOEH
tDZO
tOEA
tCAC
tAA
tOEZ
tOHO
tRAC
High-Z
Dout
Dout
tCLZ
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HM5164160A Series, HM5165160A Series
RAS-Only Refresh Cycle
t
RC
t
t
RP
RAS
RAS
t
T
t
t
t
CRP
CRP
RPC
UCAS
LCAS
t
t
ASR
RAH
Row
Address
Dout
t
OFF
High-Z
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HM5164160A Series, HM5165160A Series
CAS-Before-RAS Refresh Cycle
t
RC
t
t
t
RP
RP
RAS
RAS
t
t
t
t
t
CRP
RPC
CSR
CHR
RPC
t
T
UCAS
LCAS
t
CP
t
t
t
WRH
CP
WRP
WE
Address
Dout
t
OFF
High-Z
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HM5164160A Series, HM5165160A Series
Hidden Refresh Cycle
t
t
t
RC
RC
RC
t
t
t
t
t
t
RP
RAS
RP
RAS
RP
RAS
RAS
t
T
t
t
t
CRP
RSH
CHR
t
RCD
UCAS
LCAS
t
t
RAL
RAD
t
t
t
t
CAH
ASR RAH
Row
ASC
Address
Column
t
RRH
t
RCS
t
RCH
WE
t
t
CDD
DZC
High-Z
Din
t
t
OED
DZO
t
OEA
OE
t
t
t
CAC
OEZ
t
AA
OHO
t
t
t
RAC
OFF
OH
t
CLZ
Dout
Dout
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HM5164160A Series, HM5165160A Series
Fast Page Mode Read Cycle
t
RASP
t
t
RP
CPRH
RAS
t
T
t
t
t
t
CSH
PC
RSH
t
CRP
t
t
t
t
t
RCD
CAS
CP
CAS
CAL
CP
CAS
UCAS
LCAS
t
t
RAL
CAL
t
t
t
RAD
CAL
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Address
Column 1
Column 2
Column N
t
t
t
t
RCS
RCS
RRH
RCH
t
t
t
t
t
t
RCS
DZC
RCH
CDD
RCH
CDD
WE
Din
OE
t
t
DZC
DZC
t
CDD
High-Z
High-Z
High-Z
t
t
t
t
t
t
OED
DZO
OED
DZO OED
DZO
t
t
t
CPA
RAC
CPA
t
t
t
t
t
t
OH
AA
OH
AA
OH
AA
t
OHO
t
t
OHO
OHO
t
t
t
OEA
OEA
OEA
t
t
CAC
t
t
t
t
t
CAC
CAC
CLZ
OFF
OFF
OEZ
OFF
OEZ
t
t
t
t
CLZ
t
OEZ
CLZ
Dout 1
Dout 2
Dout N
Dout
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HM5164160A Series, HM5165160A Series
Fast Page Mode Early Write Cycle
t
t
RP
RASP
RAS
t
T
t
t
t
RSH
CSH
PC
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
UCAS
LCAS
t
t
t
t
t
t
t
t
ASR RAH
ASC CAH
ASC CAH
ASC CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
WCH
WCS
WCH
WCS
WCH
WCS
WE
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
Din 1
Din 2
Din N
Din
High-Z*
Dout
t
t
(min)
WCS
*
WCS
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HM5164160A Series, HM5165160A Series
Fast Page Mode Delayed Write Cycle*20
t
RASP
t
RP
RAS
t
t
t
t
CP
CRP
T
CP
t
t
t
t
CSH
PC
RSH
CAS
t
t
t
CAS
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
ASR
ASC
t
ASC
t
ASC
t
t
RAH
CAH
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
CWL
CWL
t
CWL
t
RWL
t
t
RCS
RCS
RCS
WE
t
t
t
WP
WP
WP
t
t
t
t
t
t
t
DZC DS
DZC DS
DZC DS
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
DZO
DZO
DZO
OED
t
t
OED
OED
t
t
t
OEH
OEH
OEH
OE
t
t
t
CLZ
CLZ
CLZ
t
t
t
OEZ
OEZ
OEZ
High-Z
Dout
Invalid Dout
Invalid Dout
Invalid Dout
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HM5164160A Series, HM5165160A Series
Fast Page Mode Read-Modify-Write Cycle*20
t
RASP
t
RP
RAS
t
t
T
PRWC
t
t
RSH
CAS
t
t
t
CRP
CP
CP
t
t
t
CAS
RCD
CAS
UCAS
LCAS
t
RAD
t
t
t
t
ASC
t
CAH
ASR
ASC
RAH
ASC
t
t
t
CAH
CAH
Row
Column 1
Column 2
Column N
Address
t
t
t
t
t
t
t
t
t
RWD
AWD
CWL
t
CPW
AWD
CWL
t
CPW
AWD
CWL
t
RCS
RCS
RWL
t
t
t
CWD
CWD
CWD
WE
t
t
t
t
t
WP
t
DS
RCS
DZO
WP
DS
WP
t
t
t
DS
t
DZC
DZC
DZC
t
t
t
DH
DH
DH
Din
1
Din
2
Din
N
Din
t
t
t
OED
OED
OED
t
t
t
DZO
DZO
t
t
t
OEH
OEH
OEH
OE
t
t
t
OHO
OHO
OHO
t
t
t
t
t
t
OEA
CAC
OEA
CAC
OEA
CAC
t
t
t
AA
AA
AA
t
t
CPA
CPA
t
t
RAC
t
OEZ
t
t
OEZ
t
t
OEZ
CLZ
CLZ
CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
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HM5164160A Series, HM5165160A Series
Self Refresh Cycle (L-version)*26, 27, 28
t
t
t
RASS
RP
RPS
RAS
t
T
t
t
t
CRP
RPC
CP
t
CSR
t
CHS
UCAS
LCAS
t
t
WRH
WRP
WE
t
OFF
High-Z
Dout
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HM5164160A Series, HM5165160A Series
Package Dimensions
HM5164160AJ Series
HM5165160AJ Series (CP-50DA)
Preliminary
Unit: mm
20.95
21.38 Max
50
26
25
1
0.47
1.09 Max
0.80
0.10
9.40 ± 0.25
0.32 ± 0.08
0.30 ± 0.04
Hitachi Code
CP-50DA
Conforms
—
JEDEC
EIAJ
Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.2 g
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HM5164160A Series, HM5165160A Series
HM5164160ATT Series
HM5165160ATT/ALTT Series (TTP-50DB)
Unit: mm
20.95
21.35 Max
50
26
25
1
0.80
0.13
0.30 ± 0.10
0.28 ± 0.08
M
0.80
11.76 ± 0.20
0° – 5°
1.15 Max
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-50DB
—
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
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HM5164160A Series, HM5165160A Series
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
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HM5164160A Series, HM5165160A Series
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Tel: 415-589-8300
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
Revision Record
Rev. Date
Contents of Modification
Initial issue
Drawn by
S. Ikenaga
J. Kitano
Approved by
J. Kitano
0.0
0.1
Jun. 3, 1996
Jan. 22, 1997
Power dissipation
J. Kitano
TBD/540/468 mW to TBD/432/360 mW (max)
(HM5164160A Series)
TBD/684/612 mW to TBD/630/540 mW (max)
(HM5165160A Series)
DC Characteristics (HM5164160A Series)
ICC1(max): TBD/140/120 mA to TBD/120/100 mA
I
I
I
CC3(max): TBD/140/120 mA to TBD/120/100 mA
CC6(max): TBD/150/130 mA to TBD/140/120 mA
CC7(max): TBD/130/120 mA to TBD/100/90 mA
ILO test conditions: 0 V ≤ Vout ≤ VCC + 0.3 to
0 V ≤ Vout ≤ VCC
DC Characteristics (HM5165160A Series)
ICC1(max): TBD/190/170 mA to TBD/175/150 mA
I
I
I
CC3(max): TBD/190/170 mA to TBD/175/150 mA
CC6(max): TBD/150/130 mA to TBD/140/120 mA
CC7(max): TBD/130/120 mA to TBD/120/110 mA
ILO test conditions: 0 V ≤ Vout ≤ VCC + 0.3 to
0 V ≤ Vout ≤ VCC
1.0
Aug. 22, 1997
Deletion of preliminary
M. Tsunozaki M. Saeki
Correct errors (HM5164160A Series)
tREF (L-version):128 ms to TBD (for suspension of
L-version),
4096 cycles to 8192 cycles
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HM5164160A Series, HM5165160A Series
2.0
Nov. 25, 1997
Deletion of HM5164/65160A/AL-5 Series
Deletion of HM5164160AL Series
Deletion of HM5165160ALTT-7
Power dissipation
Standby mode (L-version): TBD to 1.08 mW
DC Characteristics (HM5165160A Series)
ICC2 (L-version): TBD/TBD/TBD to 300/300 µA
I
I
CC10 (L-version): TBD/TBD/TBD to 650/650 µA
CC11 (L-version): TBD/TBD/TBD to 500/500 µA
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