HMS1M32Z8-12 [HANBIT]
SRAM;
| 型号： | HMS1M32Z8-12 |
| 厂家： | 
HANBIT ELECTRONICS CO.,LTD |
| 描述： | SRAM 静态存储器 |
| 文件： | 总9页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HANBit
HMS1M32M8G/Z8
H A N
SRAM MODULE 4Mbyte(1M x 32-Bit)
B I T
HMS1M32M8G, HMS1M32Z8
Part No.
GENERAL DESCRIPTION
The HMS1M32M8G/Z8 is a high-speed static random access memory (SRAM) module containing 1,048,576
words organized in a x32-bit configuration. The module consists of eight 1M x 4 SRAMs mounted on a 72-pin,
double-sided, FR4-printed circuit board.
PD0 to PD3 identify the module’s density allowing interchangeable use of alternate density, industry- standard
modules. Eight chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module’s 4 bytes
independently. Output enable(/OE) and write enable(/WE) can set the memory input and output.
Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW.
Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW.
For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be
powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible.
FEATURES
Access times : 10, 12, 15, 17 and 20ns
PIN ASSIGNMENT
1
3
5
7
9
NC
PD2
Vss
PD1
DQ8
2
4
6
8
NC
PD3
PD0
DQ0
DQ1
DQ2
DQ3
Vcc
High-density 4MByte design
High-reliability, high-speed design
Single + 5V ±10% power supply
Easy memory expansion /CE and /OE functions
All inputs and outputs are TTL-compatible
Industry-standard pinout
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
11 DQ9
13 DQ10
15 DQ11
17 A0
19 A1
21 A2
A7
A8
A9
FR4-PCB design
23 DQ12
25 DQ13
27 DQ14
29 DQ15
31 Vss
33 A15
35 / CE2
37 / CE4
39 A17
41 / OE
43 DQ24
45 DQ25
47 DQ26
49 DQ27
51 A3
53 A4
55 A5
57 Vcc
59 A6
61 DQ28
63 DQ29
65 DQ30
67 DQ31
69 A18
71 NC
DQ4
DQ5
DQ6
DQ7
/ WE
A14
/ CE1
/ CE3
A16
Low profile 72-pin
Part identification
- HMS1M32M8G : SIMM design, Gold Plate Lead
- HMS1M32Z8 : ZIP design
→ The both are pin-to-pin compatible
Vss
OPTIONS
Timing
MARKING
DQ16
DQ17
DQ18
DQ19
A10
A11
A12
A13
DQ20
DQ21
DQ22
DQ23
Vss
10ns access
12ns access
15ns access
17ns access
20ns access
Packages
-10
-12
-15
-17
-20
PD0 - Vss
PD1 - Open
PD2 - Vss
PD3 - Open
72-Pin ZIP
TOP VIEW
A19
NC
72-pin SIMM
72-pin ZIP
M
Z
1
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8G/Z8
FUNCTIONAL BLOCK DIAGRAM
32
DQ0 - DQ31
20
A0 - A19
A0-19
A0-19
DQ 0-3
DQ 4-7
/WE
/WE
/OE
U1
U5
/OE
/CE
/CE
/CE1
A0-19
A0-19
DQ 8-11
DQ12-15
/WE
/WE
/OE
U2
U6
/OE
/CE
/CE
/CE2
A0-19
/WE
A0-19
/WE
DQ16-19
DQ20-23
/OE
/OE
U3
U7
/CE
/CE
/CE3
A0-19
A0-19
DQ24-27
DQ28-31
/WE
/WE
/OE
/WE
/OE
U4
U8
/OE
/CE
/CE
/CE4
TRUTH TABLE
MODE
STANDBY
NOT SELECTED
READ
/OE
X
/CE
/WE
X
OUTPUT
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
H
L
L
L
HIGH-Z
HIGH-Z
DOUT
H
H
L
H
WRITE
X
L
DIN
2
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8G/Z8
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VIN,OUT
VCC
RATING
-0.5V to +7.0V
-0.5V to +7.0V
8W
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Power Dissipation
PD
o
o
Storage Temperature
TSTG
-65 C to +150 C
o
o
Operating Temperature
TA
0 C to +70 C
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
o
RECOMMENDED DC OPERATING CONDITIONS
( T =0 to 70 C )
A
PARAMETER
SYMBOL
MIN
4.5V
0
TYP.
MAX
5.5V
Supply Voltage
VCC
5.0V
Ground
VSS
0
-
0
Input High Voltage
Input Low Voltage
VIH
2.2
Vcc+0.5V**
0.8V
VIL
-0.5*
-
*
V (Min.) = -2.0V ac (Pulse Width 10ns) for I 20 mA
≤ ≤
IL
V (Min.) = Vcc+2.0V ac (Pulse Width 10ns) for I 20 mA
**
≤
≤
IH
o
o
DC AND OPERATING CHARACTERISTICS (1)(0 C
T
70 C ; Vcc = 5V 0.5V )
≤
≤
±
A
SYMBO
L
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
Input Leakage Current
Output Leakage Current
VIN =Vss to Vcc
ILI
-2
2
A
µ
/CE=VIH or /OE =VIH or /WE=VIL
IL0
-2
2
A
µ
VOUT=Vss to VCC
Output High Voltage
Output Low Voltage
IOH = -4.0Ma
IOL = 8.0Ma
VOH
VOL
2.4
V
0.4
V
o
* Vcc=5.0V, Temp=25 C
DC AND OPERATING CHARACTERISTICS (2)
MAX
-12
DESCRIPTION
CONDITIONS
Min. Cycle, 100% Duty
/CE=VIL, VIN=VIH or VIL,
IOUT=0mA
SYMBOL
-10
-15
UNIT
Power Supply
Current: Operating
lCC
195
190
185
mA
Min. Cycle, /CE=VIH
lSB
50
10
50
10
50
10
mA
mA
Power Supply
Current :Standby
f=0MHZ, /CE V -0.2V,
≥
CC
lSB1
VIN V -0.2V or V 0.2V
≥
≤
IN
CC
3
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8G/Z8
CAPACITANCE
DESCRIPTION
TEST CONDITIONS
VI/O=0V
SYMBOL
CI/O
MAX
UNIT
pF
Input /Output Capacitance
Input Capacitance
8
7
VIN=0V
CIN
pF
*
: Capacitance is sampled and not 100% tested
NOTE
o
o
AC CHARACTERISTICS (0 C
TEST CONDITIONS
T
70 C ; Vcc = 5V 0.5V, unless otherwise specified)
≤
≤
±
A
PARAMETER
VALUE
0 to 3V
3ns
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
1.5V
See below
Output Load (B)
Output Load (A)
VL=1.5V
for tHZ, tLZ, tWHZ, tOW, tOLZ
+5.0V
& tOHZ
50
Ω
480
Ω
DOUT
DOUT
Z0=50
Ω
255
Ω
30pF
5pF*
READ CYCLE
-10
-12
-15
PARAMETER
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Read Cycle Time
tRC
tAA
tCO
tOE
tLZ
10
-
-
10
10
5
12
-
-
12
12
6
15
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
15
15
7
Address Access Time
Chip Select to Output
-
-
-
Output Enable to Output
-
-
-
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Output Disable to High-Z Output
Chip Disable to High-Z Output
Output Hold from Address Change
Chip Select to Power Up Time
Chip Select to Power Down Time
3
0
0
0
3
0
-
-
3
0
0
0
3
0
-
3
0
0
0
3
0
-
-
tOLZ
tOHZ
tHZ
tOH
tPU
-
-
-
5
6
7
5
6
7
-
-
-
-
-
-
tPD
10
12
15
4
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8G/Z8
WRITE CYCLE
-10
-12
-15
PARAMETER
SYMBOL
UNIT
MIN
10
7
MAX
MIN
12
8
MAX
MIN
15
10
0
MAX
Write Cycle Time
tWC
tCW
tAS
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
7
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
6
-
-
-
Chip Select to End of Write
Address Set-up Time
0
0
Address Valid to End of Write
Write Pulse Width (/OE High)
Write Recovery Time
tAW
tWP
tWR
tWHZ
tDW
tDH
7
8
10
10
0
7
8
0
0
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
0
0
0
5
6
7
0
0
0
End of Write to Output Low-Z
tOW
3
3
3
TIMING DIAGRAMS
( Address Controlled)( /CE =/OE = V , /WE = V )
TIMING WAVEFORM OF READ CYCLE
IL
IH
tRC
Address
tAA
tOH
Data out
Previous Data Valid
Data Valid
( /WE = V
)
TIMING WAVEFORM OF READ CYCLE
IH
tRC
Address
tHZ(3,4,5)
tAA
tCO
/CE
/OE
tLZ(4,5)
tOHZ
tOE
tOH
tOLZ
High-Z
Data Out
Data Valid
tPD
tPU
50%
lCC
lSB
Vcc Supply
Current
50%
5
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8G/Z8
(Read Cycle)
Notes
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH
or VOL levels.
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device
to device.
5. Transition is measured 200mV from steady state voltage with Load (B). This parameter is sampled and not 100%
±
tested.
6. Device is continuously selected with /CE = VIL.
7. Address valid prior to coincident with /CE transition low.
(/OE = Clock )
TIMING WAVEFORM OF WRITE CYCLE
tWC
Address
/OE
tAW
tWR(5)
tCW(3)
/CE
tAS(4)
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tOHZ
tOW
Data Out
High-Z
(/OE Low Fixed)
TIMING WAVEFORM OF WRITE CYCLE
tWC
Address
tAW
tWR(5)
tCW(3)
/CE
tAS(4)
tOH
tWP(2)
/WE
tDW
tDH
High-Z
Data In
Data Valid
tOW
tWHZ(6,7)
(10)
(9)
High-Z(8)
Data Out
6
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8G/Z8
(Write Cycle)
Notes
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of /CE going low to the end of write.
4. tAS is measured from the address valid to the beginning of wirte.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of
opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. DOUT is the read data of the new address.
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
H
/WE
X*
H
/OE
X
MODE
Not Select
Output Disable
Read
I/O PIN
High-Z
High-Z
DOUT
SUPPLY CURRENT
I SB, I SB1
ICC
L
H
L
H
L
ICC
L
L
X
Write
DIN
ICC
Note: X means Don't Care
7
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8G/Z8
PACKAGING DIMMENSIONS
SIMM Design
1 0 8 .2 0 m m
3 .1 8 m m
TYP(2 x)
1 6 m m
6 .3 5 m m
7 2
1
2 .0 3 m m
1 .0 2 m m
6 .3 5 m m
1 .2 7 m m
3 .3 4 m m
9 5 .2 5 m m
2 .5 4 m m
0 .2 5 m m MAX
MIN
1 .2 9 m m
Gold : 1 .0 4
±0 .1 0 m m
1 .2 7
Sold er : 0 .9 1 4 ±0 .1 0 m m
(Solder & Gold Plating Lead)
ZIP Design
9 6 .5 m m
CUT 1 .5 m m
1 9 m m
7 2
1
6 m m
1 m m
1 m m
4 6 m m
2 .5 4 m m
9 7 .7 9 m m
1 .2 9 ±0 .0 8 m m
2 .5 m m
8
HANBit Electronics Co.,Ltd.
HANBit
HMS1M32M8G/Z8
ODERING INFORMATION
1
2
3
4
5
6
7
8
H M S 1 M 3 2 M8 G -1 5
15ns Access Time
HANBit
Component, Gold
SIMM
Memory
Modules
x32bit
SRAM
1M
1. - Product Line Identifier
HANBit ------------------------------------------------------- H
2. - Memory Modules
3. - SRAM
4. - Depth : 1M
5. - Width : x 32bit
6. - Package Code
SIMM ------------------------------------------------------- M
ZIP
------------------------------------------------------- Z
7. - Number of Memory Components---8 , G—Gold Plate Lead
8. - Access time
10 ----------------------------------------------------------- 10ns
12 ----------------------------------------------------------- 12ns
15 ----------------------------------------------------------- 15ns
17 ----------------------------------------------------------- 17ns
20 ----------------------------------------------------------- 20ns
9
HANBit Electronics Co.,Ltd.
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