GS880F36TT-18I [GSI]
Standard SRAM, 512KX18, 18ns, CMOS, PQFP100;型号: | GS880F36TT-18I |
厂家: | GSI TECHNOLOGY |
描述: | Standard SRAM, 512KX18, 18ns, CMOS, PQFP100 时钟 静态存储器 内存集成电路 |
文件: | 总22页 (文件大小:310K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary
GS880F18/36T-11/11.5/12/14/18
100-Pin TQFP
Commercial Temp
Industrial Temp
11 ns–18 ns
3.3 V VDD
3.3 V and 2.5 V I/O
512K x 18, 256K x 36
8Mb Sync Burst SRAMs
RAMS should be designed with V connected to the FT pin
Features
SS
location to ensure the broadest access to multiple vendor
sources. Boards designed with FT pin pads tied low may be
stuffed with GSI’s Pipeline/Flow Through-configurable Burst
RAMS or any vendor’s Flow Through or configurable Burst
SRAM. Bumps designed with the FT pin location tied high or
floating must employ a non-configurable Flow Through Burst
RAM, like this RAM, to achieve flow through functionality.
• Flow Through mode operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
• Automatic power-down for portable applications
• 100-lead TQFP package
-11
11 ns 11.5 ns 12 ns
15 ns 15 ns 15 ns
-11.5
-12
-14
-18
Sleep Mode
Flow
Through
2-1-1-1
t
14 ns
15 ns
18 ns
20 ns
KQ
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
tCycle
180 mA 180 mA 180 mA 175 mA 165 mA
I
DD
Core and Interface Voltages
The GS880F18/36T operates on a 3.3 V power supply, and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
Functional Description
output power (V
) pins are used to decouple output noise
DDQ
Applications
from the internal circuit.
The GS880F18/36T is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin
option (pin 14 on TQFP). Board sites for flow through Burst
Rev: 1.06 9/2000
1/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
GS880F18 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A18
NC
NC
V
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
V
4
DDQ
DDQ
V
V
5
SS
SS
NC
6
NC
NC
DQB1
DQB2
DQA9
DQA8
DQA7
7
8
9
512K x 18
Top View
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
DQA6
DQA5
DQB3
DQB4
NC
V
SS
NC
V
DD
V
NC
DD
ZZ
DQA4
DQA3
V
SS
DQB5
DQB6
V
V
DDQ
DDQ
V
V
SS
SS
DQA2
DQA1
NC
DQB7
DQB8
DQB9
NC
NC
V
V
SS
SS
V
V
DDQ
DDQ
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.06 9/2000
2/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
GS880F36 100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQB9
DQB8
DQB7
DQC9
DQC8
DQC7
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
V
V
4
DDQ
DDQ
V
V
5
SS
SS
DQB6
DQB5
DQB4
DQB3
6
DQC6
DQC5
DQC4
DQC3
7
8
9
256K x 36
Top View
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
DQB2
DQB1
DQC2
DQC1
V
NC
SS
NC
V
DD
V
NC
DD
ZZ
DQA1
DQA2
V
SS
DQD1
DQD2
V
V
DDQ
DDQ
V
V
SS
SS
DQA3
DQA4
DQA5
DQA6
DQD3
DQD4
DQD5
DQD6
V
V
SS
SS
V
V
DDQ
DDQ
DQA7
DQA8
DQA9
DQD7
DQD8
DQD9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.06 9/2000
3/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
TQFP Pin Description
Typ
e
Pin Location
Symbol
Description
37, 36
A0, A1
A2–A17
A18
I
I
I
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43
Address Inputs
Address Inputs
80
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
DQA1–DQA8
DQB1–DQB8
DQC1–DQC8
DQD1–DQD8
I/O
Data Input and Output pins (x36 Version)
18, 19, 22, 23, 24, 25, 28, 29
DQA9, DQB9,
DQC9, DQD9
51, 80, 1, 30
I/O
I/O
Data Input and Output pins
Data Input and Output pins
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1–DQA9
DQB1–DQB9
51, 52, 53, 56, 57
75, 78, 79,
NC
—
No Connect
1, 2, 3, 6, 7
25, 28, 29, 30
87
93, 94
95, 96
95, 96
89
BW
BA, BB
BC, BD
NC
I
I
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Byte Write Enable for DQC, DQD Data I/Os; active low (x36 Version)
No Connect (x18 Version)
I
—
I
CK
Clock Input Signal; active high
88
GW
I
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
98, 92
97
E1, E3
E2
I
I
Chip Enable; active high
86
G
I
Output Enable; active low
83
ADV
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
84, 85
64
ADSP, ADSC
ZZ
I
I
31
LBO
I
Linear Burst Order mode; active low
Core power supply
V
15, 41, 65, 91
I
DD
V
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
14, 16, 38, 39, 42, 66
I
I
I/O and Core Ground
Output driver power supply
No Connect.
SS
V
DDQ
NC
—
Rev: 1.06 9/2000
4/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
GS880F18/36 Block Diagram
Register
A0–An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
Register
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
0
G
1
DQx0–DQx9
Power Down
Control
ZZ
Note: Only x36 version shown for simplicity.
Rev: 1.06 9/2000
5/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Mode Pin Functions
Mode Name
Pin Name
State
L
Function
Linear Burst
Interleaved Burst
Active
Burst Order Control
LBO
H or NC
L or NC
H
Power Down Control
ZZ
Standby, I = I
DD SB
Note:
There is a pull-up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
B
A
B
B
B
C
B
D
Notes
1
X
X
X
X
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the and x36 version.
Rev: 1.06 9/2000
6/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Synchronous Truth Table
Operation
State
2
Address
Used
E2
3
4
Diagram
E1
ADSP ADSC ADV
W
DQ
(x36only)
5
Key
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
None
None
X
X
H
L
X
F
F
T
T
T
X
X
X
X
X
X
X
X
X
L
L
X
L
X
X
X
X
X
X
L
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
None
X
L
L
H
L
High-Z
External
External
External
Next
R
X
L
Q
Q
D
Q
Q
D
D
Q
Q
D
D
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
1. X = Don’t Care, H = High, L = Low.
2. For x36 Version, E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.06 9/2000
7/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
CR
First Write
First Read
CW
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1E2) and Write (BA, BB, BC, BD, BW, and GW) control inputs,
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.06 9/2000
8/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
CR
First Write
First Read
CR
CW
CW
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.06 9/2000
9/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
DD
DD
V
Voltage in V
Pins
–0.5 to V
V
DDQ
DDQ
DD
V
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
V
CK
V
–0.5 to V
+0.5 (£ 4.6 V max.)
DDQ
V
I/O
V
–0.5 to V +0.5 (£ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
—
Max.
Unit
V
Notes
V
3.6
DD
V
V
I/O Supply Voltage
V
1
2
2
3
3
DDQ
DD
V
V
+0.3
DD
Input High Voltage
V
IH
V
Input Low Voltage
–0.3
0
—
0.8
V
IL
T
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
70
85
°C
°C
A
T
–40
25
A
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V £ V
£ 2.375 V
DDQ
(i.e., 2.5 V I/O) and 3.6 V £ V
£ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case.
DDQ
2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be –2 V > Vi < V +2 V with a pulse width not to exceed 20% tKC.
DD
Rev: 1.06 9/2000
10/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 2.0 V
50%
VSS
50%
VDD
VSS – 2.0 V
20% tKC
VIL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 3.3 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V = 0 V
IN
Input Capacitance
4
6
5
7
IN
C
V
= 0 V
Input/Output Capacitance
pF
I/O
OUT
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
Max
40
Unit
Notes
1,2
R
single
four
—
°C/W
°C/W
°C/W
QJA
R
24
1,2
QJA
R
9
3
QJC
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.06 9/2000
11/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t , t , t and t
LZ HZ OLZ
OHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225W
DQ
*
50W
VT = 1.25 V
30pF
*
225W
5pF
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
³ V ³ V
IN
–1 uA
–1 uA
1 uA
300 uA
DD
IH
IH
I
ZZ Input Current
INZZ
0 V £ V £ V
IN
V
³ V ³ V
IN
–300 uA
–1 uA
1 uA
1 uA
DD
IL
I
Mode Pin Input Current
Output Leakage Current
INM
0 V £ V £ V
IN
IL
Output Disable,
V
I
–1 uA
1 uA
OL
= 0 to V
OUT
DD
V
I
I
= – mA, V
= – mA, V
= 2.375 V
Output High Voltage
Output High Voltage
Output Low Voltage
1.7 V
2.4 V
—
—
—
OH
OH
OH
DDQ
DDQ
V
= 3.135 V
OH
V
I
= mA
0.4 V
OL
OL
Rev: 1.06 9/2000
12/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Operating Currents
-11
-11.5
-12
-14
-18
Parameter
Test Conditions
Symbol
Unit
0 to -40to 0 to -40to 0 to -40 to 0 to -40to 0 to -40to
70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C 70°C 85°C
Device Selected;
All other inputs
³ V or £ V
I
Operating
Current
DD
180
190
180
190
180
190
175
185
165
175
mA
Flow-Thru
IH
IL
Output open
I
Standby
Current
SB
ZZ ³ V °– 0.2 V
30
65
40
75
30
65
40
75
30
65
40
75
30
55
40
65
30
50
40
60
mA
mA
DD
Flow-Thru
Device Deselected;
All other inputs
I
Deselect
Current
DD
Flow-Thru
³ V or £ V
IH
IL
Rev: 1.06 9/2000
13/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
AC Electrical Characteristics
-11
-11.5
-12
-14
-18
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
tKC
tKQ
15.0
—
—
11.0
—
15.0
—
—
11.5
—
15.0
—
—
12.0
—
15.0
—
—
14.0
—
20
—
—
18
—
—
ns
ns
ns
ns
Flow-
Thru
tKQX
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
1
—
—
—
—
tLZ
Clock HIGH Time
Clock LOW Time
tKH
tKL
1.7
2
—
—
1.7
2
—
—
2
—
—
2
—
—
2.3
2.5
1.5
—
—
ns
ns
ns
2.2
1.5
2.2
1.5
1
Clock to Output in High-Z
1.5
4.0
1.5
4.2
4.5
4.5
4.8
tHZ
G to Output Valid
tOE
—
0
4.0
—
—
0
4.2
—
—
0
4.5
—
—
0
4.5
—
—
0
4.8
—
ns
ns
1
G to output in Low-Z
tOLZ
1
G to output in High-Z
Setup time
—
1.5
0.5
5
4.0
—
—
—
—
2.0
0.5
5
4.2
—
—
—
—
2.0
0.5
5
4.5
—
—
—
—
2.0
0.5
5
4.5
—
—
—
—
2.0
0.5
5
4.8
—
—
—
ns
ns
ns
ns
tOHZ
tS
Hold time
tH
2
ZZ setup time
tZZS
tZZH
2
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
tZZR
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.06 9/2000
14/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tH
tS
ADSP is blocked by E inactive
tKC
tKL
tKH
ADSP
tS tH
ADSC initiated write
ADSC
tH
tS
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0–An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA–BD
E1
tS
tH
tH
E1 masks ADSP
tS
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
Write specified byte for 2A and all bytes for 2B, 2c& 2D
tH
Hi-Z
D2C
D2D
D3A
DQA–DQD
D1A
D2A
D2B
Rev: 1.06 9/2000
15/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Flow Through Read-Write Cycle Timing
Single Write
tKC
Burst Read
Single Read
CK
tH
tS
ADSP is blocked by E inactive
tKH tKL
tS
ADSP
ADSC
tH
ADSC initiated read
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0–An
tS
tS
tH
GW
tS
tH
BW
tS
tH
BA–BD
WR1
tS
tS
tS
tH
tH
tH
E1 masks ADSP
E1
E2 and E3 only sampled with ADSP and ADSC
E2
Deselected with E3
E3
tOHZ
tOE
G
tS
D1A
tH
tKQ
Hi-Z
DQA–DQD
Q1A
Q2A
Q2A
Q2B
Q2c
Q2D
Burst wrap around to it’s initial state
Rev: 1.06 9/2000
16/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tKH
tS
tS
tH
ADSP is blocked by E inactive
tKC
ADSP
ADSC
ADV
tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
E1
tH
tS
E1 masks ADSP
tH
tH
tS
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tOHZ
tOE
G
tKQX
tKQX
tOLZ
Q2B
Q2C
Q3A
Q2A
Q1A
Q2D
DQA–DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 1.06 9/2000
17/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Rev: 1.06 9/2000
18/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Output Driver Characteristics
120.0
100.0
Pull Down Drivers
80.0
60.0
40.0
VD D Q
20.0
I O u t
0.0
VO u t
VS S
-20.0
-40.0
-60.0
-80.0
-100.0
-120.0
-140.0
Pull Up Drivers
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD HD
3.3V PD HD
3.1V PD HD
3.1V PU HD
3.3V PU HD
3.6V PU HD
Rev: 1.06 9/2000
19/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
TQFP Package Drawing
q
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
—
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
—
0.10
7°
q
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 1.06 9/2000
20/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
Notes:
GS880F18T-11
GS880F18T-11.5
GS880F18T-12
GS880F18T-14
GS880F18T-18
GS880F36T-11
GS880F36T--11.5
GS880F36T-12
GS880F36T-14
GS880F36T-18
GS880F18T-11I
GS880F18T--11.5I
GS880F18T-12I
GS880F18T-14I
GS880F18T-18I
GS880F36T-11I
GS880F36T--11.5I
GS880F36T-12I
GS880F36T-14I
GS880F36T-18I
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
11
11.5
12
C
C
C
C
C
C
C
C
C
C
I
14
18
11
11.5
12
14
18
11
11.5
12
I
I
14
I
18
I
11
I
11.5
12
I
I
14
I
18
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880LF18TT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.06 9/2000
21/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page;Revisions;Reason
New
• First Release of 880 F.
GS880F18/361.00 11/1999J
Content
• Changed Flow Through Read-Write Cycle Timing Diagram for
accuracy.
GS880F18/36T1.00
K880F18/36T1.02 1/2000L
• Changed order of TQFP Address Inputs to match pinout.
• Changed order of TQFP DATA Input and Output pins to
match pinout.
Content
• New GSI Logo.
• Changed all speed bin information (headings, references,
tables, ordering info..) to reflect 14 -10Mhz
GS880F1836T Rev. 1.02 1/
2000L;
GS880F1836T Rev. 1.03 3/
2000N
Content
Content
• Corrections to AC Electrical Characteristics Table -
GS880F1836T Rev. 1.03 1/
2000N;
GS880F1836T Rev. 1.04 3/
2000O
• Removed 150 MHz speed bin
• Added 18 ns speed bin
• Updated format to comply with Technical Publications
standards
GS880F1836T Rev. 1.04 3/
2000O; 880F1836_r1_05
Content/Format
Content
• Updated Capitance table—removed Input row and changed
Output row to I/O
880F18_r1_05;
880F18_r1_06
Rev: 1.06 9/2000
22/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
相关型号:
©2020 ICPDF网 联系我们和版权申明