GS880L32T-100I [GSI]
Standard SRAM, 256KX32, 11.5ns, CMOS, PQFP100;
| 型号： | GS880L32T-100I |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Standard SRAM, 256KX32, 11.5ns, CMOS, PQFP100 静态存储器 |
| 文件： | 总26页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS880L32T-100
100 Pin TQFP
Commercial Temp
Industrial Temp
100Mhz
3.3V VDD
3.3V & 2.5V I/O
256K x 32
8Mb Sync Burst SRAMs
Flow Through / Pipeline Reads
Features
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation
• 3.3V +10%/-5% Core power supply.
The function of the Data Output register can be controlled by the user
via the FT mode pin (Pin 14). Holding the FT mode pin low places the
RAM in Flow through mode, causing output data to bypass the Data
Output Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
SCD Pipelined Reads
The GS880L32T is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available. SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
• Automatic power-down for portable applications.
• 100-lead TQFP package
Byte Write and Global Write
-100
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Pipeline
3-1-1-1
tCycle
10ns
4.5ns
210mA
t
KQ
DD
I
Sleep Mode
Flow Through
2-1-1-1
t
12ns
15ns
150mA
KQ
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
tCycle
I
DD
Core and Interface Voltages
The GS880L32T operates on a 3.3V power supply and all inputs/
Functional Description
outputs are 3.3V and 2.5V compatible. Separate output power (V
)
Applications
DDQ
pins are used to de-couple output noise from the internal circuit.
The GS880L32T is a 8,388,608 bit high performance synchronous
SRAM with a 2 bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPU’s, the device now finds application in synchronous
SRAM applications ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/O’s, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive edge triggered
clock input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Rev: 1.02 3/2000
1/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
GS880L32 100 Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQB8
DQB7
VDDQ
VSS
DQC8
DQC7
VDDQ
2
3
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
5
DQB6
DQB5
DQB4
DQB3
VSS
6
7
8
9
256K x 32
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQB2
DQB1
VSS
VDDQ
DQC2
DQC1
FT
VDD
NC
NC
VDD
ZZ
DQA1
DQA2
VDDQ
VSS
VSS
DQD1
DQD2
VDDQ
VSS
DQD3
DQD4
DQD5
DQD6
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
NC
VDDQ
DQD7
DQD8
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.02 3/2000
2/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
TQFP Pin Description
Pin Location
Symbol
Type
Description
37, 36
A0, A1
I
Address field LSB’s and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
A2-17
I
I
Address Inputs
Address Inputs
80
A18
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
DQA1-DQA8
DQB1-DQB8
DQC1-DQC8
DQD1-DQD8
I/O
Data Input and Output pins.
18, 19, 22, 23, 24, 25, 28, 29
DQA9, DQB9,
DQC9, DQD9
51, 80, 1, 30
51, 80, 1, 30
I/O
-
Data Input and Output pins.
No Connect
NC
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
DQA1-DQA9
DQB1- DQB9
I/O
Data Input and Output pins.
51, 52, 53, 56, 57
75, 78, 79,
NC
-
No Connect
1, 2, 3, 6, 7
25, 28, 29, 30
87
BW
BA, BB
BC, BD
CK
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write. Writes all enabled bytes. Active Low.
Byte Write Enable for DQA, DQB Data I/O’s. Active Low.
Byte Write Enable for DQC, DQD Data I/O’s. Active Low.
Clock Input Signal. Active High.
93, 94
95, 96
89
88
GW
Global Write Enable. Writes all bytes. Active Low.
Chip Enable. Active Low.
98, 92
E1, E3
E2
97
Chip Enable. Active High.
86
G
Output Enable. Active Low.
83
ADV
Burst address counter advance enable. Active Low.
Address Strobe (Processor, Cache Controller). Active Low.
Sleep Mode control. Active High.
84, 85
ADSP, ADSC
ZZ
64
14
31
FT
Flow Through or Pipeline mode. Active Low.
Linear Burst Order mode. Active Low.
Core power supply.
LBO
V
15, 41, 65, 91
DD
V
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
16, 38, 39, 42, 66
I
I
I/O and Core Ground.
Output driver power supply.
No Connect.
SS
V
DDQ
NC
-
Rev: 1.02 3/2000
3/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
GS880L32 Block Diagram
Register
A0-An
D
Q
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
Load
A
LBO
ADV
Memory
Array
CK
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
32
32
Register
D
Q
BB
BC
BD
4
Register
D
Q
Register
D
Q
Register
D
Q
Register
E1
E2
E3
D
Q
Register
D
Q
FT
G
DQx0-DQx8
Power Down
Control
ZZ
Rev: 1.02 3/2000
4/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Mode Pin Functions
Mode Name
Pin Name State
Function
Linear Burst
Interleaved Burst
Active
L
LBO
Burst Order Control
H or NC
L or NC
Power Down Control
Note:
ZZ
Standby, I = I
H
DD SB
There pull up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in
the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
B
A
B
B
B
C
B
D
Notes
1
X
X
X
X
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Note:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 1.02 3/2000
5/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Synchronous Truth Table
State
2
Address
Used
E2
3
4
Diagram
Operation
E1
ADSP ADSC ADV
W
DQ
(x36only)
5
Key
Deselect Cycle, Power
Down
None
None
None
X
X
X
H
L
X
F
F
X
L
L
X
L
X
X
X
X
X
X
High-Z
High-Z
High-Z
Deselect Cycle, Power Down
Deselect Cycle, Power
Down
L
H
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Note:
External
External
External
Next
R
R
L
L
T
T
T
X
X
X
X
X
X
X
X
L
H
H
H
X
H
X
H
X
H
X
X
L
X
X
X
L
X
F
T
F
F
T
T
F
F
T
T
Q
Q
D
Q
Q
D
D
Q
Q
D
D
W
L
L
CR
CR
CW
CW
X
H
X
H
X
H
X
H
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
1. X = Don’t Care, H = High, L = Low.
2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active driv-
ers (shown as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to
accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items
above.
Rev: 1.02 3/2000
6/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.
2. The upper portion of the diagram assumes active use of only the Enable (E1E2) and Write (BA, BB, BC, BD, BW and GW) control inputs
and that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes
ADSP is tied high and ADV is tied low.
Rev: 1.02 3/2000
7/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.02 3/2000
8/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
DD
-0.5 to 4.6
DD
V
Voltage in V
Pins
-0.5 to V
V
DDQ
DDQ
DD
V
Voltage on Clock Input Pin
Voltage on I/O Pins
-0.5 to 6
V
CK
-0.5 to V +0.5 (£ 4.6 V
DDQ
V
V
I/O
max.)
V
I
-0.5 to V +0.5 (£ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IN
DD
+/- 20
+/- 20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
T
-55 to 125
-55 to 125
C
STG
o
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
---
Max.
Unit
V
Notes
V
3.6
DD
V
V
I/O Supply Voltage
V
1
2
2
3
3
DDQ
DD
V
V +0.3
DD
Input High Voltage
V
IH
V
Input Low Voltage
-0.3
0
---
0.8
V
IL
T
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
70
85
°C
°C
A
T
-40
25
A
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V £ VDDQ £ 2.375V (i.e. 2.5V I/O)
and 3.6V £ VDDQ £ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < V +2V with a pulse width not to exceed 20% tKC.
DD
Rev: 1.02 3/2000
9/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD+-2.0V
50%
VSS
50%
VDD
VSS-2.0V
20% tKC
VIL
Capacitance
o
(T =25 C, f=1MHZ, V =3.3V)
A
DD
Parameter
Control Input Capacitance
Input Capacitance
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
3
4
6
4
5
7
I
V
=3.3V
DD
C
V =0V
IN
pF
IN
V
=0V
OUT
C
Output Capacitance
pF
OUT
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
Max
40
Unit
Notes
1,2
R
single
four
°C/W
°C/W
°C/W
QJA
R
24
1,2
QJA
R
9
3
QJC
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Rev: 1.02 3/2000
10/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3V
0.2V
Input slew rate
1V/ns
Input reference level
Output reference level
Output load
1.25V
1.25V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t , t , t and t
.
OHZ
LZ HZ OLZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5V
Output Load 1
DQ
225W
225W
DQ
*
50W
VT=1.25V
30pF
*
5pF
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Symb
Parameter
ol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
-1uA
1uA
IL
V
³ V ³ V
-1uA
-1uA
1uA
300uA
DD
IN
IH
I
ZZ Input Current
INZZ
0V £ V £ V
IN
IH
V
³ V ³ V
-300uA
-1uA
1uA
1uA
DD
IN
IL
I
Mode Pin Input Current
Output Leakage Current
INM
0V £ V £ V
IN
IL
Output Disable,
= 0 to V
I
-1uA
1uA
OL
V
OUT
DD
V
I
I
= - 4 mA, V =2.375V
Output High Voltage
Output High Voltage
Output Low Voltage
1.7V
2.4V
OH
OH
DDQ
V
= - 4 mA, V =3.135V
OH
OH
DDQ
V
I
= 4 mA
0.4V
OL
OL
Rev: 1.02 3/2000
11/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
DD
-0.5 to 4.6
DD
V
Voltage in V
Pins
-0.5 to V
V
DDQ
DDQ
DD
V
Voltage on Clock Input Pin
Voltage on I/O Pins
-0.5 to 6
V
CK
-0.5 to V +0.5 (£ 4.6 V
DDQ
V
V
I/O
max.)
V
I
-0.5 to V +0.5 (£ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IN
DD
+/- 20
+/- 20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
T
-55 to 125
-55 to 125
C
STG
o
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Min.
3.135
2.375
1.7
Typ.
3.3
2.5
---
Max.
Unit
V
Notes
V
3.6
DD
V
V
I/O Supply Voltage
V
1
2
2
3
3
DDQ
DD
V
V +0.3
DD
Input High Voltage
V
IH
V
Input Low Voltage
-0.3
0
---
0.8
V
IL
T
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
70
85
°C
°C
A
T
-40
25
A
Note:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75V £ VDDQ £ 2.375V (i.e. 2.5V I/O)
and 3.6V £ VDDQ £ 3.135V (i.e. 3.3V I/O) and quoted at whichever condition is worst case.
2. This device features input buffers compatible with both 3.3V and 2.5V I/O drivers.
3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of
Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated
for worst case in the temperature range marked on the device.
4. Input Under/overshoot voltage must be -2V > Vi < V +2V with a pulse width not to exceed 20% tKC.
DD
Rev: 1.02 3/2000
12/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD+-2.0V
50%
VSS
50%
VDD
VSS-2.0V
20% tKC
VIL
Capacitance
o
(T =25 C, f=1MHZ, V =3.3V)
A
DD
Parameter
Control Input Capacitance
Input Capacitance
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
3
4
6
4
5
7
I
V
=3.3V
DD
C
V =0V
IN
pF
IN
V
=0V
OUT
C
Output Capacitance
pF
OUT
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
Max
40
Unit
Notes
1,2
R
single
four
°C/W
°C/W
°C/W
QJA
R
24
1,2
QJA
R
9
3
QJC
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87.
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.
Rev: 1.02 3/2000
13/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3V
0.2V
Input slew rate
1V/ns
Input reference level
Output reference level
Output load
1.25V
1.25V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for t , t , t and t
.
OHZ
LZ HZ OLZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5V
Output Load 1
DQ
225W
225W
DQ
*
50W
VT=1.25V
30pF
*
5pF
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Symb
Parameter
ol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
-1uA
1uA
IL
V
³ V ³ V
-1uA
-1uA
1uA
300uA
DD
IN
IH
I
ZZ Input Current
INZZ
0V £ V £ V
IN
IH
V
³ V ³ V
-300uA
-1uA
1uA
1uA
DD
IN
IL
I
Mode Pin Input Current
Output Leakage Current
INM
0V £ V £ V
IN
IL
Output Disable,
= 0 to V
I
-1uA
1uA
OL
V
OUT
DD
V
I
I
= - 4 mA, V =2.375V
Output High Voltage
Output High Voltage
Output Low Voltage
1.7V
2.4V
OH
OH
DDQ
V
= - 4 mA, V =3.135V
OH
OH
DDQ
V
I
= 4 mA
0.4V
OL
OL
Rev: 1.02 3/2000
14/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Operating Currents
-100
Parameter
Test Conditions
Symbol
0 to 70°C
225mA
-40 to 85°C
I
DD
Device Selected;
All other inputs
³ V or £ V
235mA
190mA
40mA
40mA
90mA
75mA
Pipeline
Operating
Current
IH
IL
I
DD
180mA
30mA
30mA
80mA
65mA
Output open
Flow-Thru
I
SB
Pipeline
Standby
Current
ZZ ³ V - 0.2V
DD
I
SB
Flow-Thru
I
DD
Device Deselected;
All other inputs
Pipeline
Deselect
Current
I
DD
³ V or £ V
IH
IL
Flow-Thru
Rev: 1.02 3/2000
15/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
AC Electrical Characteristics
-100
Parameter
Symbol
Unit
Min
8.5
---
Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
tKC
tKQ
---
4.2
---
ns
ns
ns
ns
Pipeline
tKQX
1.5
1.5
1
---
tLZ
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKC
tKQ
15.0
---
---
11.5
---
ns
ns
ns
ns
ns
ns
ns
ns
Flow-Thru
tKQX
3.0
3.0
1.7
2
1
---
tLZ
tKH
tKL
---
Clock LOW Time
---
1
Clock to Output in High-Z
G to Output Valid
1.5
---
4.2
4.2
tHZ
tOE
1
G to output in Low-Z
G to output in High-Z
0
---
ns
ns
tOLZ
1
---
4.2
tOHZ
Setup time
Hold time
tS
tH
2.0
0.5
---
---
ns
ns
2
ZZ setup time
ZZ hold time
ZZ recovery
5
1
---
---
---
ns
ns
ns
tZZS
2
tZZH
tZZR
20
Notes:
1. These parameters are sampled and are not 100% tested
2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.02 3/2000
16/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tH
tS
ADSP is blocked by E inactive
tKC
tKL
tKH
ADSP
tS tH
ADSC initiated write
ADSC
tH
tS
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0-An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA - BD
E1
tS
tH
tH
E1 masks ADSP
tS
Deselected with E2
E2
tS tH
E2 and E3 only sampled with ADSP or ADSC
E3
G
tS
Write specified byte for 2A and all bytes for 2B, 2c& 2D
tH
Hi-Z
D2C
D2D
D3A
DQA - DQD
D1A
D2A
D2B
Rev: 1.02 3/2000
17/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Flow Through Read-Write Cycle Timing
Single Write
tKC
Burst Read
Single Read
CK
tH
tS
ADSP is blocked by E inactive
tKH tKL
tS
ADSP
ADSC
tH
ADSC initiated read
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0-An
tS
tS
tH
GW
tS
tH
BW
tS
tH
BA - BD
WR1
tS
tS
tS
tH
tH
tH
E1 masks ADSP
E1
E2 and E3 only sampled with ADSP and ADSC
E2
Deselected with E3
E3
tOHZ
tOE
G
tS
D1A
tH
tKQ
Hi-Z
DQA - DQD
Q1A
Q2A
Q2A
Q2B
Q2c
Q2D
Burst wrap around to it’s initial state
Rev: 1.02 3/2000
18/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tKH
tS
tS
tH
ADSP is blocked by E inactive
tKC
ADSP
ADSC
ADV
tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0-An
GW
tS
tS
tH
tH
BW
BA - BD
E1
tH
tS
E1 masks ADSP
tH
tH
tS
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tOHZ
tOE
G
tKQX
tKQX
tOLZ
Q2B
Q2C
Q3A
Q2A
Q1A
Q2D
DQA-DQD
Hi-Z
tLZ
tHZ
tKQ
Rev: 1.02 3/2000
19/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
tKC
CK
tKL
tKH
tH
tH
tS
ADSP is blocked by E inactive
ADSP
ADSC
tS
ADSC initiated read
tS
tH
Suspend Burst
ADV
tH
tS
RD2
RD3
RD1
A0-An
GW
tS
tS
tH
tH
BW
BWA - BWA
E1
tH
tH
tH
tS
E1 masks ADSP
tS
tS
E2 and E3 only sampled with ADSP or ADSC
Deselected with E2
E2
E3
tOE
G
tOHZ
tKQX
tKQX
tOLZ
tLZ
Hi-Z
DQA - DQD
Q1A
Q2A
Q2B
Q2D
Q3A
tHZ
Q2c
tKQ
Rev: 1.02 3/2000
20/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Pipelined SCD Read - Write Cycle Timing
Single Write
Burst Read
Single Read
tKL
CK
ADSP
ADSC
tH
tS
tKH
tKC
ADSP is blocked by E inactive
ADSC initiated read
tS tH
tS tH
ADV
tS
tH
RD2
RD1
WR1
A0-An
tS
tS
tH
GW
tH
BW
tH
tS
WR1
BWA - BWD
tS
tH
E1 masks ADSP
E1
tS tH
E2 and E3 only sampled with ADSP and ADSC
E2
E3
tH
tS
Deselected with E3
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2B
Q2c
DQA - DQD
Q2D
Rev: 1.02 3/2000
21/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
Rev: 1.02 3/2000
22/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Output Driver Characteristics
60
Pull Down Drivers
40
20
VDD
I Out
0
VOut
VSS
-20
-40
Pull Up Drivers
-60
-80
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
V Out (Pull Down)
VDDQ - V Out (Pull Up)
3.6V PD LD
3.3V PD LD
3.1V PD LD
3.1V PU LD
3.3V PU LD
3.6V PU LD
BPF 2000/01/07
Rev: 1.02 3/2000
23/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
TQFP Package Drawing
q
L
c
Symbol
Description
Standoff
Min. Nom. Max
L1
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
D1
E
e
E1
e
Package Body
Lead Pitch
13.9
b
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
0.75
L1
Y
0.10
q
0°
7°
A1
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
A2
E1
E
BPR 1999.05.18
Rev: 1.02 3/2000
24/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(Mhz/ns)
256K x 32
256K x 32
Notes:
GS880L32T-
GS880L32T-
Flow Through
Flow Through
TQFP
TQFP
100/12
C
I
100/12
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS880L32T.
2. The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each
device is Pipeline / Flow through mode selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.
Rev: 1.02 3/2000
25/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880L32T-100
Revision History
Types of Changes
Format or Content
DS/DateRev. Code: Old;
Page;Revisions;Reason
New
• First Release of the 880L32 Datasheet.New GSI Logo.
GS880L32T 11/
1999;880L32T1.00 1/2000L
Content
• Took out extra line in Features. It was duplicated.
•
GS880L3
Content
Content
• Changed AC Electrical Characteristics table to include only 100 speed bin
• Changed Power Currents Table to include only 100 speed bin
GS880L32 Rev 1.00 2/2000M;
GS880L32 Rev 1.01 3/2000N.
Rev: 1.02 3/2000
26/26
© 2000, Giga Semiconductor, Inc.
N
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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