GS816V73GC-200IT [GSI]
Cache SRAM, 256KX72, 2.6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209;
| 型号： | GS816V73GC-200IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Cache SRAM, 256KX72, 2.6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209 静态存储器 内存集成电路 |
| 文件： | 总29页 (文件大小：733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS816V73C-200
209-Pin BGA
Commercial Temp
Industrial Temp
200 MHz
1.8 V VDD
1.8 V I/O
256K x 72
18Mb S/DCD Sync Burst SRAM
Supplemental Datasheet
Functional Description
Current Consumption
The GS816V73C-200 complies with all specifications of the
GS816273C-250/225/200, Revision 1.01, 12/2002 (attached),
except where superceded by the following tables:
• Absolute Maximum Ratings
-200
Unit
Pipeline
3-1-1-1
t
3.0
5.0
ns
ns
KQ
tCycle
• Power supply Ranges
• V
Range Logic Levels
1.8 V
Curr (x72)
340
mA
DDQ
• Operating Currents
• JTAG Port Recommended Operating Conditions
• Ordering Information
• Datasheet Revision History
Features
• 1.8 V core power supply
• 1.8 V I/O supply
Absolute Maximum Ratings
(All voltages reference to V
)
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 3.6
DD
DD
V
Voltage in V
Pins
DDQ
–0.5 to 3.6
V
DDQ
V
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 3.6
+0.5 (≤ 3.6 V max.)
DDQ
V
CK
V
–0.5 to V
V
I/O
V
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
–0.5 to V +0.5 (≤ 3.6 V max.)
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
STG
C
o
T
Temperature Under Bias
BIAS
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Condi-
tions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Rev: 1.02 12/2002
1/4
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS816V73C-200
Power Supply Voltage Ranges
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
V
1.8 V Supply Voltage
1.7
1.7
1.8
1.8
2.0
2.0
V
V
DD
1.8 V V
I/O Supply Voltage
V
DDQ
DDQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
V
Range Logic Levels
Parameter
DDQ
Symbol
Min.
Typ.
Max.
Unit
Notes
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
—
—
—
—
V
V
V
V
1
DD
IH
DD
V
Input Low Voltage
V
0.3*V
DD
–0.3
0.6*V
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
V
+ 0.3
DDQ
1,3
1,3
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 1.02 12/2002
2/4
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816V73C-200
Operating Currents
-200
Parameter
Test Conditions
Mode
Symbol
Unit
0
–40
to 70°C
to 85°C
Device Selected;
All other inputs
≥V or ≤ V
Operating
Current
I
290
60
300
60
DD
mA
(x72)
Pipeline
I
IH
IL
DDQ
1.8 V
Output open
Standby
Current
ZZ ≥ V – 0.2 V
I
mA
mA
—
—
Pipeline
Pipeline
35
75
45
80
DD
SB
Device Deselected;
All other inputs
≥ V or ≤ V
Deselect
Current
I
DD
IH
IL
Notes:
1.
I
and I
apply to V and V operation.
DDQ
DD
DDQ
DD
2. All parameters listed are worst case scenario.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
V
0.6 * V
V
+0.3
DD
1.8 V Test Port Input High Voltage
1.8 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
V
V
1
1
IHJ
DD
V
0.3 * V
1
–0.3
ILJ
DD
I
–300
–1
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
1.2
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
—
0.4
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
—
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DD
3. 0 V ≤ V ≤ V
IN
ILJ
4. Output Disable, V
= 0 to V
DD
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
Rev: 1.02 12/2002
3/4
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816V73C-200
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz)
256K x 72
256K x 72
Notes:
GS816V73C-200
GS816V73C-200I
S/DCD Pipeline
S/DCD Pipeline
209 BGA
209 BGA
200
C
I
200
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816V73C-200IT.
2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
816V73_r1
• Removed 250 MHz and 225 MHz speed bins
• Updated tKQ from 2.5 ns to 3.0 ns
816V73_r1; 816V73_r1_01
Content
Content
• Updated base datasheet reference
• Updated I
values
DDQ
• Updated Note 1 for Operating Currents table (should only
816V73_r1_01;
816V73_r1_02
reference V and V
)
DDQ
DD
• Update Note 1 for JTAG Operating Conditions table (changed
4.6 V to 3.6 V
• Added industrial part ordering information
Rev: 1.02 12/2002
4/4
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
209-Pin BGA
Commercial Temp
250 MHz–133MHz
256K x 72
2.5 V or 3.3 V VDD
Industrial Temp 18Mb S/DCD Sync Burst SRAMs
2.5 V or 3.3 V I/O
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Features
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 209-bump BGA package
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
2.6 2.6 2.6 2.9 3.3 3.5 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
KQ
Sleep Mode
tCycle
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
3.3 V
2.5 V
Curr (x72) 430 395 350 300 270 245 mA
Curr (x72) 410 380 335 290 260 235 mA
Core and Interface Voltages
The GS816273C operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power
(VDDQ) pins are used to decouple output noise from the internal
Functional Description
Applications
circuits and are 3.3 V and 2.5 V compatible.
The GS816273C is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
SCD and DCD Pipelined Reads
The GS816273C is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
Rev: 1.01 12/2002
1/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS816273C-250/225/200/166/150/133
GS816273 Pad Out
209 Bump BGA—Top View
Package C
1
2
3
4
5
6
ADSC
BW
7
8
9
10
11
A
B
C
D
E
F
DQG5
DQG6
DQG7
DQG8
DQG9
DQC4
DQC3
DQC2
DQC1
NC
DQG1
DQG2
DQG3
DQG4
DQC9
DQC8
DQC7
DQC6
DQC5
NC
A15
E2
ADSP
NC
ADV
A16
NC
E3
A17
DQB1
DQB2
DQB3
DQB4
DQF9
DQF8
DQF7
DQF6
DQF5
NC
DQB5
DQB6
DQB7
DQB8
DQB9
DQF4
DQF3
DQF2
DQF1
NC
BC
BG
BB
BF
BH
BD
NC
E1
BE
BA
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
CK
NC
NC
G
GW
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
NC
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
VDD
ZQ
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
G
H
J
MCH
MCL
MCL
MCL
VDDQ/DNU
MCL
SCD
ZZ
K
L
DQH1
DQH2
DQH3
DQH4
DQD9
DQD8
DQD7
DQD6
DQD5
DQH5
DQH6
DQH7
DQH8
DQH9
DQD4
DQD3
DQD2
DQD1
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
DQA5
DQA6
DQA7
DQA8
DQA9
DQE4
DQE3
DQE2
DQE1
DQA1
DQA2
DQA3
DQA4
DQE9
DQE8
DQE7
DQE6
DQE5
M
N
P
R
T
VDD
LBO
A12
U
V
A14
A13
A7
A11
A6
A10
A9
A8
A1
A5
A4
W
TMS
TDI
A3
A0
A2
TDO
TCK
Rev 10
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 1.01 12/2002
2/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
GS816273 BGA Pin Description
Symbol
A0, A1
An
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
DQE1–DQE9
DQF1–DQF9
DQG1–DQG9
DQH1–DQH9
I/O
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
BA, BB, BC,BD, BE, BF,
BG,BH
I
NC
CK
—
I
No Connect
Clock Input Signal; active high
I
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
GW
I
E1, E3
E2
I
Chip Enable; active high
I
Output Enable; active low
G
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
ADV
ADSP, ADSC
ZZ
I
I
I
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
LBO
I
SCD
MCH
MCL
I
Must Connect Low
Rev: 1.01 12/2002
3/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
GS816273 BGA Pin Description
Symbol
Type
Description
I
Byte Enable; active low
BW
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
I
ZQ
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TMS
TDI
O
I
TDO
TCK
V
I
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
V
or V (must be tied high)
DDQ
DD
V
/DNU
—
or
DDQ
Do Not Use (must be left floating)
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Active
Burst Order Control
Power Down Control
LBO
H
L or NC
ZZ
Standby, I = I
H
DD SB
L
Dual Cycle Deselect
Single Cycle Deselect
Single/Dual Cycle Deselect Control
SCD
ZQ
H or NC
L
High Drive (Low Impedance)
Low Drive (High Impedance)
FLXDrive Output Impedance Control
Note:
H or NC
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Rev: 1.01 12/2002
4/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 1.01 12/2002
5/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Synchronous Truth Table
Operation
State
3
4
Diagram
Address Used
E1
ADSP ADSC
ADV
W
DQ
5
Key
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
External
External
External
Next
X
R
H
L
X
L
L
X
L
X
X
X
X
L
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.01 12/2002
6/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CR
CW
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Rev: 1.01 12/2002
7/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CR
CW
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 1.01 12/2002
8/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Absolute Maximum Ratings
(All voltages reference to V )
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
–0.5 to 4.6
–0.5 to 6
DD
DD
V
Voltage in V
Pins
DDQ
V
DDQ
V
Voltage on Clock Input Pin
Voltage on I/O Pins
V
CK
V
–0.5 to V
+0.5 (≤ 4.6 V max.)
DDQ
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Rev: 1.01 12/2002
9/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Power Supply Voltage Ranges
Parameter
Symbol
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
Notes
V
3.3 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD3
V
2.3
2.5
2.7
DD2
3.3 V V
2.5 V V
I/O Supply Voltage
I/O Supply Voltage
V
3.0
3.3
3.6
DDQ
DDQ
DDQ3
V
2.3
2.5
2.7
DDQ2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V
Range Logic Levels
Parameter
DDQ3
Symbol
Min.
2.0
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
V
Input Low Voltage
V
–0.3
2.0
—
0.8
+ 0.3
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
V
—
1,3
1,3
DDQ
IHQ
DDQ
V
V
–0.3
—
0.8
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
V
Range Logic Levels
Parameter
DDQ2
Symbol
Min.
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
DD
V
Input Low Voltage
V
0.3*V
DD
–0.3
—
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
0.6*V
V
+ 0.3
DDQ
—
1,3
1,3
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
—
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 1.01 12/2002
10/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
Note:
–40
25
85
°C
A
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V = 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
= 0 V
OUT
Input/Output Capacitance
pF
I/O
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
Max
40
Unit
Notes
1,2
R
single
four
—
°C/W
°C/W
°C/W
ΘJA
R
24
1,2
ΘJA
R
9
3
ΘJC
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.01 12/2002
11/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig.
1 unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50Ω
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
IN
–1 uA
–1 uA
1 uA
100 uA
DD
IH
IH
I
I
ZZ and PE Input Current
SCD and ZQ Input Current
IN1
IN2
0 V ≤ V ≤ V
IN
V
≥ V ≥ V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
0 V ≤ V ≤ V
IN
I
Output Disable, V
= 0 to V
DD
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
OL
OUT
DDQ
DDQ
V
V
I
I
= –8 mA, V
= –8 mA, V
= 2.375 V
= 3.135 V
OH2
OH3
OH
OH
—
V
I
= 8 mA
OL
0.4 V
OL
Rev: 1.01 12/2002
12/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Rev: 1.01 12/2002
13/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
AC Electrical Characteristics
-250
-225
-200
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
4.0
—
—
2.6
—
—
—
—
2.6
2.6
—
—
4.4
—
—
2.6
—
—
—
—
2.6
2.6
—
—
5.0
—
—
2.6
—
—
—
—
2.6
2.6
—
—
6.0
—
—
2.9
—
—
—
—
2.9
2.9
—
—
6.7
—
—
3.3
—
—
—
—
3.0
3.3
—
—
7.5
—
1.0
1.0
1.5
0.5
—
—
1.7
2
—
3.5
—
—
—
—
3.0
3.5
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.0
1.0
1.2
0.2
—
1.0
1.0
1.3
0.3
—
1.0
1.0
1.4
0.4
—
1.0
1.0
1.5
0.5
—
1.0
1.0
1.5
0.5
—
1
tLZ
Pipeline
tS
tH
Hold time
1
G to output in High-Z
G to Output Valid
Clock HIGH Time
Clock LOW Time
tOHZ
tOE
tKH
tKL
—
1.3
—
1.3
—
1.3
—
1.3
—
1.5
1.5
1.5
1.5
1.5
1.7
Clock to Output in
High-Z
1
1.5
2.6
1.5
2.6
1.5
2.6
1.5
2.9 1.5 3.0 1.5 3.0
ns
tHZ
1
G to output in Low-Z
ZZ setup time
ZZ hold time
0
5
—
—
—
—
0
5
—
—
—
—
0
5
—
—
—
—
0
5
—
—
—
—
0
5
—
—
—
—
0
5
—
—
—
—
ns
ns
ns
ns
tOLZ
2
tZZS
tZZH
2
1
1
1
1
1
1
ZZ recovery
tZZR
100
100
100
100
100
100
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 1.01 12/2002
14/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Rev: 1.01 12/2002
15/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
Rev: 1.01 12/2002
16/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and
0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising
edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI
and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Rev: 1.01 12/2002
17/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
x72 0 1 1 0 1 1 0 0 1
0
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.01 12/2002
18/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
1
1
Exit2 DR
Exit2 IR
0
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
Rev: 1.01 12/2002
19/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
EXTEST
IDCODE
Code
000
001
Description
Notes
1
1, 2
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
100
101
110
111
1
1
1
1
GSI
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.01 12/2002
20/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
2.0
Max.
Unit Notes
V
V
V
+0.3
DD3
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
IHJ3
V
–0.3
0.8
+0.3
ILJ3
V
0.6 * V
V
1
IHJ2
DD2
DD2
V
0.3 * V
1
–0.3
–300
–1
V
1
ILJ2
DD2
I
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
0.4
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
—
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
JTAG Port AC Test Conditions
Parameter
Input high level
Conditions
2.3 V
JTAG Port AC Test Load
DQ
Input low level
0.2 V
*
Input slew rate
1 V/ns
50Ω
30pF
Input reference level
Output reference level
1.25 V
V = 1.25 V
T
1.25 V
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
Rev: 1.01 12/2002
21/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
JTAG Port Timing Diagram
tTKL
tTS
tTKH
tTKC
TCK
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
TCK Cycle Time
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
ns
ns
tTH
—
Rev: 1.01 12/2002
22/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
A1
C
A
Side View
D
aaa
D1
e
Bottom View
b
e
Symbol
Min
Typ
Max
1.70
0.60
0.70
0.38
22.1
Units
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
A
A1
b
0.40
0.50
0.31
21.9
0.50
0.60
c
0.36
D
22.0
D1
E
18.0 (BSC)
14.0
13.9
14.1
E1
e
10.0 (BSC)
1.00 (BSC)
0.15
aaa
Rev 1.0
Package Dimensions—119-Pin PBGA
Rev: 1.01 12/2002
23/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
Ordering Information for GSI Synchronous Burst RAMs
2
Speed
(MHz)
3
1
Org
Type
Package
Status
T
Part Number
A
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
Notes:
GS816273C-250
GS816273C-225
GS816273C-200
GS816273C-166
GS816273C-150
GS816273C-133
GS816273C-250I
GS816273C-225I
GS816273C-200I
GS816273C-166I
GS816273C-150I
GS816273C-133I
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
S/DCD Pipeline
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
250
225
200
166
150
133
250
225
200
166
150
133
C
C
C
C
C
C
I
I
I
I
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816273B-150IB.
2. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.01 12/2002
24/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS816273C-250/225/200/166/150/133
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Creation of new datasheet
816273_r1
• Changed bump L6 to VDDQ/DNU
• Removed PE pin (replaced with NC)
• Updated tKQ numbers for 250 and 225 MHz
• Updated AC Characteristics table (tOE, tHZ, and tOHZ to
equal tKQ (PL) for 250 and 225 MHz)
• Added new timing diagrams
816273_r1; 816273_r1_01
content
Rev: 1.01 12/2002
25/25
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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