GS8170D36GB-300IT [GSI]
Standard SRAM, 512KX36, 1.8ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209;
| 型号： | GS8170D36GB-300IT |
| 厂家： | 
GSI TECHNOLOGY |
| 描述： | Standard SRAM, 512KX36, 1.8ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209 静态存储器 |
| 文件： | 总32页 (文件大小：1120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS8170D18/36B-333/300/250
209-Bump BGA
Commercial Temp
Industrial Temp
250 - 333 MHz
18Mb S1x2Lp DDR SRAM
1M x 18, 512K x 36
1.8 V V
DD
1.8 V and 1.5 V I/O
Features
• Double Data Rate Read and Write mode
• JEDEC standard SigmaRAM™ pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V I/O supply
• Pipelined read operation.
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 User programmable chip enable inputs for easy depth
expansion.
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin compatible with future 32M, 64M, and 128M devices
SigmaRAM Family Overview
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
GS8170D18/36 SigmaRAMs are built in compliance with the
SigmaRAM pinout standard for synchronous SRAMs.
18,874,368-bit (18Mb) SRAMs. These are the first in a family
of wide, very low voltage CMOS I/O SRAMs designed to
operate at the speeds needed to implement economical high
performance networking systems.
Because the DDR SRAM always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR SRAM is always one
address pin less than the advertised index depth (e.g., the 1M x
18 has a 512k addressable index).
GSI's SRAMs are offered in a number of configurations that
emulate other synchronous SRAMs, such as Burst RAMs,
NBT, Late Write, or Double Data Rate (DDR) SRAMs. The
logical differences between the protocols employed by these
RAMs hinge mainly on various combinations of address
bursting, output data registering and write cueing. The
SRAM™ family standard allows a user to implement the
interface protocol best suited to the task at hand.
In Pipeline mode, single data rate SRAMs incorporate a rising-
edge-triggered output register. In DDR mode, rising- and
falling-edge-triggered output registers are employed. For read
cycles, a DDR SRAM’s output data is staged at the input of an
edge-triggered output register during the access cycle and then
released to the output drivers at the next rising and subsequent
falling edge of clock.
Functional Description
GS817x18/36/72B SRAMs are implemented with GSI's high
performance CMOS technology and are packaged in a 209-
bump BGA.
Because SigmaRAMs are synchronous devices, address, and
read/write control inputs are captured on the rising edge of the
input clock. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.
Rev: 1.04b 06/2001
1/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
8170D36B 512K x 36 Pinout
512K x 36 Common I/O—Top View
1
2
3
4
5
6
7
8
9
10
11
A
NC
NC
A
E2
A
ADV
A
E3
A
DQb
DQb
(16M)
B
C
NC
NC
NC
NC
MCL
NC
A
W
A
MCL
NC
DQb
DQb
DQb
DQb
NC
MCL
NC
E1
NC
NC
MCL
(128M)
D
E
F
NC
NC
NC
DQPc
DQc
DQc
DQc
DQc
CQ2
NC
VSS
VDDQ
VSS
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
MCL
VDD
ZQ
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VSS
VDDQ
VSS
DQb
NC
DQb
DQPb
NC
DQc
DQc
DQc
DQc
CQ2
NC
NC
G
H
J
VDDQ
VSS
EP2
EP3
M4
VDDQ
VSS
NC
NC
NC
NC
VDDQ
CK
VDDQ
NC
NC
NC
K
L
MCL
M2
CQ1
DQa
DQa
DQa
DQa
DQPa
NC
CQ1
DQa
DQa
DQa
DQa
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
M
N
P
R
T
NC
NC
M3
NC
NC
MCH
MCL
VDD
MCL
A
NC
NC
DQPd
DQd
DQd
DQd
DQd
NC
DQd
DQd
DQd
DQd
NC
U
V
NC
A
NC (64M)
A
NC (32M)
A
A
NC
NC
NC
A
A
A1
A
A
NC
NC
W
TMS
TDI
A
MCL
A
TDO
TCK
NC
NC
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
• 2001.03
Rev: 1.04b 06/2001
2/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
8170D18 1M x 18 Pinout
1M x 18 Common I/O—Top View
1
2
3
4
5
6
7
8
9
10
11
A
NC
NC
A
E2
A
ADV
A
E3
A
NC
NC
(16M)
B
C
NC
NC
NC
NC
MCL
NC
NC
A
W
A
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
E1
MCL
(128M)
D
E
F
NC
NC
NC
DQPb
DQb
DQb
DQb
DQb
CQ2
NC
VSS
VDDQ
VSS
NC
VDDQ
VSS
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
MCL
VDD
ZQ
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
NC
VDDQ
VSS
VSS
VDDQ
VSS
NC
NC
NC
NC
DQb
DQb
DQb
DQb
CQ2
NC
NC
NC
G
H
J
VDDQ
VSS
VDDQ
VSS
EP2
EP3
M4
VDDQ
VSS
VDDQ
VSS
NC
NC
NC
NC
VDDQ
CK
VDDQ
NC
VDDQ
NC
VDDQ
NC
NC
NC
K
L
MCL
M2
CQ1
DQa
DQa
DQa
DQa
DQPa
NC
CQ1
DQa
DQa
DQa
DQa
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
M
N
P
R
T
NC
NC
M3
NC
NC
MCH
MCL
VDD
MCL
A
NC
NC
NC
NC
VDDQ
NC
VDDQ
NC
NC
NC
NC
U
NC
NC
NC
A
NC
NC
A
NC
NC
NC
(64M)
(32M)
V
W
NC
NC
NC
NC
A
A
A
A
A1
A
A
A
A
NC
NC
NC
NC
TMS
TDI
MCL
TDO
TCK
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
• 2001.03
Rev: 1.04b 06/2001
3/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Pin Description Table
Pin Location
Symbol
Description
Type
Comments
A3, A5, A7, A9, B7, U4,
U6, U8, V3, V4, V5, V6,
V7, V8, V9, W5, W7
A
Address
Input
—
C7
B5
A
A
Address
Address
Input
Input
x18 version only
x18 and x36 versions
Active High
A6
ADV
CK
CQ
CQ
Advance
Clock
Input
K3
Input
Active High
K1, K11
K2, K10
Echo Clock
Echo Clock
Output
Output
Active High
Active Low
E2, F1, F2, G1, G2, H1,
H2, J1, J2, L10, L11,
M10, M11, N10, N11,
P10, P11, R10
DQ
DQ
Data I/O
Data I/O
Input/Output
Input/Output
x18 and x36 versions
x36 version
A10, A11, B10, B11,
C10, C11, D10, D11,
E11, R1, T1, T2, U1, U2,
V1, V2, W1, W2
C6
E1
Chip Enable
Chip Enable
Input
Input
Input
Input
Input
Output
Input
Input
Input
Active Low
A4, A8
E2 & E3
Programmable Active High or Low
G6, H6
W9
EP2 & EP3
TCK
Chip Enable Program Pin
Test Clock
—
Active High
W4
TDI
Test Data In
—
W8
TDO
Test Data Out
—
W3
TMS
Test Mode Select
Mode Control Pins
Must Connect High
—
—
L6, M6, J6
N6
M2, M3 & M4
MCH
Active High
B3, C9, D6, K6, P6, T6,
W6
MCL
Must Connect Low
Input
Active Low (all versions)
Rev: 1.04b 06/2001
4/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Pin Description Table
Pin Location
Symbol
Description
Type
Comments
B8, C4
MCL
Must Connect Low
Input
Active Low (x36 version)
A1, A2, B1, B2, B4, B9,
C1, C2, C3, C5, C8, D1,
D2, D4, D5, D7, D8,E1,
E10, F10, F11, G10,
G11, H10, H11, J10,
J11, K4, K8, K9, L1, L2,
M1, M2, N1, N2, P1, P2,
R2, R11, T4, T5, T7, T8,
T10, T11, U3, U5, U7,
U9, U10, U11, V10, V11,
W10, W11
NC
No Connect
—
Not connected to die (all versions)
C7
NC
NC
No Connect
No Connect
—
—
Not connected to die (x36 version)
A1, A2, B1, B2, B4, B9,
C1, C2, C3, C8, D1, D2,
E1, E10, F10, F11, G10,
G11, H10, H11, J10,
J11, L1, L2, M1, M2, N1,
N2, P1, P2, R2, R11,
T10, T11, U10, U11,
V10, V11, W10, W11
Not connected to die (x36/x18 versions)
A10, A11, B8, B10, B11,
C4, C10, C11, D10, D11,
E11, R1, T1, T2, U1, U2,
V1, V2, W1, W2
NC
No Connect
—
Not connected to die (x18 version)
B6
W
Write
Input
Input
Active Low
E5, E6, E7, G5, G7, J5,
J7, L5, L7, N5, N7, R5,
R6, R7
VDD
Core Power Supply
1.8 V Nominal
E3, E4, E8, E9, J3, J4,
J8, J9, L3, L4, L8, L9,
N3, N4, N8, N9, R3, R4,
R8, R9
VDDQ
Output Driver Power Supply
Input
1.8 V or 1.5 V Nominal
D3, D9, F3, F4, F5, F7,
F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4,
M5, M7, M8, M9, P3, P4,
P5, P7, P8, P9, T3, T9
VSS
ZQ
Ground
Input
Input
—
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
F6
Output Impedance Control
Rev: 1.04b 06/2001
5/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Background
The central characteristics of SRAMs are that they are extremely fast and consume very little power. Because both operating and
interface power is low, SRAMs can be implemented in a wide (x36) configuration, providing very high single package bandwidth
(in excess of 20 Gb/s in ordinary pipelined configuration) and very low random access latency (5 ns). The use of very low voltage
circuits in the core and 1.8 V or 1.5 V interface voltages allow the speed, power and density performance of SRAMs.
Although the SigmaRAM family of pinouts has been designed to support a number of different common read and write protocol
options, not all SigmaRAM implementations will support all possible protocols. The following timing diagrams provide a quick
comparison between read and write protocols options available in the context of the SigmaRAM standard. This particular data
sheet covers the SigmaRAM.
The character of the applications for fast synchronous SRAMs in networking systems are extremely diverse. SRAMs have been
developed to address the diverse needs of the networking market in a manner that can be supported with a unified development and
manufacturing infrastructure. SRAMs address each of the bus protocol options commonly found in networking systems. This
allows the SRAM to find application in radical shrinks and speed-ups of existing networking chip sets that were designed for use
with older SRAMs, like the NBT, Late Write, or Double Data Rate SRAMs, as well as with new chip sets and ASIC’s that employ
the Echo Clocks and realize the full potential of the SRAMs.
Mode Selection Truth Table Standard
M2 M3 M4 Name
Function
Early Write, Flow through Read
Late Write, Flow through Read
RFU
Analogous to...
Flow through Burst RAM
Flow through NBT SRAM
In This Data Sheet?
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No
No
n/a
Yes
No
No
No
S1x1Ef
S1x1Lf
DDR
Double Data Rate SRAM
Pipelined Burst RAM
S1x2Lp
S1x1Ep
S1x1Dp
S1x1Lp
Early Write, Pipelined Read
Double Late Write, Pipelined Read
Late Write, Pipelined Read
Pipelined NBT SRAM
Pipelined Late Write SRAM
All address and control inputs (with the exception of PE2, PE3, and the mode pins, M2–M4) are synchronized to rising clock
edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the Advance/
Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip
Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. It should be noted that
ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQn.
Rev: 1.04b 06/2001
6/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Read Operations
Double Data Rate Read
In applications where a data rate markedly faster than the RAM’s latency is desired, Double Data Rate reads double the data
transfer rate (read or write bandwidth) achieved in Pipeline mode while keeping the RAM’s clock frequency constant. In Double
Data Rate mode, the RAM multiplexes the results of a read out of the RAM on half the usual number of data pins. The output
register/mux behaves just as if it were in Pipeline mode for the first transfer, but then makes a second transfer in response to the
next falling edge of clock as well. Interleaved Burst Order is not supported in DDR mode.SigmaRAM DDR RAMs burst in linear
order only.
Double Data Rate Pipelined Read
Read
Deselect
Read
Read
Read
CK
Address
/E1
A
XX
C
D
E
F
/W
QA0
QA1
QC0
QC1
QD0
QD1
DQ
CQ
Key
Hi-Z
Access
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active and the write enable input signal (W) is asserted low.
Double Data Rate Write
A Double Data Rate Write is a specialized form of Late Write. In Double Data Rate mode, the RAM will capture Data In on both
rising and falling edges of the RAM clock, CK, beginning with the rising edge of clock that follows the capture of the write address
and command.
Rev: 1.04b 06/2001
7/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
SigmaRAM Double Data Rate Read and Write
Read
Deselect
Write
Read
Read
CK
Address
/E1
A
B
C
D
E
F
/W
QA0
QA1
DC0
DC1
QD0
QD1
DQ
CQ
Key
Hi-Z
Access
Special Functions
Burst Cycles
SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write
implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use
the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded
into the SRAM by driving the ADV pin low, into Load mode.
Rev: 1.04b 06/2001
8/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
SigmaRAM DDR Burst Read with Counter Wrap-around
Read
Continue
Continue
Read
Continue
CK
External
Address
A2
A2
XX
A0
XX
A2
B0
B0
XX
B2
XX
B1
Internal
Address
A3
A1
A3
B1
B3
Counter Wraps
/E1
/W
ADV
DQ
CQ
QA2
QA3
QA0
QA1
QA2
QA3
QB0
QB1
Rev: 1.04b 06/2001
9/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
SigmaRAM DDR Burst Write with Counter Wrap-around
Write
Continue
Continue
Write
Continue
CK
External
Address
A2
A2
XX
A0
XX
A2
B0
B0
XX
B2
XX
B1
Internal
Address
A3
A1
A3
B1
B3
Counter Wraps
/E1
/W
ADV
DQ
CQ
DA2
DA3
DA0
DA1
DA2
DA3
DB0
DB1
DB2
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. SigmaRAMs always count in linear burst order.
Linear Burst Order
2
2
A[1:0]
A[1:0]
A[1:0]
01
A[1:0]
11
1st address (Rising Edge CK)
2nd address (Falling Edge CK)
3rd address (Rising Edge CK)
4th address (Falling Edge CK)
00
01
10
11
10
11
00
01
10
00
11
01
00
10
Notes:
1. The burst counter wraps to initial state on the 3rd rising edge of clock.
2. The DDR SigmaRAM always begins an read or write at A0 = 0. A0 is internally set to 0 at the rising edge of clock and is not
available to the user.
Rev: 1.04b 06/2001
10/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Echo Clock
SRAMs feature Echo Clocks, CQ1,CQ2, CQ1, and CQ2 that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. SigmaRAMs
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1 and CQ2).
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
Programmable Enables
SRAMs feature two user-programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, PE2 and PE3. For example, if PE2 is held at VDD
,
E2 functions as an active high enable. If PE2 is held to VSS, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows four banks of depth expansion to be accomplished with no additional logic. By programming
the enable inputs of four SRAMs in binary sequence (00, 01, 10, 11) and driving the enable inputs with two address inputs, four
SRAMs can be made to look like one larger RAM to the system.
Example Four Bank Depth Expansion Schematic - S1x2Lp
A1–An
E1
CK
W
DQ0–DQn
Bank 0
Bank 3
Bank 1
Bank 2
A
A1–An – 2
An – 1
An
A1–An – 2
An – 1
An
A1–An – 2
An – 1
An
A1–An – 2
An – 1
An
A
A
A
E3
E2
E1
CK
E3
E2
E1
CK
E3
E3
E2
E2
E1
E1
CK
CK
W
W
W
W
DQ
CQ
DQ
CQ
DQ
CQ
DQ
CQ
CQ
Bank Enable Truth Table
EP2
EP3
VSS
VDD
VSS
VDD
E2
E3
Bank 0
Bank 1
Bank 2
Bank 3
VSS
VSS
VDD
VDD
Active Low
Active Low
Active High
Active High
Active Low
Active High
Active Low
Active High
Rev: 1.04b 06/2001
11/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Echo Clock Control in Two Banks of SigmaRAM Double Data Rate RAMs
Read
Read
Read
Read
Read
CK
Address
A
B
C
D
E
F
/E2 Bank 1
E2 Bank 2
QA0
QA1
QC0
QC1
DQ
Bank 1
CQ
Bank 1
CQ1 + CQ2
CQ
Bank 2
QB0
QB1
QD0
QD1
DQ
Bank 2
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read
operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2
would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
Rev: 1.04b 06/2001
12/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
SigmaRAM DDR Bank Switch with E1 Deselect
Read
No Op
Read
Read
Read
CK
Address
/E1
A
XX
C
D
E
F
/E2 Bank 1
E2 Bank 2
QA0
QA1
DQ
Bank 1
CQ
Bank 1
CQ1 + CQ2
CQ
Bank 2
QC0
QC1
QD0
QD1
DQ
Bank 2
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
FLXDrive™ Output Driver Impedance Control
The ZQ pin allows selection between SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See ”Output Driver Characteristics” on page 42 for details.
Rev: 1.04b 06/2001
13/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
1x2Lp Clock Truth Table
E1
E
ADV
W
BW
DQ/CQ DQ/CQ DQ/CQ DQ/CQ
CK
Current Operation
(t ) (t ) (t ) (t )
(t )
(t )
(t
)
(t
)
(t
)
n
X
X
1
n
F
X
T
X
n
n
X
X
X
X
n
n
n+½
n+1
n+1½
0® 1
0® 1
0® 1
0® 1
0
X
Bank Deselect
X
Bank Deselect
Bank Deselect (Continue)
Deselect
***
Hi-Z
***
Hi-Z
Hi-Z
1
0
1
Hi-Z/CQ
Hi-Z/CQ
X
Deselect
Deselect (Continue)
Hi-Z/CQ
***
Dn/CQ
(tn)
Dn+½/CQ
(tn
Write
Loads new address
0® 1
0® 1
0® 1
0
X
0
T
X
T
X
0
1
0
1
0
X
1
X
)
+½
Dn-½/CQ
(tn-
Dn+½/CQ
(tn
Dn-1/CQ
Dn/CQ
(tn)
Write Continue
Increments address by 2
Write
X
(tn-1
)
)
)
+½
½
Qn/CQ
(tn)
Qn+½/CQ
(tn
Read
Loads new address
***
)
+½
Qn-½/CQ
(tn-
Qn+½/CQ
(tn
Qn-1/CQ
(tn-1
Qn/CQ
(tn)
Read Continue
Increments address by 2
0® 1
X
X
Read
)
)
)
+½
½
Notes:
1. If E2 = EP2 and E3 = EP3 then E = “T” else E = “F”.
2. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
3. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
4. DQs are tri-stated in response to Bank Deselect, Chip Deselect, and Write commands, one full cycle after the command is
sampled.
5. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
6. One (1) Continue operation may be initiated after a Read or Write operation is initiated to burst transfer four (4) distinct
pieces of data per single external address input. If a second (2nd) Continue operation is initiated, the internal address wraps
back to the initial external (base) address.
Rev: 1.04b 06/2001
14/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Common I/O State Diagram
X,F,0,X or X,X,1,X
Bank
Deselect
0,T,0,1
0,T,0,0
1,T,0,X
X,F,0,X
Deselect
0,T,0,1
0,T,0,0
1,T,0,X or X,X,1,X
1,T,0,X
1,T,0,X
0,T,0,0
0,T,0,1
Read
Write
X,F,0,X
X,F,0,X
0,T,0,1
X,X,1,X
X,X,1,X
0,T,0,0
0,T,0,0
0,T,0,1
1,T,0,X
X,F,0,X
0,T,0,0 0,T,0,1
1,T,0,X
X,F,0,X
Read
Continue
Write
Continue
X,X,1,X
X,X,1,X
n
n+1
n+2
n+3
Key
Input Command Code
Clock (CK)
ƒ
Transition
Current State (n)
Next State (n + 1)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State & Next State Definition for Read/Write Control State Diagram
Notes:
1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively.
2. If (E2 = EP2 and E3 = EP3) then E = “T” else E = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
Rev: 1.04b 06/2001
15/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
VDDQ
VI/O
Description
Value
–0.5 to 2.5
Unit
Voltage on VDD Pins
Voltage in VDDQ Pins
V
V
–0.5 to VDD
–0.5 to VDDQ+0.5 (£ 2.5 V max.)
–0.5 to VDDQ+0.5 (£ 2.5 V max.)
Voltage on I/O Pins
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Maximum Junction Temperature
Storage Temperature
V
VIN
V
IIN
+/–100
+/–100
125
mA dc
mA dc
IOUT
TJ
oC
ºC
TSTG
–55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to
Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended
period of time, may affect reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Symbol
VDD
Min.
1.7
Typ.
1.8
Max.
1.95
VDD
Unit
V
Notes
Supply Voltage
VDDQ
VDDQ
1.8 V I/O Supply Voltage
1.5 V I/O Supply Voltage
1.7
1.8
V
1
1
1.4
1.5
1.6 V
70
V
Ambient Temperature
(Commercial Range Versions)
TA
TA
0
25
25
°C
°C
2
2
Ambient Temperature
(Industrial Range Versions)
–40
85
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V £ VDDQ £ 1.6V (i.e., 1.5 V I/O)
and 1.7 V £ VDDQ £ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
2. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The
part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.04b 06/2001
16/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
CMOS I/O DC Input Characteristics
Parameter
Symbol
VIH
Min.
Typ.
—
Max.
Unit
V
Notes
0.65 * VDDQ
VDD+ 0.3
0.35 * VDDQ
CMOS Input High Voltage
1
1
VIL
CMOS Input Low Voltage
–0.3
—
V
Note:
1. For devices supplied with CMOS input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKC
VDD + 1.0 V
50%
VSS
50%
VDD
VSS – 1.0 V
20% tKC
VIL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Symbol
CIN
Test conditions
Typ.
Max.
Unit
pF
VIN = 0 V
Input Capacitance
4
6
5
7
COUT
VOUT = 0 V
Output Capacitance
pF
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Layer Board
Symbol
RQJA
Max
TBD
TBD
TBD
Unit
Notes
1,2
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
single
four
°C/W
°C/W
°C/W
RQJA
1,2
RQJC
Junction to Case (TOP)
n/a
3
Notes:
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature,
ambient. Temperature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.04b 06/2001
17/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
AC Test Conditions
Parameter
Conditions
VDDQ
Input high level
Input low level
0 V
Max. input slew rate
Input reference level
2 V/ns
VDDQ/2
VDDQ/2
Output reference level
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
ZQ = High (CMOS I/O)
50W
VT = VDDQ/2
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Notes
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–2 uA
2 uA
—
VDD ³ VIN ³ VIL
0V £ VIN £ VIL
–100 uA
–2 uA
2 uA
2 uA
IINM
Mode Pin Input Current
Output Leakage Current
—
—
Output Disable,
VOUT = 0 to VDDQ
IOL
–2 uA
2 uA
Rev: 1.04b 06/2001
18/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Selectable Impedance Output Driver DC Electrical Characteristics
Parameter
Symbol
VOHL
Test Conditions
IOHL = –4 mA
IOLL = 4 mA
Min.
Max
—
Notes
VDDQ – 0.4 V
Low Drive Output High Voltage
Low Drive Output Low Voltage
High Drive Output High Voltage
High Drive Output Low Voltage
1
1
2
2
VOLL
—
0.4 V
—
VOHH
VOLH
IOHH = –8 mA
IOLH = 8 mA
VDDQ – 0.4 V
—
0.4 V
Notes:
1. ZQ = 1; High Impedance output driver setting
2. ZQ = 0; Low Impedance output driver setting
Rev: 1.04b 06/2001
19/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Operating Currents
-333
-300
-250
Parameter
Symbol
Test Conditions
0°C to
70°C
–40°C to
+85°C
0°C to
70°C
–40°C to
+85°C
0°C to
70°C
–40°C to
+85°C
IDDP
Pipeline
650 mA TBD mA 600 mA TBD mA 525 mA TBD mA
TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA
475 mA TBD mA 445 mA TBD mA 395 mA TBD mA
TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA
250 mA TBD mA 240 mA TBD mA 225 mA TBD mA
TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA
215 mA TBD mA 210 mA TBD mA 200 mA TBD mA
TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA
250 mA TBD mA 240 mA TBD mA 225 mA TBD mA
TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA
215 mA TBD mA 210 mA TBD mA 200 mA TBD mA
TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA
x36
IDDF
Flow-through
E1 £ VIL Max.
Operating
Current
tKHKH ³ tKHKH Min.
All other inputs
IDDP
Pipeline
VIL ³ VIN ³ VIH
x18
x36
IDDF
Flow-through
ISB1
Pipeline
ISB1
Flow-through
E1 ³ VIH Min. or
Chip Disable
Current
tKHKH ³ tKHKH Min.
All other inputs
ISB1
Pipeline
VIL ³ VIN ³ VIH
x18
x36
ISB1
Flow-through
ISB2
Pipeline
ISB2
Flow-through
E2 or E3 False
tKHKH ³ tKHKH Min.
All other inputs
Bank Deselect
Current
ISB2
Pipeline
VIL ³ VIN ³ VIH
x18
ISB2
Flow-through
Device Deselected
All inputs
CMOS
Deselect
Current
VSS + 0.10 V
IDD3
150 mA
³ VIN
³
VDD – 0.10 V
Rev: 1.04b 06/2001
20/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
AC Electrical Characteristics
-333
-300
-250
Parameter
Symbol
Unit Notes
Min Max Min Max
Min
4.0
1.5
1.5
0.5
0.5
Max
—
Clock Cycle Time
Clock High Time
tKHKH
tKHKL
tKLKH
tKHCX1
tKHCH
tCHCL
tKLCL
3.0
1.2
1.2
0.5
0.5
—
—
3.3
1.3
1.3
0.5
0.5
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
2
—
Clock Low Time
—
—
—
Clock High to Echo Clock Low-Z
Clock High to Echo Clock High
Echo Clock High Time
—
—
—
1.5
1.7
2.0
—
2
tKHKL +/- 100 ps
1.5 0.5
tKLKH _/- 100 ps
tKHKL +/- 120 ps
0.5 2.0
tKHKL +/- 120 ps
Clock Low to Echo Clock Low
Echo Clock Low Time
0.5
1.7
tCLCH
tKHCZ
tKHQX1
tKHQV
tKLQX
tKLQV
tKHQX
tKHQZ
tCHQV
tCLQX
tCLQV
tCHQX
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tBVKH
tKHBX
tDVKH
2
1, 2
1
Clock High to Echo Clock High-Z
Clock High to Output in Low-Z
Clock High to Output Valid
Clock Low to Output Invalid
Clock Low to Output Valid
Clock High to Output Invalid
Clock High to Output in High-Z
Echo Clock High to Output Valid
Echo Clock Low to Output Invalid
Echo Clock Low to Output Valid
Echo Clock High to Output Invalid
Address Valid to Clock High
Clock High to Address Don’t Care
Enable Valid to Clock High
Clock High to Enable Don’t Care
Write Valid to Clock High
0.5
0.5
1.5
—
0.5
0.5
1.7
—
0.5
0.5
2.0
—
1.6
1.6
—
1.8
1.8
—
2.1
2.1
—
—
—
—
—
1
0.5
0.5
0.5
—
0.5
0.5
0.5
—
0.5
0.5
—
—
—
1.6
0.2
—
1.8
0.2
—
0.5
2.1
0.25
—
—
2
–0.2
—
–0.2
—
–0.25
—
2
0.2
—
0.2
—
0.25
—
2
-0.2
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.32
-0.2
0.7
0.4
0.7
0.4
0.7
0.4
0.7
0.4
0.35
-0.25
0.8
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
—
—
—
0.8
—
—
—
0.5
—
—
—
0.8
—
Clock High to Write Don’t Care
Byte Write Valid to Clock High
Clock High to Byte Write Don’t Care
Data In Valid to Clock High
Notes:
—
—
0.5
—
—
—
0.8
—
—
—
0.5
—
—
—
0.40
—
1. Measured at 100 mV from steady state. Not 100% tested.
2. Guaranteed by design. Not 100% tested.
3. For any specific temperature and voltage tKHCZ < tKHCX1.
Rev: 1.04b 06/2001
21/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
-333
-300
-250
Parameter
Symbol
Unit Notes
Min Max Min Max
Min
0.35
0.40
0.35
0.8
Max
—
Clock High to Data In Don’t Care
Data In Valid to Clock Low
tKHDX
tDVKL
0.27
0.32
0.27
0.6
—
—
—
—
—
0.30
0.35
0.30
0.7
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
Clock Low to Data In Don’t Care
ADV Valid to Clock High
tKLDX
—
tadvVKH
tKHadvX
—
—
—
Clock High to ADV Don’t Care
0.4
0.4
0.5
—
Notes:
1. Measured at 100 mV from steady state. Not 100% tested.
2. Guaranteed by design. Not 100% tested.
3. For any specific temperature and voltage tKHCZ < tKHCX1.
Rev: 1.04b 06/2001
22/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Timing Parameter Key—Read Cycle Timing
tKHKH
tKHKL
CK
tKHAX
tKLKH
tAVKH
C
D
A
E
tKHQZ
tKHQX
tKLQV
tKLQX
tKHQV
tKHQX1
DQ (DDR)
QB1
QB2
tCLQX
tCHQX
tCHQV
tCLQV
tKHCH
tKHCX1
tCHCL
tCLCH
tKHCZ
CQ
= CQ High Z
Rev: 1.04b 06/2001
23/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Timing Parameter Key—Control and Data In Timing
CK
tKHAX
tAVKH
A
B
A
C
tnVKH
tKHnX
E1, E2, E3,
W, Bn, ADV
tDVKH
tKHDX
DQ (Data In)
DDR Write
DA1
DA2
DB1
DB2
tDVKL
tKLDX
Note: tnVKH = tEVKH, tWVKH, tBVKH, etc. and tKHnX = tKHEX, tKHWX, tKHBX, etc.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to
VDD. TDO should be left unconnected.
Rev: 1.04b 06/2001
24/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the state
In of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction
Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same
result as a logic one input level.
Test Data In
Output that is active depending on the state of the TAP state machine. Output changes in response
to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.
TDO
Test Data Out
Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held
high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP registers are serial shift registers that capture serial input data on the
rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
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© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Bit #
9 8 7 6 5 4 3 2 1
0
x36
x18
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
1
1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads. This device will not
perform INTEST but can perform the preload portion of the SAMPLE/PRELOAD command.
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© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state, the Instruction Register is placed between TDI and TDO. In this state the
desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all
instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP
instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
0
Select IR
0
0
1
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
1
Exit1 DR
0
Exit1 IR
0
Pause DR
1
Pause IR
1
0
0
0
0
Exit2 DR
1
Exit2 IR
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified
in the BSDL file. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O
ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAP’s input
data capture set-up plus hold time (tTS plus tTH ). The RAM’s clock inputs need not be paused for any other TAP operation except capturing
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© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the Boundary Scan Register
between the TDI and TDO pins. The Update-DR controller state transfers the contents of boundary scan cells into the holding register of
each cell associated with an output pin on the RAM.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.
The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input
pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the state of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are sampled
and transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state. Boundary Scan Register con-
tents may then be shifted serially through the register using the Shift-DR command or the controller can be skipped to the Update-DR com-
mand. When the controller is placed in the Update-DR state, a RAM that has a fully compliant EXTEST function drives out the value of the
Boundary Scan Register location associated with which each output pin.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z/PRELOAD
The SAMPLE-Z instruction operates exactly like SAMPLE/PRELOAD except that loading the SAMPLE-Z instruction forces all the RAM’s
output drivers, except TDO, to an inactive drive state (high-Z).
RFU
These instructions are reserved for future use. In this device they replicate the BYPASS instruction.
Rev: 1.04b 06/2001
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© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
JTAG TAP Instruction Set Summary
Instruction
EXTEST
IDCODE
Code
Description
Notes
1
000 Places the Boundary Scan Register between TDI and TDO.
001 Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all Data and Clock output drivers to High-Z.
010
011
1
1
1
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI Private
RFU
101 GSI Private instruction.
1
1
1
110 Do not use this instruction; Reserved for Future Use.
111 Places Bypass Register between TDI and TDO.
BYPASS
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in Test-Logic-Reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
VIHT
Min.
Max.
Unit
V
Notes
0.65 * VDD
VDD+0.3
0.35 * VDD
Test Port Input High Voltage
1
1
VILT
Test Port Input Low Voltage
–0.3
V
IINTH
IINTL
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
–100
2
uA
uA
uA
V
2
–2
–2
2
2
3
IOLT
4
VOHT
VOLT
VDDQ – 100 mV
—
5, 6
7
—
100 mV
V
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDD + 1 V with a pulse width not to exceed 20% tTKC.
2. VDD ³ VIN ³ VIL
3. 0 V £ VIN £ VIL
4. Output Disable, VOUT = 0 to VDD
5. The TDO output driver is served by the VDD supply.
6. IOH = –100 uA
7. IOL = +100 uA
Rev: 1.04b 06/2001
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© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
JTAG Port AC Test Conditions
Parameter
Conditions
JTAG Port AC Test Load
VDD – 200 mV
Input high level
Input low level
DQ
200 mV
1 V/ns
VDD/2
Input slew rate
50W
Input reference level
VT = VDD/2
VDD/2
Output reference level
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
JTAG Port Timing Diagram
tTKL
tTKH
tTKC
TCK
tTS
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
TCK Cycle Time
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
ns
20
20
10
10
ns
—
ns
—
ns
tTH
—
ns
Rev: 1.04b 06/2001
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© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
209 BGA Package Drawing
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
A1
C
A
Side View
D
aaa
D1
e
Bottom View
Æb
e
Symbol
Min
Typ
Max
1.70
0.60
0.70
0.38
22.1
Units
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
A
A1
Æb
c
0.40
0.50
0.31
21.9
0.50
0.60
0.36
D
22.0
D1
E
18.0 (BSC)
14.0
13.9
14.1
E1
e
10.0 (BSC)
1.00 (BSC)
0.15
aaa
Rev 1.0
Rev: 1.04b 06/2001
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© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
Preliminary
GS8170D18/36B-333/300/250
Ordering Information—GSI SigmaRAM
T
Speed
1
Org
Type
Package
Part Number
3
(MHz)
333
300
250
333
300
250
333
300
250
333
300
250
A
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
1Mx 18
GS8170D36B-333
GS8170D36B-300
GS8170D36B-250
GS8170D36B-333I
GS8170D36B-300I
GS8170D36B-250I
GS8170D18B-333
GS8170D18B-300
GS8170D18B-250
GS8170D18B-333I
GS8170D18B-300I
GS8170D18B-250I
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
1 mm Pitch, 209-Pin BGA
C
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
S1x2 SRAM
C
C
I
I
I
C
C
C
I
1Mx 18
1Mx 18
1Mx 18
1Mx 18
I
1Mx 18
I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example:
GS817x72B-300T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
Rev: 1.04b 06/2001
32/32
© 2001, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
D
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