GS816272GC-225I [GSI]
Cache SRAM, 256KX72, 6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209;型号: | GS816272GC-225I |
厂家: | GSI TECHNOLOGY |
描述: | Cache SRAM, 256KX72, 6ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209 静态存储器 |
文件: | 总43页 (文件大小:1491K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
GS816218(B/D)/GS816236(B/D)/GS816272(C)
250 MHz–133MHz
119-, 165- & 209-Pin BGA 1M x 18, 512K x 36, 256K x 72
Commercial Temp
Industrial Temp
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
18Mb S/DCD Sync Burst SRAMs
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
• Automatic power-down for portable applications
• JEDEC-standard 119-, 165-, and 209-bump BGA package
SCD and DCD Pipelined Reads
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is a SCD
(Single Cycle Deselect) and DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. DCD SRAMs pipeline disable
commands to the same degree as read commands. SCD SRAMs
pipeline deselect commands one stage less than read commands.
SCD RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers. DCD
RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
t
2.5 2.7 3.0 3.4 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.7 7.5 ns
KQ
tCycle
Curr (x18) 280 255 230 200 185 165 mA
Curr (x36) 330 300 270 230 215 190 mA
Curr (x72) 430 395 350 300 270 245 mA
3.3 V
2.5 V
Curr (x18) 275 250 230 195 180 165 mA
Curr (x36) 320 295 265 225 210 185 mA
Curr (x72) 410 380 335 290 260 235 mA
Flow
Through
2-1-1-1
Byte Write and Global Write
t
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
KQ
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
tCycle
Curr (x18) 175 165 160 150 145 135 mA
Curr (x36) 200 190 180 170 165 150 mA
Curr (x72) 255 240 225 115 210 185 mA
3.3 V
2.5 V
Curr (x18) 175 165 160 150 145 135 mA
Curr (x36) 200 190 180 170 165 150 mA
Curr (x72) 255 240 225 115 210 185 mA
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Functional Description
Applications
Sleep Mode
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is an
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs,
the device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip set
support.
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS816218(B/D)/GS816236(B/D)/GS816272(C) operates on
a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V
compatible. Separate output power (VDDQ) pins are used to
Controls
decouple output noise from the internal circuits and are 3.3 V and
2.5 V compatible.
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
Rev: 2.15a 9/2002
1/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816272 Pad Out
209 Bump BGA—Top View
Package C
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
DQG5
DQG6
DQG7
DQG8
DQG9
DQC4
DQC3
DQC2
DQC1
NC
DQG1
DQG2
DQG3
DQG4
DQC9
DQC8
DQC7
DQC6
DQC5
NC
A15
E2
ADSP
NC
ADSC
BW
E1
ADV
A16
NC
E3
A17
DQB1
DQB2
DQB3
DQB4
DQF9
DQF8
DQF7
DQF6
DQF5
NC
DQB5
DQB6
DQB7
DQB8
DQB9
DQF4
DQF3
DQF2
DQF1
NC
BC
BG
BB
BF
BH
BD
NC
BE
BA
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
CK
NC
NC
G
GW
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
PE
NC
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
VDD
ZQ
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
G
H
J
MCH
MCL
MCL
MCL
FT
K
L
DQH1
DQH2
DQH3
DQH4
DQD9
DQD8
DQD7
DQD6
DQD5
DQH5
DQH6
DQH7
DQH8
DQH9
DQD4
DQD3
DQD2
DQD1
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
NC
DQA5
DQA6
DQA7
DQA8
DQA9
DQE4
DQE3
DQE2
DQE1
DQA1
DQA2
DQA3
DQA4
DQE9
DQE8
DQE7
DQE6
DQE5
M
N
P
R
T
MCL
SCD
ZZ
VDD
LBO
A12
A1
U
V
A14
A13
A7
A11
A6
A10
A9
A8
A5
A4
W
TMS
TDI
A3
A0
A2
TDO
TCK
Rev 10
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
Rev: 2.15a 9/2002
2/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816272 BGA Pin Description
Symbol
A0, A1
An
Type
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
I
I
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
DQE1–DQE9
DQF1–DQF9
DQG1–DQG9
DQH1–DQH9
I/O
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD, DQE,
DQF, DQG, DQH I/Os; active low
I
BA, BB, BC,BD, BE, BF, BG,BH
NC
CK
—
I
No Connect
Clock Input Signal; active high
I
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
GW
I
E1, E3
E2
I
Chip Enable; active high
I
Output Enable; active low
G
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
ADV
ADSP, ADSC
ZZ
I
I
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Single Cycle Deselect/Dual Cycle Deselect Mode Control
Must Connect High
FT
I
LBO
SCD
MCH
MCL
PE
I
I
Must Connect Low
I
I
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
Byte Enable; active low
BW
FLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
I
ZQ
I
I
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
TMS
TDI
O
I
TDO
TCK
V
I
Core power supply
DD
V
I
I
I/O and Core Ground
SS
V
Output driver power supply
DDQ
Rev: 2.15a 9/2002
3/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
165 Bump BGA—x18 Commom I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BB
NC
E3
BW
ADSC
ADV
A19
A
B
C
D
E
F
NC
NC
A
E2
NC
BA
CK
GW
G
ADSP
A
NC
NC
NC
NC
NC
ZQ
NC
DQA
DQA
DQA
DQA
DQA
ZZ
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DQB
DQB
DQB
DQB
MCL
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
NC
G
H
J
NC
G
H
J
FT
NC
NC
DQB
DQB
DQB
DQB
DQB
NC
V
V
DQA
DQA
DQA
DQA
NC
A
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
NC
V
V
V
V
V
V
V
V
NC
K
L
NC
NC
M
N
P
R
NC
NC
M
N
P
R
SCD
NC
V
NC
TDI
A18
A1
NC
V
NC
DDQ
SS
SS
DDQ
A
A
A
TDO
TCK
A
A
A
A17
A
LBO
NC
A
TMS
A0
A
A
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 2.15a 9/2002
4/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
165 Bump BGA—x36 Common I/O—Top View (Package D)
1
2
3
4
5
6
7
8
9
10
A
11
A
B
C
D
E
F
NC
A
E1
BC
BB
E3
BW
ADSC
ADV
NC
A
B
C
D
E
F
NC
A
E2
BD
BA
CK
GW
G
ADSP
A
NC
DQB
DQB
DQB
DQB
DQB
ZZ
DQC
DQC
DQC
DQC
DQC
FT
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
DDQ
DDQ
DDQ
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDQ
DDQ
DDQ
DDQ
DDQ
DQC
DQC
DQC
DQC
MCL
DQD
DQD
DQD
DQD
SCD
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQB
DQB
DQB
DQB
ZQ
G
H
J
G
H
J
NC
NC
DQD
DQD
DQD
DQD
DQD
NC
V
V
DQA
DQA
DQA
DQA
NC
DQA
DQA
DQA
DQA
DQA
A17
A
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
K
L
V
V
V
V
V
V
V
V
K
L
M
N
P
R
M
N
P
R
V
NC
TDI
A18
A1
NC
V
SS
DDQ
SS
DDQ
A
A
A
TDO
TCK
A
A
A
A
LBO
NC
A
TMS
A0
A
A
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 2.15a 9/2002
5/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816236 Pad Out
119-Bump BGA—Top View
Package B
1
2
3
4
ADSP
ADSC
VDD
ZQ
5
6
7
VDDQ
NC
A6
A7
A8
A9
VDDQ
NC
A
A18
A4
A15
A14
VSS
VSS
VSS
BB
A17
B
C
D
E
F
NC
A5
A3
A16
NC
DQC4
DQC3
VDDQ
DQC2
DQC1
VDDQ
DQD1
DQD2
VDDQ
DQD3
DQD4
NC
DQC9
DQC8
DQC7
DQC6
DQC5
VDD
DQD5
DQD6
DQD7
DQD8
DQD9
A2
VSS
VSS
VSS
BC
DQB9
DQB8
DQB7
DQB6
DQB5
VDD
DQA5
DQA6
DQA7
DQA8
DQA9
A13
DQB4
DQB3
VDDQ
DQB2
DQB1
VDDQ
DQA1
DQA2
VDDQ
DQA3
DQA4
PE
E1
G
ADV
GW
VDD
CK
G
H
J
VSS
NC
VSS
BD
VSS
NC
VSS
BA
K
L
SCD
BW
A1
VSS
VSS
VSS
LBO
A10
TDI
VSS
VSS
VSS
FT
M
N
P
R
T
A0
VDD
A11
NC
NC
A12
TDO
NC
ZZ
VDDQ
TMS
TCK
NC
VDDQ
U
Rev: 2.15a 9/2002
6/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816218 Pad Out
119-Bump BGA—Top View
Package B
1
2
A6
3
4
ADSP
ADSC
VDD
ZQ
5
6
7
VDDQ
NC
A7
A8
A9
VDDQ
NC
A
A18
A4
A15
A14
VSS
VSS
VSS
NC
A17
B
C
D
E
F
NC
A5
A3
A16
NC
DQB1
NC
NC
VSS
VSS
VSS
BB
DQA9
NC
NC
DQB2
NC
E1
DQA8
VDDQ
DQA6
NC
VDDQ
NC
G
DQA7
NC
DQB3
NC
VDD
DQB5
NC
ADV
GW
VDD
CK
G
H
J
DQB4
VDDQ
NC
VSS
NC
VSS
NC
VSS
VSS
VSS
LBO
A11
TDI
VSS
NC
DQA5
VDD
NC
VDDQ
DQA4
NC
VSS
BA
K
L
DQB6
VDDQ
DQB8
NC
SCD
BW
A1
DQA3
NC
DQB7
NC
VSS
VSS
VSS
FT
VDDQ
NC
M
N
P
R
T
DQA2
NC
DQB9
A2
A0
DQA1
PE
NC
VDD
NC
A13
NC
A10
A12
TDO
A19
ZZ
VDDQ
TMS
TCK
NC
VDDQ
U
BPR1999.05.18
Rev: 2.15a 9/2002
7/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816218/36 BGA Pin Description
Symbol
A0, A1
An
Type
Description
I
I
Address field LSBs and Address Counter Preset Inputs
Address Inputs
DQA1–DQA9
DQB1–DQB9
DQC1–DQC9
DQD1–DQD9
I/O
Data Input and Output pins
BA, BB, BC, BD
I
—
I
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version)
No Connect
NC
CK
Clock Input Signal; active high
BW
I
Byte Write—Writes all enabled bytes; active low
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
GW
I
E1
I
G
ADV
I
Output Enable; active low
I
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
ADSP, ADSC
ZZ
I
I
FT
I
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
LBO
I
FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
ZQ
I
SCD
TMS
TDI
I
I
Single Cycle Deselect/Dual Cyle Deselect Mode Control
Scan Test Mode Select
Scan Test Data In
I
O
I
Scan Test Data Out
TDO
TCK
PE
Scan Test Clock
I
Parity Bit Enable; active low
Core power supply
V
I
DD
V
I
I/O and Core Ground
SS
V
I
Output driver power supply
DDQ
Rev: 2.15a 9/2002
8/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816218/36 (PE = 0) Block Diagram
RegisteQr
A0–An
D
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
A
Load
LBO
ADV
CK
Memory
Array
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
Register
D
Q
BB
BC
BD
4
4
Register
D
Q
Register
D
Q
Register
36
D
Q
36
36
32
Register
E1
D
Q
4
36
Parity
Register
Encode
4
D
Q
Parity
Compare
FT
G
36
SCD
Power Down
Control
DQx1–DQx9
NC
NC
ZZ
Note: Only x36 version shown for simplicity.
Rev: 2.15a 9/2002
9/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
GS816218/36 (PE = 1) x32 Mode Block Diagram
RegisteQr
A0–An
D
A0
A1
A0
A1
D0
D1
Q0
Q1
Counter
A
Load
LBO
ADV
CK
Memory
Array
ADSC
ADSP
Q
D
Register
GW
BW
BA
D
Q
36
36
4
Parity
Register
Encode
D
Q
BB
BC
BD
32
4
Register
D
Q
Register
D
Q
Register
32
D
Q
36
Register
36
D
Q
Register
E1
D
Q
4
32
32
Register
Parity
D
Q
Register
Encode
D
Q
4
Parity
Compare
FT
G
32
SCD
Power Down
Control
DQx1–DQx8
NC
NC
ZZ
Note: Only x36 version shown for simplicity.
Rev: 2.15a 9/2002
10/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Mode Pin Functions
Mode Name
Pin
Name
State
Function
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Burst Order Control
Output Register Control
LBO
H
L
H or NC
L or NC
H
FT
Active
Power Down Control
ZZ
Standby, I = I
DD SB
L
Dual Cycle Deselect
Single Cycle Deselect
Single/Dual Cycle Deselect Control
SCD
ZQ
H or NC
L
High Drive (Low Impedance)
Low Drive (High Impedance)
FLXDrive Output Impedance Control
Note:
H or NC
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,
x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE
deactivates the 9th I/O of each byte.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.15a 9/2002
11/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Byte Write Truth Table
Function
Read
GW
H
BW
H
L
BA
X
BB
X
BC
X
BD
X
Notes
1
Read
H
H
L
H
H
L
H
H
H
L
H
H
H
H
L
1
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
H
L
2, 3
H
L
H
H
H
L
2, 3
H
L
H
H
L
2, 3, 4
2, 3, 4
2, 3, 4
H
L
H
L
H
L
L
L
X
X
X
X
X
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x36 version.
Rev: 2.15a 9/2002
12/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Synchronous Truth Table
Operation
State
3
4
Diagram
Address Used
E1
ADSP ADSC
ADV
W
DQ
5
Key
Deselect Cycle, Power Down
Read Cycle, Begin Burst
None
External
External
External
Next
X
R
H
L
X
L
L
X
L
X
X
X
X
L
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
R
L
L
X
H
X
H
X
H
X
H
H
H
H
X
H
X
H
X
H
X
W
L
CR
CR
CW
CW
H
H
H
H
H
H
H
H
Next
L
Next
L
Next
L
Current
Current
Current
Current
H
H
H
H
Notes:
1. X = Don’t Care, H = High, L = Low
2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding
3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 2.15a 9/2002
13/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Simplified State Diagram
X
Deselect
W
R
W
R
X
R
X
First Write
First Read
CW
CR
CR
W
R
R
X
Burst Write
X
Burst Read
CR
CW
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
Rev: 2.15a 9/2002
14/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Simplified State Diagram with G
X
Deselect
W
R
W
R
X
W
R
X
First Write
First Read
CR
CW
CW
CR
W
R
R
W
X
Burst Write
X
Burst Read
CR
CW
CW
CR
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
Rev: 2.15a 9/2002
15/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Absolute Maximum Ratings
(All voltages reference to V )
SS
Symbol
Description
Value
Unit
V
V
Voltage on V Pins
–0.5 to 4.6
–0.5 to 4.6
–0.5 to 6
DD
DD
V
Voltage in V
Pins
DDQ
V
DDQ
V
Voltage on Clock Input Pin
Voltage on I/O Pins
V
CK
V
–0.5 to V
+0.5 (≤ 4.6 V max.)
DDQ
V
I/O
V
–0.5 to V +0.5 (≤ 4.6 V max.)
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
V
IN
DD
I
+/–20
+/–20
mA
mA
W
IN
I
OUT
P
1.5
D
o
T
–55 to 125
–55 to 125
C
STG
o
T
Temperature Under Bias
C
BIAS
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Rev: 2.15a 9/2002
16/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Power Supply Voltage Ranges
Parameter
Symbol
Min.
3.0
Typ.
3.3
Max.
3.6
Unit
Notes
V
3.3 V Supply Voltage
2.5 V Supply Voltage
V
V
V
V
DD3
V
2.3
2.5
2.7
DD2
3.3 V V
2.5 V V
I/O Supply Voltage
I/O Supply Voltage
V
3.0
3.3
3.6
DDQ
DDQ
DDQ3
V
2.3
2.5
2.7
DDQ2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
V
Range Logic Levels
Parameter
DDQ3
Symbol
Min.
2.0
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
V
Input Low Voltage
V
–0.3
2.0
—
0.8
+ 0.3
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
V
—
1,3
1,3
DDQ
IHQ
DDQ
V
V
–0.3
—
0.8
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
V
Range Logic Levels
Parameter
DDQ2
Symbol
Min.
Typ.
—
Max.
Unit
Notes
V
Input High Voltage
V
0.6*V
V
+ 0.3
DD
V
V
V
V
1
DD
IH
DD
V
Input Low Voltage
V
0.3*V
DD
–0.3
—
1
DD
IL
V
I/O Input High Voltage
I/O Input Low Voltage
V
0.6*V
V
+ 0.3
DDQ
—
1,3
1,3
DDQ
IHQ
DD
V
V
0.3*V
DD
–0.3
—
DDQ
ILQ
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Rev: 2.15a 9/2002
17/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Recommended Operating Temperatures
Parameter
Symbol
Min.
0
Typ.
25
Max.
70
Unit
°C
Notes
T
Ambient Temperature (Commercial Range Versions)
2
2
A
T
Ambient Temperature (Industrial Range Versions)
Note:
–40
25
85
°C
A
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are
evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
o
(T = 25 C, f = 1 MHZ, V = 2.5 V)
A
DD
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
pF
C
V
= 0 V
Input Capacitance
4
6
5
7
IN
IN
C
V
OUT
= 0 V
Input/Output Capacitance
pF
I/O
Note: These parameters are sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
Max
40
Unit
Notes
1,2
R
R
R
single
four
—
°C/W
°C/W
°C/W
ΘJA
ΘJA
ΘJC
24
1,2
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 2.15a 9/2002
18/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
AC Test Conditions
Parameter
Conditions
V
– 0.2 V
Input high level
Input low level
DD
0.2 V
1 V/ns
/2
Input slew rate
V
Input reference level
DD
V
/2
Output reference level
Output load
DDQ
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
Output Load 1
DQ
*
50Ω
30pF
V
DDQ/2
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
I
V = 0 to V
IN DD
–1 uA
1 uA
IL
V
≥ V ≥ V
IN
–1 uA
–1 uA
1 uA
100 uA
DD
IH
IH
I
I
ZZ and PE Input Current
FT, SCD, ZQ Input Current
IN1
IN2
0 V ≤ V ≤ V
IN
V
≥ V ≥ V
IN
–100 uA
–1 uA
1 uA
1 uA
DD
IL
IL
0 V ≤ V ≤ V
IN
I
Output Disable, V
= 0 to V
DD
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
OL
OUT
DDQ
DDQ
V
V
I
I
= –8 mA, V
= –8 mA, V
= 2.375 V
= 3.135 V
OH2
OH3
OH
OH
—
V
I
= 8 mA
OL
0.4 V
OL
Rev: 2.15a 9/2002
19/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Rev: 2.15a 9/2002
20/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
AC Electrical Characteristics
-250
-225
-200
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
4.0
—
—
2.5
—
—
—
—
—
5.5
—
—
—
—
—
—
4.4
—
—
2.7
—
—
—
—
—
6.0
—
—
—
—
—
—
5.0
—
—
3.0
—
—
—
—
—
6.5
—
—
—
—
—
—
6.0
—
—
3.4
—
—
—
—
—
7.0
—
—
—
—
—
—
6.7
—
—
3.8
—
—
—
—
—
7.5
—
—
—
—
—
—
7.5
—
1.5
1.5
1.5
0.5
8.5
—
3.0
3.0
1.5
0.5
1.7
2
—
4.0
—
—
—
—
—
8.5
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKQX
1.5
1.5
1.2
0.2
5.5
—
3.0
3.0
1.5
0.5
1.3
1.5
1.5
1.5
1.3
0.3
6.0
—
3.0
3.0
1.5
0.5
1.3
1.5
1.5
1.5
1.4
0.4
6.5
—
3.0
3.0
1.5
0.5
1.3
1.5
1.5
1.5
1.5
0.5
7.0
—
3.0
3.0
1.5
0.5
1.3
1.5
1.5
1.5
1.5
0.5
7.5
—
3.0
3.0
1.5
0.5
1.5
1.7
Pipeline
1
tLZ
tS
tH
Hold time
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Setup time
tKC
tKQ
tKQX
Flow
Through
1
tLZ
tS
tH
Hold time
Clock HIGH Time
Clock LOW Time
tKH
tKL
Clock to Output in
High-Z
1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0 1.5 3.0 1.5 3.0
ns
tHZ
G to Output Valid
G to output in Low-Z
G to output in High-Z
ZZ setup time
tOE
—
0
2.3
—
2.3
—
—
—
—
0
2.5
—
2.5
—
—
—
—
0
3.2
—
3.0
—
—
—
—
0
3.5
—
3.0
—
—
—
—
0
3.8
—
3.0
—
—
—
—
0
4.0
—
3.0
—
—
—
ns
ns
ns
ns
ns
ns
1
tOLZ
tOHZ
1
—
5
—
5
—
5
—
5
—
5
—
5
2
tZZS
tZZH
2
ZZ hold time
1
1
1
1
1
1
ZZ recovery
tZZR
20
20
20
20
20
20
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Rev: 2.15a 9/2002
21/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Write Cycle Timing
Single Write
Burst Write
Deselected
Write
CK
tH
tS
ADSP is blocked by E inactive
tKC
tKL
tKH
ADSP
tS tH
ADSC initiated write
ADSC
tH
tS
ADV
ADV must be inactive for ADSP Write
tH
tS
WR2
WR3
WR1
A0–An
tS tH
GW
BW
tH
tS
tS
tH
WR3
WR1
WR2
BA–BD
tS
tH
E1 masks ADSP
E1
E1 only sampled with ADSP or ADSC
G
tS
tH
Write specified byte for 2A and all bytes for 2B, 2C& 2D
Hi-Z
D1A
D2C
D2D
D3A
DQA–DQD
D2A
D2B
Rev: 2.15a 9/2002
22/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Flow Through Read Cycle Timing
Single Read
Burst Read
tKL
CK
tS
tKH
tS
tH
ADSP is blocked by E inactive
tKC
ADSP
ADSC
ADV
tH
ADSC initiated read
tH
tS
Suspend Burst
Suspend Burst
tS
tH
RD1
RD2
RD3
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
tH
tS
E1 masks ADSP
E1
G
tOHZ
tOE
tKQX
tKQX
tHZ
tOLZ
Hi-Z
Q2B
Q2c
Q3A
Q1A
Q2A
Q2D
DQA–DQD
tLZ
tKQ
Rev: 2.15a 9/2002
23/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Flow Through Read-Write Cycle Timing
Single Write
Burst Read
Single Read
CK
tS tH
tKC
ADSP is blocked by E inactive
ADSC initiated read
tKH tKL
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0–An
tS tH
tS
GW
tH
BW
tS
tH
BA–BD
WR1
tS
tH
E1 masks ADSP
E1
tOHZ
tOE
G
tS
tH
tKQ
Hi-Z
DQA–DQD
Q1A
D1A
Q2A
Burst wrap around to it’s initial state
Q2A
Q2B
Q2c
Q2D
Rev: 2.15a 9/2002
24/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Pipelined SCD Read Cycle Timing
Single Read
Burst Read
CK
tKL
tKH
tH
tH
tS
tKC
ADSP is blocked by E inactive
ADSP
ADSC
tS
ADSC initiated read
tS
tH
Suspend Burst
ADV
A0–An
GW
tH
tS
RD2
RD3
RD1
tS
tS
tH
tH
BW
BWA–BWD
tH
tS
E1 masks ADSP
E1
tOE
G
tOHZ
tKQX
Q3A
tKQX
tOLZ
tLZ
Hi-Z
DQA–DQD
Q1A
Q2A
Q2B
Q2D
Q2c
tHZ
tKQ
Rev: 2.15a 9/2002
25/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Pipelined SCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tH
tS
tKH
tKC
ADSP is blocked by E inactive
ADSC initiated read
ADSP
ADSC
tS tH
tS tH
ADV
tS
tH
RD2
WR1
RD1
A0–An
tS
tH
GW
BW
tS
tH
tH
tS
WR1
BWA– BWD
E1
tS
tH
E1 masks ADSP
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2B
Q2c
DQA–DQD
Q2D
Rev: 2.15a 9/2002
26/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Pipelined DCD Read Cycle Timing
Single Read
Burst Read
tKL
CK
tH
tS
ADSP is blocked by E1 inactive
tKC
tKH
ADSP
tS tH
ADSC initiated read
ADSC
ADV
tS
tH
Suspend Burst
tS
tH
RD1
RD3
RD2
A0–An
GW
tS
tS
tH
tH
BW
BA–BD
tS tH
E1 masks ADSP
E1
tOE
tKQ
G
tOHZ
tKQX
Q2A
tKQX
Q3A
tOLZ
tLZ
Hi-Z
Q1A
Q2B
Q2D
Q2c
DQA–DQD
tHZ
Rev: 2.15a 9/2002
27/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Pipelined DCD Read-Write Cycle Timing
Single Write
Single Read
Burst Read
tKL
CK
tS
tH
tKH
tKC
ADSP is blocked by E1 inactive
ADSP
tS tH
ADSC initiated read
ADSC
ADV
tS
tH
tH
tS
tH
RD1
RD2
A0–An
WR1
tS
GW
tS
tH
BW
tH
tS
WR1
BA–BD
tS tH
E1 masks ADSP
E1
tOE
tOHZ
G
tS
tH
tKQ
Hi-Z
Q1A
D1A
Q2A
Q2B
DQA–DQD
Q2c
Q2D
Rev: 2.15a 9/2002
28/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I 2. The duration of
SB
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
SB
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tH
tS
tKC
tKL
tKH
ADSP
ADSC
ZZ
tZZH
tZZS
tZZR
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 2.15a 9/2002
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© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V . The JTAG output
DD
drivers are powered by V
.
DDQ
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V or V . TDO should be left unconnected.
DD
SS
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TCK
Test Clock
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
TMS
TDI
Test Mode Select
Test Data In
In controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
TDO
Test Data Out
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and
0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising
edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI
and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 2.15a 9/2002
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© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
0
Bypass Register
2
1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
2 1 0
·
· · ·
Boundary Scan Register
n
2 1 0
· · · · · · · · ·
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Not Used
Configuration
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
1
1
1
1
1
x72
x36
x32
x18
x16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Rev: 2.15a 9/2002
31/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
Select IR
0
0
0
1
1
1
1
Capture DR
Capture IR
0
0
Shift DR
Shift IR
0
0
1
1
Exit1 DR
Exit1 IR
0
0
Pause DR
Pause IR
0
0
0
0
1
1
Exit2 DR
Exit2 IR
1
1
Update DR
Update IR
1
0
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
Rev: 2.15a 9/2002
32/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the
Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it
is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although
allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be
paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-
DR state then places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The
EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK
when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-
ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the
value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID
register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any
time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Bound-
ary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 2.15a 9/2002
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© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
JTAG TAP Instruction Set Summary
Instruction
EXTEST
IDCODE
Code
000
001
Description
Notes
1
1, 2
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
SAMPLE-Z
010
011
TDO.
1
1
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
RFU
SAMPLE/
PRELOAD
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
100
101
110
111
1
1
1
1
GSI
RFU
BYPASS
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 2.15a 9/2002
34/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
2.0
Max.
Unit Notes
V
V
V
+0.3
DD3
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
2.5 V Test Port Input High Voltage
2.5 V Test Port Input Low Voltage
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
TDO Output Leakage Current
V
V
1
1
IHJ3
V
–0.3
0.8
+0.3
ILJ3
V
0.6 * V
V
1
IHJ2
DD2
DD2
V
0.3 * V
1
–0.3
–300
–1
V
1
ILJ2
DD2
I
uA
uA
uA
V
2
INHJ
I
100
1
3
INLJ
I
–1
4
OLJ
V
Test Port Output High Voltage
1.7
—
5, 6
5, 7
5, 8
5, 9
OHJ
V
Test Port Output Low Voltage
—
0.4
V
OLJ
V
V
– 100 mV
DDQ
Test Port Output CMOS High
—
V
OHJC
V
Test Port Output CMOS Low
—
100 mV
V
OLJC
Notes:
1. Input Under/overshoot voltage must be –2 V > Vi < V
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
DDn
2.
V
≤ V ≤ V
ILJ
IN
DDn
3. 0 V ≤ V ≤ V
IN
ILJn
4. Output Disable, V
= 0 to V
DDn
OUT
5. The TDO output driver is served by the V
supply.
DDQ
6.
7.
8.
9.
I
I
I
I
= –4 mA
OHJ
= + 4 mA
OLJ
= –100 uA
= +100 uA
OHJC
OHJC
JTAG Port AC Test Conditions
Parameter
Input high level
Conditions
2.3 V
JTAG Port AC Test Load
DQ
Input low level
0.2 V
*
Input slew rate
1 V/ns
50Ω
30pF
Input reference level
Output reference level
1.25 V
V = 1.25 V
T
1.25 V
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as as shown unless otherwise noted.
Rev: 2.15a 9/2002
35/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
JTAG Port Timing Diagram
tTKL
tTS
tTKH
tTKC
TCK
tTH
TMS
TDI
TDO
tTKQ
JTAG Port AC Electrical Characteristics
Parameter
TCK Cycle Time
Symbol
tTKC
tTKQ
tTKH
tTKL
tTS
Min
50
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
TCK Low to TDO Valid
TCK High Pulse Width
TCK Low Pulse Width
TDI & TMS Set Up Time
TDI & TMS Hold Time
20
—
20
20
10
10
—
—
tTH
—
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
Rev: 2.15a 9/2002
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© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
209 BGA Package Drawing (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
A1
C
A
Side View
D
aaa
D1
e
Bottom View
b
e
Symbol
Min
Typ
Max
1.70
0.60
0.70
0.38
22.1
Units
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
A
A1
b
0.40
0.50
0.31
21.9
0.50
0.60
c
0.36
D
22.0
D1
E
18.0 (BSC)
14.0
13.9
14.1
E1
e
10.0 (BSC)
1.00 (BSC)
0.15
aaa
Rev 1.0
Rev: 2.15a 9/2002
37/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Package Dimensions—165-Bump FPBGA
(Package D)
A1 CORNER
TOP VIEW
BOTTOM VIEW
A1 CORNER
M
M
Ø0.10
C
Ø0.25 C A B
Ø0.40~0.50 (165x)
1
2 3 4 5 6 7 8 9 10 11
11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
I
A
B
C
D
E
F
G
H
I
J
J
K
L
K
L
M
N
P
R
M
N
P
R
A
1.0
10.0
13±0.07
1.0
B
0.20(4x)
SEATING PLANE
C
Package Dimensions—119-Pin PBGA
Rev: 2.15a 9/2002
38/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
119-Bump BGA Package (Package B)
Pin 1
A
Corner
7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
G
G
H
J
K
L
M
N
P
R
T
U
H
D
B
J
S
K
L
M
N
P
R
T
U
R
Bottom View
Top View
Package Dimensions—119-Pin PBGA
Symbol
Description
Width
Min. Nom. Max
13.9 14.0 14.1
21.9 22.0 22.1
A
B
Length
C
Package Height (including ball) 1.73 1.86 1.99
D
Ball Size
0.60 0.75 0.90
0.50 0.60 0.70
E
Ball Height
F
Package Height (excluding balls) 1.16 1.26 1.36
G
Width between Balls
Package Height above board
Width of package between balls
Length of package between balls
Variance of Ball Height
1.27
K
0.65 0.70 0.75
R
7.62
20.32
0.15
S
T
Unit: mm
Side View
Rev: 2.15a 9/2002
39/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Ordering Information for GSI Synchronous
Burst RAMs
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS816218B-250
GS816218B-225
GS816218B-200
GS816218B-166
GS816218B-150
GS816218B-133
GS816236B-250
GS816236B-225
GS816236B-200
GS816236B-166
GS816236B-150
GS816236B-133
GS816218D-250
GS816218D-225
GS816218D-200
GS816218D-166
GS816218D-150
GS816218D-133
GS816236D-250
GS816236D-225
GS816236D-200
GS816236D-166
GS816236D-150
GS816236D-133
GS816272C-250
GS816272C-225
GS816272C-200
GS816272C-166
GS816272C-150
GS816272C-133
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
250/5.5
225/6
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1M x 18
200/6.5
166/7
1M x 18
1M x 18
150/7.5
133/8.5
250/5.5
225/6
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
200/6.5
166/7
150/7.5
133/8.5
250/5.5
225/6
1M x 18
1M x 18
200/6.5
166/7
1M x 18
1M x 18
150/7.5
133/8.5
250/5.5
225/6
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
Notes:
200/6.5
166/7
150/7.5
133/8.5
250/5.5
225/6
200/6.5
166/7
150/7.5
133/8.5
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 2.15a 9/2002
40/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS816218B-250I
GS816218B-225I
GS816218B-200I
GS816218B-166I
GS816218B-150I
GS816218B-133I
GS816236B-250I
GS816236B-225I
GS816236B-200I
GS816236B-166I
GS816236B-150I
GS816236B-133I
GS816218D-250I
GS816218D-225I
GS816218D-200I
GS816218D-166I
GS816218D-150I
GS816218D-133I
GS816236D-250I
GS816236D-225I
GS816236D-200I
GS816236D-166I
GS816236D-150I
GS816236D-133I
GS816272C-250I
GS816272C-225I
GS816272C-200I
GS816272C-166I
GS816272C-150I
GS816272C-133I
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
119 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
165 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
209 BGA
250/5.5
225/6
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Not Available
1M x 18
200/6.5
166/7
1M x 18
1M x 18
150/7.5
133/8.5
250/5.5
225/6
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
Not Available
Not Available
200/6.5
166/7
150/7.5
133/8.5
250/5.5
225/6
1M x 18
1M x 18
200/6.5
166/7
1M x 18
1M x 18
150/7.5
133/8.5
250/5.5
225/6
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
256K x 72
Notes:
200/6.5
166/7
150/7.5
133/8.5
250/5.5
225/6
Not Available
200/6.5
166/7
150/7.5
133/8.5
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236-200IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. T = C = Commercial Temperature Range. T = I = Industrial Temperature Range.
A
A
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which
are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 2.15a 9/2002
41/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Converted from 0.25u 3.3V process to 0.18u 2.5V process.
Master File Rev B
GS816218B-150IB 1.00 9/
1999A;GS816218B-150IB
2.00 1/1999B
Content
• Added x72 Pinout.
• Added GSI Logo.
• Changed BGA package drawing for 209 pin package.
GS816218B 2.01 1/
2000C;GS816218 B 2.02 1/
2000D
• Front page; Features - changed 2.5V I/O supply to 2.5V
or3.3V I/O supply; Core and Interface voltages - Changed
paragraph to include information for 3.3V;Completeness
• Absolute Maximum Ratings; Changed VDDQ - Value: From: -
.05 to VDD : to : -.05 to 3.6; Completeness.
GS18/362.0 1/2000DGS18/
362.03 2/2000E
• Recommended Operating Conditions;Changed: I/O Supply
Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from
VDD +0.3 to 3.6; Same page - took out Note 1;Completeness
• Electrical Characteristics - Added second Output High Voltage
line to table; completeness.
• Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
• Updated pad out and pin description table (7D changed from
GS18/362.03 2/2000E;
816218_r2_04
Content
Content
Content
NC to GW)
• Updated BGA pin description table to comply with JEDEC
standards
816218_r2_04;
816218_r2_05
• Changed the value of ZZ recovery in the AC Electrical
Characteristics table on page 19 from 20 ns to 100 ns
816218_r2_05;
816218_r2_06
• Added 225 MHz speed bin
• Updated numbers in page 1 table, AC Characteristics table,
and Operating Currents table
816218_r2_06;
816218_r2_07
Content/Format
Content
• Updated format to comply with Technical Publications
standards
• Changed V
references to V
SS
SSQ
816218_r2_07;
816218_r2_08
• Changed K4 and K8 in 209-bump BGA to NC
• Updated Capitance table—removed Input row and changed
Output row to I/O
• Updated numbers for Clock to Output Valid (PL) and Clock to
Output Valid (FT) for 166 MHz and 133 MHz on AC Electrical
Characteristics table
816218_r2_08;
816218_r2_09
Content
Content
• Updated Features list on page 1
816218_r2_09;
816218_r2_10
• Completely reworked table on page 1
• Updated Mode Pin Functions table on page 9
Rev: 2.15a 9/2002
42/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS816218(B/D)/GS816236(B/D)/GS816272(C)
18Mb Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Added 3.3 V references to entire document
• Updated Operating Conditions table
• Updated JTAG section
816218_r2_10;
816218_r2_11
Content
Content
• Updated Boundary Scan Chain table
• Updated Operating Currents table and added note
• Updated Application Tips paragraph
• Update table on page 1; added power numbers
• Updated JTAG ID Register table
• Updated Synchronous Truth table
• Updated Operating Currents table
816218_r2_11;
816218_r2_12
• Updated table on page 1; updated power numbers
• Updated Recommended Operating Conditions table (added
V
references)
DDQ
• Updated table on page 1
• Added 119-Bump BGA Pin Description table
• Created recommended operating conditions tables on pages
16 and 17
• Updated AC Electrical Characteristics table
• Added Sleep mode description on page 29
• Updated Ordering Information for 225 MHz part (changed
from 7ns to 6.5 ns)
816218_r2_12;
816218_r2_13
Content
• Updated BSR table (2 and 3 changed to X (value undefined))
• Added 250 MHz speed bin
• Deleted 180 MHz speed bin
• Updated AC Characteristics table
• Updated package designator for 209 BGA from B to C
• Updated VIH from 1.7 to 2.0
• Updated FT power numbers
• Updated Mb references from 16Mb to 18Mb
• Removed ByteSafe references
816218_r2_13;
816218_r2_14
Content
Content
• Changed DP and QE pins to NC
• Updated ZZ recovery time diagram
• Add 165-bump FPBGA package
• Updated AC Test Conditions table and removed Output Load
2 diagram
• Removed parity I/O bit designation from 165 BGA pinout
816218_r2_14;
816218_r2_15
• Removed Preliminary banner
• Removed BSR table
• Removed pin locations from pin description tables
Rev: 2.15a 9/2002
43/43
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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