GS816273AC-300T_技术文档

Preliminary

GS816273AC-300/275/250/225/200

300 MHz–200 MHz

209-Pin BGA

Commercial Temp

Industrial Temp

256K x 72

1.8 V or 2.5 V V

DD

18Mb S/DCD Sync Burst SRAMs

1.8 V or 2.5 V I/O

command for one full cycle and then begin turning off their

Features

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

• Automatic power-down for portable applications

• JEDEC-standard 209-bump BGA package

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

-300 -275 -250 -225 -200 Unit

Pipeline

3-1-1-1

t_KQ

tCycle

1.7 1.9 2.0 2.2 2.5 ns

3.3 3.6 4.0 4.4 5.0 ns

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

2.5 V

1.8 V

Curr (x72)

475 445 410 380 335 mA

470 435 400 365 325 mA

Core and Interface Voltages

The GS816273A operates on a 2.5 V or 1.8 V power supply. All

input are 1.8 V and 2.5 V compatible. Separate output power

(V_DDQ) pins are used to decouple output noise from the internal

Functional Description

Applications

The GS816273A is a 18,874,368-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

circuits and are 1.8 V and 2.5 V compatible.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

SCD and DCD Pipelined Reads

The GS816273A is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage

less than read commands. SCD RAMs begin turning off their

outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).

Preliminary

GS816273AC-300/275/250/225/200

GS816273A Pad Out

209 Bump BGA—Top View

(Package C)

1

2

3

4

5

ADSP

NC

6

ADSC

BW

E1

7

8

9

10

11

A

B

C

D

E

F

DQG5

DQG6

DQG7

DQG8

DQG9

DQC4

DQC3

DQC2

DQC1

NC

DQG1

DQG2

DQG3

DQG4

DQC9

DQC8

DQC7

DQC6

DQC5

NC

A15

BC

BH

E2

BG

BD

NC

ADV

A16

NC

E3

BB

BE

NC

A17

BF

BA

DQB1

DQB2

DQB3

DQB4

DQF9

DQF8

DQF7

DQF6

DQF5

NC

DQB5

DQB6

DQB7

DQB8

DQB9

DQF4

DQF3

DQF2

DQF1

NC

V

NC

G

GW

V

SS

V

DDQ

DD

DDQ

V

ZQ

MCH

MCL

FT

V

SS

DD

SS

G

H

J

V

DDQ

DD

DDQ

V

SS

DD

SS

V

DDQ

DD

DDQ

K

L

CK

NC

V

NC

SS

DD

SS

DQH1

DQH2

DQH3

DQH4

DQD9

DQD8

DQD7

DQD6

DQD5

DQH5

DQH6

DQH7

DQH8

DQH9

DQD4

DQD3

DQD2

DQD1

V

DDQ

DQA5

DQA6

DQA7

DQA8

DQA9

DQE4

DQE3

DQE2

DQE1

DQA1

DQA2

DQA3

DQA4

DQE9

DQE8

DQE7

DQE6

DQE5

DDQ

DD

DDQ

M

N

P

R

T

V

MCL

SCD

ZZ

V

SS

DD

SS

V

DDQ

DD

DDQ

V

SS

DD

SS

V

DDQ

DD

DDQ

V

NC

A14

A8

NC

A13

A7

LBO

A12

A1

PE

A11

A6

NC

A10

A5

V

SS

U

V

NC

A9

A4

W

TMS

TDI

A3

A0

A2

TDO

TCK

Rev 10

2

11 x 19 Bump BGA—14 x 22 mm Body—1 mm Bump Pitch

Rev: 1.00 3/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

GS816273A 209-Bump BGA Pin Description

Pin Location

Symbol Type

Description

W6, V6

A0, A1

I

Address field LSBs and Address Counter Preset Inputs.

W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6,

U5, U4, A3, B7, A9

An

I

Address Inputs

L11, M11, N11, P11, L10, M10, N10, P10, R10 DQA1–DQA9

A10, B10, C10, D10, A11, B11, C11, D11, E11 DQB1–DQB9

J1, H1, G1, F1, J2, H2, G2, F2, E2

W2, V2, U2, T2, W1, V1, U1, T1, R1

W10, V10, U10, T10, W11, V11, U11, T11, R11 DQE1–DQE9

J11, H11, G11, F11, J10, H10, G10, F10, E10 DQF1–DQF9

DQC1–DQC9

DQD1–DQD9

I/O

Data Input and Output pins (x36 Version)

A2, B2, C2, D2, A1, B1, C1, D1, E1

L1, M1, N1, P1, L2, M2, N2, P2, R2

DQG1–DQG9

DQH1–DQH9

Byte Write Enable for DQA, DQB, DQC, DQD, DQE,

DQF, DQG, DQH I/Os; active low

B^A, BB, BC,BD,

BE, BF, BG,BH

C9, B8, B3, C4, C8, B9, B4, C3

I

B5, C5, C7, D4, D5, D8, K1, K2, K4, K8, K9,

K10, K11, T4, T5, T8, U3, U9

NC

—

No Connect

K3

CK

GW

I

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

D7

C6, A8

E1, E3

E2

A4

Chip Enable; active high

D6

Output Enable; active low

G

A7

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

ADV

ADSP, ADSC

ZZ

A5, A6

P6

L6

Flow Through or Pipeline mode; active low

Linear Burst Order mode; active low

Single Cycle Deselect/Dual Cycle Deselect Mode Control

Must Connect High

FT

T6

LBO

N6

G6

SCD

MCH

MCL

H6, J6, K6, M6

Must Connect Low

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

GS816273A 209-Bump BGA Pin Description

Pin Location

Symbol Type

Description

Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36

Mode)

T7

B6

I

PE

Byte Enable; active low

BW

FLXDrive Output Impedance Control

(Low = Low Impedance [High Drive], High = High Impedance [Low

Drive])

F6

I

ZQ

W3

W4

W8

W9

I

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

TMS

TDI

O

I

TDO

TCK

E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5,

R6, R7

V_DD

I

Core power supply

D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7,

H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3,

P4, P5, P7, P8, P9, T3, T9

V_SS

I/O and Core Ground

E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9,

L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9

V_DDQ

Output driver power supply

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Mode Pin Functions

Mode Name

Name

State

Function

L

Linear Burst

Interleaved Burst

Flow Through

Pipeline

Burst Order Control

Output Register Control

Power Down Control

LBO

H

L

FT

H or NC

L or NC

H

Active

ZZ

Standby, I_DD= I_SB

L

Dual Cycle Deselect

Single Cycle Deselect

Single/Dual Cycle Deselect Control

Parity Enable

SCD

PE

H or NC

L or NC Activate 9th I/O’s (x18/36 Mode)

H

L

Deactivate 9th I/O’s (x16/32 Mode)

High Drive (Low Impedance)

Low Drive (High Impedance)

FLXDrive Output Impedance Control

Note:

ZQ

H or NC

There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the PE and ZZ pins, so those input pins can be unconnected

and the chip will operate in the default states as specified in the above tables.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16,

x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE

deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits

generated and read into the ByteSafe parity circuits.

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

1st address

2nd address

3rd address

4th address

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

Note: The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.00 3/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Byte Write Truth Table

Function

Read

GW

H

BW

H

L

BA

X

BB

X

BC

X

BD

X

Notes

1

Read

H

L

H

L

H

L

H

L

1

Write byte a

Write byte b

Write byte c

Write byte d

Write all bytes

H

L

2, 3

H

L

H

L

2, 3

H

L

H

L

2, 3, 4

H

L

H

L

H

L

X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x36 version.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Synchronous Truth Table

Operation

State

3

4

Diagram

Address Used

E1

ADSP ADSC

ADV

W

DQ

5

Key

Deselect Cycle, Power Down

Read Cycle, Begin Burst

None

External

R

H

L

X

L

X

L

X

L

X

F

T

F

T

F

T

High-Z

Q

D

Q

D

Q

D

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

R

L

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

W

L

CR

CW

H

Current

H

Notes:

1. X = Don’t Care, H = High, L = Low

2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding

3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Simplified State Diagram

X

Deselect

W

R

W

R

X

R

X

First Write

First Read

CW

CR

W

R

X

Burst Write

X

Burst Read

CR

CW

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and

assumes ADSP is tied high and ADV is tied low.

Rev: 1.00 3/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

W

R

X

First Write

First Read

CR

CW

CR

W

R

W

X

Burst Write

X

Burst Read

CR

CW

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.

3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

Rev: 1.00 3/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Absolute Maximum Ratings

(All voltages reference to V_SS)

Symbol

V_DD

Description

Value

–0.5 to 3.6

Unit

V

Voltage on V_DDPins

V_DDQ

V_CK

Voltage in V_DDQPins

–0.5 to 3.6

V

Voltage on Clock Input Pin

Voltage on I/O Pins

–0.5 to 3.6

V

V_I/O

–0.5 to V_DDQ+0.5 (£ 3.6 V max.)

–0.5 to V_DD+0.5 (£ 3.6 V max.)

V

V_IN

Voltage on Other Input Pins

Input Current on Any Pin

Output Current on Any I/O Pin

Package Power Dissipation

Storage Temperature

V

I_IN

+/–20

mA

W

I_OUT

P_D

1.5

^oC

T_STG

–55 to 125

T_BIAS

Temperature Under Bias

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Rev: 1.00 3/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Power Supply Voltage Ranges

Parameter

2.5 V Supply Voltage

Symbol

V_DD2

Min.

2.3

Typ.

2.5

Max.

2.7

Unit

Notes

V

V_DD1

1.8 V Supply Voltage

1.6

1.8

2.0

2.5 V V_DDQI/O Supply Voltage

V_DDQ2

V_DDQ1

2.3

2.5

2.7

1.8 V V_DDQI/O Supply Voltage

Notes:

1.6

1.8

2.0

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

V

Range Logic Levels

DDQ2

Parameter

Symbol

V_IH

Min.

Typ.

—

Max.

V_DD+ 0.3

0.3*V_DD

Unit

Notes

V_DDInput High Voltage

V_DDInput Low Voltage

V_DDQI/O Input High Voltage

V_DDQI/O Input Low Voltage

0.6*V_DD

V

1

V_IL

–0.3

—

1

V_IHQ

V_ILQ

0.6*V_DD

V_DDQ+ 0.3

0.3*V_DD

—

1,3

–0.3

—

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V_IHQ(max) is voltage on V_DDQpins plus 0.3 V.

V

Range Logic Levels

DDQ1

Parameter

Symbol

V_IH

Min.

Typ.

—

Max.

V_DD+ 0.3

0.3*V_DD

Unit

Notes

V_DDInput High Voltage

V_DDInput Low Voltage

V_DDQI/O Input High Voltage

V_DDQI/O Input Low Voltage

0.6*V_DD

V

1

V_IL

–0.3

—

1

V_IHQ

V_ILQ

0.6*V_DD

V_DDQ+ 0.3

0.3*V_DD

—

1,3

–0.3

—

Notes:

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

3. V_IHQ(max) is voltage on V_DDQpins plus 0.3 V.

Rev: 1.00 3/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Recommended Operating Temperatures

Parameter

Symbol

Min.

0

Typ.

25

Max.

70

Unit

°C

Notes

T_A

Ambient Temperature (Commercial Range Versions)

2

Ambient Temperature (Industrial Range Versions)

Note:

–40

25

85

°C

1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are

evaluated for worst case in the temperature range marked on the device.

2. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC.

Undershoot Measurement and Timing

Overshoot Measurement and Timing

V_IH

20% tKC

V_DD+ 2.0 V

V_SS

50%

V_DD

50%

V

_SS– 2.0 V

20% tKC

V_IL

Capacitance

(T_A= 25^oC, f = 1 MHZ, V_DD= 2.5 V)

Parameter

Input Capacitance

Symbol

C_IN

Test conditions

V_IN= 0 V

Typ.

Max.

Unit

pF

4

6

5

7

C_I/O

V_OUT= 0 V

Input/Output Capacitance

pF

Note: These parameters are sample tested.

Package Thermal Characteristics

Rating

Junction to Ambient (at 200 lfm)

Junction to Case (TOP)

Notes:

Layer Board

Symbol

R_QJA

Max

40

Unit

Notes

1,2

single

four

—

°C/W

R_QJA

24

1,2

R_QJC

9

3

1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-

ature air flow, board density, and PCB thermal resistance.

2. SCMI G-38-87

3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1

Rev: 1.00 3/2002

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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

AC Test Conditions

Parameter

Input high level

Input low level

Conditions

V_DD– 0.2 V

0.2 V

1 V/ns

V_DD/2

Input slew rate

Input reference level

V_DDQ/2

Output reference level

Output load

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig.

1 unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Output Load 1

DQ

30pF^*

50W

V_DDQ/2

* Distributed Test Jig Capacitance

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

I_IL

V_IN= 0 to V_DD

–1 uA

1 uA

V_DD³ V_IN³ V_IH

0 V £ V_IN£ V_IH

–1 uA

1 uA

100 uA

I_IN1

ZZ and PE Input Current

SCD and ZQ Input Current

V_DD³ V_IN³ V_IL

0 V £ V_IN£ V_IL

–100 uA

–1 uA

1 uA

I_IN2

I_OL

Output Disable, V_OUT= 0 to V_DD

I_OH= –8 mA, V_DDQ= 2.3 V

I_OH= –4 mA, V_DDQ= 1.6 V

I_OL= 8 mA, V_DD= 2.3 V

Output Leakage Current

Output High Voltage

Output Low Voltage

–1 uA

1 uA

—

V_OH2

V_OH1

V_OL2

V_OL1

V_DDQ– 0.4 V

—

0.4 V

I_OL= 4 mA, V_DD= 1.6 V

Rev: 1.00 3/2002

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Preliminary

GS816273AC-300/275/250/225/200

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Preliminary

GS816273AC-300/275/250/225/200

AC Electrical Characteristics

-300

-275

-250

-225

-200

Parameter

Symbol

Unit

Min Max Min Max Min Max Min Max Min Max

Clock Cycle Time

Clock to Output Valid

Clock to Output Invalid

Clock to Output in Low-Z

Clock HIGH Time

tKC

tKQ

3.3

—

1.7

—

3.6

—

1.9

—

4.0

—

2.0

—

4.4

—

2.2

—

5.0

—

2.5

—

ns

tKQX

1.0

1.2

1.0

1.3

1.5

1.0

1.3

1.5

1.0

1.3

1.5

1.0

1.3

1.5

tLZ¹

tKH

tKL

Clock LOW Time

Pipeline

Clock to Output in

High-Z

tHZ¹

1.0

1.3

1.0

2.0

1.0

2.0

1.0

2.2

1.0

2.5

ns

G to Output Valid

tOE

—

1.7

—

1.7

—

1.8

—

2.0

—

2.5

ns

tOLZ¹

G to output in Low-Z

0

—

0

—

0

—

0

—

0

—

tOHZ¹

tS

G to output in High-Z

Setup time

—

1.1

0.1

5

1.5

—

1.2

0.2

5

1.8

—

1.2

0.2

5

1.8

—

1.3

0.3

5

2.0

—

1.4

0.4

5

2.5

—

ns

Hold time

tH

tZZS²

ZZ setup time

tZZH²

tZZR

ZZ hold time

ZZ recovery

1

—

1

—

1

—

1

—

1

—

ns

20

Notes:

1. These parameters are sampled and are not 100% tested.

2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

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Preliminary

GS816273AC-300/275/250/225/200

Write Cycle Timing

Single Write

tS tH

Burst Write

Deselected

Write

CK

ADSP is blocked by E inactive

tKC

tKL

tKH

ADSP

tH

tS

ADSC initiated write

ADSC

tS

ADV

ADV must be inactive for ADSP Write

tH

tS

WR2

WR3

WR1

A0–An

tS tH

GW

BW

tH

tS

tH

WR3

WR1

WR2

BA–BD

E1

tS

tH

E1 masks ADSP

E1 only sampled with ADSP or ADSC

G

tS

tH

Write specified byte for 2A and all bytes for 2B, 2C& 2D

Hi-Z

D1A

D2C

D2D

D3A

DQA–DQD

D2A

D2B

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Preliminary

GS816273AC-300/275/250/225/200

Pipelined SCD Read Cycle Timing

Single Read

Burst Read

tKC

CK

tKL

tKH

tH

tS

ADSP is blocked by E inactive

ADSP

ADSC

tS

ADSC initiated read

tS tH

Suspend Burst

ADV

tH

tS

RD2

RD3

RD1

A0–An

tS

tH

GW

BW

tH

BWA–BWD

tH

tS

E1 masks ADSP

E1

tOE

G

tOHZ

tKQX

Q2D

Q3A

tKQX

Q2A

tOLZ

tLZ

Hi-Z

DQA–DQD

Q1A

Q2B

Q2c

tHZ

tKQ

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Preliminary

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Pipelined SCD Read-Write Cycle Timing

Single Write

Single Read

Burst Read

tKL

CK

tH

tS

tKH

tKC

ADSP is blocked by E inactive

ADSC initiated read

ADSP

ADSC

tS tH

ADV

tS

tH

RD2

WR1

A0–An

RD1

tS

tH

GW

BW

tS

tH

tS

WR1

BWA– BWD

E1

tS

tH

E1 masks ADSP

tOE

tOHZ

G

tS

tH

tKQ

Hi-Z

Q1A

D1A

Q2A

Q2B

Q2c

DQA–DQD

Q2D

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Preliminary

GS816273AC-300/275/250/225/200

Pipelined DCD Read Cycle Timing

Single Read

Burst Read

tKL

CK

tH

tS

ADSP is blocked by E1 inactive

tKC

tKH

ADSP

tS tH

ADSC initiated read

ADSC

ADV

tS tH

Suspend Burst

tS

tH

RD1

RD3

RD2

A0–An

GW

tS

tH

BW

BA–BD

tS tH

E1 masks ADSP

E1

tOE

G

tOHZ

tKQX

Q2A

tKQX

Q3A

tHZ

tOLZ

tLZ

Hi-Z

Q1A

Q2B

Q2D

Q2c

DQA–DQD

tKQ

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Preliminary

GS816273AC-300/275/250/225/200

Pipelined DCD Read-Write Cycle Timing

Single Write

tKC

Single Read

Burst Read

tKL

CK

tS

tH

tKH

ADSP is blocked by E1 inactive

ADSP

tS tH

ADSC initiated read

ADSC

ADV

tS

tH

tS

tH

RD1

RD2

A0–An

WR1

tS

GW

tS

tH

BW

tH

tS

WR1

BA–BD

tS tH

E1 masks ADSP

E1

tOE

tOHZ

G

tS

tH

tKQ

Hi-Z

Q1A

D1A

Q2A

Q2B

DQA–DQD

Q2c

Q2D

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Preliminary

GS816273AC-300/275/250/225/200

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I_SB2. The duration of

Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, I_SB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

CK

tH

tS

tKC

tKL

tKH

ADSP

ADSC

ZZ

tZZH

tZZS

tZZR

Snooze

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with

the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually

assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste

bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at

bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V_DD. The JTAG output

drivers are powered by V_DDQ

.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

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Preliminary

GS816273AC-300/275/250/225/200

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either V_DDor V_SS. TDO should be left unconnected.

JTAG Pin Descriptions

Pin Name

I/O

Description

Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TCK

Test Clock

In

The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

TMS

TDI

Test Mode Select

Test Data In

In controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

In state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

Output that is active depending on the state of the TAP state machine. Output changes in

Out response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

TDO

Test Data Out

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

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Preliminary

GS816273AC-300/275/250/225/200

JTAG TAP Block Diagram

0

Bypass Register

2

1 0

Instruction Register

TDI

TDO

ID Code Register

31 30 29

2 1 0

·

· · ·

Boundary Scan Register

n

2 1 0

· · · · · · · · ·

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

GSI Technology

JEDEC Vendor

ID Code

I/O

Not Used

Configuration

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

x72 0 1 1 0 1 1 0 0 1

0

1

X

0

1

0

1

0

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

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Preliminary

GS816273AC-300/275/250/225/200

JTAG Tap Controller State Diagram

Test Logic Reset

1

0

1

Run Test Idle

Select DR

Select IR

0

1

Capture DR

Capture IR

0

Shift DR

Shift IR

0

1

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

0

1

Exit2 DR

Exit2 IR

0

1

Update DR

Update IR

1

0

1

0

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when

the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices

in the scan path.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruc-

tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan

Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the

Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it

is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although

allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be

stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be

paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-

DR state then places the boundary scan register between the TDI and TDO pins.

EXTEST

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Preliminary

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EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s.

The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input

pins.

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST

command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK

when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,

the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are trans-

ferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the

value of the Boundary Scan Register location with which each output pin is associated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID

register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any

time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the

Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state.

RFU

These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction

EXTEST

Code

000

Description

Notes

1

Places the Boundary Scan Register between TDI and TDO.

Preloads ID Register and places it between TDI and TDO.

IDCODE

001

1, 2

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

SAMPLE-Z

010

011

TDO.

1

Forces all RAM output drivers to High-Z.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

SAMPLE/

PRELOAD

Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

100

101

110

111

1

GSI

GSI private instruction.

Do not use this instruction; Reserved for Future Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.

RFU

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

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Preliminary

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JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

V_IHJ3

V_ILJ3

Min.

2.0

Max.

Unit Notes

V_DD3+0.3

3.3 V Test Port Input High Voltage

3.3 V Test Port Input Low Voltage

2.5 V Test Port Input High Voltage

2.5 V Test Port Input Low Voltage

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

V

1

–0.3

0.8

V_IHJ2

V_ILJ2

0.6 * V_DD2

V_DD2+0.3

0.3 * V_DD2

V

1

–0.3

V

1

I_INHJ

–300

1

100

1

uA

V

2

I_INLJ

–1

3

I_OLJ

–1

4

V_OHJ

V_OLJ

Test Port Output High Voltage

Test Port Output Low Voltage

1.7

—

5, 6

5, 7

5, 8

5, 9

0.4

V

V_OHJC

V_OLJC

V_DDQ– 100 mV

Test Port Output CMOS High

—

V

Test Port Output CMOS Low

—

100 mV

V

Notes:

1. Input Under/overshoot voltage must be –2 V > Vi < V_DDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. _ILJ£ V_IN£ V_DDn

V

3. 0 V £ V_IN£ V_ILJn

4. Output Disable, V_OUT= 0 to V_DDn

5. The TDO output driver is served by the V_DDQsupply.

6. I_OHJ= –4 mA

7. I_OLJ= + 4 mA

8. I_OHJC= –100 uA

9. I_OHJC= +100 uA

JTAG Port AC Test Conditions

Parameter

Input high level

Conditions

JTAG Port AC Test Load

2.3 V

0.2 V

DQ

Input low level

30pF^*

Input slew rate

1 V/ns

1.25 V

50W

Input reference level

Output reference level

V_T= 1.25 V

* Distributed Test Jig Capacitance

Notes:

1. Include scope and jig capacitance.

2. Test conditions as as shown unless otherwise noted.

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Preliminary

GS816273AC-300/275/250/225/200

JTAG Port Timing Diagram

tTKL

tTS

tTKH

tTKC

TCK

tTH

TMS

TDI

TDO

tTKQ

JTAG Port AC Electrical Characteristics

Parameter

Symbol

tTKC

tTKQ

tTKH

tTKL

tTS

Min

50

—

Max

—

Unit

ns

TCK Cycle Time

TCK Low to TDO Valid

TCK High Pulse Width

TCK Low Pulse Width

TDI & TMS Set Up Time

TDI & TMS Hold Time

20

—

ns

20

10

ns

—

ns

—

ns

tTH

—

ns

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Preliminary

GS816273AC-300/275/250/225/200

GS816273A Boundary Scan Chain Order (Cont.)

Order

x72

DA3

QE3

DE3

QA6

DA6

QE7

DE7

QA2

DA2

QE6

DE6

QA1

DA1

QE2

DE2

QA5

DA5

ZZ

Bump

N11

U10

M10

U11

M11

V11

L11

V10

L10

P6

GS816273A Boundary Scan Chain Order

30

Order

x72

PE

Bump

T7

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

1

2

A13

A11

A3

U5

3

U7

4

W5

5

A12

A6

U6

6

V7

7

A2

W7

8

A10

A5

U8

9

V8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

A4

V9

QE9

DE9

QA9

DA9

QE5

DE5

QA4

DA4

QE1

DE1

QA8

DA8

QE4

DE4

QA7

DA7

QE8

DE8

QA3

R11

R10

W11

P11

W10

P10

T10

N10

T11

N11

PH = 0

NC = 1

QB1

DB1

QF1

DF1

n/a

K11

A10

J11

QB5

DB5

QF5

DF5

A11

J10

QB2

DB2

QF2

B10

H11

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Preliminary

GS816273AC-300/275/250/225/200

GS816273A Boundary Scan Chain Order (Cont.)

Order

x72

DF2

Bump

H11

C10

H10

B11

G10

D10

G11

C11

F10

D11

F11

E11

E10

n/a

Order

x72

G

Bump

D6

B6

D7

C3

B3

B9

C9

K3

n/a

A8

C8

B8

B4

C4

A4

C6

B7

A3

E1

E2

D2

F2

61

92

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

93

QB3

BW

GW

BH

94

DB3

95

QF6

96

DF6

B^F

97

QB6

BD

98

DB6

BB

99

QF7

CK

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

DF7

NC = 1

PH = 0

E³

QB4

DB4

QF3

B^A

DF3

BC

QB7

B^E

DB7

B^G

QF8

E2

DF8

E¹

QB8

A16

A15

QG9

DG9

QC9

DC9

QG4

DG4

QC8

DC8

QG8

DG8

QC4

DC4

DB8

QF4

DF4

QB9

DB9

QF9

DF9

NC = 1

A17

n/a

F2

A9

D1

F1

ADV

ADSP

ADSC

A7

A5

A6

F1

Rev: 1.00 3/2002

29/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

GS816273A Boundary Scan Chain Order (Cont.)

Order

x72

QG7

DG7

QC7

DC7

QG3

DG3

QC3

DC3

QG6

DG6

QC6

DC6

QG5

DG5

QC2

DC2

QG2

DG2

QC1

DC1

QG1

DG1

QC5

DC5

FT

Bump

C1

G2

C2

G1

B1

H2

A1

H1

B2

J1

Order

x72

QD1

DD1

QH5

DH5

QD5

DD5

QH2

DH2

QD6

DD6

QH6

DH6

QD7

DD7

QH4

DH4

QD3

DD3

QH7

DH7

QD4

DD4

QH3

DH3

QD8

DD8

QH8

DH8

QD9

DD9

QH9

Bump

W2

L2

123

154

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

L2

W1

M1

V1

M2

U1

P1

U2

N2

T2

J1

A2

J2

T2

N1

T1

J2

L6

NC = 1

SCD

QD2

DD2

QH1

DH1

K9

N6

V2

L1

T1

P2

R1

R2

L1

Rev: 1.00 3/2002

30/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

GS816273A Boundary Scan Chain Order (Cont.)

Order

x72

DH9

LBO

A9

Bump

R2

185

186

187

188

189

190

191

192

193

194

T6

V3

A14

A8

U4

V4

A7

V5

A1

V6

A0

W6

F6

ZQ

G

D6

Notes:

1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1,

PE = 0, SD = 0, ZZ = 0, FT = 1, and SCD = 1.

2. Every DQ pad consists of two scan registers—D is for input capture, and Q is for output capture.

3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control

is effective after JTAG EXTEST instruction is executed.

4. 1 = no connect, internally set to logic value 1

5. 0 = no connect, internally set to logic value 0

6. X = no connect, value is undefined

Rev: 1.00 3/2002

31/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

209 BGA Package Drawing (Package C)

14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array

A1

C

A

Side View

D

aaa

D1

e

Bottom View

Æb

e

Symbol

Min

Typ

Max

1.70

0.60

0.70

0.38

22.1

Units

mm

A

A1

Æb

c

0.40

0.50

0.31

21.9

0.50

0.60

0.36

D

22.0

D1

E

18.0 (BSC)

14.0

13.9

14.1

E1

e

10.0 (BSC)

1.00 (BSC)

0.15

aaa

Rev 1.0

Package Dimensions—119-Pin PBGA

Rev: 1.00 3/2002

32/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

Ordering Information for GSI Synchronous Burst RAMs

2

Speed

(MHz)

3

1

Org

Type

Package

Status

T

Part Number

A

256K x 72

GS816273AC-300

GS816273AC-275

GS816273AC-250

GS816273AC-225

GS816273AC-200

S/DCD Pipeline

209 BGA

300

275

250

225

200

300

275

250

225

200

C

I

256K x 72 GS816273AC-300I

256K x 72 GS816273AC-275I

256K x 72 GS816273AC-250I

256K x 72 GS816273AC-225I

256K x 72 GS816273AC-200I

Notes:

I

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816218AB-200IB.

2. T_A= C = Commercial Temperature Range. T_A= I = Industrial Temperature Range.

3. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which

are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

Rev: 1.00 3/2002

33/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS816273AC-300/275/250/225/200

18Mb Sync SRAM Datasheet Revision History

DS/DateRev. Code: Old;

New

Types of Changes

Format or Content

Page;Revisions;Reason

• Creation of new datasheet

816273A_r1

Rev: 1.00 3/2002

34/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.


型号：	GS816273AC-300T
厂家：	GSI TECHNOLOGY
描述：	Cache SRAM, 256KX72, 1.7ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209 静态存储器
文件：	总38页 (文件大小：1079K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GS816273AC-300T [GSI]

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