GS1510-CQR [GENNUM]
HDTV Serial Digital Deformatter; 高清晰度电视串行数字格式化
| 型号： | GS1510-CQR |
| 厂家： | 
GENNUM CORPORATION |
| 描述： | HDTV Serial Digital Deformatter |
| 文件： | 总11页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
HD-LINX GS1510
HDTV Serial Digital Deformatter
PRELIMINARY DATA SHEET
FEATURES
DESCRIPTION
• SMPTE 292M compliant
When interfaced to the Gennum GS1545 HDTV Equalizing
Receiver or GS1540 Non-Equalizing Receiver, the GS1510
performs the final conversion to word aligned data. The
device performs NRZI decoding and de-scrambling as per
SMPTE 292M and word-aligns to the incoming data stream.
Line based CRCs are calculated on the incoming data
stream and are compared against the CRCs embedded
within the data stream.
• standards detection/indication for SMPTE 292M levels
A/B,C,D/E,F,G/H,I,J/K,L/M
• NRZI decoding and SMPTE descrambling with
BYPASS option
• line CRC calculation, comparison
• selectable line based CRC re-Insertion
• H, V, F timing reference signal (TRS) extraction
• selectable flywheel for noise immune H, V, F extraction
• selectable automatic switch line handling
• selectable TRS and line number re-insertion
• selectable active picture illegal code re-mapping
• configurable FIFO LOAD pulse
HVF timing information is extracted from the data stream. A
selectable internal HVF flywheel provides superior noise
immunity against TRS signal errors. The device also detects
and indicates the input video signal standard.
The GS1510 can detect and re-map illegal code words
contained within the active portion of the video signal. Prior
to exiting the device, TRS, Line Numbers and CRCs based
on internal calculations may be re-inserted into the data
stream.
• 20 bit 3.3V CMOS input data bus
• optimized input interface to GS1545 or GS1540
• single +3.3V power supply
ORDERING INFORMATION
• 5V tolerant I/O
PART NUMBER
PACKAGE
TEMPERATURE
APPLICATIONS
GS1510-CQR
128 pin MQFP
0°C to 70°C
SMPTE 292M Serial Digital Interfaces.
TRS_Y/C
FW_EN/DIS
F_E/S
FAST_LOCK
WB_NI
BP_DSC
BP_FR
TRS_INS
LN_INS
CRC_INS
CODE
PROTECT
2
2
MUTE
RESET
3
3
DATA_OUT
[19:10]
DATA_IN
[19:0]
TRS DETECTION
FLYWHEEL
CRC CALCULATION
CRC COMPARISON
TRS,
LNUM,
AND CRC
INSERTION
(LUMA)
INPUT
BUFFER
DESCRAMBLE
FRAME
DATA_OUT
[9:0]
STANDARD DETECTION
TRS EXTRACTION
ILLEGAL CODE REMAPPING
(CHROMA)
PCLK_IN
3
[H:V:F]
FIFO_L
OEN
3
4
2
VD_STD [3:0]
LN_ERR
SAV_ERR
EAV_ERR
LINE_CRC_ERR [Y:C]
BLOCK DIAGRAM
Revision Date: November 2000
Document No. 522 - 47 - 00
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VALUE
-0.5V to +4.6V
-0.5V < VIN < 5.5V
0°C ≤ TA ≤ 70°C
-40°C ≤ TS ≤ 125°C
260°C
Supply Voltage
Input Voltage Range (any input)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering 10 seconds)
DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0°C to 70°C, unless otherwise shown
PARAMETER
Positive Supply Voltage
Supply Current
SYMBOL
VDD
CONDITIONS
MIN
3.0
-
TYP
3.3
402
-
MAX
3.6
480
0.8
5.0
0.4
-
UNITS
NOTES
V
mA
V
ΙDD
ƒ = 74.25MHz, TA = 25°C
ILEAKAGE < 10µA
Input Logic LOW Voltage
Input Logic HIGH Voltage
Output Logic LOW Voltage
Output Logic HIGH Voltage
VIL
-
VIH
ILEAKAGE < 10µA
2.1
-
3.3
0.2
-
V
VOL
VDD = 3.0 to 3.6V, IOL= 4mA
VDD = 3.0 to 3.6V, IOH = -4mA
V
VOH
2.6
V
AC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0°C to 70°C
PARAMETER
Clock Input Frequency
Input Data Setup Time
Input Data Hold Time
Input Clock Duty Cycle
Output Data Hold Time
Output Enable Time
SYMBOL
FHSCI
tSU
CONDITIONS
MIN
-
TYP
MAX
80
-
UNITS
MHz
ns
NOTES
74.25
Also supports 74.25/1.001MHz
50% levels
2.5
1.5
40
2.0
-
-
-
-
-
-
-
-
-
tIH
-
ns
50% levels
60
-
%
tOH
tOEN
tODIS
tOD
With 15pF load
With 15pF load
With 15pF load
With 15pF load
With 15pF load
ns
8
ns
Output Disable Time
Output Data Delay Time
Output Data Rise/Fall Time
-
9
ns
-
10
2.5
ns
t
ROD/tFOD
-
ns
20% to 80% levels
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PIN CONNECTIONS
LN_ERR
SAV_ERR
EAV_ERR
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
V
DD
GND
OEN
V
TN
DD
GND
TEST
NC
FIFO_L
LINE_CRC_ERR_Y
LINE_CRC_ERR_C
VD_STD[0]
VD_STD[1]
VD_STD[2]
VD_STD[3]
NC
NC
NC
NC
NC
NC
NC
NC
V
V
DD
DD
GND
NC
GND
F
V
V
DD
GS1510
TOP
VIEW
GND
NC
NC
NC
NC
NC
NC
NC
H
V
DD
GND
RESET
FAST_LOCK
CRC_INS
LN_INS
GND
V
TRS_INS
TRS_Y/C
WB_NI
DD
GND
V
DD
V
BP_DSC
BP_FR
DD
GND
GND
8
CODE_PROTECT
FW_EN/DIS
MUTE
V
7
DD
V
6
DD
V
5
F_E/S
DD
V
4
GND
DD
V
3
V
DD
DD
V
2
GND
DD
GND
1
PCLK_IN
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PIN DESCRIPTIONS
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
1
PCLK_IN
Synchronous
wrt PCLK_IN
Input
Input Clock. The device uses PCLK_IN for clocking the input
data stream into DATA_IN[19:0]. This clock is generated by
the GS1545 or GS1540
2, 4, 14, 19, 24, 37,
46, 50, 58, 69, 79,
82, 91, 94, 110,
116, 128
GND
VDD
Gnd
Power
Input
Ground power supply connections.
3, 20, 25, 38, 47,
51, 59, 68, 78, 81,
90, 93, 109, 115,
127
Positive power supply connections.
5
F_E/S
Non-
synchronous
Control Signal Input. Used to control where the FIFO_L signal
is generated. When F_E/S is high, the GS1510 generates
FIFO_L signal at EAV. When F_E/S is low, the GS1510
generates FIFO_L signal at SAV. See Fig. 4 for timing
information.
6
MUTE
Synchronous
wrt PCLK_IN
Input
Control Signal Input. Used to enable or disable blanking of
the LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT[9:0]). When MUTE is low, the device sets the
accompanying LUMA and CHROMA data to their appropriate
blanking levels. When MUTE is high, the LUMA and CHROMA
data streams pass through this stage of the device unaltered.
7
8
FW_EN/DIS
Non-
synchronous
Input
Input
Control Signal Input. Used to enable or disable the internal
flywheel. When FW_EN/DIS is high, the internal flywheel is
enabled. When FW_EN/DIS is low, the internal fly-wheel is
disabled.
CODE_PROTECT
Non-
synchronous
Control Signal Input. Used to enable or disable re-mapping of
out-of-range words contained in the active portion of the video
signal. When this signal is high, the device re-maps out-of-
range words contained within the active portion of the video
signal into CCIR-601 compliant words. Values between
000-003 are re-mapped to 004. Values between 3FC and 3FF
are re-mapped to 3FB. When this signal is low, out-of-range
words in the active video region pass through the device
unaltered.
9
BP_FR
Non-
synchronous
Input
Input
Control Signal Input. Used to enable or disable word
boundary framing. When BP_FR is low internal framing is
enabled. When BP_FR is high internal framing is bypassed.
10
BP_DSC
Non-
synchronous
Control Signal Input. Used to enable or disable the SMPTE
292M descrambler. When BP_DSC is low, the internal SMPTE
292M descrambler is enabled. When BP_DSC is high, the
internal SMPTE 292M de-scrambler is bypassed.
11
12
WB_NI
Non-
synchronous
Input
Input
Control Signal Input. Used to enable or disable noise immune
operation of the word boundary framer. When WB_NI is high,
noise-immune word boundary alignment is enabled. The
device switches to a new word boundary only when it has
detected two consecutive identical new TRS positions. When
WB_NI is low, the device re-aligns the word boundary position
at every instance of a TRS.
TRS_Y/C
Non-
synchronous
Control Signal Input. Used to control whether LUMA or
CHROMA TRS IDs are detected and used. When TRS_Y/C is
high, the device detects and uses TRS signals embedded in
the LUMA channel. When TRS_Y/C is low, the device detects
and uses TRS signals embedded in the CHROMA channel.
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PIN DESCRIPTIONS
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
13
TRS_INS
Non-
synchronous
Input
Control Signal Input. Used to enable or disable re-insertion of
the TRS into the data stream. When TRS_INS is high, the
device re-inserts TRS into the incoming data stream based on
the internal calculation. The original TRS packets are set to the
blanking levels. If the flywheel is enabled, TRS calculated by
the flywheel is used for insertion. When TRS_INS is low, the
device will not re-insert TRS even if errors in TRS signals are
detected.
15
LN_INS
Non-
synchronous
Input
Control Signal Input. Used to enable or disable re-insertion of
the line number into the data stream. When LN_INS is high, the
device re-inserts the line number into the incoming data
stream based on the internal calculation. The original line
number packets are set to the blanking levels. If the flywheel is
enabled, the line number calculated by the flywheel is used for
insertion. When LN_INS is low, the device will not re-insert the
line number.
16
17
CRC_INS
Non-
synchronous
Input
Input
Control Signal Input. Used to enable or disable re-insertion of
the CRC into the data stream. When CRC_INS is high, the
device is enabled to re-insert line CRCs based on the internal
calculation. When CRC_INS is low, the device will not re-insert
the CRCs.
FAST_LOCK
Synchronous
wrt PCLK_IN
Control Signal Input. Used to control the flywheel
synchronization when a switch line occurs. When a low to high
transition occurs on the FAST_LOCK signal, the internal
flywheel will immediately re-synchronize to the next valid EAV
or SAV TRS in the incoming data stream. See Fig. 5 for timing
information.
18
RESET
Non-
synchronous
Input
Control Signal Input. Used to reset the system state registers to
their default 720p parameters. When RESET is high, the fly
wheel, TRS Detection, and ANC Detection operate normally.
When RESET is low, the flywheel, TRS Detection, and ANC
Detection are reset to the 720p parameters after a rising edge
on PCLK_IN. The read and write counters are not affected.
21
22
23
H
V
F
Synchronous
wrt PCLK_IN
Output
Output
Output
Control Signal Input. This signal indicates the Horizontal
blanking period of the video signal. Refer to Fig. 2 for timing
information of H relative to DATA_OUT[19:10] and
DATA_OUT[9:0], LUMA and CHROMA respectively.
Synchronous
wrt PCLK_IN
Control Signal Input. This signal indicates the Vertical blanking
period of the video signal. Refer to Fig. 2 for timing information
of V relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA
and CHROMA respectively.
Synchronous
wrt PCLK_IN
Control Signal Input. This signal indicates the ODD/EVEN field
of the video signal. Refer to Fig. 2 for timing information of F
relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and
CHROMA respectively. When locked and the input signal is of
a progressive scan nature, F stays low at all times.
26,27,71-77,80,
83-89
NC
N/A
N/A
No Connect. Do not connect these pins.
28, 29, 30, 31
VD_STD[3:0]
Synchronous
wrt PCLK_IN
Output
Control Signal Output. VD_STD[3:0] indicates which input
video standard the device has detected. The GS1510 will
indicate all of the formats in SMPTE292M (see Table 1) plus it
will indicate an unknown interlace or progressive scan format.
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PIN DESCRIPTIONS
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
32
LINE_CRC_ERR_C
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Indicates a difference in the calculated
versus embedded CRC in the CHROMA channel. When
LINE_CRC_ERR_C is high, it indicates that the GS1510 has
detected a difference between the line based CRCs it
calculates for the CHROMA channel and the line based CRCs
embedded within the CHROMA channel. When
LINE_CRC_ERR_C is low, the embedded and calculated CRCs
match. Refer to Fig. 6 for timing information of
LINE_CRC_ERR_C.
33
LINE_CRC_ERR_Y
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Indicates a difference in the calculated
versus embedded CRC in the LUMA channel. When
LINE_CRC_ERR_Y is high, it indicates that the GS1510 has
detected a difference between the line based CRCs it
calculates for the LUMA channel and the line based CRCs
embedded within the LUMA channel. When LINE_CRC_ERR_Y
is low, the embedded and calculated CRCs match. Refer to
Fig. 6 for timing information of LINE_CRC_ERR_Y.
34
FIFO_L
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Used to control an external FIFO(s).
FIFO_L is normally high, but is set low for the EAV or SAV word
depending on the state of F_E/S. Refer to Fig. 4 for timing
information of FIFO_L relative to LUMA (DATA_OUT[19:10])
and CHROMA (DATA_OUT[9:0]).
35
36
TN
TEST
Input
Test Pin. Used for test purposes only. This pin must be
connected to VDD for normal operation
OEN
Non-
synchronous
Control Signal Input. Used to enable the DATA_OUT[19:0]
output bus or set it to a high Z state. When OEN is low, the
LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0])
busses are enabled. When OEN is high, these busses are in a
high Z state.
39, 40, 41, 42, 43,
44, 45, 48, 49, 52
DATA_OUT[9:0]
Synchronous
wrt PCLK_IN
Output
Output
Output
CHROMA Output Data Bus. DATA_OUT [9] is
CHROMA_OUT[9] which is the MSB of the CHROMA output
signal (pin 52). DATA_OUT [0] is CHROMA_OUT[0] which is
the LSB of the CHROMA output signal (pin 39).
(CHROMA channel)
53, 54, 55, 56, 57,
60, 61, 62, 63, 64
DATA_OUT[19:10]
(LUMA channel)
Synchronous
wrt PCLK_IN
LUMA Output Data Bus. DATA_OUT [19] is LUMA_OUT[9]
which is the MSB of the LUMA output signal (pin 64).
DATA_OUT [10] is LUMA_OUT[0] which is the LSB of the
LUMA output signal (pin 53).
65
LN_ERR
Synchronous
wrt PCLK_IN
Status Signal Output. Used to indicate a Line Number error or
a mismatch between the embedded line number and the
flywheel line number when the flywheel is enabled. When
LN_ERR is high, a line number error is detected or the internal
flywheel indicates mismatching line numbers. Refer to Fig. 3
for timing information of LN_ERR relative to LUMA
(DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]) Since
LN_ERR depends on the sequence of line numbers, a line
number error will actually cause LN_ERR to go high for two
lines.
66
SAV_ERR
Synchronous
wrt PCLK_IN
Output
Status Signal Output. Indicates a TRS error or a mismatch
between the embedded TRS and the flywheel TRS when the
flywheel is enabled. This signal is set high when an error in the
SAV TRS is detected or when the internal flywheel indicates
there is a mismatching SAV TRS. Refer to Fig. 3 for timing
information of SAV_ERR relative to LUMA (DATA_OUT[19:10])
and CHROMA (DATA_OUT [9:0]).
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PIN DESCRIPTIONS
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
67
EAV_ERR
Synchronous
wrt PCLK_IN
Output
Status signal output. Indicates a TRS error or a mismatch
between the embedded TRS and the flywheel TRS when the
flywheel is enabled. This signal is set high when an error in the
EAV TRS is detected or when the internal flywheel indicates
there is a mismatching EAV TRS. Refer to Fig. 3 for timing
information of EAV_ERR relative to LUMA (DATA_OUT[19:10])
and CHROMA (DATA_OUT [9:0]).
70
TEST
VDD
TEST
N/A
Test pin. Used for test purposes only. This pin must be
connected to GND for normal operation.
92, 96, 97, 98,
99,100,101
N/A
N/A
Must be connected to VDD for normal operation.
95, 102
GND
N/A
Must be connected to GND for normal operation.
103,104,105, 106,
107, 108, 111, 112,
113, 114, 117, 118,
119,120, 121, 122,
123, 124, 125, 126
DATA_IN [19:0]
Synchronous
wrt PCLK_IN
Input
Input data bus. DATA_IN [19] is the MSB of the signal (pin 103).
DATA_IN [0] is the LSB of the signal (pin 126).
This data is typically scrambled and not word aligned.
Progressive Scan Standards Indication
(VD_STD[3]=0)
DETAILED DESCRIPTION
1. DATA INPUT AND OUTPUTS
VD_STD[3:0]
0000
DESCRIPTION
720p (60 & 60/1.001Hz → L/M) [SMPTE296M]
Reserved
Data enters and exits the device on the rising edge of
PCLK_IN as shown in Figures 1 and 2. This data can be
scrambled or unscrambled and framed or unframed.
0001
0010
1080p (30 & 30/1.001Hz → G/H)
2. DESCRAMBLER AND FRAMER
[SMPTE274M]
Both the descrambler and framer can be enabled or
disabled independently of each other to allow the input to
remain scrambled or unscrambled. If the data is
unscrambled, it can be word aligned (framed) or passed
through unaltered.
0011
0100
0101
0110
0111
Reserved
1080p (25Hz → I) [SMPTE274M]
Reserved
1080p (24 & 24/1.001Hz → J/K) [SMPTE274M]
Unknown Progressive with F = 0 always.
3. STANDARDS INDICATION
VD_STD[3:0] indicates the standard that the device has
detected. The states of VD_STD[3:0] are shown in the
following standards indication tables.
Note the following in the above tables:
SMPTE260M is 1125 lines/frame
SMPTE274M is 1125 lines/frame
SMPTE295M is 1250 lines/frame
SMPTE296M is 750 lines/frame
Interlaced Standards Indication
(VD_STD[3]=1)
VD_STD[3:0]
1000
DESCRIPTION
1080i (30 & 30/1.001Hz → D/E) [SMPTE274M]
Reserved
1001
See Table 1 for more specific details on the source format
parameters.
1010
1080i (25Hz → F) [SMPTE274M]
Reserved
1011
1100
1080i (25Hz → C) [SMPTE295M]
Reserved
1101
1110
1035i (30 & 30/1.001Hz → A/B) [SMPTE260M]
Unknown Interlaced with F switching 0/1
1111
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4. FLY WHEEL OPERATION
5. AUTOMATIC SWITCH LINE LOCK HANDLING
The flywheel logic will check the incoming video data for
valid video lines. If the incoming data represents a valid
line, the flywheel remains in sync with the incoming data. If
the incoming data represents an invalid line, the flywheel
will use the stored timing information for the past valid line
to generate the output HVF timing signals until three (3)
consecutive lines having identical timing are detected. In
this case, the new timing information will be saved and the
flywheel operation is updated to this new timing.
Mismatches between the HVF information decoded from
the data stream and that indicated by the flywheel will
trigger the EAV_ERR and SAV_ERR signals as shown in
Figure 3. HVF output timing is shown in Figure 2.
The automatic switch line lock is based on the assumption
that the switching of video sources will only cause the H
signal to be out of alignment whereas V and F signals
remain in sync; i.e. switching between video sources of the
same format. Therefore, when in the automatic switch line
lock mode (FAST_LOCK transitions for low to high), the
flywheel positive H signal transition will align with the
detected positive H signal transition. Timing for the
FAST_LOCK signal is shown in Figure 5.
TABLE 1: Source Format Parameters
Reference SMPTE
Standard
260m
260m
295m
274m
274m
274m
274m
274m
274m
274m
274m
296m
296m
Format ID
A
B
C
D
E
F
G
H
I
J
K
L
M
Lines/Frame
Words/Active Line
1125
1920
1125
1920
1250
1920
1125
1920
1125
1920
1125
1920
1125
1920
1125
1920
1125
1920
1125
1920
1125
1920
750
1280
750
1280
(each channel Y,
Cb/Cr)
Total Active Lines
1035
2200
1035
2200
1080
2376
1080
2200
1080
2200
1080
2640
1080
2200
1080
2200
1080
2640
1080
2750
1080
2750
720
720
Words/Total Line
(each channel Y,
Cb/Cr)
1650
1650
Frame Rate (Hz)
Fields /Frame
30
2
30/M
2
25
2
30
2
30/M
2
25
2
30
1
30/M
1
25
1
24
1
24/M
1
60
1
60/M
1
Data Rate Divisor
1
M
1
1
M
1
1
M
1
1
M
1
M
NOTE: M=1.001 in the above table.
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PCLK_IN
DATA_IN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA_OUT
tSU
tIH
tOH
tOD
Fig. 1 Synchronous I/O Timing
PCLK_IN
XYZ
(EAV ID)
XYZ
(SAV ID)
DATA_OUT[19:10]
(LUMA)
3FF
3FF
000
000
000
000
YLN0
CLN0
3FF
3FF
000
000
000
000
XYZ
(EAV ID)
XYZ
(SAV ID)
DATA_OUT[9:0]
(CHROMA)
H
V
F
Fig. 2 HVF Timing
PCLK_IN
Correct/Incorrect
Line Number
Correct/Incorrect ID
000
Correct/Incorrect ID
000
DATA_OUT
(Luma or Chroma
depending on the
state of TRS_Y/C)
XYZ
(EAV-ID)
XYZ
(SAV-ID)
3FF
000
LN0
LN1
3FF
000
EAV_ERR
SAV_ERR
LN_ERR
Fig. 3 EAV_ERR, SAV_ERR and LN_ERR Timing
PCLK_IN
DATA_OUT[19:10]
(LUMA)
XYZ
000
XYZ
(SAV-ID)
3FF
3FF
000
3FF
3FF
000
000
000
000
(EAV-ID)
DATA_OUT[9:0]
(CHROMA)
XYZ
000
XYZ
(SAV-ID)
000
(EAV-ID)
FIFO_L
(F_E/S=1)
FIFO_L
(F_E/S=0)
Fig. 4 FIFO_L Timing
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GENNUM CORPORATION
522 - 47 - 00
DATA_IN
(Luma or Chroma
depending on the
state of TRS_Y/C)
ANC
SPACE
ANC
SPACE
EAV
SAV
ACTIVE PICTURE
EAV
SAV
ACTIVE PICTURE
Switch Line
Switch Line + 1
FAST_LOCK
A Low to High Transition in the Active
Picture of a Line Forces the GS1500 to
Resynchronize to the next valid TRS ID
Fig. 5 FAST_LOCK Timing
PCLK_IN
DATA_OUT[19:10]
(LUMA)
XYZ
(EAV-ID)
3FF
3FF
000
000
000
YLN0
YLN1
YCCR0
YCCR1
LINE_CRC_ERR_Y
DATA_OUT[9:0]
(CHROMA)
XYZ
(EAV-ID)
000
CLN0
CLN1
CCCR0
CCCR1
LINE_CRC_ERR_C
Fig. 6 Luma and Chroma LINE_CRC_ERR Timing
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GENNUM CORPORATION
522 - 47 - 00
PACKAGE DIMENSIONS
0.2ꢀ
23.20
20.0
0.ꢁ0
ꢁ8.ꢀ0 REF
0.2ꢀ
ꢁ7.20
ꢁ2.ꢀ0 REF
ꢁ4.0
0.ꢁ0
3.00 MAX
0.2ꢀ
2.80
0.08
0.ꢀ0 BSC
0.27
ꢁ2 TYP
0.7ꢀ MIN
0 -7
0.30 MAX RADIUS
0 - 7
0.ꢁ3 MIN.
RADIUS
0.ꢁꢀ
0.88
128 pin MQFP
ꢁ.6
REF
All dimensions in millimetres
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
REVISION NOTES:
Updated Absolute Maximum Ratings; Updated AC and DC
Electrical Characteristics Tables; Updated Figure 4.
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET
The product is in a preproduction phase and specifications
are subject to change.
For latest product information, visit www.gennum.com
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright August 1999 Gennum Corporation. All rights reserved. Printed in Canada.
522 - 47 - 00
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