GS1508-CTA [GENNUM]

HDTV Cable Driver; HDTV电缆驱动器
GS1508-CTA
型号: GS1508-CTA
厂家: GENNUM CORPORATION    GENNUM CORPORATION
描述:

HDTV Cable Driver
HDTV电缆驱动器

驱动器 电视
文件: 总8页 (文件大小:118K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
HD-LINX GS1508  
HDTV Cable Driver  
PRELIMINARY DATA SHEET  
FEATURES  
DESCRIPTION  
• SMPTE 292M compliant  
The GS1508 is a first generation very high speed bipolar  
integrated circuit designed to drive two 75co-axial  
cables. The GS1508 is a SMPTE 292M compliant cable  
driver that directly interfaces with other Gennum HDTV  
devices and can also be used as a general purpose high  
speed cable driver.  
• dual cable driving outputs optimized for driving data  
up to 1.485Gb/s  
• ±7% tolerance output  
• >17dB output return loss  
• minimum external components  
The GS1508 features two complementary outputs whose  
amplitude is controlled within a precise 7% variation. The  
output amplitude can be varied by adjusting the RSET  
resistor value.  
• seamless interface with the HD-LINX™ family of  
products  
• low power  
• standard packaging  
The serial inputs can be AC coupled. The GS1508 is a low  
power device that does not require external pull down  
resistors. The GS1508 is packaged in an 8 pin SOIC and  
operates from a single 5V power supply.  
APPLICATIONS  
1.485Gb/s HDTV Serial Digital Receiver Interfaces for:  
Routers, Distribution Amplifiers, Switchers, and other  
transmitting equipment.  
ORDERING INFORMATION  
PART NUMBER  
GS1508-CKA  
GS1508-CTA  
PACKAGE  
8 pin SOIC  
TEMPERATURE  
0°C to 70°C  
8 pin Tape and Reel  
0°C to 70°C  
BANDGAP REFERENCE AND BIASING CIRCUIT  
R
SET  
SDI  
SDI  
SDO  
SDO  
INPUT  
DIFFERENTIAL  
PAIR  
OUTPUT STAGE &  
CONTROL  
PATENT PENDING  
BLOCK DIAGRAM  
Revision Date: March 2000  
Document No. 522 - 02 - 03  
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3  
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com  
www.gennum.com  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C unless otherwise indicated  
PARAMETER  
VALUE  
5.5V  
Supply Voltage  
Input Voltage Range (any input)  
Operating Temperature Range  
Storage Temperature  
-0.3 to (VCC +0.3)V  
0°C to 70°C  
-65°C to 150°C  
300mW  
Power Dissipation  
Lead Temperature (soldering, 10 sec)  
Input ESD Voltage  
260°C  
2000V  
DC ELECTRICAL CHARACTERISTICS  
VCC = 5V, TA = 0°C to 70°C unless otherwise shown.  
Specifications assume 800mV output amplitude level settings into end terminated 75transmission lines. Data Rate = 1485Mb/s unless otherwise shown.  
TEST  
LEVEL  
PARAMETER  
Supply Voltage  
CONDITIONS  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
VCC  
PD  
4.75  
-
5.00  
215  
5.25  
265  
V
1
1
System Power  
Consumption  
Driving two  
75cables  
mW  
Supply Current  
IS  
-
43  
-
54  
mA  
V
1
2
Common Mode Input  
Voltage Range  
VCM,IN  
2.5+(VDIFF/2  
)
VCC-(VDIFF/2)  
Common Mode Output  
Voltage Range  
VCM,OUT  
-
VCC-VOUT  
-
V
2
AC ELECTRICAL CHARACTERISTICS  
VCC = 5V, TA = 0°C to 70°C unless otherwise shown.  
Specifications assume 800mV output amplitude levels into end terminated 75transmission lines. Data Rate = 1485Mb/s unless otherwise shown.  
TEST  
LEVEL  
PARAMETER  
Serial Digital Rate  
CONDITIONS  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
DC  
1485  
5
-
Mb/s  
psRMS  
mV  
1
3
2
1
1
4
Additive Jitter  
1485Mb/s  
-
150  
750  
-
-
1
diff p-p  
p-p  
Differential Input  
Differential Output  
Output Rise/Fall Times  
VDIFF  
VOUT  
tR, tF  
-
800  
850  
250  
30  
800  
120  
15  
mV  
(20% - 80%)  
ps  
2
Mismatch in Output Rise/Fall  
Times  
-
ps  
Overshoot  
-
-
-
1
8
30  
-
%
ps  
dB  
4
1
4
Duty Cycle Distortion  
Output Return Loss  
NOTES:  
15  
17  
5MHz to 1485MHz  
2
TEST LEVELS:  
23  
1. 100% tested at 25°C.  
2. Guaranteed by design.  
3. Correlated Value.  
1. RMS additive jitter measured using Pseudo Random bit sequence (2 - 1).  
2. Measured with Gennum Evaluation Board (EB1508).  
4. Tested with EB1508  
2
522 - 02 - 03  
PIN CONNECTIONS  
1
2
3
4
8
7
6
5
SDI  
SDI  
SDO  
SDO  
GND  
GS1508  
TOP  
VIEW  
V
EE  
R
V
SET  
CC  
PIN DESCRIPTIONS  
NUMBER  
SYMBOL  
SDI, SDI  
VEE  
TYPE  
DESCRIPTION  
Serial data inputs (non-inverting and inverting).  
Most negative supply voltage.  
1, 2  
3
I
P
I
4
RSET  
Output amplitude control resistor.  
5
VCC  
P
P
O
Most positive supply voltage.  
6
GND  
Not connected internally. Connect to Ground. Used for isolation.  
Serial data outputs (non-inverting and inverting).  
7, 8  
SDO, SDO  
INPUT / OUTPUT CIRCUITS  
V
CC  
5k  
SDO  
SDO  
SDI  
SDI  
20k  
+
-
R
SET  
Fig. 1 (Pins 1 and 2)  
Fig. 2 (Pins 7 and 8)  
3
522 - 02 - 03  
DETAILED DESCRIPTION  
INPUT INTERFACING  
SDI/SDI are high impedance differential inputs. (See  
Figure 1 for equivalent input circuit).  
Several conditions must be observed when interfacing to  
these inputs:  
1. The differential input signal amplitude must be between  
150 and 800mVpp.  
2. The common mode voltage range must be as specified  
in the DC Characteristics table. For a 400mV input from  
the GS1504 HD cable equalizer, this corresponds to a  
common mode voltage range of between 2.7 and 4.8  
volts.  
3. For input trace lengths longer than approximately 1cm,  
the inputs should be terminated as shown in the Typical  
Application Circuit.  
Fig. 3 Output Optimized for Waveform Symmetry  
L=8.2nH, R=75 (Typical ORL=13.5dB)  
The GS1508 inputs are self biased, allowing for simple AC  
coupling to the device. For serial digital HDTV, a minimum  
capacitor value of 4.7µF should be used to allow coupling  
of pathological test signals.  
recommended.  
A tantalum capacitor is  
OUTPUT INTERFACING  
The GS1508 outputs are current mode, and will drive  
800mV into a 75 ohm load. These outputs are protected  
from accidental static damage with internal static protection  
diodes.  
The SMPTE 292M standard requires that the output of a  
cable driver have a source impedance of 75and a return  
loss of at least 15dB between 5Mhz and 1.485GHz.  
Fig. 4 Output Optimized for Return Loss  
L=12nH, C=0.5pF, R=75 (Typical ORL=18dB)  
In order for an HD SDI output circuit using the GS1508 to  
meet this specification, the output circuit shown in the  
Typical Application Circuit is recommended.  
Figures 3 and 4 show the eye diagram of the GS1508  
output for two different output compensation conditions.  
Figure 4 shows the GS1508 output optimized for wideband  
return loss of 18dB. Figure 3 shows the GS1508 output  
optimized for output waveform symmetry. In this case the  
output may not exhibit a return loss of 15dB.  
The values of LCOMP and CCOMP will vary depending on PCB  
layout, but typical values are 12nH and 0.5pF respectively.  
The small value of CCOMP can be easily swamped by  
parasitic PCB capacitance, so it is recommended that the  
ground plane be removed under the GS1508 output  
circuitry (see the Application Information section in this data  
sheet for further details). A 4.7µF capacitor is used for AC  
coupling the output of the GS1508. This value is chosen to  
ensure that pathological signals can be coupled without a  
significant DC component occurring.  
When measuring return loss at the GS1508 output it is  
necessary to take the measurement for both a logic high  
and a logic low output condition. This is because the output  
protection diodes act as a varactor (voltage controlled  
capacitor) as shown in Figure 5.  
Consequently, the output capacitance of the GS1508 is  
dependent on the logic state of the output.  
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522 - 02 - 03  
1.000  
0.800  
0.600  
0.400  
0.200  
0.000  
GS1508  
SDO  
SDO  
0.0000  
0.0050  
0.0100  
1 / R  
0.0150  
0.0200  
0.0250  
Fig. 5 Static Protection Diodes  
(mho)  
SET  
OUTPUT RETURN LOSS MEASUREMENT  
Fig. 6 GS1508 Output Amplitude vs. 1/RSET  
TABLE 1: RSET vs VOUT  
RSET  
To perform a practical return loss measurement, it is  
necessary to force the GS1508 output to a DC high or low  
condition. The actual measured return loss will be based on  
the outputs being static at VCC or VCC-1.6V. Under normal  
operating conditions the outputs of the GS1508 swing  
between VCC-0.4V and VCC-1.2V, so the measured value of  
return loss will not represent the actual operating return  
loss.  
R
1/RSET  
0.0020  
0.0067  
0.0133  
0.0187  
0.0231  
OUTPUT SWING  
0.095  
500.0  
150.0  
75.0  
0.298  
0.575  
A simple method of calculating the values of actual  
operating return loss is to interpolate the two return loss  
measurements. In this way, the values of return loss are  
53.6  
0.785  
43.2  
0.937  
estimated at  
VCC-0.4V and VCC-1.2V based on the  
measurements at VCC and VCC-1.6V.  
NOTE: For reliable operation of the GS1508 over the full  
temperature range, do not use an RSET value below 49.9.  
The two values of return loss (high and low) will typically  
differ by several decibels. If the measured return loss is RH  
for logic high and RL for logic low, then the two values can  
be interpolated as follows:  
RIH = RH- (RH-RL)/4 and  
RIL = RL+(RH-RL)/4  
where RIH is the interpolated logic high value and RIL is the  
interpolated logic low value.  
For example, if RH = -18dB and RL = -14dB, then the  
interpolated values are RIH = -17dB and RIL = -15dB.  
OUTPUT AMPLITUDE ADJUSTMENT  
The output amplitude of the GS1508 can be adjusted by  
changing the value of the RSET resistor as shown in Figure 6  
and Table 1. For an 800mVp-p output with a nominal 7%  
tolerance, a value of 53.6% is required. A 1% SMT resistor  
should be used.  
The RSET resistor is part of the high speed output circuit of  
the GS1508. The resistor should be placed as close as  
possible to the RSET pin. In addition, PCB capacitance  
should be minimized at this node by removing the PCB  
groundplane beneath the RSET resistor and the RSET pin.  
5
522 - 02 - 03  
TYPICAL APPLICATION CIRCUIT  
V
CC  
75  
C
L
COMP  
100n  
COMP  
75  
75  
PECL INPUT  
4µ7  
+
1
2
3
4
8
7
6
5
SDI  
SDI  
SDO  
SDO  
GND  
OUT  
OUT  
75  
GS1508  
+
V
L
EE  
COMP  
Z
Z
0
0
V
CC  
4µ7  
C
R
V
COMP  
SET  
CC  
1n  
All resistors in ohms,  
all capacitors in farads,  
unless otherwise shown.  
53.6  
0µ1  
TABLE 2: Typical Application Circuit Component Values  
COMPONENT  
RSET  
VALUE  
53.6  
COMMENT  
For 800mV Output  
For 50PCB trace impedance  
Z0  
50Ω  
LCOMP  
12nH  
0.5pF  
Typical value. Component value will vary depending on PCB layout.  
Typical value. Component value will vary depending on PCB layout.  
CCOMP  
APPLICATION INFORMATION  
PCB LAYOUT  
Special attention must be paid to component layout when  
designing serial digital interfaces for HDTV. Figures 8  
through 11 show the artwork for a four layer printed circuit  
evaluation board for the GS1508. The schematic is shown in  
Figure 7. An FR-4 dielectric can be used, however,  
controlled impedance transmission lines are required for  
PCB traces longer than approximately 1cm. Note the  
following PCB artwork features used to optimize  
performance:  
PCB trace width for HD rate signals is closely matched to  
SMT component width to minimize reflections due to  
change in trace impedance  
The PCB ground plane is removed under the GS1508  
output components to minimize parasitic capacitance.  
The PCB ground plane is removed under the GS1508 RSET  
pin and resistor to minimize parasitic capacitance  
Input and output BNC connectors are surface mounted in-  
line to eliminate a transmission line stub caused by a BNC  
mounting via High speed traces are curved to minimize  
impedance changes due to change of PCB trace width.  
6
522 - 02 - 03  
GS1508 EVALUATION BOARD  
V
CC  
1µ  
C1  
TP1  
C2 100n  
C3 1n  
TP2  
V
CC  
C16  
1n  
L2 10n  
R9  
C10  
R12  
50  
R8  
75  
100n  
R13  
50  
75  
R7  
75  
C14  
C11  
U2  
C17 0p5  
J7  
J4  
1µ  
SDI SDO  
SDI SDO  
4µ7  
C12  
EDGEMNT_BNC  
EDGEMNT_BNC  
L3 10n  
R10  
C13  
J6  
J5  
V
GND  
EE  
V
4µ7  
1µ  
CC  
C15  
10n  
EDGEMNT_BNC  
R
V
EDGEMNT_BNC  
SET CC  
75  
R11  
53.6  
C18 0p5  
All resistors in ohms,  
all capacitors in farads,  
unless otherwise shown.  
Fig. 7 Schematic Diagram for the GS1508 Evaluation Board  
Fig. 8 Top Layer of EB1508 PCB Layout  
Fig. 10 Ground Layer of EB1508 PCB Layout  
Fig. 9 Power Layer of EB1508 PCB Layout  
Fig. 11 Bottom Layer of EB1508 PCB Layout  
7
522 - 02 - 03  
PACKAGE DIMENSIONS  
1.91  
5.00 MAX.  
MAX  
1.27 MAX  
0.49 MAX  
5
4
8
1
0.25  
4.0  
6.20  
MAX  
MAX  
MAX  
0.25  
MAX  
=
=
=
0.60 MAX  
3.81 ±0.05  
3 spaces  
8-pin SOIC  
All dimensions are in millimetres  
@ 1.27 ±0.05  
CAUTION  
ELECTROSTATIC  
SENSITIVE DEVICES  
DO NOT OPEN PACKAGES OR HANDLE  
EXCEPT AT A STATIC-FREE WORKSTATION  
REVISION NOTES:  
DOCUMENT IDENTIFICATION  
Updated ordering information; Replaced evaluation board diagrams;  
Updated pin descriptions; Added note to Table 1.  
PRELIMINARY DATA SHEET  
This product is in production. Gennum reserves the right to make  
changes to the product and to the documentation.  
For the latest product information, visit www.gennum.com  
GENNUM JAPAN CORPORATION  
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku  
Tokyo 168-0081, Japan  
GENNUM CORPORATION  
MAILING ADDRESS:  
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3  
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946  
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839  
GENNUM UK LIMITED  
SHIPPING ADDRESS:  
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5  
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX  
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523  
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.  
© Copyright August 1998 Gennum Corporation. All rights reserved. Printed in Canada.  
522 - 02 - 03  
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