MBM29DL640E90TR_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20887-1E

FLASH MEMORY

CMOS

64 M (8 M × 8/4 M × 16) BIT

Dual Operation

MBM29DL640E^80/90/12

■ DESCRIPTION

The MBM29DL640E is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 Mwords

of 16 bits each. The device is offered in 48-pin TSOP (I) and 63-ball FBGA packages. This device is designed to

be programmed in system with 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase

operations. The device can also be reprogrammed in standard EPROM programmers.

The device is organized into four physical banks: Bank A, Bank B, Bank C and Bank D, which can be considered

to be four separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu’s

standard 3 V only Flash memories with the additional capability of allowing a normal non-delayed read access

from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simulta-

neously taking place on the other bank.

(Continued)

■ PRODUCT LINE UP

Part No.

V^CC= 3.3 V

MBM29DL640E

+0.3 V

−0.3 V

80

Ordering Part No.

+0.6 V

−0.3 V

V^CC= 3.0 V

90

35

12

120

50

Max. Address Access Time (ns)

Max. CE Access Time (ns)

Max. OE Access Time (ns)

80

30

■ PACKAGES

48-pin plastic TSOP (I)

63-ball plastic FBGA

Marking Side

(FPT-48P-M19)

(FPT-48P-M20)

(BGA-63P-M02)

MBM29DL640E^80/90/12

(Continued)

In the device, a new design concept called FlexBank^TM*¹Architecture is implemented. Using this concept the

device can execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and

Bank 2, a bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1.

(Refer to FUNCTIONAL DESCRIPTION for Simultaneous Operation.)

The standard device offers access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed

microprocessors without the wait. To eliminate bus contention the device has separate chip enable (CE) , write

enable (WE) and output enable (OE) controls.

This device consists of pin and command set compatible with JEDEC standard E²PROMs. Commands are

written to the command register using standard microprocessor write timings. Register contents serve as input

to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally

latch addresses and data needed for the programming and erase operations. Reading data out of the device is

similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded

Program Algorithm^TMwhich is an internal algorithm that automatically times the program pulse widths and verifies

proper cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is

accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm^TM

which is an internal algorithm that automatically preprograms the array if it is not already programmed before

executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies

the proper cell margin.

A sector is typically erased and verified in 1.0 second (if already completely preprogrammed) .

The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once a program or erase cycle has been completed,

the device internally resets to the read mode.

The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program

Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read

mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the

Embedded Program^TM*²Algorithm or Embedded Erase^TM*²Algorithm, the device is automatically reset to the

read mode and have erroneous data stored in the address locations being programmed or erased. These

locations need rewriting after the Reset. Resetting the device enables the system’s microprocessor to read the

boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of EPROM and E²PROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits

within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word

at a time using the EPROM programming mechanism of hot electron injection.

*1: FlexBank^TMis a trademark of Fujitsu Limited.

*2: Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

2

MBM29DL640E^80/90/12

■ FEATURES

• 0.23 µm Process Technology

• Simultaneous Read/Write operations (Dual Bank)

• FlexBank^TM

Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)

Bank B : 24 Mbit (64 KB × 48)

Bank C : 24 Mbit (64 KB × 48)

Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)

Two virtual Banks are chosen from the combination of four physical banks (Refer to Table 9, 10)

Host system can program or erase in one bank, and then read immediately and simultaneously from the other

bank with zero latency between read and write operations.

Read-while-erase

Read-while-program

• Single 3.0 V read, program, and erase

Minimized system level power requirements

• Compatible with JEDEC-standard commands

Uses the same software commands as E²PROMs

• Compatible with JEDEC-standard world-wide pinouts

48-pin TSOP (I) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type)

63-ball FBGA (Package suffix : PBT)

• Minimum 100,000 program/erase cycles

• High performance

80 ns maximum access time

• Sector erase architecture

Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode

Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode

Any combination of sectors can be concurrently erased. It also supports full chip erase.

• Hidden ROM (Hi-ROM) region

256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

AtV^IL, allowsprotectionof“outermost”2× 8Kbytesonbothendsofbootsectors, regardlessofsectorprotection/

unprotection status

At V^IH, allows removal of boot sector protection

At VACC, increases program performance

• Embedded Erase^TMAlgorithms

Automatically preprograms and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

(Continued)

3

MBM29DL640E^80/90/12

(Continued)

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, the device automatically switches itself to low power mode.

• Low V^CCwrite inhibit ≤ 2.5 V

• Program Suspend/Resume

Suspends the program operation to allow a read in another byte

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector group protection

Hardware method disables any combination of sector groups from program or erase operations

• Sector Group Protection Set function by Extended sector group protection command

• Fast Programming Function by Extended Command

• Temporary sector group unprotection

Temporary sector group unprotection via the RESET pin.

• In accordance with CFI (Common Flash Memory Interface)

4

MBM29DL640E^80/90/12

■ PIN ASSIGNMENTS

TSOP (I)

A15

A14

A13

A12

A11

A10

A9

A8

A19

A16

48

1

2

3

4

5

6

7

8

(Marking Side)

BYTE

47

VSS

46

DQ15/A-1

45

DQ7

44

DQ14

43

DQ6

42

DQ13

41

DQ5

40

9

A20

DQ12

39

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE

RESET

A21

WP/ACC

RY/BY

A18

DQ4

38

VCC

37

Standard Pinout

DQ11

36

DQ3

35

DQ10

34

DQ2

33

A17

A7

A6

A5

A4

A3

A2

A1

DQ9

32

DQ1

31

DQ8

30

DQ0

29

OE

28

VSS

27

CE

26

A0

25

(FPT-48P-M19)

A1

A2

A3

A4

A5

A6

A7

A17

A18

A0

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

(Marking Side)

CE

26

VSS

27

OE

28

DQ0

29

DQ8

30

DQ1

31

DQ9

32

DQ2

33

RY/BY

WP/ACC

A21

RESET

WE

A20

DQ10

34

DQ3

35

DQ11

36

Reverse Pinout

VCC

37

DQ4

38

DQ12

39

A19

A8

A9

A10

A11

A12

A13

A14

DQ5

40

DQ13

41

DQ6

42

DQ14

43

DQ7

44

DQ15/A-1

45

VSS

46

BYTE

47

A15

A16

48

(FPT-48P-M20)

(Continued)

5

MBM29DL640E^80/90/12

(Continued)

FBGA

(TOP VIEW)

(Marking Side)

A8

N.C. N.C.

A7 B7

B8

L8

N.C. N.C.

L7 M7

N.C. N.C.

M8

C7

D7

E7

F7

G7

A16 BYTEDQ15/A-1 VSS

G6 H6 J6 K6

DQ7 DQ14 DQ13 DQ6

H7

J7

K7

N.C. N.C.

A13

A12

A14

A15

C6

A9

D6

A8

E6

F6

A10

A11

C5

D5

E5

F5

G5

DQ5 DQ12

G4 H4

H5

J5

K5

WE RESET A21

C4 D4 E4

RY/BYWP/ACC A18

A19

VCC

DQ4

F4

J4

K4

A20

DQ2 DQ10 DQ11 DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

A2

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

CE

J2

K2

L2

N.C. N.C.

L1 M1

N.C. N.C.

M2

N.C.

OE

VSS

A1

B1

N.C. N.C.

(BGA-63P-M02)

6

MBM29DL640E^80/90/12

■ PIN DESCRIPTIONS

Table 1 MBM29DL640E Pin Configuration

Function

A²¹to A0, A-1

DQ¹⁵to DQ0

CE

Address Input

Data Input/Output

Chip Enable

OE

Output Enable

Write Enable

WE

RY/BY

RESET

BYTE

WP/ACC

V^SS

Ready/Busy Output

Hardware Reset Pin/Temporary Sector Group Unprotection

Selects 8-bit or 16-bit mode

Hardware Write Protection/Program Acceleration

Device Ground

VCC

Device Power Supply

N.C.

No Internal Connection

7

MBM29DL640E^80/90/12

■ BLOCK DIAGRAM

VCC

VSS

Bank A

address

Cell Matrix

8 Mbit

Cell Matrix

24 Mbit

A21 to A0

(A-1)

(Bank A)

(Bank B)

X-Decoder

Bank B Address

State

Control

&

Command

Register

RESET

RY/BY

WE

CE

OE

DQ15

to

DQ0

Status

Control

BYTE

WP/ACC

DQ15 to DQ0

Bank C Address

X-Decoder

Cell Matrix

8 Mbit

Cell Matrix

24 Mbit

(Bank D)

(Bank C)

Bank D

address

■ LOGIC SYMBOL

A-1

22

A21 to A0

16 or 8

DQ0 to DQ15

RY/BY

CE

OE

WE

RESET

BYTE

8

MBM29DL640E^80/90/12

■ DEVICE BUS OPERATION

Table 2 MBM29DL640E User Bus Operations (BYTE = V^IH)

DQ¹⁵to

DQ⁰

WP/

ACC

Operation

CE OE WE A⁰

A¹

A²

A³

A⁶

A⁹

RESET

Auto-Select Manufacturer

Code *¹

L

H

L

VID

Code

H

X

Auto-Select Device Code *¹

L

H

L

H

X

H

L

H

L

H

L

H

A2

X

L

H

A3

X

L

VID

V^ID

A9

X

Code

DOUT

H

X

Extended Auto-Select Device

Code *¹

L

H

A0

X

H

L

Read *³

L

A1

X

A6

X

Standby

X

H

High-Z

DIN

Output Disable

Write (Program/Erase)

X

A⁰

A1

A2

A3

A6

A9

Enable Sector Group

Protection *^2,*⁴

L

VID

L

H

L

VID

X

H

X

Verify Sector Group Protection

*^2,*⁴

L

H

Code

Temporary Sector Group

Unprotection *⁵

X

High-Z

X

VID

L

X

L

Reset (Hardware) /Standby

Boot Block Sector Write

Protection *⁶

X

Legend : L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See DC Characteristics for voltage levels.

*1: Manufacturer and device codes may also be accessed via a command register write sequence. SeeTable 4.

*2: Refer to section on Sector Group Protection.

*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4: VCC = 3.3 V ± 10%

*5: It is also used for the extended sector group protection.

*6: Protect “outermost” 2 × 8 Kbytes (4 Kwords) on both ends of the boot block sectors.

(Continued)

9

MBM29DL640E^80/90/12

(Continued)

Table 3 MBM29DL640E User Bus Operations (BYTE = V^IL)

DQ¹⁵

/A^-1

WP/

ACC

Operation

CE OE WE

A⁰

A¹

A²

A³

A⁶

A⁹DQ⁷to DQ⁰RESET

Auto-Select

L

H

L

VID

Code

H

X

Manufacturer Code *¹

Auto-Select Device

Code *¹

H

L

H

L

H

X

H

L

H

L

VID

V^ID

A9

X

Code

DOUT

H

X

Extended Auto-Select

Device Code *¹

Read *³

L

A-1

X

A0

X

A1

X

A2

X

A3

X

A6

X

Standby

X

H

High-Z

DIN

Output Disable

Write (Program/Erase)

X

A^-1

A0

A1

A2

A3

A6

A9

Enable Sector Group

Protection *^2,*⁴

L

VID

L

H

X

L

VID

X

Code

X

H

X

L

Verify Sector Group

Protection *^2,*⁴

H

X

Temporary Sector

Group Unprotection *⁵

X

VID

L

Reset (Hardware) /

Standby

X

High-Z

X

Boot Block Sector Write

Protection *⁶

X

Legend : L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See DC Characteristics for voltage levels.

*1: Manufacturer and device codes may also be accessed via a command register write sequence. See Table 4.

*2: Refer to section on Sector Group Protection.

*3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4: V^CC= 3.3 V ± 10%

*5: Also used for extended sector group protection.

*6: Protects “outermost” 2 × 8 Kbytes (4 Kwords) on both ends of the boot block sectors.

10

MBM29DL640E^80/90/12

Table 4 MBM29DL640E Command Definitions

Fourth Bus

Read/Write

Cycle

Bus

Write

Cy-

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Command

Sequence

cles

Req’d

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

Byte

Word

Byte

Read/

Reset

1

3

XXXh F0h

—

555h

AAh

2AAh

555h

Read/

Reset

55h

F0h

RA

RD

AAAh

(BA)

555h

Word

Byte

555h

AAh

2AAh

555h

Autoselect

3

4

55h

90h

A0h

—

(BA)

AAAh

Word

Byte

555h

AAh

2AAh

555h

Program

PA

—

PD

—

AAAh

Program

Suspend

1

BA

B0h

30h

—

Program Resume

BA

555h

AAAh

555h

AAAh

BA

—

555h

AAAh

555h

AAAh

—

2AAh

555h

2AAh

555h

—

Word

Chip Erase

Byte

2AAh

555h

2AAh

555h

—

555h

AAAh

555h

AAAh

—

555h

AAAh

6

AAh

55h

80h

AAh

55h

10h

30h

Word

Sector

Erase

SA

Byte

Erase Suspend

Erase Resume

1

B0h

30h

—

BA

—

Word

555h

AAAh

XXXh

BA

2AAh

555h

AAAh

Set to

Fast Mode

3

2

AAh

A0h

55h

PD

20h

—

Byte

Word

Byte

Word

Fast

Program *¹

PA

—

Reset from

Fast Mode

XXXh

4

*

2

4

90h

—

F0h

Byte

Word

BA

1

*

Extended

Sector

Group

XXXh 60h SPA 60h SPA 40h SPA SD

Protection

*

Byte

2

(BA)

55h

Word

Byte

Query

1

98h

—

(BA)

AAh

(Continued)

11

MBM29DL640E^80/90/12

(Continued)

Fourth Bus

Read/Write

Cycle

Bus

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Write

Cy-

Command

Sequence

cles

Req’d

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

Byte

Word

Byte

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

Hi-ROM

Entry

3

4

AAh

55h

88h

A0h

—

Hi-ROM

Program *³

(HRA)

PA

PD

(HRBA)

Word

Byte

555h

2AAh

555h

Hi-ROM

Exit *³

4

AAh

55h

90h XXXh 00h

—

(HRBA)

AAAh

*1: This command is valid during Fast Mode.

*2: This command is valid while RESET = VID.

*3: This command is valid during Hi-ROM mode.

*4: The data “00h” is also acceptable.

Notes : 1. Address bits A²¹to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector

Address (SA) , Bank Address (BA) and Sector Group Address (SPA) .

2. Bus operations are defined in Tables 2 and 3.

3. RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A²¹, A20, A19, A18, A17, A16, A15, A14, A13 and

A12 will uniquely select any sector.

BA = Bank Address. Address setted by A21, A20, A19 will select Bank A, Bank B, Bank C and Bank D.

4. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5. SPA = Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) =

(0, 0, 0, 1, 0) .

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

6. HRA = Address of the Hi-ROM area Word Mode : 000000h to 00007Fh

Byte Mode : 000000h to 0000FFh

7. HRBA = Bank Address of the Hi-ROM area (A²¹= A20 = A19 = VIL)

8. The system should generate the following address patterns:

Word Mode : 555h or 2AAh to addresses A¹⁰to A0

Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1

9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

12

MBM29DL640E^80/90/12

Table 5.1 MBM29DL640E Sector Group Protection Verify Autoselect Codes

*1

Type

A²¹to A¹²

A⁶

A³

A²

A¹

A⁰

A^-1

Code (HEX)

04h

Manufacture’s Code

BA^*3

VIL

X

Byte

7Eh

Device Code

BA^*3

VIL

VIH

VIL

VIH

VIL

VIH

VIL

Word

Byte

227Eh

02h

VIL

X

Word

Byte

2202h

01h

Extended Device

Code^*4

VIL

X

VIL

VIH

VIL

VIH

VIL

VIH

VIL

Word

2201h

Sector Group

Addresses

Sector Group Protection

V^IL

VIL

01h^*2

*1 : A^-1is for Byte mode.

*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*3 : When V^IDis applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous

operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank

address needs to be indicated when Autoselect mode is read out at command mode, because then it becomes

possible to activate simultaneous operation.

*4 : At WORD mode, a read cycle at address (BA) 01h (at BYTE mode, (BA) 02h) outputs device code. When 227Eh

(at BYTE mode, 7Eh) is output, it indicates that two additional codes, called Extended Device Codes, will be

required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA)

0Eh (at BYTE mode, (BA) 1Ch) , as well as at (BA) 0Fh (at BYTE mode, (BA) 1Eh) .

Table 5.2 Expanded Autoselect Code Table

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10

DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A-1/

0

Manufacturer’s Code

04h

0

1

0

HI- HI- HI- HI- HI- HI- HI-

(B)

7Eh A-1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Z

Device Code

(W) 227Eh

0

1

0

1

0

HI- HI- HI- HI- HI- HI- HI-

(B)

02h A^-1

Z

(W) 2202h

0

1

0

1

0

Extended

Device Code

HI- HI- HI- HI- HI- HI- HI-

(B)

01h A^-1

Z

(W) 2201h

0

1

0

1

0

Sector Group

Protection

A^-1/

0

01h

0

(B) : Byte mode

(W) : Word mode

13

MBM29DL640E^80/90/12

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

Table 6.1 Sector Address Tables (Bank A)

Sector Address

Sector

Sec-

tor

( × 8)

Address Range

( × 16)

Address Range

Bank

Address

Size

(Kbytes/

Kwords)

Bank

A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8/4

000000h to 001FFFh 000000h to 000FFFh

002000h to 003FFFh 001000h to 001FFFh

004000h to 005FFFh 002000h to 002FFFh

006000h to 007FFFh 003000h to 003FFFh

008000h to 009FFFh 004000h to 004FFFh

00A000h to 00BFFFh 005000h to 005FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00E000h to 00FFFFh 007000h to 007FFFh

SA1

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

SA8

X

64/32 010000h to 01FFFFh 008000h to 00FFFFh

64/32 020000h to 02FFFFh 010000h to 017FFFh

64/32 030000h to 03FFFFh 018000h to 01FFFFh

64/32 040000h to 04FFFFh 020000h to 027FFFh

64/32 050000h to 05FFFFh 028000h to 02FFFFh

64/32 060000h to 06FFFFh 030000h to 037FFFh

64/32 070000h to 07FFFFh 038000h to 03FFFFh

64/32 080000h to 08FFFFh 040000h to 047FFFh

64/32 090000h to 09FFFFh 048000h to 04FFFFh

64/32 0A0000h to 0AFFFFh 050000h to 057FFFh

64/32 0B0000h to 0BFFFFh 058000h to 06FFFFh

64/32 0C0000h to 0CFFFFh 060000h to 067FFFh

64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh

64/32 0E0000h to 0EFFFFh 070000h to 077FFFh

64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Bank

A

Note : The address range is A²¹: A-1 if in byte mode (BYTE = VIL) .

The address range is A21 : A0 if in word mode (BYTE = VIH) .

14

MBM29DL640E^80/90/12

Table 6.2 Sector Address Tables (Bank B)

Sector Address

Sector

Size

Sec-

tor

( × 8)

Address Range

( × 16)

Address Range

Bank

Address

Bank

(Kbytes/

Kwords)

A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

64/32 100000h to 10FFFFh 080000h to 087FFFh

64/32 110000h to 11FFFFh 088000h to 08FFFFh

64/32 120000h to 12FFFFh 090000h to 097FFFh

64/32 130000h to 13FFFFh 098000h to 09FFFFh

64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh

64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh

64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh

64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh

64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh

64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh

64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

64/32 200000h to 20FFFFh 100000h to 107FFFh

64/32 210000h to 21FFFFh 108000h to 10FFFFh

64/32 220000h to 22FFFFh 110000h to 117FFFh

64/32 230000h to 23FFFFh 118000h to 11FFFFh

64/32 240000h to 24FFFFh 120000h to 127FFFh

64/32 250000h to 25FFFFh 128000h to 12FFFFh

64/32 260000h to 26FFFFh 130000h to 137FFFh

64/32 270000h to 27FFFFh 138000h to 13FFFFh

64/32 280000h to 28FFFFh 140000h to 147FFFh

64/32 290000h to 29FFFFh 148000h to 14FFFFh

64/32 2A0000h to 2AFFFFh 150000h to 157FFFh

64/32 2B0000h to 2BFFFFh 158000h to 15FFFFh

64/32 2C0000h to 2CFFFFh 160000h to 167FFFh

64/32 2D0000h to 2DFFFFh 168000h to 16FFFFh

64/32 2E0000h to 2EFFFFh 170000h to 177FFFh

Bank

B

(Continued)

15

MBM29DL640E^80/90/12

(Continued)

Sector Address

Sector

Size

Sec-

tor

( × 8)

Address Range

( × 16)

Address Range

Bank

Address

Bank

(Kbytes/

Kwords)

A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

64/32 2F0000h to 2FFFFFh 178000h to 17FFFFh

64/32 300000h to 30FFFFh 180000h to 187FFFh

64/32 310000h to 31FFFFh 188000h to 18FFFFh

64/32 320000h to 32FFFFh 190000h to 197FFFh

64/32 330000h to 33FFFFh 198000h to 19FFFFh

64/32 340000h to 34FFFFh 1A0000h to 1A7FFFh

64/32 350000h to 35FFFFh 1A8000h to 1AFFFFh

64/32 360000h to 36FFFFh 1B0000h to 1B7FFFh

64/32 370000h to 37FFFFh 1B8000h to 1BFFFFh

64/32 380000h to 38FFFFh 1C0000h to 1C7FFFh

64/32 390000h to 39FFFFh 1C8000h to 1CFFFFh

64/32 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

64/32 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

64/32 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

64/32 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

64/32 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

64/32 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

Bank

B

Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .

The address range is A21 : A0 if in word mode (BYTE = VIH) .

16

MBM29DL640E^80/90/12

Table 6.3 Sector Address Tables (Bank C)

Sector Address

Sector

Size

Sec-

tor

( × 8)

Address Range

( × 16)

Address Range

Bank

Address

Bank

(Kbytes/

Kwords)

A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

64/32 400000h to 40FFFFh 200000h to 207FFFh

64/32 410000h to 41FFFFh 208000h to 20FFFFh

64/32 420000h to 42FFFFh 210000h to 217FFFh

64/32 430000h to 43FFFFh 218000h to 21FFFFh

64/32 440000h to 44FFFFh 220000h to 227FFFh

64/32 450000h to 45FFFFh 228000h to 22FFFFh

64/32 460000h to 46FFFFh 230000h to 237FFFh

64/32 470000h to 47FFFFh 238000h to 23FFFFh

64/32 480000h to 48FFFFh 240000h to 247FFFh

64/32 490000h to 49FFFFh 248000h to 24FFFFh

64/32 4A0000h to 4AFFFFh 250000h to 257FFFh

64/32 4B0000h to 4BFFFFh 258000h to 25FFFFh

64/32 4C0000h to 4CFFFFh 260000h to 267FFFh

64/32 4D0000h to 4DFFFFh 268000h to 26FFFFh

64/32 4E0000h to 4EFFFFh 270000h to 277FFFh

64/32 4F0000h to 4FFFFFh 278000h to 27FFFFh

64/32 500000h to 50FFFFh 280000h to 287FFFh

64/32 510000h to 51FFFFh 288000h to 28FFFFh

64/32 520000h to 52FFFFh 290000h to 297FFFh

64/32 530000h to 53FFFFh 298000h to 29FFFFh

64/32 540000h to 54FFFFh 2A0000h to 2A7FFFh

64/32 550000h to 55FFFFh 2A8000h to 2AFFFFh

64/32 560000h to 56FFFFh 2B0000h to 2B7FFFh

64/32 570000h to 57FFFFh 2B8000h to 2BFFFFh

64/32 580000h to 58FFFFh 2C0000h to 2C7FFFh

64/32 590000h to 59FFFFh 2C8000h to 2CFFFFh

64/32 5A0000h to 5AFFFFh 2D0000h to 2D7FFFh

64/32 5B0000h to 5BFFFFh 2D8000h to 2DFFFFh

64/32 5C0000h to 5CFFFFh 2E0000h to 2EE7FFh

64/32 5D0000h to 5DFFFFh 2E8000h to 2EFFFFh

64/32 5E0000h to 5EFFFFh 2F0000h to 2F7FFFh

64/32 5F0000h to 5FFFFFh 2F8000h to 2FFFFFh

Bank

C

(Continued)

17

MBM29DL640E^80/90/12

(Continued)

Sector Address

Sector

Size

Sec-

tor

( × 8)

Address Range

( × 16)

Address Range

Bank

Address

Bank

(Kbytes/

Kwords)

A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

64/32 600000h to 60FFFFh 300000h to 307FFFh

64/32 610000h to 61FFFFh 308000h to 30FFFFh

64/32 620000h to 62FFFFh 310000h to 317FFFh

64/32 630000h to 63FFFFh 318000h to 31FFFFh

64/32 640000h to 64FFFFh 320000h to 327FFFh

64/32 650000h to 65FFFFh 328000h to 32FFFFh

64/32 660000h to 66FFFFh 330000h to 337FFFh

64/32 670000h to 67FFFFh 338000h to 33FFFFh

64/32 680000h to 68FFFFh 340000h to 347FFFh

64/32 690000h to 69FFFFh 348000h to 34FFFFh

64/32 6A0000h to 6AFFFFh 350000h to 357FFFh

64/32 6B0000h to 6BFFFFh 358000h to 35FFFFh

64/32 6C0000h to 6CFFFFh 360000h to 367FFFh

64/32 6D0000h to 6DFFFFh 368000h to 36FFFFh

64/32 6E0000h to 6EFFFFh 370000h to 377FFFh

64/32 6F0000h to 6FFFFFh 378000h to 37FFFFh

Bank

C

Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .

The address range is A21 : A0 if in word mode (BYTE = VIH) .

18

MBM29DL640E^80/90/12

Table 6.4 Sector Address Tables (Bank D)

Sector Address

Sector

Size

Sec-

tor

( × 8)

Address Range

( × 16)

Address Range

Bank

Address

Bank

(Kbytes/

Kwords)

A²¹A²⁰A¹⁹A¹⁸A¹⁷A¹⁶A¹⁵A¹⁴A¹³A¹²

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32 700000h to 70FFFFh 380000h to 387FFFh

64/32 710000h to 71FFFFh 388000h to 38FFFFh

64/32 720000h to 72FFFFh 390000h to 397FFFh

64/32 730000h to 73FFFFh 398000h to 39FFFFh

64/32 740000h to 74FFFFh 3A0000h to 3A7FFFh

64/32 750000h to 75FFFFh 3A8000h to 3AFFFFh

64/32 760000h to 76FFFFh 3B0000h to 3B7FFFh

64/32 770000h to 77FFFFh 3B8000h to 3BFFFFh

64/32 780000h to 78FFFFh 3C0000h to 3C7FFFh

64/32 790000h to 79FFFFh 3C8000h to 3CFFFFh

64/32 7A0000h to 7AFFFFh 3D0000h to 3D7FFFh

64/32 7B0000h to 7BFFFFh 3D8000h to 3DFFFFh

64/32 7C0000h to 7CFFFFh 3E0000h to 3E7FFFh

64/32 7D0000h to 7DFFFFh 3E8000h to 3EFFFFh

64/32 7E0000h to 7EFFFFh 3F0000h to 3F7FFFh

Bank

D

8/4

7F0000h to 7F1FFFh 3F8000h to 3F8FFFh

7F2000h to 7F3FFFh 3F9000h to 3F9FFFh

7F4000h to 7F5FFFh 3FA000h to 3FAFFFh

7F6000h to 7F7FFFh 3FB000h to 3FBFFFh

7F8000h to 7F9FFFh 3FC000h to 3FCFFFh

7FA000h to 7FBFFFh 3FD000h to 3FDFFFh

7FC000h to 7FDFFFh 3FE000h to 3FEFFFh

7FE000h to 7FFFFFh 3FF000h to 3FFFFFh

0

1

0

1

0

1

0

1

0

1

0

1

Note : The address range is A²¹: A-1 if in byte mode (BYTE = VIL) .

The address range is A21 : A0 if in word mode (BYTE = VIH) .

19

MBM29DL640E^80/90/12

Table 7 Sector Group Address Table

Sector Group

SGA0

A²¹

0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

SGA8

0

1

X

SA8 to SA10

1

0

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SA67 to SA70

(Continued)

20

MBM29DL640E^80/90/12

(Continued)

Sector Group

A²¹

1

A²⁰

0

1

A¹⁹

0

1

0

1

A¹⁸

0

1

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A¹⁶

X

0

A¹⁵

X

0

A¹⁴

X

A¹³

X

A¹²

X

Sectors

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

SGA38

SA71 to SA74

SA75 to SA78

SA79 to SA82

SA83 to SA86

SA87 to SA90

SA91 to SA94

SA95 to SA98

SA99 to SA102

SA103 to SA106

SA107 to SA110

SA111 to SA114

SA115 to SA118

SA119 to SA122

SA123 to SA126

SA127 to SA130

SGA39

1

0

1

X

SA131 to SA133

1

0

SGA40

SGA41

SGA42

SGA43

SGA44

SGA45

SGA46

SGA47

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1

21

MBM29DL640E^80/90/12

Table 8 Common Flash Memory Interface Code

A⁶to A⁰DQ¹⁵to DQ⁰

Description

10h

11h

12h

0051h

0052h

0059h

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “QRY”

Query-unique ASCII string “PRI”

Primary OEM Command Set

2h : AMD/FJ standard type

13h

14h

0002h

0000h

Major version number, ASCII

Minor version number, ASCII

43h

44h

0031h

0033h

15h

16h

0040h

0000h

Address Sensitive Unlock

0h = Required

1h = Not Required

Address for Primary Extended Table

45h

46h

47h

0000h

0002h

0001h

Alternate OEM Command Set

(00h = not applicable)

17h

18h

0000h

Erase Suspend

Address for Alternate OEM Extended

Table

19h

1Ah

0000h

0h = Not Supported

1h = To Read Only

2h = To Read & Write

V^CCMin. (write/erase)

D7-4 : 1 V, D3-0 : 100 mV

1Bh

1Ch

0027h

0036h

Sector Protection

0h = Not Supported

X = Number of sectors per group

V^CCMax. (write/erase)

D7-4 : 1 V, D3-0 : 100 mV

Sector Temporary

Unprotection

00h = Not Supported

01h = Supported

V^PPMin. voltage

V^PPMax. voltage

1Dh

1Eh

0000h

48h

49h

4Ah

0001h

0004h

0077h

Typical timeout per single byte/word write

2^Nµs

1Fh

20h

0004h

0000h

Sector Protection Algorithm

Typical timeout for Min. size

buffer write 2^Nµs

Simultaneous Operation

00h = Not Supported

X = Total number of sectors in all banks

except Bank 1

Typical timeout per individual block erase

2^Nms

Typical timeout for full chip erase 2^Nms

Max. timeout for byte/word write 2^Ntimes

typical

Max. timeout for buffer write 2^Ntimes

typical

Max. timeout per individual block erase 2^N

times typical

Max. timeout for full chip erase 2^Ntimes

typical

21h

22h

23h

000Ah

0000h

0005h

Burst Mode Type

00h = Not Supported

4Bh

4Ch

0000h

Page Mode Type

00h = Not Supported

24h

25h

0000h

0004h

ACC (Acceleration) Supply

Minimum

00h = Not Supported,

D7-4 : 1 V, D3-0 : 100 mV

4Dh

4Eh

0085h

0095h

26h

27h

0000h

0017h

ACC (Acceleration) Supply

Maximum

00h = Not Supported,

D7-4 : 1 V, D3-0 : 100 mV

Device Size = 2^Nbyte

Flash Device Interface

description ×: ×8 / ×16

28h

29h

0002h

0000h

Boot Type

4Fh

50h

0001h

Max. number of bytes in

2Ah

2Bh

0000h

multi-byte write = 2^N

Program Suspend

00h = Not Supported

01h = Supported

Number of Erase Block Regions within

device

2Ch

0003h

Bank Organization

00h = If data at 4Ah is zero.

X = Number of Banks

Erase Block Region 1 Information

bit 0 to 15: y = number of sectors

bit 16 to 31: z = size

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

57h

0004h

(z × 256 bytes)

Bank A Region Information

58h

59h

5Ah

5Bh

0017h

0030h

0017h

X

=

Number of sectors in Bank A

Bank B Region Information

Number of sectors in Bank B

Bank C Region Information

Number of sectors in Bank C

Bank D Region Information

Number of sectors in Bank D

Erase Block Region 2 Information

bit 0 to 15: y = number of sectors

bit 16 to 31: z = size

31h

32h

33h

34h

007Dh

0000h

0001h

X

=

(z × 256 bytes)

Erase Block Region 3 Information

bit 0 to 15: y = number of sectors

bit 16 to 31: z = size

35h

36h

37h

38h

0007h

0000h

0020h

0000h

X

=

X

=

(z × 256 bytes)

22

MBM29DL640E^80/90/12

■ FUNCTIONAL DESCRIPTION

Simultaneous Operation

The device features functions that enable reading of data from one memory bank while a program or erase

operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features

(read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank

address (A²¹, A20, A19) with zero latency. The device consists of the following four banks :

Bank A : 8 × 8 KB and 15 × 64 KB; Bank B : 48 × 64 KB; Bank C : 48 × 64 KB; Bank D : 8 × 8 KB and 15 × 64 KB.

The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks,

and Bank 2, a bank consisting of the three remaining banks. (See Table 9.) This is what we call a “FlexBank”,

for example, the rest of banks B, C and D to let the system read while Bank A is in the process of program (or

erase) operation. However, the different types of operations for the three banks are impossible, e.g. Bank A

writing, Bank B erasing, and Bank C reading out. With this “FlexBank”, as described in Table 10, the system

gets to select from four combinations of data volume for Bank 1 and Bank 2, which works well to meet the system

requirement. The simultaneous operation cannot execute multi-function mode in the same bank. Table 11 shows

the possible combinations for simultaneous operation. (Refer to Figure 11 Bank-to-Bank Read/Write Timing

Diagram.)

Table 9 FlexBank^TMArchitecture

Bank 1

Combination

Bank 2

Combination

Bank

Splits

Volume

8 Mbit

Volume

56 Mbit

40 Mbit

56 Mbit

1

2

3

4

Bank A

Bank B

Bank C

Bank D

Remainder (Bank B, C, D)

Remainder (Bank A, C, D)

Remainder (Bank A, B, D)

Remainder (Bank A, B, C)

24 Mbit

8 Mbit

Table 10 Example of Virtual Banks Combination

Bank 1 Bank 2

Volume Combination

Bank

Splits

Sector Size

Volume Combination

Sector Size

Bank B

8 × 8 Kbyte/4 Kword

+

8 × 8 Kbyte/4 Kword

1

2

3

4

8 Mbit

16 Mbit

24 Mbit

32 Mbit

Bank A

+

56 Mbit

48 Mbit

Bank C

+

Bank D

+

15 × 64 Kbyte/32 Kword

111 × 64 Kbyte/32 Kword

Bank A

+

Bank D

16 × 8 Kbyte/4 Kword

Bank B

+

Bank C

+

96 × 64 Kbyte/32 Kword

30 × 64 Kbyte/32 Kword

Bank A

+

Bank C

+

16 × 8 Kbyte/4 Kword

Bank B

48 × 64 Kbyte/32 Kword 40 Mbit

8 × 8 Kbyte/4 Kword

+

78 × 64 Kbyte/32 Kword

Bank D

Bank A

+

Bank C

+

8 × 8 Kbyte/4 Kword

+

32 Mbit

+

Bank B

63 × 64 Kbyte/32 Kword

Bank D

63 × 64 Kbyte/32 Kword

Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which

a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,

neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)

Meanwhile the system would get to read from either Bank C or Bank D.

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MBM29DL640E^80/90/12

Table 11 Simultaneous Operation

Case

Bank 1 Status

Read mode

Bank 2 Status

Read mode

1

2

3

4

5

6

7

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets

suspended so that it enables reading from or programming the remaining sectors.

Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank

consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the

Banks.

Read Mode

The device has two control functions which are required in order to obtain data at the outputs. CE is the power

control and should be used for a device selection. OE is the output control and should be used to gate data to

the output pins.

Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access

time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable

access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses

have been stable for at least tACC-tOE time) . When reading out data without changing addresses after power-up,

it is necessary to input hardware reset or to change CE pin from “H” or “L”

Standby Mode

There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and

the other via the RESET pin only.

When using both pins, a CMOS standby mode is achieved with CE and RESET input held at VCC ± 0.3 V. Under

this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active

current (ICC2) is required even if CE = “H”. The device can be read with standard access time (tCE) from either of

these standby modes.

When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE

= “H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high,

the device requires tRH as a wake-up time for output to be valid for read access.

During standby mode, the output is in the high impedance state, regardless of OE input.

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MBM29DL640E^80/90/12

Automatic Sleep Mode

Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in

applications such as handy terminal, which requires low power consumption.

To activate this mode, the device automatically switches itself to low power mode when the device addresses

remain stable during access time of 150 ns. It is not necessary to control CE, WE and OE in this mode. In this

mode the current consumed is typically 1 µA (CMOS Level) .

During simultaneous operation, V^CCactive current (ICC2) is required.

Since the data are latched during this mode, the data are continuously read out. When the addresses are

changed, the mode is automatically canceled and the device reads the data for changed addresses.

Output Disable

With the OE input at a logic high level (VIH) , output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The Autoselect mode allows the reading out of a binary code and identifies its manufacturer and type.It is intended

for use by programming equipment for the purpose of automatically matching the device to be programmed with

itscorrespondingprogrammingalgorithm. Thismodeisfunctionalovertheentiretemperaturerangeofthedevice.

To activate this mode, the programming equipment must force V^IDon address pin A9. Three identifier bytes may

then be sequenced from the device outputs by toggling addresses. All addresses are DON’T CARES except A6,

A3, A2, A1 and A0 (A-1) . (See Tables 2 and 3.)

The manufacturer and device codes may also be read via the command register, for instances when the device

is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is

illustrated in Table 4. (Refer to Autoselect Command section.)

In the command Autoselect mode, the bank addresses BA; (A²¹, A20, A19) must point to a specific bank during

the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while

array data can be read from the other bank.

In WORD mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle

at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended

Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes

at addresses of 0Eh and 0Fh. Notice that the above applies to WORD mode; the addresses and codes differ

from those of BYTE mode. (Refer to Table 5.1 and 5.2. )

In the case of applying V^IDon A9, since both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation

cannot be executed.

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as input to the internal state machine. The state machine output dictates the function of the device.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

fallingedgeofWE or CE, whicheverhappens later, whiledataislatchedontherisingedgeof WEor CE, whichever

happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

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MBM29DL640E^80/90/12

Sector Group Protection

The device features hardware sector group protection. This feature will disable both program and erase opera-

tions in any combination of forty eight sector groups of memory. (See Table 7) . The user‘s side can use the

sector group protection using programming equipment. The device is shipped with all sector groups that are

unprotected.

To activate this mode, the programming equipment must force V^IDon address pin A9 and control pin OE, CE =

VIL and A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13 and

A12) should be set to the sector to be protected. Tables 6.1 to 6.4 define the sector address for each of the one

hundred forty-two (142) individual sectors, and Table 7 defines the sector group address for each of the forty

eight (48) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE

pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during

the WE pulse. See Figures 18 and 26 for sector group protection waveforms and algorithms.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14,

A13 and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a

protected sector. Otherwise the device will produce “0” for unprotected sectors. In this mode, the lower order

addresses, except for A0, A1, A2, A3 and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for

Autoselect manufacturer and device codes. A-1 requires applying to VIL on byte mode.

Whether the sector group is protected in the system can be determined by writing an Autoselect command.

Performing a read operation at the address location (BA) XX02h, where the higher order addresses (A21, A20,

A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address, will produce a logical “1” at DQ0

for a protected sector group. Note that the bank addresses (A21, A20, A19) must be pointing to a specific bank

during the third write bus cycle of the Autoselect command. Then the Autoselect data can be read from that

bank while array data can still be read from the other bank. To read Autoselect data from the other bank, it must

be reset to read mode and then write the Autoselect command to the other bank. See Tables 5.1 and 5.2 for

Autoselect codes.

Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector groups of the device in order to change

data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During

this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad-

dresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be

protected again. Refer to Figures 19 and 27.

Extended Sector Group Protection

In addition to normal sector group protection, the device has Extended Sector Group Protection as extended

function. This function enables protection of the sector group by forcing V^IDon RESET pin and writes a command

sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins.

The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection

requires VID on RESET pin. With this condition the operation is initiated by writing the set-up command (60h) in

the command register. Then the sector group addresses pins (A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12)

and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (setting VIL for the other

addresses pins is recommended) , and an extended sector group protection command (60h) should be written.

A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group

addresses pins (A²¹, A20, A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should

be set a command (40h) should be written. Following the command write, a logical “1” at device output DQ0 will

produce a protected sector in the read operation. If the output is logical “0”, write the extended sector group

protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to

Figures 20 and 28.)

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MBM29DL640E^80/90/12

RESET

Hardware Reset

The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to

be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process

of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after

the RESET pin is driven low. Furthermore, once the RESET pin goes high the device requires an additional “tRH”

before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the

duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program

or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal

should be ignored during the RESET pulse. See Figure 14 for the timing diagram. Refer to Temporary Sector

Group Unprotection for additional functionality.

Boot Block Sector Protection

The Write Protection function provides a hardware method of protecting certain boot sectors without using VID.

This function is one of two provided by the WP/ACC pin.

If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two

outermost 8 Kbytes on both ends of boot sectors independently of whether those sectors are protected or

unprotected using the method described in “Sector Protection/Unprotection.”

(MBM29DL640E : SA0, SA1, SA140, and SA141)

If the system asserts V^IHon the WP/ACC pin, the device reverts to whether the two outermost 8 Kbyte on both

ends of boot sectors were last set to be protected or unprotected. Sector protection or unprotection for these

four sectors depends on whether they were last protected or unprotected using the method described in “Sector

protection/unprotection.”

Accelerated Program Operation

Thedeviceoffersacceleratedprogramoperationwhichenablesprogramminginhighspeed. Ifthesystemasserts

V^ACCto the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program

operation will reduce to about 60%. This function is primarily intended to allow high speed programming, so

caution is needed as the sector group will temporarily be unprotected.

The system would use a fast program command sequence when programming during acceleration mode.

Set command to fast mode and reset command from fast mode are not necessary. When the device enters the

acceleration mode, the device is automatically set to fast mode. Therefore, the present sequence could be used

for programming and detection of completion during acceleration mode.

Removing V^ACCfrom the WP/ACC pin returns the device to normal operation. Do not remove V^ACCfrom WP/

ACC pin while programming. See Figure 21.

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MBM29DL640E^80/90/12

■ COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register. Some

commands require Bank Address (BA) input. When command sequences are input into a bank reading, the

commands have priority over the reading. Table 4 shows the valid register command sequences. Note that the

Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is

in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the

Program operation is in progress. Moreover, Read/Reset commands are functionally equivalent, resetting the

device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits

are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to Read/Reset mode, the Read/

Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro-

processor read cycles retrieve array data from the memory. The device remains enabled for reads until the

command register contents are altered.

The device will automatically power-up in the Read/Reset state. In this case a command sequence is not required

in order to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures

that no spurious alteration of the memory content occurs during the power transition. Refer to AC Read Char-

acteristics and Timing Diagram for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore,

manufacture and device codes must be accessible while the device resides in the target system. PROM pro-

grammers typically access the signature codes by raising A⁹to a higher voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming method-

ology. The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write

cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device

codes can be read from the bank, and actual data from the memory cell can be read from another bank. The

higher order address (A²¹, A20, A19) required for reading out the manufacture and device codes demands the

bank address (BA) set at the third write cycle.

Following the command write, in WORD mode, a read cycle from address (BA) 00h returns the manufacturer’s

code (Fujitsu = 04h) . And a read cycle at address (BA) 01h outputs device code. When 227Eh was output, this

indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may

continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. Notice

that the above applies to WORD mode. The addresses and codes differ from those of BYTE mode. (Refer to

Table 5.1 and 5.2. )

The sector state (protection or unprotection) will be informed by address (BA) 02h for × 16 ( (BA) 04h for × 8) .

Scanning the sector group addresses (A²¹, A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1, A0)

= (0, 0, 0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. The programming

verificationshouldbeperformedbyverifyingsectorgroupprotectionontheprotectedsector.(SeeTables2and3.)

The manufacture and device codes can be read from the selected bank. To read the manufacture and device

codes and sector protection status from a non-selected bank, it is necessary to write the Read/Reset command

sequence into the register. Autoselect command should then be written into the bank to be read.

If the software (program code) for Autoselect command is stored in the Flash memory, the device and manu-

facture codes should be read from the other bank, which does not contain the software.

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To

execute the Autoselect command during the operation, Read/Reset command sequence must be written before

the Autoselect command.

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MBM29DL640E^80/90/12

Byte/Word Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.

Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data is latched on the

rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts

programming. UponexecutingtheEmbeddedProgramAlgorithmcommandsequence, thesystemisnotrequired

to provide further controls or timings. The device will automatically provide adequate internally generated pro-

gram pulses and verify the programmed cell margin.

The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit)

or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.

The automatic programming operation is completed when the data on DQ⁷is equivalent to data written to this

bit at which time the device returns to the read mode and addresses are no longer latched (see Table 12,

Hardware Sequence Flags). Therefore, the device requires that a valid address to the device be supplied by the

system in this particular instance. Hence, Data Polling must be performed at the memory location which is being

programmed.

If hardware reset occurs during the programming operation, the data being written is not guaranteed.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only

erase operations can convert from “0”s to “1”s.

Figure 22 illustrates the Embedded Program^TMAlgorithm using typical command strings and bus operations.

Program Suspend/Resume

The Program Suspend command allows the system to interrupt a program operation so that data can be read

from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation

immediately suspends the programming. The Program Suspend command may also be issued during a pro-

gramming operation while an erase is suspended. The bank addresses of sector being programmed should be

set when writing the Program Suspend command.

When the Program Suspend command is written during a programming process, the device halts the program

operation within 1 µs and updates the status bits.

After the program operation has been suspended, the system can read data from any address. The data at

program-suspended address is not valid. Normal read timing and command definitions apply.

After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses

of sectors being suspended should be set when writing the Program Resume command. The system can

determine the status of the program operation using the DQ⁷or DQ6 status bits, just as in the standard program

operation. See “Write Operation Status” for more information.

The system may also write the Autoselect command sequence when the device in the Program Suspend mode.

The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are

not stored in the memory. When the device exits the Autoselect mode, the device reverts to the Program Suspend

mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information.

The system must write the Program Resume command (address bits are “Bank Address”) to exit from the

Program Suspend mode and continue the programming operation. Further writes of the Resume command are

ignored. Another Program Suspend command can be written after the device has resumed programming.

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase

Algorithm command sequence, the device will automatically program and verify the entire memory for an all-

29

MBM29DL640E^80/90/12

zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any

controls or timings during these operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) or

RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command

sequence, and terminates when the data on DQ7 is “1” (see Write Operation Status section), at which time the

device returns to the read mode.

Chip Erase Time; Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

Figure 23 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever

happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE, whichever happens

first. After time-out of “t^TOW” from the rising edge of the last sector erase command, the sector erase operation

begins.

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 4. This sequence

is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently

erased. The time between writes must be less than “tTOW”. Otherwise, that command will not be accepted and

erasure will not start. It is recommended that processor interrupts be disabled during this time to guarantee such

a condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out of “tTOW” from

the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector Erase command

(s) . If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out window, the

timer is reset (monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector

Erase Timer). Resetting the device once execution has begun will corrupt the data in the sector. In that case,

restart the erase on those sectors and allow them to complete (refer to Write Operation Status section for Sector

Erase Timer operation). Loading the sector erase buffer may be done in any sequence and with any number of

sectors (0 to 141) .

Sector erase does not require the user to program the device before erase. The device automatically programs

all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing

a sector, the rest remain unaffected. The system is not required to provide any controls or timings during these

operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) or

RY/BY.

The sector erase begins after the “tTOW” time-out from the rising edge of CE or WE, whichever happens first, for

the last sector erase command pulse and terminates when the data on DQ7 is “1” (see Write Operation Status

section), at which time the device returns to the read mode. Data polling and Toggle Bit must be performed at

an address within any of the sectors being erased.

Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of

Sector Erase

In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which

sectors being erased belong cannot be performed.

Figure 23 illustrates the Embedded Erase^TMAlgorithm using typical command strings and bus operations.

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt Sector Erase operation and then reads data from or

programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation

which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector

Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.

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MBM29DL640E^80/90/12

Writing the Erase Resume command (30h) resumes the erase operation. The bank address of sector being

erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum

of “t^SPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the

RY/BY output pin will be at Hi-Z and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must

use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been

suspended. Further writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode, except that the data must be read from

sectors that have not been erase-suspended. Reading successively from the erase-suspended sector while the

device is in the erase-suspend-read mode will cause DQ2 to toggle (see the section on DQ2).

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-

mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again, it is

the same as programming in the regular Program mode, except that the data must be programmed to sectors

that are not erase-suspended. Reading successively from the erase-suspended sector while the device is in the

erase-suspend-program mode will cause DQ²to toggle. The end of the erase-suspended Program operation is

detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6), which is the same as the

regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from

any address within bank being erase-suspended.

To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase

suspended. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend

command can be written after the chip has resumed erasing.

Extended Command

(1) Fast Mode

The device has a Fast Mode function. It dispenses with the initial two unclock cycles required in the standard

program command sequence by writing the Fast Mode command into the command register. In this mode, the

required bus cycle for programming consists of two bus cycles instead of four in standard program command.

Do not write erase command in this mode. The read operation is also executed after exiting from the fast mode.

To exit from this mode, it is necessary to write Fast Mode Reset command into the command register. The first

cycle must contain the bank address (see Figure 29) .The V^CCactive current is required even if CE = VIH during

Fast Mode.

(2) Fast Programming

During Fast Mode, programming can be executed with two bus cycle operation. The Embedded Program Algo-

rithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) (see Figure 29) .

(3) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and the host system software interro-

gation handshake, which allows specific vendor-specified software algorithms to be used for entire families of

devices. This allows device-independent, JEDEC ID-independent and forward-and backward-compatible soft-

ware support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. The bank address

should be set when writing this command. Then the device information can be read from the bank, and data

from the memory cell can be read from the another bank. The higher order address (A²¹, A20, A19) required for

reading out the CFI Codes requires that the bank address (BA) be set at the write cycle. Following the command

write, a read cycle from specific address retrieves device information. Please note that output data of upper byte

(DQ¹⁵to DQ8) is “0” in word mode (16 bit) read. Refer to CFI code table (Table 12) . To terminate operation, it is

necessary to write the read/reset command sequence into the register.

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MBM29DL640E^80/90/12

Hidden ROM (Hi-ROM) Region

The Hi-ROM feature provides a Flash memory region that the system may access through a new command

sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the

device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modifi-

cation of that region becomes impossible. This ensures the security of the ESN once the product is shipped to

the field.

The Hi-ROM region is 256 bytes in length and is stored at the same address of the “outermost” 8 Kbyte boot

sector in Bank A. The device occupies the address of the byte mode 000000h to 0000FFh (word mode 000000h

to 00007Fh) . After the system has written the Enter Hi-ROM command sequence, the system may read the Hi-

ROM region by using the addresses normally occupied by the boot sector (particular area of SA0) . That is, the

device sends all commands that would normally be sent to the boot sector (particular area of SA0) to the Hi-

ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence,

or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to

sending commands to the boot sector.

WhenreadingtheHi-ROMregion, eitherchangeaddressesorchangeCEpinfrom“H”to“L”. Thesameprocedure

should be taken (changing addresses or CE pinfrom“H”to “L”)afterthesystemissuestheExitHi-ROMcommand

sequence to read actual memory cell data.

Hidden ROM (Hi-ROM) Entry Command

The device has a Hidden ROM area with One Time Protect function. This area is to enter the security code and

to unable the change of the code once set. Programming is allowed in this area until it is protected. However,

once it gets protected, it is impossible to unprotect. Therefore, extreme caution is required.

The hidden ROM area is 256 bytes. This area is normally the “outermost” 8 Kbyte boot block area in Bank A.

Therefore, write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called Hidden

ROM mode when the Hidden ROM area appears.

Sectors other than the boot block area SA0 can be read during Hidden ROM mode. Read/program of the Hidden

ROM area is possible during Hidden ROM mode. Write the Hidden ROM reset command sequence to exit the

Hidden ROM mode. The bank address of the Hidden ROM should be set on the third cycle of this reset command

sequence.

In Hidden ROM mode, the simultaneous operation cannot be executed multi-function mode between the Hidden

ROM area and the Bank A.

Hidden ROM (Hi-ROM) Program Command

To program the data to the Hidden ROM area, write the Hidden ROM program command sequence during Hidden

ROM mode. This command is the same as the usual program command, except that it needs to write the

command during Hidden ROM mode. Therefore the detection of completion method is the same as in the past,

using the DQ⁷data pooling, DQ6 toggle bit and RY/BY pin. You should pay attention to the address to be

programmed. If an address not in the Hidden ROM area is selected, the previous data will be deleted.

Hidden ROM (Hi-ROM) Protect Command

There are two methods to protect the Hidden ROM area. One is to write the sector group protect setup command

(60h) , set the sector address in the Hidden ROM area and (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and write the

sector group protect command (60h) during the Hidden ROM mode. The same command sequence may be

used because it is the same as the extension sector group protect in the past, except that it is in the Hidden

ROM mode and does not apply high voltage to the RESET pin. Please refer to “Function Explanation Extended

Sector Group Protection” for details of extension sector group protect setting.

The other method is to apply high voltage (V^ID) to A9 and OE, set the sector address in the Hidden ROM area

and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the Hidden ROM mode. To verify the

protect circuit, apply high voltage (V^ID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address

in the Hidden ROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear

on DQ0 if it is not protected. Apply write pulse again. The same command sequence could be used for the above

32

MBM29DL640E^80/90/12

method because other than the Hidden ROM mode, it is the same as the sector group protect previously

mentioned. Refer to “Function Explanation Secor Group Protection” for details of the sector group protect setting.

Take note that other sector groups will be affected if an address other than those for the Hidden ROM area is

selected for the sector group address, so please be careful. Pay close attention that once it is protected, protection

CANNOT BE CANCELLED.

Write Operation Status

Detailed in Table 12 are all the status flags which can determine the status of the bank for the current mode

operation. The read operation from the bank which doesn’t operate Embedded Algorithm returns data of memory

cells. These bits offer a method for determining whether an Embedded Algorithm is properly completed. The

information on DQ²is address-sensitive. This means that if an address from an erasing sector is consecutively

read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively

read. This allows users to determine which sectors are in erase and which are not.

The status flag is not output from banks (non-busy banks) which do not execute Embedded Algorithms. For

example, a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy bank

> , [2] < non-busy bank > , [3] < busy bank > , the DQ⁶toggles in the case of [1] and [3]. In case of [2], the data

of memory cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not be

toggled in [1] and [3].

In the erase suspend read mode, DQ²is toggled in [1] and [3]. In case of [2], the data of memory cell is output.

Table 12 Hardware Sequence Flags

Status

DQ⁷

0

DQ⁶

DQ⁵

0

DQ³

0

DQ²

1

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

1

Toggle *¹

Program Suspend Read

(Program Suspended Sector)

Data

Program

Suspended

Mode

Program Suspend Read

(Non-Program Suspended Sec-

tor)

Data

In Progress

Erase Suspend Read

(Erase Suspended Sector)

1

0

Data

0

Data

0

Toggle

Data

1 *²

Erase

Suspended

Mode

Erase Suspend Read

(Non-Erase Suspended Sector)

Data

DQ⁷

Data

Erase Suspend Program

(Non-Erase Suspended Sector)

Toggle

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ⁷

0

Toggle

1

0

1

N/A

Exceeded

Time Limits

Erase Suspend Program

Suspended

Mode

DQ⁷

Toggle

1

0

N/A

(Non-Erase Suspended Sector)

*1: Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle.

*2: Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.

Notes: 1. DQ⁰and DQ1 are reserve pins for future use.

2. DQ4 is limited to Fujitsu internal use.

33

MBM29DL640E^80/90/12

DQ⁷

Data Polling

The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in

progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a

complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to

read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to

read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an

attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in Figure 24.

For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse

sequences.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not pro-

tected sectors. Otherwise the status may become invalid.

If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then

that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for

erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.

Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ⁷) may change

asynchronously while the output enable (OE) is asserted low. This means that device is driving status information

on DQ7 at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples

the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm

operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to

DQ7 will be read on successive read attempts.

TheDataPollingfeatureisactiveonlyduringtheEmbeddedProgrammingAlgorithm, EmbeddedEraseAlgorithm

or sector erase time-out. (See Table 12.)

See Figure 9 for the Data Polling timing specifications and diagrams.

DQ⁶

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the

busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse

sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse

in the six write pulse sequences. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop

toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If

all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into

read mode, having data kept remained.

Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause

DQ6 to toggle.

The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank

is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the

Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6

to toggle.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

See Figure 10 for the Toggle Bit I timing specifications and diagrams.

34

MBM29DL640E^80/90/12

DQ⁵

Exceeded Timing Limits

DQ⁵will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under

these conditions DQ5 will produce “1”. This is a failure condition indicating that the program or erase cycle was

not successfully completed. Data Polling is only operating function of the device under this condition. The CE

circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins

will control the output disable functions as described in Tables 2 and 3.

The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In

this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never

reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.

If this occurs, reset device with the command sequence.

DQ³

Sector Erase Timer

After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain

low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command

sequence.

If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to

determine whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase

cycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the

command has been accepted, the system software should check the status of DQ3 prior to and following each

subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have

been accepted.

See Table 12 : Hardware Sequence Flags.

DQ²

Toggle Bit II

This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause

DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase

suspended sector will indicate a logic “1” at the DQ2 bit.

DQ⁶is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized

as follows :

For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

(DQ2 toggles while DQ6 does not.) See also Table 13 and Figure 12.

Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles

if this bit is read from an erasing sector.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

Reading Toggle Bits DQ⁶/DQ²

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit

after the first read. After the second read, the system would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can

read array data on DQ⁷to DQ0 on the following read cycle.

35

MBM29DL640E^80/90/12

However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system

also should note whether the value of DQ⁵is high (see the section on DQ5) . If it is, the system should then

determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5

went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase

operation. If it is still toggling, the device did not complete the operation successfully, and the system must write

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ⁵has not

gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, deter-

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system

tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the

status of the operation. (Refer to Figure 25.)

Table 13 Toggle Bit Status

Mode

DQ⁷

DQ7

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Toggle (Note)

Erase-Suspend Read

(Erase-Suspended Sector)

1

Toggle

Erase-Suspend Program

DQ⁷

Toggle

1 (Note)

Note : Successive reads from the erasing or erase-suspend sector will cause DQ²to toggle. Reading from the non-

erase suspend sector address will indicate logic “1” at the DQ2 bit.

RY/BY

Ready/Busy

The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded

Algorithms are either in progress or have been completed. If output is low, the device is busy with either a program

or erase operation. If output is high, the device is ready to accept any read/write or erase operation. If the device

is placed in an Erase Suspend mode, RY/BY output will be high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate

a busy condition during RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY pin

is pulled high in standby mode.

Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.

Byte/Word Configuration

BYTE pin selects byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the device

operates in word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, the

device operates in byte (8-bit) mode. In this mode, the DQ15/A-1 pin becomes the lowest address bit, and DQ14

to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands

are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to Figures 15, 16 and 17 for the timing diagram.

Data Protection

The device is designed to offer protection against accidental erasure or programming caused by spurious system

level signals that may exist during power transitions. During power-up, the device automatically resets the internal

state machine in Read mode. Also, with its control register architecture, alteration of memory contents only

occurs after successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting from V^CCpower-up

and power-down transitions or system noise.

36

MBM29DL640E^80/90/12

Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, a write cycle is locked out for VCC less

than VLKO (Min.) . If VCC < VLKO, the command register is disabled and all internal program/erase circuits are

disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until

the VCC level is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when VCC is above VLKO (Min.) .

If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

37

MBM29DL640E^80/90/12

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min.

−55

−40

Max.

+125

+85

Storage Temperature

Tstg

Ta

°C

Ambient Temperature with Power Applied

Voltage with Respect to Ground All pins except A⁹,

OE, and RESET (Note 1)

VIN, VOUT

−0.5

VCC + 0.5

V

Power Supply Voltage (Note 1)

A9, OE, and RESET (Note 2)

WP/ACC (Note 3)

V^CC

VIN

−0.5

+4.0

+13.0

+10.5

V

VACC

Notes : 1. Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may

undershoot V^SSto −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is

VCC +0.5V.Duringvoltagetransitions,inputorI/OpinsmayovershoottoVCC +2.0Vforperiodsofupto20ns.

2. Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and

RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input

and supply voltage (VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET

pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.

3. Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may

undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is

+10.5 V which may overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING RANGES

Ranges

Parameter

Ambient Temperature

Power Supply Voltage

Symbol

Ta

Part No.

Unit

Min.

−20

Max.

+70

MBM29DL640E 80

MBM29DL640E 90/12

MBM29DL640E 80

MBM29DL640E 90/12

°C

V

−40

+85

+3.0

+2.7

+3.6

V^CC

V

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Operating ranges define those limits between which the proper device function is guaranteed.

38

MBM29DL640E^80/90/12

■ MAXIMUM OVERSHOOT/UNDERSHOOT

20 ns

+0.6 V

−0.5 V

−2.0 V

20 ns

Figure 1 Maximum Undershoot Waveform

20 ns

VCC + 2.0 V

VCC + 0.5 V

+2.0 V

20 ns

Figure 2 Maximum Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

VCC + 0.5 V

20 ns

Note : This waveform is applied for A9, OE and RESET.

Figure 3 Maximum Overshoot Waveform 2

39

MBM29DL640E^80/90/12

■ ELECTRICAL CHARACTERISTICS

1. DC Characteristics

Value

Typ.

Symbol

Parameter

Conditions

Unit

Min.

−1.0

Max.

+1.0

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCC, VCC = VCC Max.

VOUT = VSS to VCC, VCC = VCC Max.

µA

ILO

A9, OE, RESET Inputs Leakage

Current

VCC = VCC Max.,

A9, OE, RESET = 12.5 V

ILIT

ILIA

+35

µA

WP/ACC Accelerated Program

Current

VCC = VCC Max.

WP/ACC = VACC Max.

20

mA

Byte

Word

Byte

16

18

7

CE = VIL, OE = VIH,

f = 5 MHz

mA

V^CCActive Current *¹

ICC1

CE = VIL, OE = VIH,

f = 1 MHz

mA

Word

7

V^CCActive Current *²

V^CCCurrent (Standby)

ICC2

ICC3

CE = VIL, OE = VIH

40

VCC = VCC Max., CE = VCC ± 0.3 V,

RESET = VCC ± 0.3 V

1

5

µA

WP/ACC = VCC ± 0.3 V

VCC = VCC Max.,

RESET = VSS ± 0.3 V

V^CCCurrent (Standby, Reset)

ICC4

ICC5

VCC = VCC Max., CE = VSS ± 0.3 V,

RESET = VCC ± 0.3 V

VIN = VCC ± 0.3 V or VSS ± 0.3 V

V^CCCurrent

(Automatic Sleep Mode) *³

V^CCActive Current *⁵

(Read-While-Program)

Byte

CE = VIL, OE = VIH

Word

56

58

56

58

ICC6

mA

V^CCActive Current *⁵

(Read-While-Erase)

Byte

CE = VIL, OE = VIH

Word

ICC7

ICC8

V^CCActive Current

(Erase-Suspend-Program)

CE = VIL, OE = VIH

40

Input Low Level

Input High Level

V^IL

−0.5

0.6

V

VIH

2.0

V^CC+ 0.3

Voltage for Autoselect and Sector

Protection (A⁹, OE, RESET) *⁴

VID

11.5

12

12.5

V

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration *⁴

VACC

8.5

9.0

9.5

V

Output Low Voltage Level

Output High Voltage Level

Low VCC Lock-Out Voltage

V^OL

VOH1

VOH2

VLKO

IOL = 100 µA, VCC = VCC Min.

IOH = −2.0 mA, VCC = VCC Min.

IOH = −100 µA

0.45

V

2.4

V^CC− 0.4

2.3

2.4

2.5

*1: The ICC current listed includes both the DC operating current and the frequency dependent component.

*2: ICC active while Embedded Algorithm (program or erase) is in progress.

*3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

*4: Applicable for only V^CC.

*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)

40

MBM29DL640E^80/90/12

2. AC Characteristics

• Read Only Operations Characteristics

Value (Note)

Symbol

Condition

Parameter

80

Min. Max. Min. Max. Min. Max.

80 90 120

90

12

Unit

JEDEC Standard

Read Cycle Time

tAVAV

tAVQV

tRC

ns

CE = VIL

OE = VIL

Address to Output Delay

tACC

80

90

120

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

tEHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

80

30

25

90

35

30

120

50

ns

30

Output Hold Time From Addresses,

CE or OE, Whichever Occurs First

tAXQX

tOH

0

ns

µs

ns

RESET Pin Low to Read Mode

tREADY

20

5

20

5

20

5

tELFL

tELFH

CE to BYTE Switching Low or High

Note : Test Conditions :

Output Load : 1 TTL gate and 30 pF (MBM29DL640E-80)

1 TTL gate and 100 pF (MBM29DL640E-90/120)

Input rise and fall times : 5 ns

Input pulse levels : 0.0 V to 3.0 V

Timing measurement reference level

Input : 1.5 V

Output : 1.5 V

3.3 V

IN3064

or equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

CL

Diodes = IN3064

or equivalent

Figure 4 Test Conditions

41

MBM29DL640E^80/90/12

• Write/Erase/Program Operations

Value

90

Symbol

Unit

Parameter

80

12

JEDEC Standard Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Write Cycle Time

tAVAV

tAVWL

tWC

tAS

80

0

90

0

120

0

ns

Address Setup Time

Address Setup Time to OE Low

During Toggle Bit Polling

tASO

tAH

12

45

0

15

45

0

15

50

0

ns

Address Hold Time

t^WLAX

Address Hold Time from CE or OE

High During Toggle Bit Polling

tAHT

Data Setup Time

Data Hold Time

t^DVWH

t^WHDX

tDS

tDH

30

0

35

0

50

0

ns

Read

0

Output

Enable

Hold Time

t^OEH

Toggle and Data

Polling

10

ns

CE High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write

CE Setup Time

tCEPH

tOEPH

tGHWL

tGHEL

tCS

20

0

20

0

20

0

ns

t^GHWL

t^GHEL

tELWL

tWLEL

tWHEH

tEHWH

t^WLWH

tELEH

tWHWL

tEHEL

ns

0

ns

0

ns

WE Setup Time

tWS

0

ns

CE Hold Time

tCH

0

ns

WE Hold Time

tWH

0

ns

Write Pulse Width

tWP

35

25

35

30

50

30

ns

CE Pulse Width

tCP

ns

Write Pulse Width High

CE Pulse Width High

tWPH

tCPH

ns

Byte

Programming Operation

Word

8

16

1

8

16

1

8

16

1

µs

t^WHWH1

tWHWH1

µs

Sector Erase Operation *¹

tWHWH2

tVCS

s

VCC Setup Time

50

500

4

50

500

4

50

500

4

µs

Rise Time to VID *²

tVIDR

ns

Rise Time to V^ACC*³

Voltage Transition Time *²

Write Pulse Width *²

tVACCR

tVLHT

tWPP

ns

µs

100

µs

(Continued)

42

MBM29DL640E^80/90/12

(Continued)

Value

90

JEDEC Standard Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Symbol

Unit

Parameter

80

12

OE Setup Time to WE Active *²

CE Setup Time to WE Active *²

Recover Time from RY/BY

RESET Pulse Width

tOESP

tCSP

tRB

4

µs

ns

0

tRP

500

RESET High Level Period Before

Read

tRH

200

ns

40 ns

120 ns

90 ns

120 ns

BYTE Switching Low to Output

High-Z

tFLQZ

tFHQV

tBUSY

t^EOE

30

80

90

80

30

90

BYTE Switching High to Output

Active

Program/Erase Valid to RY/BY

Delay

Delay Time from Embedded

Output Enable

Erase Time-out Time

tTOW

50

µs

Erase Suspend Transition Time

t^SPD

20

20 µs

*1: This does not include preprogramming time.

*2: This timing is for Sector Group Protection operation.

*3: This timing is for Accelerated Program operation.

43

MBM29DL640E^80/90/12

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min.

Typ.

Max.

Excludes programming time

prior to erasure

Sector Erase Time

1

10

s

Word Programming Time

Byte Programming Time

16

8

360

300

µs

Excludes system-level

overhead

Excludes system-level

overhead

Chip Programming Time

Program/Erase Cycle

200

s

100,000

cycle

■ TSOP (I) PIN CAPACITANCE

Value

Unit

Parameter

Symbol

Condition

Typ.

Max.

7.5

12

Input Capacitance

C^IN

COUT

CIN2

CIN3

VIN = 0

6

8.5

8

pF

Output Capacitance

VOUT = 0

VIN = 0

Control Pin Capacitance

WP/ACC Pin Capacitance

11

9

11

Note : Test conditions Ta = 25 °C, f = 1.0 MHz

■ FBGA PIN CAPACITANCE

Value

Parameter

Symbol

Condition

Unit

Typ.

TBD

Max.

TBD

Input Capacitance

C^IN

C^OUT

CIN2

CIN3

VIN = 0

VOUT = 0

VIN = 0

pF

Output Capacitance

Control Pin Capacitance

WP/ACC Pin Capacitance

Note : Test conditions Ta = 25 °C, f = 1.0 MHz

44

MBM29DL640E^80/90/12

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will

Change

from H to L

May

Change

from L to H

Will

Change

from L to H

"H" or "L":

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

"Off" State

tRC

Address

Address Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tOH

tCE

High-Z

Outputs Valid

Outputs

Figure 5.1 Read Operation Timing Diagram

45

MBM29DL640E^80/90/12

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

Figure 5.2 Hardware Reset/Read Operation Timing Diagram

46

MBM29DL640E^80/90/12

3rd Bus Cycle

555h

Data Polling

PA

Address

CE

tWC

tRC

tAS

tAH

tCS

tCH

tCE

OE

tOE

tWP

tWPH

tWHWH1

tGHWL

WE

tOH

tDF

tDH

tDS

A0h

PD

DOUT

DQ7

Data

Notes : 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at word address.

3. DQ7 is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)

Figure 6 Alternate WE Controlled Program Operation Timing Diagram

47

MBM29DL640E^80/90/12

3rd Bus Cycle

Data Polling

PA

555h

tWC

PA

Address

WE

tAS

tAH

tWS

tWH

OE

CE

tCPH

tCP

tWHWH1

tGHEL

tDS

tDH

A0h

PD

DOUT

DQ7

Data

Notes : 1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at word address.

3. DQ7 is the output of the complement of the data written to the device.

4. DOUT is the output of the data written to the device.

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)

Figure 7 Alternate CE Controlled Program Operation Timing Diagram

48

MBM29DL640E^80/90/12

555h

tWC

2AAh

555h

2AAh

SA*

Address

tAS

tAH

CE

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

30h for Sector Erase

10h

AAh

55h

80h

AAh

55h

Data

VCC

tVCS

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.

Note : These waveforms are for the × 16 mode. (The addresses differ from × 8 mode.)

Figure 8 Chip/Sector Erase Operation Timing Diagram

49

MBM29DL640E^80/90/12

CE

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ0 =

Output Flag

DQ6 to DQ0

Valid Data

DQ6 to DQ0

RY/BY

Data

tEOE

tBUSY

* : DQ7 = Valid Data (The device has completed the Embedded operation) .

Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram

50

MBM29DL640E^80/90/12

Address

CE

tAHT tASO

tAHT tAS

tCEPH

WE

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

* : DQ6 stops toggling (The device has completed the Embedded operation).

Figure 10 AC Waveforms for Toggle Bit I during Embedded Algorithm Operations

51

MBM29DL640E^80/90/12

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

CE

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDH

tDS

tDF

Valid

Output

Valid

Output

Valid

Output

Status

Intput

(A0H)

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1 : Address corresponding to Bank 1

BA2 : Address corresponding to Bank 2

Figure 11 Bank-to-Bank Read/Write Timing Diagram

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase Suspend

Read

Erase Suspend

Read

WE

Erase

Suspend

Program

Erase

Complete

DQ6

DQ2

Toggle

DQ2 and DQ6

with OE

Note : DQ2 is read from the erase-suspended sector.

Figure 12 DQ²vs. DQ⁶

52

MBM29DL640E^80/90/12

CE

The rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

Figure 13 RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

WE

RESET

tRP

tRB

RY/BY

tREADY

Figure 14 RESET, RY/BY Timing Diagram

53

MBM29DL640E^80/90/12

CE

tCE

BYTE

Data Output

(DQ7 to DQ0)

Data Output

(DQ14 to DQ0)

DQ14 to DQ0

tELFH

tFHQV

A-1

DQ15

DQ15/A-1

Figure 15 Timing Diagram for Word Mode Configuration

CE

BYTE

tELFL

DQ14 to DQ0

Data Output

(DQ7 to DQ0)

Data Output

(DQ14 to DQ0)

tACC

DQ15/A-1

A-1

DQ15

tFLQZ

Figure 16 Timing Diagram for Byte Mode Configuration

Falling edge of the last write signal

CE or WE

BYTE

Input

Valid

tAS

tAH

Figure 17 BYTE Timing Diagram for Write Operations

54

MBM29DL640E^80/90/12

A21, A20, A19

A18, A17, A16

A15, A14, A13

A12

SPAX

SPAY

A6, A3, A2, A0

A1

VID

VIH

A9

tVLHT

VID

VIH

OE

tVLHT

tWPP

WE

tOESP

tCSP

CE

01h

Data

VCC

tOE

tVCS

SPAX : Sector Group Address to be protected

SPAY : Next Sector Group Address to be protected

Note : A-¹is VIL on byte mode.

Figure 18 Sector Group Protection Timing Diagram

55

MBM29DL640E^80/90/12

VCC

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

Figure 19 Temporary Sector Group Unprotection Timing Diagram

56

MBM29DL640E^80/90/12

VCC

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SPAX

SPAY

A6, A3,

A2, A0

A1

CE

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

SPAX : Sector Group Address to be protected

SPAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min.)

Figure 20 Extended Sector Group Protection Timing Diagram

57

MBM29DL640E^80/90/12

VCC

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CE

WE

tVLHT

Program or Erase Command Sequence

Acceleration period

RY/BY

Figure 21 Accelerated Program Timing Diagram

58

MBM29DL640E^80/90/12

■ FLOW CHART

EMBEDDED ALGORITHM

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded

Program

Algorithm

in program

No

Verify Data

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Note : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Figure 22 Embedded Program^TMAlgorithm

59

MBM29DL640E^80/90/12

EMBEDDED ALGORITHM

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Embedded

Erase

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

Sector Address

/30h

Sector Address

/30h

Additional sector

erase commands

are optional.

Sector Address

/30h

Note : The sequence is applied for × 16 mode.

The addresses differ from × 8 mode.

Figure 23 Embedded Erase^TMAlgorithm

60

MBM29DL640E^80/90/12

VA = Address for programming

= Any of the sector addresses

within the sector being erased

during sector erase or multiple

erases operation.

Start

Read Byte

(DQ7 to DQ0)

Addr. = VA

= Any of the sector addresses

within the sector not being

protected during sector erase or

multiple sector erases

operation.

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Byte

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data?

*

No

Fail

Pass

* : DQ⁷is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 24 Data Polling Algorithm

61

MBM29DL640E^80/90/12

Start

VA = Bank address being executed

Read DQ7 to DQ0

Embedded Algorithm.

Addr. = VA

*1

Read DQ7 to DQ0

Addr. = VA

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

*1, 2

Read DQ7 to DQ0

Twice

Addr. = VA

No

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete.Write

Reset Command

Program/Erase

Operation

Complete

*1 : Read toggle bit twice to determine whether or not it is toggling.

*2 : Recheck toggle bit because it may stop toggling as DQ⁵changes to “1”.

Figure 25 Toggle Bit Algorithm

62

MBM29DL640E^80/90/12

Start

Setup Sector Group Addr.

A21, A20, A19, A18, A17,

A16, A15, A14, A13, A12

(

)

PLSCNT = 1

OE = VID, A9 = VID

CE = VIL, RESET = VIH

A6 = A3 = A2 = A0 = VIL, A1 = VIH

Activate WE Pulse

Increment PLSCNT

Time out 100 µs

WE = VIH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

Addr. = SPA, A1 = VIH

A6 = A3 = A2 = A0 = VIL

*

(

)

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove VID from A9

Write Reset Command

Protect Another Sector

Group?

No

Remove VID from A9

Write Reset Command

Device Failed

Sector Group Protection

Completed

* : A^-1is VIL in byte mode.

Figure 26 Sector Group Protection Algorithm

63

MBM29DL640E^80/90/12

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*2

*1 : All protected sectors are unprotected.

*2 : All previously protected sectors are reprotected.

Figure 27 Temporary Sector Group Unprotection Algorithm

64

MBM29DL640E^80/90/12

Start

RESET = VID

Wait to 4 µs

Device is Operating in

Temporary Sector Group

Unprotection Mode

No

Extended Sector Group

Protection Entry?

Yes

To Setup Sector Group Protection

Write XXXh/60h

PLSCNT = 1

To Protect Sector Group

Write 60h to Sector Address

(A6 = A3 = A2 = A0 = VIL, A1 = VIH)

Time out 250 µs

To Verify Sector Group Protection

Write 40h to Sector Address

Increment PLSCNT

(A6 = A3 = A2 = A0 = VIL, A1 = VIH)

Read from Sector Group Address

(Addr. = SPA, A0 = VIL,

A1 = VIH, A6 = VIL)

No

Setup Next Sector Address

No

Data = 01h?

PLSCNT = 25?

Yes

Protect Other Sector

Group?

Remove VID from RESET

Write Reset Command

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Protection

Completed

Figure 28 Extended Sector Group Protection Algorithm

65

MBM29DL640E^80/90/12

FAST MODE ALGORITHM

Start

555h/AAh

2AAh/55h

Set Fast Mode

555h/20h

XXXh/A0h

In Fast Program

Program Address/Program Data

Data Polling

No

Verify Data?

Yes

No

Last Address?

Yes

Increment Address

Programming Completed

(BA)XXXh/90h

XXXh/F0h

Reset Fast Mode

Notes: • The sequence is applied for × 16 mode.

• The addresses differ from × 8 mode.

Figure 29 Embedded Programming Algorithm for Fast Mode

66

MBM29DL640E^80/90/12

■ ORDERING INFORMATION

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of :

MBM29DL640

E

80

TN

PACKAGE TYPE

TN = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout

TR = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

PBT = 63-Ball Fine pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

DEVICE NUMBER/DESCRIPTION

MBM29DL640

64 Mega-bit (8 M × 8-Bit or 4 M × 16-Bit) CMOS Flash Memory

3.0 V-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to

be supported in volume for this device. Consult

the local Fujitsu sales office to confirm availability

of specific valid combinations and to check on

newly released combinations.

80

90

12

TN

TR

PBT

MBM29DL640E

67

MBM29DL640E^80/90/12

■ PACKAGE DIMENSIONS

48-pin plastic TSOP (I)

(FPT-48P-M19)

* Resin Protrusion. (Each Side : 0.15 (.006) Max)

LEAD No.

1

48

Details of "A" part

0.15(.006)

MAX

INDEX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

20.00±0.20

(.787±.008)

* 12.00±0.20

(.472±.008)

*18.40±0.20

(.724±.008)

11.50REF

(.460)

1.10⁺^0.⁰⁰^.⁵¹⁰

.043⁺^.0^.⁰⁰²⁰⁴

(Mounting height)

0.50(.0197)

TYP

0.05(0.02)MIN

STAND OFF

0.10(.004)

0.15±0.05

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

C

1996 FUJITSU LIMITED F48029S-2C-2

Dimensions in mm (inches)

68

MBM29DL640E^80/90/12

48-pin plastic TSOP (I)

(FPT-48P-M20)

* Resin Protrusion. (Each Side : 0.15 (.006) Max)

LEAD No.

1

48

Details of "A" part

0.15(.006)

MAX

INDEX

0.35(.014)

MAX

"A"

0.15(.006)

0.25(.010)

24

25

19.00±0.20

(.748±.008)

0.50±0.10

(.020±.004)

0.15±0.10

(.006±.002)

0.20±0.10

(.008±.004)

M

0.10(.004)

0.50(.0197)

TYP

0.05(0.02)MIN

STAND OFF

0.10(.004)

1.10⁺^0.⁰⁰^.⁵¹⁰

.043⁺^.0^.⁰⁰²⁰⁴

*18.40±0.20

(.724±.008)

11.50(.460)REF

* 12.00±0.20(.472±.008)

(Mounting height)

20.00±0.20

(.787±.008)

C

1996 FUJITSU LIMITED F48030S-2C-2

Dimensions in mm (inches)

69

MBM29DL640E^80/90/12

63-ball plastic FBGA

(BGA-63P-M02)

11.00±0.10(.433±.004)

1.05 –⁺0⁰.^.1¹0⁵

(8.80(.346))

(7.20(.283))

.041 –⁺.^.0⁰0⁰4⁶

(Mounting height)

0.38±0.10

(.015±.004)

(Stand off)

(5.60(.220))

0.80(.031)TYP

8

7

6

5

4

3

2

1

(4.00(.157))

(5.60(.220))

10.00±0.10

(.394±.004)

M

L

K

J

H

G

F

E

D

C

B

A

INDEX AREA

INDEX BALL

63-Ø0.45±0.05

(63-Ø0.18±.002)

M

0.08(.003)

0.10(.004)

C

1999 FUJITSU LIMITED B63002S-1C-1

Dimensions in mm (inches)

70

MBM29DL640E^80/90/12

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0101

FUJITSU LIMITED Printed in Japan


型号：	MBM29DL640E90TR
厂家：	FUJITSU
描述：	64 M (8 M X 8/4 M X 16) BIT Dual Operation 64米（8米乘8/4米乘16 ）位双操作闪存存储内存集成电路光电二极管
文件：	总71页 (文件大小：850K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29DL640E90TR [FUJITSU]

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