MBM29DL64DF70TN_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20905-1E

FLASH MEMORY

CMOS

64 M (8 M × 8/4 M × 16) BIT

Dual Operation

MBM29DL64DF^-70

■ DESCRIPTION

MBM29DL64DF is a 64 M-bit, 3.0 V-only Flash memory organized as 8 Mbytes of 8 bits each or 4 M words of 16

bits each. The device comes in 48-pin TSOP (1) and 48-ball FBGA packages. This device is designed to be

programmedinsystemwith3.0VV^CCsupply. 12.0VVPP and5.0VVCC arenotrequiredforwriteoreraseoperations.

The device can also be reprogrammed in standard EPROM programmers.

The device is organized into four physical banks : Bank A, Bank B, Bank C and Bank D, which are considered to

be four separate memory arrays operations. This device is the almost identical to Fujitsu’s standard 3 V only Flash

memories, with the additional capability of allowing a normal non-delayed read access from a non-busy bank of

the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the

other bank.

(Continued)

■ PRODUCT LINE UP

Part No.

Power Supply Voltage V^CC(V)

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

MBM29DL64DF-70

+0.6 V

−0.3 V

3.0 V

70

30

■ PACKAGES

48-pin plastic TSOP (1)

48-ball plastic FBGA

Marking Side

(FPT-48P-M19)

(BGA-48P-M13)

MBM29DL64DF-70

(Continued)

The new design concept called FlexBank^TM*¹Architecture is implemented. With this concept the device can

execute simultaneous operation between Bank 1, a bank chosen from among the four banks, and Bank 2, a

bank consisting of the three remaining banks. This means that any bank can be chosen as Bank 1. (Refer to

■FUNCTIONAL DESCRIPTION for Simultaneous Operation.)

The standard device offers access times 70 ns, allowing operation of high-speed microprocessors without the

wait. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) and output enable

(OE) controls.

This device supports pin and command set compatible with JEDEC standard E²PROMs. Commands are written

to the command register using standard microprocessor write timings. Register contents serve as input to an

internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out of the device is similar

to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This invokes the Embedded Program

Algorithm^TMwhich is an internal algorithm that automatically times the program pulse widths and verifies proper

cell margin. Typically each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished

by executing the erase command sequence. This invokes the Embedded Erase Algorithm^TMwhich is an internal

algorithm that automatically preprograms the array if it is not already programmed before executing the erase

operation. During erase, the device automatically times the erase pulse widths and verifies the proper cell margin.

Each sector is typically erased and verified in 0.5 second (if already completely preprogrammed) .

The device also features sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device features single 3.0 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V^CCdetector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed,

the device internally returns to the read mode.

The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program

Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read

mode. The RESET pin may be tied to the system reset circuitry. Therefore if a system reset occurs during the

Embedded Program^TM*²Algorithm or Embedded Erase^TM*²Algorithm, the device is automatically reset to the

read mode and have erroneous data stored in the address locations being programmed or erased. These

locations need rewriting after the reset. Resetting the device enables the system’s microprocessor to read the

boot-up firmware from the Flash memory.

Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all

bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/

word at a time using the EPROM programming mechanism of hot electron injection.

*1 : FlexBank^TMis a trademark of Fujitsu Limited.

*2 : Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

2

MBM29DL64DF-70

■ FEATURES

• 0.17 µm Process Technology

• Two-bank Architecture for Simultaneous Read/Program and Read/Erase

1

• FlexBank^TM

*

Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)

Bank B : 24 Mbit (64 KB × 48)

Bank C : 24 Mbit (64 KB × 48)

Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)

Two virtual Banks are chosen from the combination of four physical banks (Refer to “■FUNCTIONAL

DESCRIPTION FlexBank^TMArchitecture”and “Example of Virtual Banks Combination”.)

Host system can program or erase in one bank, and then read immediately and simultaneously from the other

bank with zero latency between read and write operations.

Read-while-erase

Read-while-program

• Single 3.0 V Read, Program, and Erase

Minimized system level power requirements

• Compatible with JEDEC-standard Commands

Uses the same software commands as E²PROMs

• Compatible with JEDEC-standard Worldwide Pinouts

48-pin TSOP (1) (Package suffix : TN − Normal Bend Type)

48-ball FBGA (Package suffix : PBT)

• Minimum 100,000 Program/Erase Cycles

• High Performance

70 ns maximum access time

• Sector Erase Architecture

Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode

Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• HiddenROM Region

256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

At V^ILallows protection of “outermost” 2 × 8 Kbytes on both ends of boot sectors, regardless of sector group

protection/unprotection status

At V^ACC, increases program performance

• Embedded Erase^TM*²Algorithms

Automatically preprograms and erases the chip or any sector

• Embedded Program^TM*²Algorithms

Automatically programs and verifies data at specified address

*1 : FlexBank^TMis a trademark of Fujitsu Limited

*2 : Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

(Continued)

3

MBM29DL64DF-70

(Continued)

• Data Polling and Toggle Bit feature for program detection or erase cycle completion

• Ready/Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, the device automatically switches itself to low power mode.

• Low V^CCWrite Inhibit ≤ 2.5 V

• Program Suspend/Resume

Suspends the program operation to allow a read in another byte

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector Group Protection

Hardware method disables any combination of sector groups from program or erase operations

• Sector Group Protection Set function by Extended sector group protection command

• Fast Programming Function by Extended Command

• Temporary Sector Group Unprotection

Temporary sector group unprotection via the RESET pin.

• In accordance with CFI (Common Flash Memory Interface)

4

MBM29DL64DF-70

■ PIN ASSIGNMENTS

TSOP (1)

A15

A14

A13

A12

A11

A10

A9

A8

A19

A16

BYTE

VSS

DQ15/A-1

1

2

3

4

5

6

7

8

48

47

46

45

(Marking Side)

DQ7

44

DQ14

43

DQ6

42

DQ13

41

DQ5

40

9

A20

DQ12

39

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE

RESET

A²¹

WP/ACC

RY/BY

A¹⁸

DQ4

VCC

DQ11

38

37

36

Normal Bend

DQ3

35

DQ10

34

DQ2

33

A17

A7

A6

A5

A4

A3

A2

A1

DQ9

32

DQ1

31

DQ8

30

DQ0

29

OE

VSS

28

27

CE

26

A⁰

25

(FPT-48P-M19)

(Continued)

5

MBM29DL64DF-70

(Continued)

FBGA

(TOP VIEW)

(Marking side)

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16 BYTE DQ15/ VSS

A-1

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7 DQ14 DQ13 DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE RESET A21

A19

DQ5 DQ12

VCC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY WP/

A18

A20

DQ2 DQ10 DQ11 DQ3

ACC

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

OE

H1

CE

VSS

(BGA-48P-M13)

■ PIN DESCRIPTIONS

A²¹to A0, A-1

DQ¹⁵to DQ0

CE

Function

Address Input

Data Input/Output

Chip Enable

OE

Output Enable

Write Enable

WE

RESET

RY/BY

BYTE

WP/ACC

V^CC

Hardware Reset Pin/Temporary Sector Group Unprotection

Ready/Busy Output

Selects 8-bit or 16-bit mode

Hardware Write Protection/Program Acceleration

Device Power Supply

V^SS

Device Ground

N.C.

No Internal Connection

6

MBM29DL64DF-70

■ BLOCK DIAGRAM

VCC

VSS

Bank A

address

Cell Matrix

8 Mbit

Cell Matrix

24 Mbit

A21 to A0

(A-1)

(Bank A)

(Bank B)

X-Decoder

Bank B Address

State

Control

&

Command

Register

RESET

WE

CE

OE

BYTE

WP/ACC

DQ15 to DQ0

RY/BY

DQ15

to

DQ0

Status

Control

Bank C Address

X-Decoder

Cell Matrix

8 Mbit

Cell Matrix

24 Mbit

(Bank D)

(Bank C)

Bank D

address

■ LOGIC SYMBOL

A-1

22

A21 to A0

16 or 8

DQ15 to DQ0

RY/BY

CE

OE

WE

RESET

BYTE

7

MBM29DL64DF-70

■ DEVICE BUS OPERATION

MBM29DL64DF User Bus Operations Table (BYTE = V^IH)

WP/

ACC

Operation

CE OE WE A⁰

A¹

A²

A³

A⁶

A⁹DQ¹⁵to DQ⁰RESET

Standby

H

L

X

L

X

H

L

X

L

X

L

X

L

X

L

X

L

X

High-Z

Code

DOUT

H

X

Autoselect Manufacturer Code *¹

Autoselect Device Code *¹

VID

V^ID

A9

X

L

H

L

H

A1

X

H

A2

X

H

A3

X

L

Extended Autoselect Device

Code *¹

L

H

A0

X

L

Read *³

L

A6

X

A6

Output Disable

Write (Program/Erase)

H

High-Z

DIN

A⁰

A1

A2

A3

A9

Enable Sector Group

Protection *^2,*⁴

L

VID

L

H

L

VID

X

H

X

Verify Sector Group

Protection *^2,*⁴

L

H

Code

Temporary Sector Group

Unprotection *⁵

X

High-Z

X

VID

L

X

L

Reset (Hardware) /Standby

Boot Block Sector Write

Protection *⁶

X

Legend : L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.

*1 : Manufacturer and device codes are accessed via a command register write sequence. See “ Command

Definitions Table”.

*2 : Refer to “Sector Group Protection” in ■FUNCTIONAL DESCRIPTION.

*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4 : VCC = 2.7 V to 3.6 V

*5 : Also used for the extended sector group protection.

*6 : Protects “outermost” 2 × 4 Kwords on both ends of the boot block sectors (SA0, SA1, SA140, SA141) .

8

MBM29DL64DF-70

MBM29DL64DF User Bus Operations Table (BYTE = V^IL)

DQ¹⁵/

A^-1

WP/

ACC

Operation

Standby

CE OE WE

A⁰

A¹

A²

A³

A⁶

A⁹DQ⁷to DQ⁰RESET

H

L

X

L

X

H

X

L

X

L

X

L

X

L

X

L

X

L

X

High-Z

Code

H

X

Autoselect Manufacturer

Code *¹

VID

Autoselect Device Code *¹

L

H

L

H

L

H

L

H

L

H

L

VID

V^ID

A9

X

Code

DOUT

H

X

Extended Autoselect

Device Code *¹

L

H

L

Read *³

L

A-1

X

A0

X

A1

X

A2

X

A3

X

A6

X

Output Disable

Write (Program/Erase)

H

High-Z

DIN

A^-1

A0

A1

A2

A3

A6

A9

Enable Sector Group

Protection *^2,*⁴

L

VID

L

H

X

L

VID

X

Code

X

H

X

L

Verify Sector Group

Protection *^2,*⁴

H

X

Temporary Sector Group

Unprotection *⁵

X

VID

L

Reset (Hardware) /

Standby

X

High-Z

X

Boot Block Sector Write

Protection *⁶

X

Legend : L = V^IL, H = VIH, X = VIL or VIH,

= Pulse input. See “■DC CHARACTERISTICS” for voltage levels.

*1 : Manufacturer and device codes are accessed via command register write sequence. See “Command

Definitions Table”.

*2 : Refer to “Sector Group Protection” in ■FUNCTIONAL DESCRIPTION.

*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*4 : V^CC= 2.7 V to 3.6 V

*5 : Also used for extended sector group protection.

*6 : Protect “outermost” 2 × 8K bytes on both ends of the boot block sectors (SA0, SA1, SA140, SA141) .

9

MBM29DL64DF-70

MBM29DL64DF Command Definitions Table *¹

Fourth Bus

Read/Write

Cycle

First Bus Second Bus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Bus

Write

Cycles

Req’d

Command

Sequence

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

Byte

Word

Byte

Read/

1

3

XXXh F0h

Reset *²

12

555h

2AAh

555h

Read/

Reset*²

*

AAh

55h

F0h RA*¹²

RD

AAAh

(BA)

555h

Word

Byte

555h

2AAh

555h

Autoselect

3

4

90h IA*¹²ID*¹²

(BA)

AAAh

Word

Byte

555h

2AAh

555h

Program

A0h

PA

PD

AAAh

Program

Suspend

1

6

BA

B0h

30h

AAh

Program Resume

BA

555h

AAAh

555h

AAAh

BA

Word

Chip Erase

Byte

2AAh

555h

2AAh

555h

AAAh

555h

AAAh

555h

AAAh

555h

AAAh

2AAh

555h

2AAh

555h

55h

80h

AAh

55h

10h

30h

AAAh

Word

Sector

Erase

Erase Suspend*³

Erase Resume*³

6

AAh

SA

Byte

1

B0h

30h

BA

Word

555h

AAAh

2AAh

555h

Set to

Fast Mode

3

2

AAh

55h

PD

20h

Byte

Word

Byte

Word

AAAh

Fast

Program *⁴

XXXh A0h

PA

Reset from

Fast Mode

11

*

2

3

BA

90h XXXh

00h

Byte

Word

5

*

Extended

Sector

Group

Protection

*^6,*⁷

12

*

XXXh 60h SPA 60h SPA 40h

SPA SD

Byte

Word

(BA)

55h

98h

(BA)

Query *⁸

1

3

Byte

Word

Byte

AAh

Hidden-

ROM

Entry*⁹

555h

2AAh

555h

AAh

55h

88h

AAAh

(Continued)

10

MBM29DL64DF-70

(Continued)

Fourth Bus

Read/Write

Cycle

First Bus SecondBus Third Bus

Write Cycle Write Cycle Write Cycle

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Bus

Write

Cycles

Req’d

Command

Sequence

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Word

555h

2AAh

555h

HiddenROM

(HRA)

PA

4

AAh

55h

A0h

PD

Program *^9,*¹⁰

Byte

Word

AAAh

(HRBA)

555h

2AAh

555h

HiddenROM

Exit *¹⁰

AAh

55h

90h XXXh 00h

(HRBA)

Byte

AAAh

*1 : Command combinations not described in “MBM29DL64DF Command Definitions” are illegal.

*2 : Both of these reset commands are equivalent.

*3 : Erase Suspend and Erase Resume command are valid only during a sector erase operations.

*4 : This command is valid during Fast Mode.

*5 : The Reset from Fast mode command is required to return to the Read mode when the device is in Fast mode.

*6 : This command is valid while RESET = VID (except during HiddenROM mode) .

*7 : Sector Group Address (SGA) with (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0) .

*8 : The valid address are A⁶to A0.

*9 : The HiddenROM Entry command is required prior to the HiddenROM programming.

*10 : This command is valid during HiddenROM mode.

*11 : The data “F0h” is also acceptable.

*12 : Fourth bus cycle becomes read cycle.

Notes : • Address bits A²¹to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector

Address (SA) , Bank Address (BA) and Sector Group Address (SPA) .

• Bus operations are defined in “MBM29DL64DF User Bus Operations (BYTE = VIH) ” and “MBM29DL64DF

User Bus Operations (BYTE = VIL) ”.

• RA

= Address of the memory location to be read

IA

= Autoselect read address that sets both the bank address specified at (A21, A20, A19) and all the

other A6, A3, A2, A1, A0 and (A-1) .

PA

= Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

= Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13 and

A12 will uniquely select any sector.

SA

BA

• RD

ID

= Bank Address. Address setted by A21, A20, A19 will select Bank A, Bank B, Bank C and Bank D.

= Data read from location RA during read operation.

= Device code/manufacture code for the address located by IA.

= Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

PD

• SPA = Sector group address to be protected. Set sector group address and (A⁶, A3, A2, A1, A0) =

(0, 0, 0, 1, 0) .

• SGA = Sector Group Address. The combination of A21 to A12 will uniquely select any sector group.

SD

= Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

• HRA = Address of the HiddenROM area

Word Mode : 000000h to 00007Fh

Byte Mode : 000000h to 0000FFh

• HRBA = Bank Address of the HiddenROM area (A²¹= A20 = A19 = VIL)

• The system should generate the following address patterns :

Word Mode : 555h or 2AAh to addresses A10 to A0

Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

11

MBM29DL64DF-70

MBM29DL64DF Sector Group Protection Verify Autoselect Codes Table

A^-1*¹

VIL

X

Type

Manufacture’s

Code

A²¹to A¹²

A⁶

A³

A²

A¹

A⁰

Code (HEX)

04h

Byte

Word

Byte

BA*³

VIL

0004h

7Eh

VIL

X

Device Code

BA*³

VIL

V^IL

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

Word

Byte

227Eh

02h

VIL

X

Word

Byte

2202h

01h

Extended Device

Code*⁴

VIL

X

Word

Byte

2201h

01h*²

0001h*²

VIL

X

Sector Group

Protection

Sector Group

Addresses

Word

*1 : A^-1is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address.

*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*3 : When V^IDis applied to A9, both Bank 1 and Bank 2 are put into Autoselect mode, which makes simultaneous

operation unable to be executed. Consequently, specifying the bank address is not required. However, the bank

address needs to be indicated when Autoselect mode is read out at command mode, because then it enables

to activate simultaneous operation.

*4 : At Word mode, a read cycle at address (BA) 01h (at Byte mode, (BA) 02h) outputs device code. When 227Eh

(at Byte mode, 7Eh) is output, it indicates that two additional codes, called Extended Device Codes, will be

required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA)

0Eh (at Byte mode, (BA) 1Ch) , as well as at (BA) 0Fh (at Byte mode, (BA) 1Eh) .

Extended Autoselect Code Table

DQ¹⁵DQ¹⁴DQ¹³DQ¹²DQ¹¹DQ¹⁰DQ⁹DQ⁸DQ⁷DQ⁶DQ⁵DQ⁴DQ³DQ²DQ¹DQ⁰

Type

Code

A^-1

0

(B)*

04h

HZ HZ HZ HZ HZ HZ HZ

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Manufactur-

er’s Code

(W) 0004h

(B)*

(W) 227Eh

(B)* 02h A-1 HZ HZ HZ HZ HZ HZ HZ

(W) 2202h

(B)* 01h A-1 HZ HZ HZ HZ HZ HZ HZ

(W) 2201h

0

7Eh A-1 HZ HZ HZ HZ HZ HZ HZ

Device

Code

0

1

0

1

0

Extended

Device

Code

0

1

0

1

0

1

0

1

0

A^-1

Sector

(B)*

01h

HZ HZ HZ HZ HZ HZ HZ

Group

Protection

0

(W) 0001h

0

1

(B) : Byte mode

(W) : Word mode

HZ : High-Z

* : At Byte mode, DQ¹⁴to DQ8 are High-Z and DQ15 is A-1, the lowest address.

12

MBM29DL64DF-70

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE

Sector Address Table (Bank A)

Sector Address

Sector

Size

Bank

Address

( × 8)

Address Range

( × 16)

Address Range

Bank Sector

(Kbytes/

Kwords)

A A A A A A A A A A

21 20 19 18 17 16 15 14 13 12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8/4

000000h to 001FFFh 000000h to 000FFFh

002000h to 003FFFh 001000h to 001FFFh

004000h to 005FFFh 002000h to 002FFFh

006000h to 007FFFh 003000h to 003FFFh

008000h to 009FFFh 004000h to 004FFFh

00A000h to 00BFFFh 005000h to 005FFFh

00C000h to 00DFFFh 006000h to 006FFFh

00E000h to 00FFFFh 007000h to 007FFFh

010000h to 01FFFFh 008000h to 00FFFFh

020000h to 02FFFFh 010000h to 017FFFh

030000h to 03FFFFh 018000h to 01FFFFh

040000h to 04FFFFh 020000h to 027FFFh

050000h to 05FFFFh 028000h to 02FFFFh

060000h to 06FFFFh 030000h to 037FFFh

070000h to 07FFFFh 038000h to 03FFFFh

080000h to 08FFFFh 040000h to 047FFFh

090000h to 09FFFFh 048000h to 04FFFFh

0A0000h to 0AFFFFh 050000h to 057FFFh

0B0000h to 0BFFFFh 058000h to 05FFFFh

0C0000h to 0CFFFFh 060000h to 067FFFh

0D0000h to 0DFFFFh 068000h to 06FFFFh

0E0000h to 0EFFFFh 070000h to 077FFFh

0F0000h to 0FFFFFh 078000h to 07FFFFh

8/4

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

64/32

Bank

SA11

A

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Note : The address range is A²¹: A-1 if in byte mode (BYTE = VIL) .

The address range is A21 : A0 if in word mode (BYTE = VIH) .

13

MBM29DL64DF-70

Sector Address Table (Bank B)

Sector Address

Sector

Size

Bank

Address

( × 8)

Address Range

( × 16)

Address Range

Bank Sector

(Kbytes/

Kwords)

A A A A A A A A A A

21 20 19 18 17 16 15 14 13 12

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

64/32

100000h to 10FFFFh 080000h to 087FFFh

110000h to 11FFFFh 088000h to 08FFFFh

120000h to 12FFFFh 090000h to 097FFFh

130000h to 13FFFFh 098000h to 09FFFFh

140000h to 14FFFFh 0A0000h to 0A7FFFh

150000h to 15FFFFh 0A8000h to 0AFFFFh

160000h to 16FFFFh 0B0000h to 0B7FFFh

170000h to 17FFFFh 0B8000h to 0BFFFFh

180000h to 18FFFFh 0C0000h to 0C7FFFh

190000h to 19FFFFh 0C8000h to 0CFFFFh

1A0000h to 1AFFFFh 0D0000h to 0D7FFFh

1B0000h to 1BFFFFh 0D8000h to 0DFFFFh

1C0000h to 1CFFFFh 0E0000h to 0E7FFFh

1D0000h to 1DFFFFh 0E8000h to 0EFFFFh

1E0000h to 1EFFFFh 0F0000h to 0F7FFFh

1F0000h to 1FFFFFh 0F8000h to 0FFFFFh

200000h to 20FFFFh 100000h to 107FFFh

210000h to 21FFFFh 108000h to 10FFFFh

220000h to 22FFFFh 110000h to 117FFFh

230000h to 23FFFFh 118000h to 11FFFFh

240000h to 24FFFFh 120000h to 127FFFh

250000h to 25FFFFh 128000h to 12FFFFh

260000h to 26FFFFh 130000h to 137FFFh

270000h to 27FFFFh 138000h to 13FFFFh

280000h to 28FFFFh 140000h to 147FFFh

290000h to 29FFFFh 148000h to 14FFFFh

2A0000h to 2AFFFFh 150000h to 157FFFh

2B0000h to 2BFFFFh 158000h to 15FFFFh

2C0000h to 2CFFFFh 160000h to 167FFFh

2D0000h to 2DFFFFh 168000h to 16FFFFh

2E0000h to 2EFFFFh 170000h to 177FFFh

Bank

SA38

B

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

(Continued)

14

MBM29DL64DF-70

(Continued)

Sector Address

Sector

Size

Bank

Address

( × 8)

Address Range

( × 16)

Address Range

Bank Sector

(Kbytes/

Kwords)

A A A A A A A A A A

21 20 19 18 17 16 15 14 13 12

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

64/32

2F0000h to 2FFFFFh 178000h to 17FFFFh

300000h to 30FFFFh 180000h to 187FFFh

310000h to 31FFFFh 188000h to 18FFFFh

320000h to 32FFFFh 190000h to 197FFFh

330000h to 33FFFFh 198000h to 19FFFFh

340000h to 34FFFFh 1A0000h to 1A7FFFh

350000h to 35FFFFh 1A8000h to 1AFFFFh

360000h to 36FFFFh 1B0000h to 1B7FFFh

370000h to 37FFFFh 1B8000h to 1BFFFFh

380000h to 38FFFFh 1C0000h to 1C7FFFh

390000h to 39FFFFh 1C8000h to 1CFFFFh

3A0000h to 3AFFFFh 1D0000h to 1D7FFFh

3B0000h to 3BFFFFh 1D8000h to 1DFFFFh

3C0000h to 3CFFFFh 1E0000h to 1E7FFFh

3D0000h to 3DFFFFh 1E8000h to 1EFFFFh

3E0000h to 3EFFFFh 1F0000h to 1F7FFFh

3F0000h to 3FFFFFh 1F8000h to 1FFFFFh

Bank

SA62

B

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .

The address range is A21 : A0 if in word mode (BYTE = VIH) .

15

MBM29DL64DF-70

Sector Address Table (Bank C)

Sector Address

Sector

Size

Bank

Address

( × 8)

Address Range

( × 16)

Address Range

Bank Sector

(Kbytes/

Kwords)

A A A A A A A A A A

21 20 19 18 17 16 15 14 13 12

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

64/32

400000h to 40FFFFh 200000h to 207FFFh

410000h to 41FFFFh 208000h to 20FFFFh

420000h to 42FFFFh 210000h to 217FFFh

430000h to 43FFFFh 218000h to 21FFFFh

440000h to 44FFFFh 220000h to 227FFFh

450000h to 45FFFFh 228000h to 22FFFFh

460000h to 46FFFFh 230000h to 237FFFh

470000h to 47FFFFh 238000h to 23FFFFh

480000h to 48FFFFh 240000h to 247FFFh

490000h to 49FFFFh 248000h to 24FFFFh

4A0000h to 4AFFFFh 250000h to 257FFFh

4B0000h to 4BFFFFh 258000h to 25FFFFh

4C0000h to 4CFFFFh 260000h to 267FFFh

4D0000h to 4DFFFFh 268000h to 26FFFFh

4E0000h to 4EFFFFh 270000h to 277FFFh

4F0000h to 4FFFFFh 278000h to 27FFFFh

500000h to 50FFFFh 280000h to 287FFFh

510000h to 51FFFFh 288000h to 28FFFFh

520000h to 52FFFFh 290000h to 297FFFh

530000h to 53FFFFh 298000h to 29FFFFh

540000h to 54FFFFh 2A0000h to 2A7FFFh

550000h to 55FFFFh 2A8000h to 2AFFFFh

560000h to 56FFFFh 2B0000h to 2B7FFFh

570000h to 57FFFFh 2B8000h to 2BFFFFh

580000h to 58FFFFh 2C0000h to 2C7FFFh

590000h to 59FFFFh 2C8000h to 2CFFFFh

5A0000h to 5AFFFFh 2D0000h to 2D7FFFh

5B0000h to 5BFFFFh 2D8000h to 2DFFFFh

5C0000h to 5CFFFFh 2E0000h to 2E7FFFh

5D0000h to 5DFFFFh 2E8000h to 2EFFFFh

5E0000h to 5EFFFFh 2F0000h to 2F7FFFh

5F0000h to 5FFFFFh 2F8000h to 2FFFFFh

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

Bank

C

(Continued)

16

MBM29DL64DF-70

(Continued)

Sector Address

Sector

Size

Bank

Address

( × 8)

Address Range

( × 16)

Address Range

Bank Sector

(Kbytes/

Kwords)

A A A A A A A A A A

21 20 19 18 17 16 15 14 13 12

SA103

SA104

SA105

SA106

SA107

SA108

SA109

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

64/32

600000h to 60FFFFh 300000h to 307FFFh

610000h to 61FFFFh 308000h to 30FFFFh

620000h to 62FFFFh 310000h to 317FFFh

630000h to 63FFFFh 318000h to 31FFFFh

640000h to 64FFFFh 320000h to 327FFFh

650000h to 65FFFFh 328000h to 32FFFFh

660000h to 66FFFFh 330000h to 337FFFh

670000h to 67FFFFh 338000h to 33FFFFh

680000h to 68FFFFh 340000h to 347FFFh

690000h to 69FFFFh 348000h to 34FFFFh

6A0000h to 6AFFFFh 350000h to 357FFFh

6B0000h to 6BFFFFh 358000h to 35FFFFh

6C0000h to 6CFFFFh 360000h to 367FFFh

6D0000h to 6DFFFFh 368000h to 36FFFFh

6E0000h to 6EFFFFh 370000h to 377FFFh

6F0000h to 6FFFFFh 378000h to 37FFFFh

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

Bank

C

Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .

The address range is A21 : A0 if in word mode (BYTE = VIH) .

17

MBM29DL64DF-70

Sector Address Table (Bank D)

Sector Address

Sector

Size

Bank

Address

( × 8)

Address Range

( × 16)

Address Range

Bank Sector

(Kbytes/

Kwords)

A A A A A A A A A A

21 20 19 18 17 16 15 14 13 12

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

1 X X X

0 X X X

64/32

8/4

700000h to 70FFFFh 380000h to 387FFFh

710000h to 71FFFFh 388000h to 38FFFFh

720000h to 72FFFFh 390000h to 397FFFh

730000h to 73FFFFh 398000h to 39FFFFh

740000h to 74FFFFh 3A0000h to 3A7FFFh

750000h to 75FFFFh 3A8000h to 3AFFFFh

760000h to 76FFFFh 3B0000h to 3B7FFFh

770000h to 77FFFFh 3B8000h to 3BFFFFh

780000h to 78FFFFh 3C0000h to 3C7FFFh

790000h to 79FFFFh 3C8000h to 3CFFFFh

7A0000h to 7AFFFFh 3D0000h to 3D7FFFh

7B0000h to 7BFFFFh 3D8000h to 3DFFFFh

7C0000h to 7CFFFFh 3E0000h to 3E7FFFh

7D0000h to 7DFFFFh 3E8000h to 3EFFFFh

7E0000h to 7EFFFFh 3F0000h to 3F7FFFh

7F0000h to 7F1FFFh 3F8000h to 3F8FFFh

7F2000h to 7F3FFFh 3F9000h to 3F9FFFh

7F4000h to 7F5FFFh 3FA000h to 3FAFFFh

7F6000h to 7F7FFFh 3FB000h to 3FBFFFh

7F8000h to 7F9FFFh 3FC000h to 3FCFFFh

7FA000h to 7FBFFFh 3FD000h to 3FDFFFh

7FC000h to 7FDFFFh 3FE000h to 3FEFFFh

7FE000h to 7FFFFFh 3FF000h to 3FFFFFh

Bank

SA130

D

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8/4

Note : The address range is A21 : A-1 if in byte mode (BYTE = VIL) .

The address range is A21 : A0 if in word mode (BYTE = VIH) .

18

MBM29DL64DF-70

Sector Group Address Table

Sector Group

SGA0

A²¹

0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

1

SGA8

0

1

0

X

SA8 to SA10

1

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SA67 to SA70

(Continued)

19

MBM29DL64DF-70

(Continued)

Sector Group

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

SGA38

A²¹

1

A²⁰

0

1

A¹⁹

0

1

0

1

A¹⁸

0

1

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A¹⁶

X

0

A¹⁵

X

0

A¹⁴

X

A¹³

X

A¹²

X

Sectors

SA71 to SA74

SA75 to SA78

SA79 to SA82

SA83 to SA86

SA87 to SA90

SA91 to SA94

SA95 to SA98

SA99 to SA102

SA103 to SA106

SA107 to SA110

SA111 to SA114

SA115 to SA118

SA119 to SA122

SA123 to SA126

SA127 to SA130

SGA39

1

0

1

X

SA131 to SA133

1

0

SGA40

SGA41

SGA42

SGA43

SGA44

SGA45

SGA46

SGA47

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1

20

MBM29DL64DF-70

Common Flash Memory Interface Code Table

Description A⁶to A⁰

DQ¹⁵to DQ⁰

10h

11h

12h

0051h

0052h

0059h

Query-unique ASCII string “QRY”

Primary OEM Command Set

02h : AMD/FJ standard type

13h

14h

0002h

0000h

15h

16h

0040h

0000h

Address for Primary Extended Table

Alternate OEM Command Set

(00h = not applicable)

17h

18h

0000h

19h

1Ah

0000h

Address for Alternate OEM Extended Table

V^CCMin (write/erase)

DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV

1Bh

1Ch

0027h

0036h

V^CCMax (write/erase)

DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV

VPP Min voltage

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

0017h

V^PPMax voltage

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min size buffer write 2^Nµs

Typical timeout per individual sector erase 2^Nms

Typical timeout for full chip erase 2^Nms

Max timeout for byte/word write 2^Ntimes typical

Max timeout for buffer write 2^Ntimes typical

Max timeout per individual sector erase 2^Ntimes typical

Max timeout for full chip erase 2^Ntimes typical

Device Size = 2^Nbyte

28h

29h

0002h

0000h

Flash Device Interface description 02h : ×8 / ×16

2Ah

2Bh

0000h

Max number of bytes in multi-byte write = 2^N

Number of Erase Block Regions within device

2Ch

0003h

Erase Block Region 1 Information

bit 15 to bit 0 : y = number of sectors

bit 31 to bit 16 : z = size

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

(z × 256 bytes)

Erase Block Region 2 Information

bit 15 to bit 0 : y = number of sectors

bit 31 to bit 16 : z = size

31h

32h

33h

34h

007Dh

0000h

0001h

(z × 256 bytes)

(Continued)

21

MBM29DL64DF-70

(Continued)

Description

A⁶to A⁰

DQ¹⁵to DQ⁰

Erase Block Region 3 Information

bit 15 to bit 0 : y = number of sectors

bit 31 to bit 16 : z = size

35h

36h

37h

38h

0007h

0000h

0020h

0000h

(z × 256 bytes)

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

43h

44h

0031h

0033h

Address for command write and process technology

DQ¹, DQ0 : Address requied for command write (00h : requied)

04h : Required and 0.17 µm technology

45h

0004h

DQ⁷to DQ2 : 0.17 µm process technology

Erase Suspend

02h = To Read & Write

46h

47h

0002h

0001h

Sector Protection

00h = Not Supported

X = Number of sectors per group

Sector Temporary Unprotection

01h = Supported

48h

49h

0001h

0004h

Sector Protection Algorithm

Dual Operation

00h = Not Supported

4Ah

0077h

X = Total number of sectors in all banks except Bank 1

Burst Mode Type

00h = Not Supported

4Bh

4Ch

4Dh

0000h

0085h

Page Mode Type

00h = Not Supported

V^ACC(Acceleration) Supply Minimum

DQ7 to DQ4 : 1 V, DQ3 to DQ0 : 100 mV

V^ACC(Acceleration) Supply Maximum

DQ⁷to DQ4 : 1 V, DQ3 to DQ0 : 100 mV

4Eh

4Fh

50h

0095h

0001h

Boot Type

Program Suspend

01h = Supported

Bank Organization

X = Number of Banks

57h

58h

59h

5Ah

5Bh

0004h

0017h

0030h

0017h

Bank A Region Information

X = Number of sectors in Bank A

Bank B Region Information

X = Number of sectors in Bank B

Bank C Region Information

X = Number of sectors in Bank C

Bank D Region Information

X = Number of sectors in Bank D

22

MBM29DL64DF-70

■ FUNCTIONAL DESCRIPTION

Simultaneous Operation

The device features functions that enable data reading of one memory bank while a program or erase operation

is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read,

program, erase, erase-suspend read, and erase-suspend program) . The bank is selected by bank address (A²¹,

A20, A19) with zero latency. The device consists of the following four banks :

Bank A : 8 × 8 KB and 15 × 64 KB; Bank B : 48 × 64 KB; Bank C : 48 × 64 KB; Bank D : 8 × 8 KB and 15 × 64 KB.

The device can execute simultaneous operations between Bank 1, a bank chosen from among the four banks,

and Bank 2, a bank consisting of the three remaining banks (see “FlexBank^TMArchitecture”.) This is what we

call “FlexBank”, for example, the rest of banks B, C and D to let the system read while Bank A is in the process

of program (or erase) operation. However the different types of operations for the three banks are not allowed,

e.g., Bank A writing, Bank B erasing, and Bank C reading out. With this “FlexBank”, as described in “Example

of Virtual Banks Combination”, the system gets to select from four combinations of data volume for Bank 1 and

Bank 2, which works well to meet the system requirement. The simultaneous operation cannot execute multi-

function mode in the same bank. “Simultaneous Operation” shows the possible combinations for simultaneous

operation (refer to “(8) Bank-to-Bank Read/Write Timing Diagram” in ■TIMING DIAGRAM.)

FlexBank^TMArchitecture Table

Bank 1

Combination

Bank 2

Combination

Bank

Splits

Volume

8 Mbit

Volume

56 Mbit

40 Mbit

56 Mbit

1

2

3

4

Bank A

Bank B

Bank C

Bank D

Bank B, C, D

Bank A, C, D

Bank A, B, D

Bank A, B, C

24 Mbit

8 Mbit

Example of Virtual Banks Combination Table

Bank 1

Volume Combination

Bank 2

Bank

Splits

Sector Size

Volume Combination

Sector Size

Bank B

+

8 × 8 Kbyte/4 Kword

1

2

3

4

8 Mbit

16 Mbit

24 Mbit

32 Mbit

Bank A

+

56 Mbit

48 Mbit

Bank C

+

15 × 64 Kbyte/32 Kword

111 × 64 Kbyte/32 Kword

Bank D

Bank A

+

Bank D

16 × 8 Kbyte/4 Kword

Bank B

+

Bank C

+

96 × 64 Kbyte/32 Kword

30 × 64 Kbyte/32 Kword

Bank A

+

16 × 8 Kbyte/4 Kword

Bank B

48 × 64 Kbyte/32 Kword 40 Mbit

Bank C

+

78 × 64 Kbyte/32 Kword

Bank D

Bank A

+

Bank B

8 × 8 Kbyte/4 Kword

Bank C

+

Bank D

8 × 8 Kbyte/4 Kword

+

32 Mbit

+

63 × 64 Kbyte/32 Kword

Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which

a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,

neither Bank A nor Bank B is read out They output the sequence flag once they are selected.

Meanwhile the system would get to read from either Bank C or Bank D.

23

MBM29DL64DF-70

Simultaneous Operation Table

Case

Bank 1 Status

Read mode

Bank 2 Status

Read mode

1

2

3

4

5

6

7

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

* : By writing erase suspend command on the bank address of sector being erased, the erase operation becomes

suspended so that it enables reading from or programming the remaining sectors.

Note : Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. The Bank consists

of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) means to specify each of the Banks.

Read Mode

The device has two control functions required to obtain data at the outputs. CE is the power control and used

for a device selection. OE is the output control and used to gate data to the output pins.

Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable

access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE to valid data at the output pins, assuming the

addresses have been stable for at least tACC-tOE time. When reading out data without changing addresses after

power-up, it is required to input hardware reset or to change CE pin from “H” to “L”

Standby Mode

There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and

the other via the RESET pin only.

When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC ± 0.3 V. Under

this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active

current (ICC2) is required even when CE = “H”. The device can be read with standard access time (tCE) from either

of these standby modes.

When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V

(CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is

set high, the device requires tRH as a wake-up time for output to be valid for read access.

During standby mode, the output is in the high impedance state regardless of OE input.

Automatic Sleep Mode

Automatic sleep mode works to restrain power consumption during read-out of device data. This is useful in

applications such as handy terminal which requires low power consumption.

To activate this mode, the device automatically switches itself to low power mode when the device addresses

remain stable during after 150 ns from data valid. It is not necessary to control CE, WE and OE in this mode. In

this mode the current consumed is typically 1 µA (CMOS Level) .

During simultaneous operation, VCC active current (ICC2) is required.

Since the data are latched during this mode, the data are continuously read out. When the addresses are

changed, the mode is automatically canceled and the device reads the data for changed addresses.

24

MBM29DL64DF-70

Output Disable

With the OE input at a logic high level (VIH) , output from the device is disabled. This causes the output pins to

be in a high impedance state.

Autoselect

Autoselect mode allows reading out of binary code and identifies its manufacturer and type.It is intended for use

by programming equipment for the purpose of automatically matching the device to be programmed with its

corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force V^IDon address pin A9. Three identifier bytes may

then be sequenced from the device outputs by toggling addresses. All addresses can be either High or Low

except A6, A3, A2, A1, A0 and (A-1) See User Bus Operations.

The manufacturer and device codes may also be read via the command register, for instances when the device

is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is

illustrated in “Command Definitions”.

In the command Autoselect mode, the bank addresses BA; (A²¹, A20, A19) must point to a specific bank during

the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while

array data can be read from the other bank.

In Word mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle at

address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended

Device Codes is required. Therefore the system may continue reading out these Extended Device Codes at

addresses of 0Eh and 0Fh. Notice that the above applies to Word mode; the addresses and codes differ from

those of Byte mode (refer to “Sector Group Protection Verify Autoselect Codes Table” and “Extended Autoselect

Code Table” in ■DEVICE BUS OPERATION.

In the case of applying V^IDon A9, as both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation

cannot be executed.

Write

Device erasure and programming are accomplished via the command register. The contents of the register serve

as input to the internal state machine. The state machine output dictates the device function.

The command register itself does not occupy any addressable memory location. The register is a latch used to

store the commands, along with the address and data information needed to execute the command. The com-

mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

falling edge of WE or CE, whichever starts later, while data is latched on the rising edge of WE or CE, whichever

starts first. Standard microprocessor write timings are used.

Refer to “■AC WRITE CHARACTERISTICS” and Erase/Programming Waveforms for specific timing parameters.

Sector Group Protection

The device features hardware sector group protection. This feature disables both program and erase operations

in any combination of forty eight sector groups of memory. See “Sector Group Address Table”. The user‘s side

can use sector group protection using programming equipment. The device is shipped with all sector groups

unprotected.

To activate it, the programming equipment must force V^IDon address pin A9 and control pin OE, CE = VIL and

A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12)

should be set to the sector to be protected. Sector Address Tables (Bank A to Bank D) define the sector address

for each of the one hundred forty-two (142) individual sectors, and Sector Group Address Table defines the

sector group address for each of the forty eight (48) individual group sectors. Programming of the protection

circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector

group addresses must be held constant during the WE pulse. See Sector Group Protection waveforms and

algorithms.

To verify programming of the protection circuitry, the programming equipment must force V^IDon address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18, A17, A16, A15, A14,

A13 and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) produces a logica “1” code at device output DQ0 for a

protected sector. Otherwise the device produces “0” for unprotected sectors. In this mode, the lower order

25

MBM29DL64DF-70

addresses, except for A⁶, A3, A2, A1 and A0 are DON’T CARES. Address locations with A1 = VIL are reserved for

Autoselect manufacturer and device codes. A-1 requires applying to VIL on byte mode.

Whether the sector group is protected in the system can be determined by writing an Autoselect command.

Performing a read operation at the address location (BA) XX02h, where the higher order addresses (A²¹, A20,

A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address, will produce a logical “1” at DQ0

for a protected sector group. Note that the bank addresses (A21, A20, A19) must be pointing to a specific bank

during the third write bus cycle of the Autoselect command. Then the Autoselect data can be read from that

bank while array data can still be read from the other bank. To read Autoselect data from the other bank, it must

be reset to read mode and then write the Autoselect command to the other bank. See Sector Group Protection

Verify Autoselect Codes.

Temporary Sector Group Unprotection

This feature allows temporary unprotection of previously protected sector groups of the device in order to change

data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During

this mode, formerly protected sector groups can be programmed or erased by selecting the sector group ad-

dresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be

protected again. Refer to “(6) Temporary Sector Group Unprotection Algorithm” in ■FLOW CHRAT.

RESET

Hardware Reset

The device is reset by driving the RESET pin to VIL. The RESET pin works pulse requirement and has to be kept

low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of

being executed is terminated and the internal state machine is reset to the read mode “tREADY” after the RESET

pin is driven low. Furthermore once the RESET pin goes high the device requires an additional “tRH” before it

allows read access. When the RESET pin is low, the device will be in the standby mode for the duration of the

pulse and all the data output pins are tri-stated. If a hardware reset occurs during a program or erase operation,

the data at that particular location is corrupted. Please note that the RY/BY output signal should be ignored

during the RESET pulse. See “(11) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for the timing

diagram. Refer to “Temporary Sector Group Unprotection” for additional functionality.

Byte/Word Configuration

BYTE pin selects Byte (8-bit) mode or Word (16-bit) mode for the device. When this pin is driven high, the device

operates in Word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, the

device operates in Byte (8-bit) mode. In this mode the DQ15/A-1 pin becomes the lowest address bit, and DQ14

to DQ8 bits are tri-stated. However the command bus cycle is always an 8-bit operation and hence commands

are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to Timing Diagram for Word Mode/Byte Mode

Configuration.

Boot Block Sector Protection

The Write Protection function provides a hardware method of protecting certain boot sectors without using VID.

This function is one of two provided by the WP/ACC pin.

If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two

outermost 8 Kbytes on both ends of boot sectors (SA0, SA1, SA140, and SA141) independently of whether

those sectors are protected or unprotected using the method described in “Sector Group Protection.”

If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8 Kbyte on both

ends of boot sectors were last set to be protected or unprotected. Sector group protection or unprotection for

these four sectors depends on whether they ware last protected or unprotected using the method described in

“Sector Group Protection.”

26

MBM29DL64DF-70

Accelerated Program Operation

Thedeviceoffersacceleratedprogramoperationwhichenablesprogramminginhighspeed. Ifthesystemasserts

V^ACCto the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program

operation reduces to about 60%. This function is primarily intended to allow high speed programming, so caution

is needed as the sector group temporarily becomes unprotected.

The system uses a fast program command sequence when programming during acceleration mode.

Set command to fast mode and reset command from fast mode are not necessary. When the device enters the

acceleration mode, the device is automatically set to fast mode. Therefore the present sequence could be used

for programming and detection of completion during acceleration mode.

Removing V^ACCfrom the WP/ACC pin returns the device to normal operation. Do not remove V^ACCfrom WP/

ACC pin while programming. See “(18) Accelerated Program Timing Diagram” in ■TIMING DIAGRAM.

Erase operation at Acceleration mode is strictly prohibited.

27

MBM29DL64DF-70

■ COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register. Some

commands require Bank Address (BA) input. When command sequences are input into a bank reading, the

commands have priority over the reading. ■DEVICE BUS OPERATION table shows the valid register command

sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the

Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands

are valid only while the Program operation is in progress. Furthermore Read/Reset commands are functionally

equivalent, resetting the device to the read mode. Note that commands are always written at DQ7 to DQ0 and

DQ15 to DQ8 bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ⁵= 1) to Read/Reset mode, the Read/

Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro-

processor read cycles retrieve array data from the memory. The device remains enabled for reads until the

command register contents are altered.

The device automatically powers-up in the Read/Reset state. In this case a command sequence is not required

in order to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures

that no spurious alteration of the memory content occurs during the power transition. Refer to “■AC CHARAC-

TERISTICS” and “■TIMING DIAGRAM” for the specific timing parameters.

Autoselect Command

Flash memories are designed for use in applications where the local CPU alters memory contents. Therefore

manufacture and device codes must be accessible while the device resides in the target system. PROM pro-

grammers typically access the signature codes by raising A⁹to a higher voltage. However multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains Autoselect command operation to supplement traditional PROM programming methodology.

The operation is initiated by writing the Autoselect command sequence into the command register.

The Autoselect command sequence is initiated first by writing two unlock cycles. This is followed by a third write

cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device

codes can be read from the bank, and actual data from the memory cell can be read from another bank. The

higher order address (A²¹, A20, A19) required for reading out the manufacture and device codes demands the

bank address (BA) set at the third write cycle.

Following the command write, in WORD mode, a read cycle from address (BA) 00h returns the manufacturer’s

code (Fujitsu = 04h) . And a read cycle at address (BA) 01h outputs device code. When 227Eh was output, this

indicates that two additional codes, called Extended Device Codes will be required. Therefore the system may

continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. Notice

that the above applies to WORD mode. The addresses and codes differ from those of BYTE mode (refer to

“MBM29DL64DF Sector Group Protection Verify Autoselect Codes” and “Extended Autoselect Code Table” in

■DEVICE BUS OPERATION. )

The sector state (protection or unprotection) will be informed by address (BA) 02h for × 16 ( (BA) 04h for × 8) .

Scanning the sector group addresses (A²¹, A20, A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A3, A2, A1,

A0) = (0, 0, 0, 1, 0) produces a logic “1” at device output DQ0 for a protected sector group. The programming

verification should be performed by verifying sector group protection on the protected sector (see User Bus

Operations Tables.

The manufacture and device codes can be read from the selected bank. To read the manufacture and device

codes and sector group protection status from a non-selected bank, it is necessary to write the Read/Reset

command sequence into the register. Autoselect command should then be written into the bank to be read.

If the software (program code) for Autoselect command is stored in the Flash memory, the device and manu-

facture codes should be read from the other bank, which does not contain the software.

28

MBM29DL64DF-70

To terminate the operation, write the Read/Reset command sequence into the register. To execute the Autoselect

command during the operation, Read/Reset command sequence must be written before the Autoselect com-

mand.

Byte/Word Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.

Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data is latched on the

rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) starts

programming. UponexecutingtheEmbeddedProgramAlgorithmcommandsequence, thesystemisnotrequired

to provide further controls or timings. The device automatically provides adequate internally generated program

pulses and verify programmed cell margin.

The system can determine program operation status by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) or RY/BY.

The Data Polling and Toggle Bit must be performed at the memory location being programmed.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which the device returns to the read mode and addresses are no longer latched (see “Hardware Sequence

Flags”) . Therefore the device requires that a valid address to the device be supplied by the system in this

particular instance. Hence Data Polling must be performed at the memory location being programmed.

If hardware reset occurs during the programming operation, the data being written is not guaranteed.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success

according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only

erase operations can convert from “0”s to “1”s.

“(1) Embedded Program^TMAlgorithm” in ■FLOW CHART illustrates the Embedded Program^TMAlgorithm using

typical command strings and bus operations.

Program Suspend/Resume

The Program Suspend command allows the system to interrupt a program operation so that data can be read

from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation

immediately suspends the programming. The Program Suspend command is issued during programming op-

eration as well while an erase is suspended. The bank addresses of sector being programmed should be set

when writing the Program Suspend command.

When the Program Suspend command is written during programming process, the device halts the program

operation within 1 µs and updates the status bits.

After the program operation is suspended, the system can read data from any address. The data at program-

suspended address is not valid. Normal read timing and command definitions apply.

After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses

of sectors being suspended should be set when writing the Program Resume command. The system can

determine the program operation status using the DQ⁷or DQ6 status bits, just as in the standard program

operation. See “Write Operation Status” for more information.

The system may also write the Autoselect command sequence when the device in the Program Suspend mode.

The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are

not stored in the memory. When the device exits from the Autoselect mode, the device reverts to the Program

Suspend mode, and is ready for another valid operation. See “Autoselect Command” for more information.

The system must write the Program Resume command (address bits are “Bank Address”) to exit from the

Program Suspend mode and continue the programming operation. Further writes of the Resume command are

ignored. Another Program Suspend command can be written after the device resumes programming.

29

MBM29DL64DF-70

Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithm

command sequence, the device automatically programs and verifies the entire memory for an all-zero data

pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or

timings during these operations.

The system can determine the erase operation status by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) or RY/BY.

The chip erase begins on the rising edge of the last CEor WE, whichever happens first in the command sequence,

and terminates when the data on DQ⁷is “1” (see “Write Operation Status” section) , at which the device returns

to the read mode.

Chip Erase Time : Sector Erase Time × All sectors + Chip Program Time (Preprogramming)

“(2) Embedded Erase^TMAlgorithm” in ■FLOW CHART illustrates the Embedded Erase^TMAlgorithm using typical

command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector

address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever

starts later, while the command (Data = 30h) is latched on the rising edge of CE or WE, whichever starts first.

After time-out of “t^TOW” from the rising edge of the last sector erase command, the sector erase operation begins.

Multiple sectors are erased concurrently by writing the six bus cycle operations on Command Definitions. This

sequence is followed by writes of the Sector Erase command to addresses in other sectors desired to be

concurrently erased. The time between writes must be less than “t^TOW”. Otherwise that command is not accepted

and erasure does not start. It is recommended that processor interrupts be disabled during this time to guarantee

such condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out of “t^TOW”

from the rising edge of last CE or WE, whichever starts first, initiates the execution of the Sector Erase command

(s) . If another falling edge of CE or WE, whichever starts first occurs within the “tTOW” time-out window, the timer

is reset (monitor DQ³to determine if the sector erase timer window is still open, see section DQ3, Sector Erase

Timer) . Resetting the device once execution begins may corrupt the data in the sector. In that case restart the

erase on those sectors and allow them to complete. Refer to “Write Operation Status” section for Sector Erase

Timer operation. Loading the sector erase buffer may be done in any sequence and with any number of sectors

(0 to 141) .

Sector erase does not require the user to program the device before erase. The device automatically programs

all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing

a sector, the rest remain unaffected. The system is not required to provide any controls or timings during these

operations.

The system can determine the status of the erase operation by using DQ⁷(Data Polling) , DQ6 (Toggle Bit) or

RY/BY.

The sector erase begins after the “t^TOW” time-out from the rising edge of CE or WE, whichever starts first, for the

last sector erase command pulse and terminates when the data on DQ⁷is “1” (see “Write Operation Status”

section) at which the device returns to the read mode. Data polling and Toggle Bit must be performed at an

address within any of the sectors being erased.

Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of

Sector Erase

In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which

sectors being erased belong cannot be performed.

“(2)EmbeddedErase^TMAlgorithm”in ■FLOWCHARTillustratesthetypicalcommandstringsandbusoperations.

30

MBM29DL64DF-70

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt Sector Erase operation and then reads data from or

programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation

which includes the time-out period for sector erase. Writing the Erase Suspend command (B0h) during the Sector

Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.

Writing the Erase Resume command (30h) resumes the erase operation. The bank address of sector being

erased or erase-suspended should be set when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum

of “t^SPD” to suspend the erase operation. When the device enters the erase-suspended mode, the

RY/BY output pin is at High-Z and the DQ7 is at logic “1”, and DQ6 stops toggling. The user must use the address

of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation is suspended. Further writes

of the Erase Suspend command are ignored.

When the erase operation is suspended, the device defaults to the erase-suspend-read mode. Reading data in

this mode is the same as reading from the standard read mode, except that the data must be read from sectors

that have not been erase-suspended. Reading successively from the erase-suspended sector while the device

is in the erase-suspend-read mode may cause DQ²to toggle (see the section on “DQ2”) .

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate com-

mand sequence for Program. This program mode is known as the erase-suspend-program mode. Again it is the

same with programming in the regular Program mode, except that the data must be programmed to sectors not

being erase-suspended. Reading successively from the erase-suspended sector while the device is in the erase-

suspend-program mode may cause DQ²to toggle. The end of the erase-suspended Program operation is

detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) , which is the same with the

regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from

any address within bank being erase-suspended.

To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase

suspended. Any further writes of the Resume command at this point are ignored. Another Erase Suspend

command can be written after the chip resumes erasing.

Fast Mode Set/Reset

Fast Mode function dispenses with the initial two unclock cycles required in the standard program command

sequence by writing the Fast Mode command into the command register. In this mode the required bus cycle

for programming consists of two bus cycles instead of four in standard program command. Do not write erase

command in this mode. The read operation is also executed after exiting from the fast mode. To exit from this

mode, write Fast Mode Reset command into the command register. The first cycle must contain the bank address.

The V^CCactive current is required even if CE = VIH during Fast Mode.

Fast Programming

During Fast Mode, programming is executed with two bus cycle operation. The Embedded Program Algorithm

is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . See “(8) Embedded

Programming Algorithm for Fast Mode” in ■FLOW CHART. The address of the program set-up command is

don’t care. Fast Program command, with the exception of its process taken place at the two bus cycles, emulates

the conventional programming so that the programming termination can be detected by Data polling of DQ7,

Toggle Bit I (DQ6) and RY/BY output pins.

Extended Sector Group Protection

In addition to normal sector group protection, the device has Extended Sector Group Protection as extended

function. This function enables protection of the sector group by forcing V^IDon RESET pin and writes a command

sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins.

The extended sector group protection requires VID on RESET pin only. With this condition the operation is initiated

by writing the set-up command (60h) in the command register. Then the sector group addresses pins (A21, A20,

A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set to the sector group

to be protected (setting VIL for the other addresses pins is recommended) , and an extended sector group

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MBM29DL64DF-70

protection command (60h) should be written. A sector group is typically protected in 250 µs. To verify program-

ming of the protection circuitry, the sector group addresses pins (A²¹, A20, A19, A18, A17, A16, A15, A14, A13 and A12)

and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set a command (40h) should be written. Following the command

write, a logic “1” at device output DQ0 will produce a protected sector in the read operation. If the output is logic

“0”, write the extended sector group protection command (60h) again. To terminate the operation, it is necessary

tosetRESET pintoVIH. (referto“(17)ExtendedSectorGroupProtectionTimingDiagram”in ■TIMINGDIAGRAM

and “(7) Extended Sector Group Protection Algorithm” in ■FLOW CHART.)

Query (CFI : Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines device and the host system software interro-

gation handshake, which allows specific vendor-specified software algorithms to be used for entire families of

devices. This allows device-independent, JEDEC ID-independent and forward-and backward-compatible soft-

ware support for the specified flash device families. Refer to Common Flash Memory Interface Code in detail.

The operation is initiated by writing the query command (98h) into the command register. The bank address

should be set when writing this command. Then the device information can be read from the bank, and data

from the memory cell can be read from the another bank. The higher order address (A²¹, A20, A19) required for

reading out the CFI Codes demands that the bank address (BA) be set at the write cycle. Following the command

write, a read cycle from specific address retrieves device information. Note that output data of upper byte

(DQ15 to DQ8) is “0” in word mode (16 bit) read. Refer to Common Flash Memory Interface Code. To terminate

operation, write the read/reset command sequence into the register.

HiddenROM Region

The HiddenROM feature provides Flash memory region that the system may access through a new command

sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the

device with the ESN protected against modification. Once the HiddenROM region is protected, any further

modification of that region becomes impossible. This ensures the security of the ESN once the product is shipped

to be sold.

The HiddenROM region is 256 bytes in length and is stored at the same address of SA0 in Bank A. The device

occupies the address of the byte mode 000000h to 0000FFh (word mode 000000h to 00007Fh) . After the system

writes the Enter HiddenROM command sequence, the system reads the HiddenROM region by using the

addresses normally occupied by the boot sector (particular area of SA0) . That is, the device sends all commands

that would normally be sent to the boot sector (particular area of SA0) to the HiddenROM region. This mode of

operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed

from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the

boot sector.

When reading the HiddenROM region, either change addresses or change CE pin from “H” to “L”. The same

procedure should be taken (changing addresses or CE pin from “H” to “L”) after the system issues the Exit

HiddenROM command sequence to read actual memory cell data.

HiddenROM Entry Command

The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and

to remain once set. Programming is allowed in this area until it is protected. However once protection goes on,

unprotecting it is not allowed. Therefore extreme caution is required.

The HiddenROM area is 256 bytes. This area is normally the “outermost” 8 Kbyte boot block area in Bank A.

Therefore write the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM

mode when the HiddenROM area appears.

Sectors other than the boot block area SA0 can be read during HiddenROM mode. Read/Program of the

HiddenROM area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit

the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset

command sequence.

In HiddenROM mode, the simultaneous operation cannot be executed multi-function mode between the Hid-

denROM area and the Bank A.

32

MBM29DL64DF-70

HiddenROM Program Command

To program the data to the HiddenROM area, write the HiddenROM program command sequence during Hid-

denROM mode. This command is the same with the usual program command, except that it needs to write the

command during HiddenROM mode. Therefore the detection of completion method is the same, using the DQ⁷

data polling, DQ6 toggle bit and RY/BY pin. You should pay attention to the address to be programmed. If an

address not in the HiddenROM area is selected, the previous data is deleted.

HiddenROM Protect Command

There are two methods to protect the HiddenROM area. One of them is to write the sector group protect setup

command (60h) , set the sector address in the HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and

write the sector group protect command (60h) during the HiddenROM mode. The same command sequence is

used because it is the same with the extension sector group protect, except that it is in the HiddenROM mode

and does not apply high voltage to the RESET pin. Refer to “Extended Sector Group Protection” for details of

extension sector group protect setting.

The other method is to apply high voltage (V^ID) to A9 and OE, set the sector address in the HiddenROM area

and (A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the

protect circuit, apply high voltage (V^ID) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and the sector address

in the HiddenROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear

on DQ0 if it is not protected. Apply write pulse again. The same command sequence is used for the above method

because other than the HiddenROM mode, it is the same method with the sector group protect previously

mentioned. Refer to Secor Group Protection for details of the sector group protect setting.

Take note that other sector groups are affected if an address other than those for the HiddenROM area is selected

for the sector group address. Pay close attention that once it is protected, protection CANNOT BE CANCELLED.

Write Operation Status

Details in “Hardware Sequence Flags” are all the status flags which determine the status of the bank for the

current mode operation. The read operation from the bank which does not operate Embedded Algorithm returns

data of memory cells. These bits offer a method for determining whether an Embedded Algorithm is properly

completed. The information on DQ²is address-sensitive. This means that if an address from an erasing sector

is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing

sector is consecutively read. This allows users to determine which sectors are in erase.

The status flag is not output from banks (non-busy banks) that do not execute Embedded Algorithms. For example

a bank (busy bank) is executing an Embedded Algorithm. When the read sequence is [1] < busy bank > , [2] <

non-busy bank > , [3] < busy bank > , the DQ6 toggles in the case of [1] and [3]. In case of [2], the data of memory

cells are output. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in [1]

and [3].

In the erase suspend read mode, DQ2 is toggled in [1] and [3]. In case of [2], the data of memory cell is output.

33

MBM29DL64DF-70

Hardware Sequence Flags Table

DQ⁷

Status

DQ⁶

DQ⁵

0

DQ³

0

DQ²

1

Toggle *¹

Embedded Program Algorithm

Embedded Erase Algorithm

DQ⁷

0

Toggle

0

1

Erase Suspend Read

(Erase Suspended Sector)

1

0

Toggle

Data

1 *²

Erase

Erase Suspend Read

Suspended

Data

DQ⁷

Data

Toggle

Data

0

Data

0

(Non-Erase Suspended Sector)

In Progress Mode

Erase Suspend Program

(Non-Erase Suspended Sector)

Program Suspend Read

(Program Suspended Sector)

Data

Program

Suspended

Mode

Program Suspend Read

(Non-Program Suspended Sector)

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ⁷

0

Toggle

1

0

1

N/A

Exceeded

Time Limits

Erase Suspend Program

Suspended

Mode

DQ⁷

Toggle

1

0

N/A

(Non-Erase Suspended Sector)

*1 : Successive reads from the erasing or erase-suspend sector causes DQ²to toggle.

*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit.

DQ⁷

Data Polling

The device features Data Polling as a method to indicate the host that the Embedded Algorithms are in progress

or completed. During the Embedded Program Algorithm, an attempt to read the device produces reverse data

lastwrittentoDQ7. UponcompletionoftheEmbeddedProgramAlgorithm, anattempttoreadthedeviceproduces

true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device produces a

“0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read device produces

a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “(3) Data Polling Algorithm” in ■FLOW CHART.

For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse

sequences.

For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six

write pulse sequences. Data polling also works as a flag to indicate whether the device is in erase-suspend

mode. DQ7 goes from “0” to “1” during erase-suspend mode. Notice that to determine DQ7 entering erase-

suspend mode, indicate the sector address of sector being erased. Data Polling must be performed at sector

addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid.

If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then

that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for

erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.

Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ⁷) may change

asynchronously while the output enable (OE) is asserted low. This means that device is driving status information

on DQ7 at one instant, and then that byte’s valid data the next. Depending on when the system samples the DQ7

output, it may read the status or valid data. Even if device completes the Embedded Algorithm operation and

DQ7 has valid data, data outputs on DQ6 to DQ0 may still be invalid. The valid data on DQ7 to DQ0 is read on

successive read attempts.

34

MBM29DL64DF-70

The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algo-

rithm, Erase Suspend Mode or sector erase time-out. See Data Polling timing specifications and diagrams.

DQ⁶

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded

Algorithms are in progress or completed.

During Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data

from the busy bank results in DQ⁶toggling between one and zero. Once the Embedded Program or Erase

Algorithm cycle is completed, DQ⁶stops toggling and valid data is read on the next successive attempts. During

programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse

sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse

in the six write pulse sequences. The Toggle Bit I is active during the sector time out.

In Program Operation, if the sector being written to is protected, the toggle bit toggles for about 1 µs and then

stops toggling with data unchanged. In erase operation, the device erases all selected sectors except for pro-

tected ones. If all selected sectors are protected, the chip toggles the toggle bit for about 400 µs and then drop

back into read mode, having data kept remained.

Either CE or OE toggling causes DQ6 to toggle.

DQ⁶determines whether a sector erase is active or is erase-suspended. When a bank is actively erased (that

is, the Embedded Erase Algorithm is in progress) , DQ⁶toggles. When a bank enters the Erase Suspend mode,

DQ⁶stops toggling. Successive read cycles during erase-suspend-program cause DQ6 to toggle.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

See “(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” (in ■TIMING DIAGRAM) in for

the Toggle Bit I timing specifications and diagrams.

DQ⁵

Exceeded Timing Limits

DQ⁵indicates if the program or erase time exceeds the specified limits (internal pulse count) . Under these

conditions DQ5 produces “1”. This is a failure condition indicating that the program or erase cycle was not

successfully completed. Data Polling is only operating function of the device under this condition. The CE circuit

partially powers down device under these conditions (to approximately 2 mA) . The OE and WE pins control the

output disable functions as described in User Bus Operations.

The DQ5 failure condition may also appear if the user tries to program a non-blank location without pre-erase.

In this case the device locks out and never completes the Embedded Algorithm operation. Hence the system

never reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device exceeds timing limits, the DQ5

bit indicates a “1.” Please note that this is not a device failure condition since the device was incorrectly used.

If this occurs, reset device with the command sequence.

DQ³

Sector Erase Timer

After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 remains low

until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command

sequence.

If Data Polling or the Toggle Bit I indicates that a valid erase command is written, DQ3 determines whether the

sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle begins. If DQ3 is

low (“0”) , the device accepts additional sector erase commands. To insure the command is accepted, the system

software checks the status of DQ³prior to and following each subsequent Sector Erase command. If DQ3 is high

on the second status check, the command may not be accepted.

See Hardware Sequence Flags.

35

MBM29DL64DF-70

DQ²

Toggle Bit II

This toggle bit II, along with DQ⁶, determines whether the device is in the Embedded Erase Algorithm or in Erase

Suspend.

Successive reads from the erasing sector causes DQ2 to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector causes DQ2

to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase

suspended sector indicates a logic “1” at the DQ2 bit.

DQ⁶is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. These two status bits, along with that of DQ7, operate as follows :

For example DQ²and DQ6 determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6

does not.) See also “Toggle Bit Status” table and “DQ2 vs.DQ6” waveform.

Furthermore DQ2 determines which sector is being erased. At the erase mode, DQ2 toggles if this bit is read

from an erasing sector.

To operate toggle bit function properly, CE or OE must be high when bank address is changed.

Reading Toggle Bits DQ⁶/DQ²

Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row

to determine whether a toggle bit is on. Typically the system would note and store the value of the toggle bit

after the first read. After the second read, the system compares the new value of the toggle bit with the first. If

the toggle bit is not toggling, this indicates that the device completes the program or erase operation. The system

reads array data on DQ7 to DQ0 on the following read cycle.

However if after the initial two read cycles, the system determines that the toggle bit is still on, the system also

should note whether the value of DQ5 is high (see the section on “DQ5”) . If it is, the system should then determine

again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high.

If the toggle bit is no longer toggling, the device successfully completes the program or erase operation. If it is

still toggling, the device does not complete the operation successfully, and the system must write the reset

command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ⁵has not

gone high. The system continues to monitor the toggle bit and DQ5 through successive read cycles, determining

the status as described in the previous paragraph. Alternatively the system chooses to perform other system

tasks. In this case the system must start at the beginning of the algorithm to determine the status of the operation.

Toggle Bit Status Table

Mode

DQ⁷

DQ7

0

DQ⁶

DQ²

1

Program

Erase

Toggle

Toggle*¹

Erase-Suspend Read

(Erase-Suspended Sector)

1

Toggle

1*²

Erase-Suspend Program

DQ⁷

Toggle

*1 : Successive reads from the erasing or erase-suspend sector cause DQ²to toggle.

*2 : Reading from the non-erase suspend sector address indicates logic “1” at the DQ2 bit.

RY/BY

Ready/Busy

The device provides a RY/BY open-drain output pin as a way to indicate that Embedded Algorithms are either

in progress or have been completed. When output is low the device is busy with either a program or erase

36

MBM29DL64DF-70

operation. If output is high, the device is ready to accept any read/write or erase operation. If the device is placed

in an Erase Suspend mode, RY/BY output is high.

During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase

operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin indicates busy

condition during RESET pulse. Refer to “(10) RY/BY Timing Diagram during Program/Erase Operation Timing

Diagram” and “(11) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM. RY/BY pin is pulled high in standby

mode.

Since this is an open-drain output, Pull-up resistor needs to be connected to VCC; multiples of devices may be

connected to the host system via more than one RY/BY pin in parallel.

Data Protection

The device offers protection against accidental erasure or programming caused by spurious system level signals

that may exist during power transitions. During power-up the device automatically resets the internal state

machine in Read mode. With its control register architecture, alteration of memory contents only occurs after

successful completion of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting from V^CCpower-up

and power-down transitions or system noise.

Low V^CCWrite Inhibit

To avoid initiation of a write cycle during V^CCpower-up and power-down, the write cycle is locked out for VCC less

than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled.

Under this condition the device resets to the read mode. Subsequent writes are ignored until the VCC level goes

higher than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent

unintentional writes when VCC is above VLKO.

If the Embedded Erase Algorithm is interrupted, the intervened erasing sector (s) is (are) not valid.

Write Pulse “Glitch” Protection

Noise pulses of less than 3 ns (typical) on OE, CE or WE does not initiate write cycle.

Logical Inhibit

Writing is prohibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE

must be logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE = VIH does not accept commands on the rising edge of WE.

Internal state machine is automatically reset to the read mode on power-up.

Sector Group Protection

Device user is able to protect each sector group individually to store and protect data. Protection circuit voids

both program and erase command that are addressed to protect sectors. Any commands to program or erase

addressed to protected sector are ignored (see ■FUNCTIONAL DESCRIPTION, Sector Group Protection) .

37

MBM29DL64DF-70

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min

−55

−40

Max

+125

+85

Storage Temperature

Tstg

T^A

°C

Ambient Temperature with Power Applied

Voltage with Respect to Ground All pins except A⁹,

OE, and RESET *^1,*²

VIN, VOUT

−0.5

VCC + 0.5

V

Power Supply Voltage *¹

A9, OE, and RESET *^1,*³

WP/ACC *^1,*⁴

VCC

VIN

−0.5

+4.0

+13.0

+10.5

V

VACC

*1: Voltage is defined on the basis of VSS = GND = 0 V.

*2: Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot

VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage

transitions, input or I/O pins may overshoot to VCC + 2.0 V for periods of up to 20 ns.

*3: Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET

pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage

(VIN - VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may

overshoot to +14.0 V for periods of up to 20 ns.

*4: Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may undershoot

VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min

−40

+2.7

Max

+85

Ambient Temperature

Power Supply Voltage*

T^A

°C

V^CC

+3.6

V

* : Voltage is defined on the basis of VSS = GND = 0 V.

Note: Operating ranges define those limits between which the proper device function is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

38

MBM29DL64DF-70

■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT

20 ns

+0.6 V

−0.5 V

−2.0 V

20 ns

Maximum Undershoot Waveform

20 ns

VCC + 2.0 V

VCC + 0.5 V

+2.0 V

20 ns

Maximum Overshoot Waveform 1

20 ns

+14.0 V

+13.0 V

VCC + 0.5 V

20 ns

Note : Applicable for A⁹, OE and RESET.

Maximum Overshoot Waveform 2

39

MBM29DL64DF-70

■ DC CHARACTERISTICS

Value

Typ

Sym-

Parameter

bol

Conditions

Unit

Min

−1.0

Max

+1.0

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCC, VCC = VCC Max

VOUT = VSS to VCC, VCC = VCC Max

µA

ILO

A9, OE, RESET Inputs Leakage

Current

VCC = VCC Max,

A9, OE, RESET = 12.5 V

ILIT

ILIA

+35

µA

WP/ACC Accelerated Program

Current

VCC = VCC Max,

WP/ACC = VACC Max

20

mA

Byte

Word

Byte

16

18

4

CE = VIL, OE = VIH,

f = 5 MHz

mA

V^CCActive Current *¹

ICC1

CE = VIL, OE = VIH,

f = 1 MHz

mA

Word

4

V^CCActive Current *²

V^CCCurrent (Standby)

ICC2

ICC3

CE = VIL, OE = VIH

30

VCC = VCC Max, CE = VCC ± 0.3 V,

RESET = VCC ± 0.3 V,

1

5

µA

WP/ACC = VCC ± 0.3 V

VCC = VCC Max,

RESET = VSS ± 0.3 V

V^CCCurrent (Standby, Reset)

ICC4

ICC5

VCC = VCC Max, CE = VSS ± 0.3 V,

RESET = VCC ± 0.3 V

VIN = VCC ± 0.3 V or VSS ± 0.3 V

V^CCCurrent

(Automatic Sleep Mode) *⁵

V^CCActive Current *⁶

(Read-While-Program)

Byte

CE = VIL, OE = VIH

Word

46

48

46

48

ICC6

mA

V^CCActive Current *⁶

(Read-While-Erase)

Byte

CE = VIL, OE = VIH

Word

ICC7

ICC8

mA

V^CCActive Current

(Erase-Suspend-Program)

CE = VIL, OE = VIH

40

Input Low Level

Input High Level

V^IL

−0.5

0.6

V

VIH

2.0

VCC + 0.3

Voltage for Autoselect and Sector

Protection (A⁹, OE, RESET) *^3,*⁴

VID

11.5

12

12.5

V

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration *⁴

VACC

VOL

8.5

9.0

9.5

V

Output Low Voltage Level

Output High Voltage Level

Low VCC Lock-Out Voltage

IOL = 4 mA, VCC = VCC Min

0.45

V

VOH1 IOH = −2.0 mA, VCC = VCC Min

VOH2 IOH = −100 µA

VLKO

2.4

VCC − 0.4

2.3

2.4

2.5

*1 : ICC current listed includes both the DC operating current and the frequency dependent component.

*2 : ICC active while Embedded Algorithm (program or erase) is in progress.

*3 : This timing is only for Sector Group Protection Operation and Autoselect mode.

*4 : Applicable for only V^CC.

*5 : Automatic sleep mode enables the low power mode when addresses remain stable for 150 ns.

*6 : Embedded Algorithm (program or erase) is in progress (@5 MHz.)

40

MBM29DL64DF-70

■ AC CHARACTERISTICS

• Read Only Operations Characteristics

Symbol

Value (Note)

Condition

Parameter

Unit

Min

Max

JEDEC

Standard

Read Cycle Time

tAVAV

tRC

70

ns

CE = VIL

OE = VIL

Address to Output Delay

t^AVQV

tACC

70

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

tELQV

t^GLQV

t^EHQZ

tGHQZ

tCE

tOE

tDF

OE = VIL

70

30

25

ns

Output Hold Time From Addresses,

CE or OE, Whichever Occurs First

tAXQX

tOH

0

ns

µs

ns

RESET Pin Low to Read Mode

tREADY

20

5

tELFL

tELFH

CE to BYTE Switching Low or High

Note : Test Conditions :

Output Load : 30 pF (MBM29DL64DF^-70)

Input rise and fall times : 5 ns

Input pulse levels : 0.0 V or VCC

Timing measurement reference level

Input : 0.5 × V^CC

Output : 0.5 × VCC

3.3 V

1N3064

or Equivalent

2.7 kΩ

Device

Under

Test

6.2 kΩ

CL

Diodes = 1N3064

or Equivalent

Notes: C^L= 30 pF including jig capacitance (MBM29DL64DF-70)

In case of CL = 100 pF, the device can be operated at an access time of 80 ns.

Test Conditions

41

MBM29DL64DF-70

• Write/Erase/Program Operations

Symbol

Standard

Value

Typ

Unit

Parameter

JEDEC

tAVAV

Min

70

0

Max

Write Cycle Time

tWC

tAS

ns

Address Setup Time

t^AVWL

Address Setup Time to OE Low During Toggle Bit

Polling

tASO

tAH

12

30

0

ns

Address Hold Time

tWLAX

Address Hold Time from CE or OE High During

Toggle Bit Polling

tAHT

Data Setup Time

Data Hold Time

t^DVWH

tDS

tDH

25

0

ns

µs

s

tWHDX

Read

0

Output Enable

Hold Time

t^OEH

Toggle and Data Polling

10

20

0

CE High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write

CE Setup Time

tCEPH

tOEPH

tGHWL

tGHEL

tCS

tGHWL

t^GHEL

tELWL

tWLEL

tWHEH

tEHWH

t^WLWH

tELEH

tWHWL

tEHEL

0

WE Setup Time

tWS

0

CE Hold Time

tCH

0

WE Hold Time

tWH

0

Write Pulse Width

tWP

35

20

CE Pulse Width

tCP

Write Pulse Width High

CE Pulse Width High

tWPH

tCPH

Byte

4

6

Programming Operation

t^WHWH1

tWHWH1

Word

Sector Erase Operation *¹

V^CCSetup Time

tWHWH2

tVCS

0.5

50

500

4

µs

ns

µs

Rise Time to VID *²

tVIDR

Rise Time to VACC *³

Voltage Transition Time *²

Write Pulse Width *²

tVACCR

tVLHT

tWPP

100

(Continued)

42

MBM29DL64DF-70

(Continued)

Symbol

Standard

Value

Unit

Parameter

JEDEC

Min

4

Typ

Max

OE Setup Time to WE Active *²

CE Setup Time to WE Active *²

Recover Time from RY/BY

tOESP

tCSP

tRB

µs

ns

4

0

RESET Pulse Width

tRP

500

200

RESET High Level Period Before Read

BYTE Switching Low to Output High-Z

BYTE Switching High to Output Active

Program/Erase Valid to RY/BY Delay

tRH

tFLQZ

tFHQV

tBUSY

25

70

90

Delay Time from Embedded

Output Enable

t^EOE

70

ns

Erase Time-out Time

t^TOW

t^SPD

50

µs

Erase Suspend Transition Time

20

*1 : Does not include preprogramming time.

*2 : For Sector Group Protection operation.

*3 : For Accelerated Program operation only.

43

MBM29DL64DF-70

■ ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Unit

Comments

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

0.5

2.0

s

Word Programming Time

Byte Programming Time

6.0

4.0

100

80

µs

Excludes system-level

overhead

Excludes system-level

overhead

Chip Programming Time

Program/Erase Cycle

200

s

100,000

cycle

Notes : Typical Erase conditions TA = + 25 °C, VCC = 2.9 V

Typical Program conditions TA = + 25 °C, VCC = 2.9 V, Data = Checker

■ TSOP (1) PIN CAPACITANCE

Value

Unit

Parameter

Symbol

Condition

Typ

Max

10.0

12.0

11.0

12.0

Input Capacitance

C^IN

COUT

C^IN2

CIN3

VIN = 0

6.0

8.5

8.0

9.0

pF

Output Capacitance

VOUT = 0

VIN = 0

Control Pin Capacitance

WP/ACC Pin Capacitance

Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz

• DQ15/A-1 pin capacitance is stipulated by output capacitance.

■ FBGA PIN CAPACITANCE

Value

Parameter

Symbol

Condition

Unit

Typ

6.0

8.5

8.0

9.0

Max

10.0

12.0

11.0

12.0

Input Capacitance

C^IN

C^OUT

CIN2

CIN3

VIN = 0

pF

Output Capacitance

VOUT = 0

VIN = 0

Control Pin Capacitance

WP/ACC Pin Capacitance

Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz

• DQ15/A-1 pin capacitance is stipulated by output capacitance.

44

MBM29DL64DF-70

■ TIMING DIAGRAM

• Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Must Be

Steady

Will Be

Steady

May

Change

from H to L

Will

Change

from H to L

May

Change

from L to H

Will

Change

from L to H

"H" or "L":

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center Line is

High-

Impedance

"Off" State

(1) Read Operation Timing Diagram

tRC

Address

Address Stable

tACC

CE

OE

tOE

tDF

tOEH

WE

tCE

tOH

High-Z

Outputs Valid

Outputs

45

MBM29DL64DF-70

(2) Hardware Reset/Read Operation Timing Diagram

tRC

Address

Address Stable

tACC

CE

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

(3) Alternate WE Controlled Program Operation Timing Diagram

3rd Bus Cycle

555h

Data Polling

PA

Address

CE

tWC

tRC

tAS

tAH

tCS

tCH

tCE

OE

tOE

tWP

tWPH

tWHWH1

tGHWL

WE

tOH

tDF

tDS

tDH

A0h

PD

DOUT

DQ7

Data

Notes: • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

• These waveforms are for the × 16 mode.

46

MBM29DL64DF-70

(4) Alternate CE Controlled Program Operation Timing Diagram

3rd Bus Cycle

555h

Data Polling

PA

Address

WE

tWC

tAS

tAH

tWS

tWH

OE

CE

tCPH

tCP

tWHWH1

tGHEL

tDS

tDH

A0h

PD

DOUT

DQ7

Data

Notes: • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

• These waveforms are for the × 16 mode.

47

MBM29DL64DF-70

(5) Chip/Sector Erase Operation Timing Diagram

555h

tWC

2AAh

555h

2AAh

SA*

Address

tAS

tAH

CE

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

10h for Chip Erase

10h/

30h

AAh

55h

80h

AAh

55h

Data

VCC

tVCS

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.

Note : These waveforms are for the × 16 mode. The addresses differ from the × 8 mode.

(6) Data Polling during Embedded Algorithm Operation Timing Diagram

CE

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ0 =

Output Flag

DQ6 to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tEOE

tBUSY

* : DQ7 = Valid Data (the device has completed the Embedded operation) .

48

MBM29DL64DF-70

(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations

Address

CE

tAHT

tAS

tASO

tCEPH

WE

OE

tOEPH

tOEH

tDH

tOE

tCE

*

Stop

Toggling

Output

Valid

Data

Toggle Data

DQ6/DQ2

RY/BY

tBUSY

* : DQ6 stops toggling (the device has completed the Embedded operation) .

49

MBM29DL64DF-70

(8) Bank-to-Bank Read/Write Timing Diagram

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

CE

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDS

tDH

tDF

Valid

Output

Valid

Output

Valid

Output

Status

Intput

(A0h)

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1 : Address corresponding to Bank 1

BA2 : Address corresponding to Bank 2

(9) DQ²vs. DQ⁶

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase Suspend

Read

Erase Suspend

Read

WE

Erase

Suspend

Program

Erase

Complete

DQ6

DQ2*

Toggle

DQ2 and DQ6

with OE or CE

* : DQ2 is read from the erase-suspended sector.

50

MBM29DL64DF-70

(10) RY/BY Timing Diagram during Program/Erase Operation Timing Diagram

CE

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

(11) RESET, RY/BY Timing Diagram

WE

RESET

tRP

tRB

RY/BY

tREADY

(12) Timing Diagram for Word Mode Configuration

CE

tCE

BYTE

Data Output

(DQ14 to DQ0)

DQ14 to DQ0

(DQ7 to DQ0)

tELFH

tFHQV

A-1

DQ15

DQ15/A-1

51

MBM29DL64DF-70

(13) Timing Diagram for Byte Mode Configuration

CE

BYTE

tELFL

DQ14 to DQ0

Data Output

(DQ7 to DQ0)

(DQ14 to DQ0)

tACC

DQ15/A-1

A-1

DQ15

tFLQZ

(14) BYTE Timing Diagram for Write Operations

Falling edge of the last write signal

CE or WE

Input

Valid

BYTE

tAS

tAH

52

MBM29DL64DF-70

(15) Sector Group Protection Timing Diagram

A21, A20, A19

A18, A17, A16

SPAX

SPAY

A15, A14, A13

A12

A6, A3, A2, A0

A1

VID

VIH

A9

tVLHT

VID

VIH

OE

tVLHT

tWPP

WE

tOESP

tCSP

CE

01h

Data

tOE

tVCS

VCC

SPAX : Sector Group Address to be protected

SPAY : Next Sector Group Address to be protected

Note : A^-1is VIL on byte mode.

53

MBM29DL64DF-70

(16) Temporary Sector Group Unprotection Timing Diagram

VCC

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CE

WE

tVLHT

Program or Erase Command Sequence

Unprotection Period

RY/BY

54

MBM29DL64DF-70

(17) Extended Sector Group Protection Timing Diagram

VCC

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SPAX

SPAY

A6, A3,

A2, A0

A1

CE

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

SPAX : Sector Group Address to be protected

SPAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

55

MBM29DL64DF-70

(18) Accelerated Program Timing Diagram

VCC

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CE

WE

tVLHT

Program Command Sequence

Acceleration Period

RY/BY

56

MBM29DL64DF-70

■ FLOW CHART

(1) Embedded Program^TMAlgorithm

EMBEDDED ALGORITHM

Start

Write Program

Command Sequence

(See Below)

Data Polling

Embedded

Program

Algorithm

in program

No

Verify Data

?

Yes

No

Increment Address

Last Address

?

Yes

Programming Completed

Program Command Sequence (Address/Command):

555h/AAh

2AAh/55h

555h/A0h

Program Address/Program Data

Note : The sequence is applied for × 16 mode.

57

MBM29DL64DF-70

(2) Embedded Erase^TMAlgorithm

EMBEDDED ALGORITHM

Start

Write Erase

Command Sequence

(See Below)

Data Polling

Embedded

Erase

Algorithm

in progress

No

Data = FFh

?

Yes

Erasure Completed

Individual Sector/Multiple Sector

Erase Command Sequence

(Address/Command):

Chip Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Additional sector

erase commands

are optional.

Sector Address

/30h

Note : The sequence is applied for × 16 mode.

58

MBM29DL64DF-70

(3) Data Polling Algorithm

Start

VA = Address for programming

= Any of the sector addresses

within the sector being erased

during sector erase or multiple

sector erases operation.

Read Byte

(DQ7 to DQ0)

Addr. = VA

= Any of the sector addresses

within the sector not being

protected during chip erase

operation.

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read Byte

(DQ7 to DQ0)

Addr. = VA

Yes

DQ7 = Data?

*

No

Fail

Pass

* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

59

MBM29DL64DF-70

(4) Toggle Bit Algorithm

Start

Read DQ7 to DQ0

VA = Bank address being executed

Addr. = VA

Embedded Algorithm.

*1

Read DQ7 to DQ0

Addr. = VA

No

DQ6

= Toggle?

Yes

No

DQ5 = 1?

Yes

*1, *2

Read DQ7 to DQ0

Addr. = VA

Read DQ7 to DQ0

Addr. = VA

No

DQ6

= Toggle?

Yes

Program/Erase

Operation Not

Complete.Write

Reset Command

Program/Erase

Operation

Complete

*1 : Read toggle bit twice to determine whether it is toggling.

*2 : Recheck toggle bit because it may stop toggling as DQ⁵changes to “1”.

60

MBM29DL64DF-70

(5) Sector Group Protection Algorithm

Start

Setup Sector Group Addr.

A21, A20, A19, A18, A17,

(

)

A16, A15, A14, A13, A12

PLSCNT = 1

OE = VID, A9 = VID

CE = VIL, RESET = VIH

A6 = A3 = A2 = A0 = VIL, A1 = VIH

Activate WE Pulse

Increment PLSCNT

Time out 100 µs

WE = VIH, CE = OE = VIL

(A9 should remain VID)

Read from Sector Group

Addr. = SPA, A1 = VIH

A6 = A3 = A2 = A0 = VIL

*

(

)

No

PLSCNT = 25?

Yes

No

Data = 01h?

Yes

Remove VID from A9

Write Reset Command

Protect Another Sector

Group?

No

Remove VID from A9

Write Reset Command

Device Failed

Sector Group Protection

Completed

* : A-1 is VIL in byte mode.

61

MBM29DL64DF-70

(6) Temporary Sector Group Unprotection Algorithm

Start

RESET = VID

*1

Perform Erase or

Program Operations

RESET = VIH

Temporary Sector Group

Unprotection Completed

*2

*1 : All protected sector groups are unprotected.

*2 : All previously protected sector groups are reprotected.

62

MBM29DL64DF-70

(7) Extended Sector Group Protection Algorithm

Start

RESET = VID

Wait to 4 µs

Device is Operating in

No

Extended Sector Group

Protection Entry?

Temporary Sector Group

Unprotection Mode

Yes

To Setup Sector Group Protection

Write XXXh/60h

PLSCNT = 1

To Protect Secter Group

Write 60h to Secter Address

(A6 = A3 = A2 = A0 = VIL, A1 = VIH)

Time out 250 µs

To Verify Sector Group Protection

Write 40h to Secter Address

Increment PLSCNT

(A6 = A3 = A2 = A0 = VIL, A1 = VIH)

Read from Sector Group Address

(Addr. = SPA, A1 = VIH,

No

A6 = A3 = A2 = A0 = VIL)

Setup Next Sector Group Address

No

Data = 01h?

PLSCNT = 25?

Yes

Protect Other Sector

Group?

Remove VID from RESET

Write Reset Command

No

Remove VID from RESET

Write Reset Command

Device Failed

Sector Group Protection

Completed

63

MBM29DL64DF-70

(8) Embedded Programming Algorithm for Fast Mode

FAST MODE ALGORITHM

Start

555h/AAh

2AAh/55h

Set Fast Mode

555h/20h

XXXh/A0h

In Fast Program

Program Address/Program Data

Data Polling

No

Verify Data?

Yes

No

Last Address?

Yes

Increment Address

Programming Completed

(BA) XXXh/90h

XXXh/F0h

Reset Fast Mode

Note : The sequence is applied for × 16 mode.

64

MBM29DL64DF-70

■ ORDERING INFORMATION

MBM29DL64D

F

70

TN

PACKAGE TYPE

TN = 48-Pin Thin Small Outline Package

(TSOP) Normal Bend

PBT = 48-Ball Fine pitch Ball Grid Array

Package (FBGA)

SPEED OPTION

See Product Selector Guide

DEVICE REVISION

DEVICE NUMBER/DESCRIPTION

MBM29DL64D

64 Mega-bit (8 M × 8-Bit or 4 M × 16-Bit) Flash Memory

3.0 V-only Read, Program, and Erase

Remarks

Part No.

MBM29DL64DF70TN

Package

Access Time (ns)

48-pin plastic TSOP (1)

(FPT-48P-M19)

70

Normal Bend

48-pin plastic FBGA

(BGA-48P-M13)

MBM29DL64DF70PBT

65

MBM29DL64DF-70

■ PACKAGE DIMENSIONS

Note 1) * : Values do not include resin protrusion.

48-pin plastic TSOP (1)

(FPT-48P-M19)

Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

LEAD No.

1

48

INDEX

Details of "A" part

0.25(.010)

0~8˚

0.60±0.15

(.024±.006)

24

25

*

20.00±0.20

(.787±.008)

12.00±0.20

(.472±.008)

*18.40±0.20

(.724±.008)

1.10 –⁺0⁰.^.0¹5⁰

.043 –⁺.^.0⁰0⁰2⁴

(Mounting

height)

0.10±0.05

(.004±.002)

(Stand off height)

0.50(.020)

"A"

0.10(.004)

0.17 ^–⁺⁰⁰^.^.⁰⁰⁸³

0.22±0.05

(.009±.002)

M

0.10(.004)

.007 –⁺.^.0⁰0⁰3¹

C

2003 FUJITSU LIMITED F48029S-c-6-7

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

66

MBM29DL64DF-70

(Continued)

48-pin plastic FBGA

(BGA-48P-M13)

9.00±0.20(.354±.008)

1.05 ⁺–0⁰.^.1¹0⁵.041 –⁺.^.0⁰0⁰4⁶

5.60(.220)

(Mounting height)

0.38±0.10(.015±.004)

(Stand off)

0.80(.031)TYP

6

5

4

3

2

1

8.00±0.20

(.315±.008)

4.00(.157)

INDEX

H

G

F

E

D

C

B

A

C0.25(.010)

48-ø0.45±0.10

M

ø0.08(.003)

(48-ø.018±.004)

0.10(.004)

C

2001 FUJITSU LIMITED B48013S-c-3-2

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

67

MBM29DL64DF-70

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0303

FUJITSU LIMITED Printed in Japan


型号：	MBM29DL64DF70TN
厂家：	FUJITSU
描述：	FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT FLASH存储器CMOS 64米（8米乘8/4米乘16 ）位闪存存储内存集成电路光电二极管
文件：	总68页 (文件大小：793K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MBM29DL64DF70TN [FUJITSU]

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