MB90F962PMT_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13749-1E

16-bit Microcontroller

CMOS

F²MC-16LX MB90960 Series

MB90F962(S)/V340E-101/V340E-102

■ DESCRIPTION

The MB90960-series is a 16-bit general-purpose microcontroller. Fujitsu now offers on-chip Flash-ROM program

memory up to 64 Kbytes.

The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates

a major advantage in terms of EMI and power consumption.

The unit features a 4 channel input capture unit, 1 channel 16-bit free-run timer, 2-channel LIN-UART, and 16-

channel 8/10-bit A/D converter as the peripheral resource.

Note : F²MC is the abbreviation of FUJITSU Flexible Microcontroller.

■ FEATURES

• Clock

• Built-in PLL clock frequency multiplying circuit

• Machine clock (PLL clock) selectable from frequency division by 2 of oscillation clock or 1 to 6-multiplied

oscillation clock (4 MHz to 24 MHz when oscillation clock is 4 MHz) .

• Sub clock operation : Up to 50 kHz (devices without S-suffix only)

• Minimum instruction execution time : 42 ns (4 MHz oscillation clock and 6-multiplied PLL clock) .

(Continued)

Be sure to refer to the “Check Sheet” for the latest cautions on development.

“Check Sheet” is seen at the following support page

URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system

development.

MB90960 Series

• Instruction system optimized controllers

• 16 Mbytes CPU memory space : Internal 24-bit addressing

• Various data types (bit, byte, word, and long word)

• Various addressing modes (23 types)

• Enhanced signed instructions of multiplication/division and RETI

• Enhanced high-accuracy operations by 32-bit accumulator

• Instruction system for high-level language (C language) / multitask

• System stack pointer

• Enhanced pointer indirect instructions

• Barrel shift instructions

• Higher execution speed

• 4-byte instruction queue

• Powerful interrupt function

• Powerful interrupt function with 8 levels and 34 factors

• Corresponds to 8-channel external interrupt

• CPU-independent automatic data transfer function

• Expanded intelligent I/O service function (EI²OS) : Maximum 16 channels

• Low-power consumption mode

• Clock mode

PLL clock mode (a PLL clock that is a multiple of the oscillation clock is used to operate the CPU and peripheral

functions.)

Main clock mode (the main clock, with the oscillation clock frequency divided by 2 is used to operate the CPU

and peripheral functions.)

Sub clock mode (the sub clock is used to operate the CPU and peripheral functions.)

• Standby mode

Sleep mode (stops the operation clock to the CPU.)

Watch mode (operates the sub clock and watch timer only.)

Time-base timer mode (operates the oscillation clock, sub clock, time-base timer and watch timer only.)

Stop mode (stops the operates the oscillation clock and sub clock.)

• CPU intermittent operation mode

• I/O port

• General-purpose input/output ports (CMOS output)

- 34 ports (products without S-suffix)

- 36 ports (products with S-suffix)

• Sub clock pin (X0A, X1A)

• Yes : (external oscillator used), products without S-suffix

• No : products with S-suffix

• Timer

• Time-base timer, watch timer (products without S-suffix), watchdog timer : 1 channel

• 8/16-bit PPG timer : 8-bit × 4 channels or 16-bit × 2 channels

• 16-bit reload timer : 2 channels

• 16- bit input/output timer

- 16-bit free-run timer : 1 channel

- 16- bit input capture (ICU) : 4 channels

(Continued)

2

MB90960 Series

(Continued)

• LIN-UART (LIN/SCI) : Maximum 2 channels

• Full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transfer

• DTP/External interrupt : 8 channels

• Module for activation of expanded intelligent I/O service (EI²OS) and generation of external interrupt by external

input.

• Delayed interrupt generator module

• Generates interrupt request for task switching.

• 8/10-bit A/D converter : 16 channels

• 8-bit and 10-bit resolution.

• Start by external trigger input.

• Conversion time : 3 µs (frequency, including sampling time at 24 MHz machine clock)

• Program patch function

• Detects address match for 6 address pointers.

• Changeable port input voltage level

• Automotive input level/CMOS Schmitt input level (initial value in single-chip mode is Automotive level).

3

MB90960 Series

■ PRODUCT LINEUP

Part number

MB90F962

MB90F962S

MB90V340E-101

MB90V340E-102

Parameter

Type

Flash memory product

Evaluation product

CPU

F²MC-16LX CPU

PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)

Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)

System clock

Flash memory

64 Kbytes (60 Kbytes + 4 Kbytes Sectors)

ROM

External

RAM capacitance

3 Kbytes

30 Kbytes

Yes

Power supply for

emulator*¹

⎯

Sub clock pin

(X0A, X1A)

Yes

No

Yes

3.5 V to 5.5 V : at normal operation

(not using A/D converter and not doing

flash programming)

Operating

voltage range

5 V ± ±10%

4.0 V to 5.5 V : at normal operation

Operating

temperature range

− 40 °C to + 125°C *²

⎯

Package

LQFP-48P

2 channels

PGA-299C

5 channels

Wide range of baud rate settings using a dedicated reload timer

Special synchronous options for adapting to different synchronous serial protocols

LIN functionality working either as master or slave LIN device

LIN-UART

16 channels

10-bit or 8-bit resolution

Conversion time: Min. 3 µs includes sample time (per one channel)

24 channels

8/10-bit

A/D Converter

2 channels

4 channels

Operation clock frequency: fsys/2¹, fsys/2³, fsys/2⁵(fsys = Machine clock frequency)

Supports External Event Count function

16-bit Reload Timer

16-bit I/O Timer

1 channel

4 channels

Signals an interrupt when overflowing.

Operating clock frequency: fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, fsys/2⁵, fsys/2⁶, fsys/2⁷

(fsys = Machine clock frequency)

4 channels

6 channels

16-bit Input Capture

Maintains I/O timer value by pin input (rising edge, falling edge, or both edge),

and generates interrupt

(Continued)

4

MB90960 Series

(Continued)

Part number

MB90F962

MB90F962S

MB90V340E-101

MB90V340E-102

Parameter

8 channels (16-bit) /

2 channels (16-bit) / 4 channels (8-bit)

8-bit reload counters × 4

8-bit reload registers for

“L” pulse width × 4

16 channels (8-bit)

8-bit reload counters × 16

8-bit reload registers for

“L” pulse width × 16

8-bit reload registers for

“H” pulse width × 16

8-bit reload registers for

“H” pulse width × 4

8/16-bit

PPG timer

Supports 8-bit and 16-bit operation modes.

A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as

8-bit prescaler + 8-bit reload counter.

Operating clock frequency: fsys, fsys/2¹, fsys/2², fsys/2³, fsys/2⁴, or 128 µs

@ fosc = 4 MHz

(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

8 channels

External Interrupts

Can be used rising edge, falling edge, starting up by “H”/“L” level input, external

input,extended intelligent I/O services (EI²OS) and DMA.

Corresponding evaluation

product

MB90V340E-102 MB90V340E-101

⎯

*1 : It is setting of Jumper switch (TOOL V^CC) when emulator (MB2147-01) is used. Please refer to the Emulator

hardware manual for the details.

*2 : If used exceeding T^A= +105°C, be sure to contact Fujitsu for reliability limitations.

5

MB90960 Series

■ PIN ASSIGNMENT

• MB90F962(S)

(TOP VIEW)

(LQFP-48P)

P20

P21

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

27

26

25

AVcc

AVR

P60/AN0

P22/PPGD(C)

P23/PPGF(E)

P24/IN0

P25/IN1

P26/IN2

P27/IN3

X1

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6/PPGC(D)

P67/AN7/PPGE(F)

P80/ADTG/INT12R

P50/AN8

10

11

12

X0

C

Vss

(FPT-48P-M26)

* : MB90F962: X0A, X1A

MB90F962S: P40, P41

6

MB90960 Series

■ PIN DESCRIPTION

Pin No.

Pin name

LQFP-48P*

Circuit type

Function

1

AV^CC

I

VCC power input pin for analog circuit.

Power (Vref+) input pin for A/D converter.

AVR should not exceed VCC.

2

AVR

⎯

P60 to P65

AN0 to AN5

P66, P67

General-purpose I/O ports.

3 to 8

9, 10

H

Analog input pins for A/D converter.

General-purpose I/O ports.

AN6, AN7

Analog input pins for A/D converter.

PPGC (D) ,

PPGE (F)

Output pins for PPG.

P80

General-purpose I/O port.

11

12 to 14

15

ADTG

INT12R

F

H

Trigger input pin for A/D converter.

External interrupt request input pin for INT12R.

General-purpose I/O ports (I/O circuit type of P50 is different

from that of MB90V340E) .

P50 to P52

AN8 to AN10

P53

Analog input pins for A/D converter.

General-purpose I/O port.

AN11

Analog input pin for A/D converter.

Event input pin for reload timer 3.

General-purpose I/O port.

TIN3

P54

AN12

Analog input pin for A/D converter.

Output pin for reload timer 3.

16

H

TOT3

INT8

External interrupt request input pin for INT8.

General-purpose I/O ports.

P55 to P57

AN13 to AN15

Analog input pins for A/D converter.

17 to 19

INT10, INT11,

INT13

External interrupt request input pins for INT10, INT11, INT13.

20

21, 22

23

MD2

MD1, MD0

RST

D

C

Input pin for selecting operation mode.

Input pins for selecting operation mode.

Reset input.

E

24

V^CC

⎯

Power input pin (3.5 V to 5.5 V) .

Power input pin (0 V) .

25

VSS

Capacity pin for stabilizing power supply. It should be connect-

ed to a higher than or equal to 0.1 µF ceramic capacitor.

26

C

I

27

28

X0

X1

Oscillation input pin.

Oscillation output pin.

A

(Continued)

7

MB90960 Series

Pin No.

Pin name

Circuit type

Function

LQFP-48P*

General-purpose I/O ports.

P27 to P24

IN3 to IN0

P23, P22

The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

29 to 32

G

Event input pins for input capture 0 to 3.

General-purpose I/O ports.

The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

33, 34

35, 36

G

PPGF (E) ,

PPGD (C)

Output pins for PPG.

General-purpose I/O ports.

The register can be set to select whether to use a pull-up resistor.

This function is enabled in single-chip mode.

P21, P20

P85

SIN1

P87

General-purpose I/O port.

37

38

K

F

Serial data input pin for LIN-UART1.

General-purpose I/O port.

SCK1

P86

Clock I/O pin for LIN-UART1.

General-purpose I/O port.

39

40

41

F

SOT1

P43

Serial data output pin for LIN-UART1.

General-purpose I/O port.

P42

General-purpose I/O port.

INT9R

P83

External interrupt request input pin for INT9R.

General-purpose I/O port.

42

43

SOT0

TOT2

P84

F

Serial data output pin for LIN-UART0.

Output pin for reload timer 2

General-purpose I/O port.

SCK0

INT15R

P82

Clock I/O pin for LIN-UART0.

External interrupt request input pin for INT15R.

General-purpose I/O port.

SIN0

INT14R

TIN2

Serial data input pin for LIN-UART0.

External interrupt request input pin for INT14R.

Event input pin for reload timer 2.

44

45

K

F

General-purpose I/O port (I/O circuit type of P44 is different from

that of MB90V340E) .

P44

FRCK0

Free-run timer 0 clock input pin.

(Continued)

8

MB90960 Series

(Continued)

Pin No.

Pin name

Circuit type

Function

LQFP-48P*

General-purpose I/O ports.

(products with S-suffix and MB90V340E-101)

P40, P41

F

46, 47

X0A: Oscillation input pin for sub clock

X1A: Oscillation output pin for sub clock

(products without S-suffix and MB90V340E-102)

X0A, X1A

AV^SS

B

I

48

VSS power input pin for analog circuit.

* : FPT-48P-M26

9

MB90960 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

Oscillation circuit

High-speed oscillation feedback

resistor = approx. 1 MΩ

X1

X0

Xout

A

Standby control signal

Oscillation circuit

Low-speed oscillation feedback

resistor = approx. 10 MΩ

X1A

X0A

Xout

B

Standby control signal

CMOS input

R

C

D

CMOS Hysteresis

inputs

• CMOS input

• No Pull-down

R

CMOS Hysteresis

inputs

Pull-down

resistor

CMOS hysteresis input

Pull-up resistor value : approx. 50 kΩ

Pull-up

resistor

E

R

CMOS Hysteresis

inputs

(Continued)

10

MB90960 Series

Type

Circuit

Remarks

• CMOS level output (IOL = 4 mA,

IOH = − 4 mA)

• CMOS hysteresis input (With the

standby-time input shutdown function)

• Automotive input (With the standby-

time input shutdown function)

P-ch

N-ch

Pout

Nout

F

R

CMOS hysteresis input

Automotive input

Standby control for

input shutdown

• CMOS level output (I^OL= 4 mA,

IOH = − 4 mA)

Pull-up control

Pout

Pull-up

resistor

• CMOS hysteresis input (With the

standby-time input shutdown function)

• Automotive input (With the standby-

time input shutdown function)

• Programmable pull-up resistor :

approx. 50 kΩ

P-ch

N-ch

Nout

G

R

CMOS hysteresis input

Automotive input

Standby control for

input shutdown

• CMOS level output (I^OL= 4 mA,

I^OH= − 4 mA)

• CMOS hysteresis input (With the

standby-time input shutdown function)

• Automotive input (With the standby-

time input shutdown function)

• A/D analog input

P-ch

N-ch

Pout

Nout

R

H

CMOS hysteresis input

Automotive input

Standby control for

input shutdown

A/D analog input

(Continued)

11

MB90960 Series

(Continued)

Type

Circuit

Remarks

Power supply input protection circuit

P-ch

N-ch

I

• CMOS level output (I^OL= 4 mA,

IOH = − 4 mA)

• CMOS input (With standby-time input

shutdown function)

• Automotive input (With the standby-

time input shutdown function)

P-ch

N-ch

Pout

Nout

R

K

CMOS input

Automotive input

Standby control for

input shutdown

12

MB90960 Series

■ HANDLING DEVICES

Special care is required for the following when handling the device :

• Preventing latch-up

• Treatment of unused pins

• Using external clock

• Notes on during operation of PLL clock mode

• Power supply pins (V^CC/VSS)

• Pull-up/down resistors

• Crystal oscillator circuit

• Turning-on sequence of power supply to A/D converter and analog inputs

• Connection of unused pins of A/D converter

• Notes on energization

• Stabilization of power supply voltage

• Initialization

• Correspondence with +105 °C or more

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions :

• A voltage higher than VCC or lower than VSS is applied to an input or output pin.

• A voltage higher than the rated voltage is applied between V^CCand VSS.

• The AVCC power supply is applied before the VCC voltage.

Latch-up may increase the power supply current drastically, causing thermal damage to the device.

When used, note that maximum rated voltage is not exceeded.

For the same reason, also be careful not to let the analog power-supply voltage (AV^CC, AVR) exceed the digital

power-supply voltage.

2. Treatment of unused pins

Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage of the

device. Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should

be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above

described connection.

3. Using external clock

To use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open.

MB90960 Series

X0 (X0A)

X1 (X1A)

Open

13

MB90960 Series

4. Notes on during operation of PLL clock mode

On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while

the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its

self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.

5. Power supply pins (VCC/VSS)

• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential

are connected the inside of the device to prevent such malfunctioning as latch-up.

To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,

and to keep the recommended DC characteristics specified as the total output current, be sure to connect the

V^CCand VSS pins to the power supply and ground externally.

• Connect VCC and VSS to the device from the power supply source with lowest possible impedance.

• It is recommended to connect a capacitor of about 0.1 µF as a bypass capacitor between V^CCand VSS in the

vicinity of VCC and VSS pins of the device.

VCC

VSS

VCC

VSS

MB90960

Series

VCC

VSS

VCC

VSS

6. Pull-up/down resistors

The MB90960 series does not support internal pull-up/down resistors (except Port 2 : programmable pull-up

resistors) . Use pull-up/down handling where needed.

7. Crystal oscillator circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass

capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and

make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly

recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for

stabilizing the operation.

8. Turning-on sequence of power supply to A/D converter and analog inputs

Make sure to turn on the A/D converter power supply (AVCC, AVR) and analog inputs (AN0 to AN15) after turning-

on the digital power supply (VCC) . Turn-off the digital power supply after turning off the A/D converter power

supply and analog inputs. In this case, make sure that the voltage does not exceed AVR or AVCC (turning on/off

the analog and digital power supplies simultaneously is acceptable) .

9. Connection of unused pins of A/D converter if A/D converter is not used

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.

14

MB90960 Series

10. Notes on energization

To prevent malfunction of the internal voltage regulator , supply voltage profile while turning on the power supply

should be slower than 50 µs (0.2 V to 2.7 V) .

11. Stabilization of power supply voltage

If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply

voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization

guide lines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the

commercial frequencies (50 Hz/60 Hz) fall within 10% of the standard VCC power supply voltage and the transient

fluctuation rate becomes 0.1 V/ms or less in instantaneous fluctuation for power supply switching.

12. Initialization

Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,

turn on the power again.

13. Correspondence with +105 °C or more

If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations.

15

MB90960 Series

■ BLOCK DIAGRAMS

• MB90V340E-101/V340E-102

X0

X1

RST

X0A*

X1A*

Clock

controller

F²MC-16LX

core

16-bit

I/O timer 0

FRCK0

Input

capture

IN7 to IN0

8 channels

RAM

30 Kbytes

Output

compare

8 channels

OUT7 to OUT0

FRCK1

Prescaler

(5 channels)

16-bit

I/O timer 1

SOT4 to SOT0

SCK4 to SCK0

SIN4 to SIN0

CAN

controller

3 channels

RX2 to RX0

TX2 to TX0

LIN-UART

5 channels

16-bit

reload Timer

4 channels

AVCC

AVSS

AN23 to AN0

TIN3 to TIN0

TOT3 to TOT0

8/10-bit

A/D

converter

24 channels

AVRH

AVRL

ADTG

AD15 to AD00

A23 to A16

ALE

RD

10-bit

D/A converter

2 channels

WRL

WRH

HRQ

External

bus

DA01, DA00

8/16-bit

PPG timer

16/8 channels

HAK

RDY

CLK

PPGF to PPG0

I²C

interface

2 channels

SDA1, SDA0

SCL1, SCL0

INT15 to INT8

(INT15R to INT8R)

INT7 to INT0

DTP/

External

interrupt

DMA

Clock

monitor

CKOT

* : Only for MB90V340E-102

16

MB90960 Series

• MB90F962(S)

X0

X1

RST

X0A*

X1A*

Clock

controller

F²MC-16LX

core

Input

capture

IN0 to IN3

4 channels

16-bit

I/O

timer 0

FRCK0

RAM

3 Kbytes

ROM

64 Kbytes

16-bit

reload

TIN2, TIN3

TOT2, TOT3

timer

2 channels

Prescaler

(2 channels)

SOT0, SOT1

SCK0, SCK1

SIN0, SIN1

LIN-UART

2 channels

AVCC

AVSS

AN15 to AN0

8/10-bit

A/D

converter

16 channels

AVR

ADTG

INT8, INT9R

DTP/

External

interrupt

INT10, INT11

INT12R, INT13

INT14R, INT15R

8/16-bit

PPG timer

4/2 channels

PPGF(E), PPGD(C),

PPGC(D), PPGE(F)

* : Only for MB90F962

17

MB90960 Series

■ MEMORY MAP

MB90V340E-101

MB90V340E-102

MB90F962(S)

FFFFFF^H

FFFFFFH

ROM (FF bank)

ROM (FE bank)

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (F8 bank)

ROM (FF bank)

FF0000H

FEFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FD0000H

FCFFFFH

FC0000H

FBFFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

F90000H

F8FFFFH

F80000H

00FFFFH

010000^H

00FFFFH

ROM (image

of FF bank)

008000H

007FFFH

008000H

007FFFH

Peripheral

007900H

0078FFH

RAM 30 Kbytes

000CFFH

000100H

RAM 3 Kbytes

000100H

0000FFH

0000F0H

0000EFH

000000H

0000EFH

000000H

Peripheral

: Access prohibited

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using

the far specification in the pointer declaration.

For example, an attempt to access 00C000^Haccesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.

The image between FF8000^Hand FFFFFFH is visible in bank 00, while the image between FF0000H and

FF7FFFH is visible only in bank FF.

18

MB90960 Series

■ I/O MAP

Address

Register

Abbreviation Access

Resource name Initial value

000000H,

000001H

Reserved

000002^HPort 2 Data Register

000003H

PDR2

Reserved

R/W

Port 2

XXXXXXXXB

000004^HPort 4 Data Register

000005H Port 5 Data Register

000006H Port 6 Data Register

000007H

PDR4

PDR5

PDR6

R/W

Port 4

Port 5

Port 6

XXXXXXXXB

Reserved

PDR8

000008^HPort 8 Data Register

R/W

Port 8

XXXXXXXXB

000009H,

00000AH

Reserved

00000BH Port 5 Analog Input Enable Register

00000CH Port 6 Analog Input Enable Register

00000DH

ADER5

ADER6

R/W

Port 5, A/D

Port 6, A/D

11111111B

Reserved

00000EH Input Level Select Register 0

00000FH Input Level Select Register 1

ILSR0

ILSR1

R/W

Port 2, 4, 5, 6

Port 8

X000X0XXB

XXXXXXX0B

0000010H,

000011H

Reserved

000012H Port 2 Direction Register

000013H

DDR2

Reserved

R/W

Port 2

00000000B

000014H Port 4 Direction Register

000015H Port 5 Direction Register

000016H Port 6 Direction Register

000017H

DDR4

DDR5

DDR6

R/W

Port 4

Port 5

Port 6

XXX00000B

00000000B

Reserved

DDR8

Reserved

DDRA

000018H Port 8 Direction Register

000019H

R/W

W

Port 8

Port A

000000X0B

00001A^HPort A Direction Register

XXX00XXXB

00001BH

to

Reserved

00001DH

00001E^HPort 2 Pull-up Control Register

00001FH

PUCR2

Reserved

R/W

Port 2

00000000B

(Continued)

19

MB90960 Series

Address

Register

Abbreviation Access Resource name Initial value

000020^HSerial Mode Register 0

000021H Serial Control Register 0

SMR0

SCR0

W, R/W

R/W

00000000B

00001000B

000022H Reception/Transmission Data Register 0 RDR0/TDR0

000023H Serial Status Register 0

Extended Communication Control

SSR0

R, R/W

LIN-UART0

R, W,

R/W

000024H

ECCR0

000000XXB

Register 0

000025H Extended Status Control Register 0

000026H Baud Rate Generator Register 00

000027H Baud Rate Generator Register 01

000028H Serial Mode Register 1

ESCR0

BGR00

BGR01

SMR1

R/W

00000100B

00000000B

00001000B

R/W, R

W, R/W

R/W

000029H Serial Control Register 1

SCR1

00002AH Reception/Transmission Data Register 1 RDR1/TDR1

00002BH Serial Status Register 1

SSR1

R, R/W

LIN-UART1

Extended Communication Control

Register 1

R, W,

R/W

00002CH

ECCR1

000000XXB

00002DH Extended Status Control Register 1

00002EH Baud Rate Generator Register 10

00002FH Baud Rate Generator Register 11

ESCR1

BGR10

BGR11

R/W

00000100B

00000000B

R/W, R

000030H

to

00003AH

Reserved

PACSR1

Reserved

Address Match

Detection 1

00003B^HAddress Detect Control Register 1

R/W

00000000B

00003CH

to

000047H

000048H PPGC Operation Mode Control Register

000049H PPGD Operation Mode Control Register

PPGCC

PPGCD

W, R/W

0X000XX1B

0X000001B

16-bit PPG C/D

16-bit PPG E/F

PPGC/PPGD Count Clock Select

00004AH

Register

PPGCD

R/W

000000X0B

00004BH

Reserved

PPGCE

PPGCF

00004CH PPGE Operation Mode Control Register

00004DH PPGF Operation Mode Control Register

W, R/W

0X000XX1B

0X000001B

PPGE/PPGF Count Clock Select

00004EH

Register

PPGEF

R/W

000000X0B

00004FH

Reserved

(Continued)

20

MB90960 Series

Address

Register

Abbreviation Access

Resource name

Initial value

00000000B

XXX0X0XXB

00000000B

XXXXXXXXB

000050^HInput Capture Control Status 0/1

000051H Input Capture Edge 0/1

ICS01

ICE01

ICS23

ICE23

R/W

R/W, R

R/W

R

Input Capture 0/1

000052H Input Capture Control Status 2/3

000053H Input Capture Edge 2/3

Input Capture 2/3

000054H

to

Reserved

000063H

000064^HTimer Control Status 2

000065H Timer Control Status 2

000066H Timer Control Status 3

000067H Timer Control Status 3

000068H A/D Control Status 0

000069H A/D Control Status 1

00006AH A/D Data Register 0

00006BH A/D Data Register 1

00006CH A/D Converter Setting 0

00006DH A/D Converter Setting 1

00006EH

TMCSR2

TMCSR3

ADCS0

ADCS1

ADCR0

ADCR1

ADSR0

ADSR1

R/W

R/W, W

R

00000000B

XXXX0000B

00000000B

XXXX0000B

000XXXX0B

0000000XB

00000000B

XXXXXX00B

00000000B

16-bit Reload Timer 2

16-bit Reload Timer 3

A/D Converter

ROM Mirror

R

R/W

Reserved

00006FH ROM Mirror Function Select

ROMM

W

XXXXXXX1B

000070H

to

Reserved

00009DH

Address Match

Detection 0

00009E^HAddress Detect Control Register 0

00009FH Delayed Interrupt/Release Register

PACSR0

DIRR

R/W

00000000B

Delayed Interrupt

generation module

XXXXXXX0B

Low-Power

consumption

Control Circuit

Low-power Consumption Mode

0000A0H

LPMCR

CKSCR

W, R/W

R, R/W

00011000B

11111100B

Control Register

Low-Power

consumption

Control Circuit

0000A1H Clock Selection Register

0000A2H

to

Reserved

0000A7H

0000A8^HWatchdog Timer Control Register

0000A9H Time-base Timer Control Register

WDTC

TBTC

R, W

Watchdog Timer

Time-base Timer

XXXXX111B

1XX00100B

(Continued)

W, R/W

21

MB90960 Series

Address

Register

Abbreviation Access

Resource name

Initial value

0000AA^HWatch Timer Control Register

WTC

R, R/W

Watch Timer

1X001000B

0000ABH

to

Reserved

0000ADH

0000AE^HFlash Control Status

FMCS

R, R/W

Flash Memory

000X0000B

0000AFH

Reserved

0000B0^HInterrupt Control Register 00

0000B1H Interrupt Control Register 01

0000B2H Interrupt Control Register 02

0000B3H Interrupt Control Register 03

0000B4H Interrupt Control Register 04

0000B5H Interrupt Control Register 05

0000B6H Interrupt Control Register 06

0000B7H Interrupt Control Register 07

0000B8H Interrupt Control Register 08

0000B9H Interrupt Control Register 09

0000BAH Interrupt Control Register 10

0000BBH Interrupt Control Register 11

0000BCH Interrupt Control Register 12

0000BDH Interrupt Control Register 13

0000BEH Interrupt Control Register 14

0000BFH Interrupt Control Register 15

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

W, R/W

00000111B

Interrupt Control

0000C0H

to

Reserved

0000C9H

0000CAH DTP/External Interrupt Enable 1

0000CBH DTP/External Interrupt Source 1

0000CCH Detection Level Setting 1

ENIR1

EIRR1

ELVR1

EISSR

PSCCR

R/W

W

00000000B

XXXXXXXXB

00000000B

XXXX0000B

External Interrupt 1

PLL

0000CDH Detection Level Setting 1

0000CEH External Interrupt factor Select

0000CFH PLL/Sub clock Control Register

0000D0H

to

Reserved

0000FFH

(Continued)

22

MB90960 Series

Address

Register

Abbreviation

Access

Resource name

Initial value

007900^H

to

Reserved

007917H

007918^HReload Register LC

007919H Reload Register HC

00791AH Reload Register LD

00791BH Reload Register HD

00791CH Reload Register LE

00791DH Reload Register HE

00791EH Reload Register LF

00791FH Reload Register HF

007920H Input Capture 0

007921H Input Capture 0

007922H Input Capture 1

007923H Input Capture 1

007924H Input Capture 2

007925H Input Capture 2

007926H Input Capture 3

007927H Input Capture 3

PRLLC

PRLHC

PRLLD

PRLHD

PRLLE

PRLHE

PRLLF

PRLHF

IPCP0

IPCP1

IPCP2

IPCP3

R/W

R

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

16-bit PPG C/D

16-bit PPG E/F

Input Capture 0/1

Input Capture 2/3

R

007928H

to

Reserved

00793FH

007940^HTimer Data 0

TCDT0

R/W

00000000B

0XXXXXXXB

007941H Timer Data 0

I/O Timer 0

007942H Timer Control Status 0

007943H Timer Control Status 0

TCCSL0

TCCSH0

007944H

to

Reserved

00794BH

00794CH

R/W

XXXXXXXX^B

XXXXXXXXB

XXXXXXXX^B

XXXXXXXXB

16-bit Reload

Timer 2

Timer 2/Reload 2

00794DH

TMR2/TMRLR2

TMR3/TMRLR3

00794EH

16-bit Reload

Timer 3

Timer 3/Reload 3

00794FH

007950H

to

Reserved

0079DFH

(Continued)

23

MB90960 Series

(Continued)

Address

Register

Abbreviation Access

Resource name

Initial value

XXXXXXXX^B

XXXXXXXXB

0079E0H Detect Address Setting 0

0079E1H Detect Address Setting 0

0079E2H Detect Address Setting 0

0079E3H Detect Address Setting 1

0079E4H Detect Address Setting 1

0079E5H Detect Address Setting 1

0079E6H Detect Address Setting 2

0079E7H Detect Address Setting 2

0079E8H Detect Address Setting 2

PADR0

PADR1

PADR2

R/W

Address Match

Detection 0

0079E9H

to

Reserved

0079EFH

0079F0^HDetect Address Setting 3

0079F1H Detect Address Setting 3

0079F2H Detect Address Setting 3

0079F3H Detect Address Setting 4

0079F4H Detect Address Setting 4

0079F5H Detect Address Setting 4

0079F6H Detect Address Setting 5

0079F7H Detect Address Setting 5

0079F8H Detect Address Setting 5

PADR3

PADR4

PADR5

R/W

XXXXXXXXB

Address Match

Detection 1

0079F9H

to

Reserved

007FFFH

Notes : • Initial value of “X” represents unknown value.

• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved

addresses results in reading “X”.

24

MB90960 Series

■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

Interrupt control

Interrupt vector

Number Address

EI²OS

corresponding

register

Interrupt cause

Number

Address

Reset

N

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

FFFFDC^H

FFFFD8^H

FFFFD4^H

FFFFD0H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

FFFF84H

FFFF80H

FFFF7CH

FFFF78H

FFFF74H

FFFF70H

FFFF6CH

FFFF68H

FFFF64H

⎯

INT9 instruction

Exception processing

Reserved

N

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

0000B0H

0000B1H

0000B2H

0000B3H

0000B4H

0000B5H

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

0000BBH

0000BCH

Reserved

N

Reserved

N

Reserved

N

Reserved

N

Reserved

N

Reserved

N

Reserved

N

16-bit reload timer 2

16-bit reload timer 3

Reserved

Y1

N

Reserved

N

PPG C/D

N

PPG E/F

N

Time-base timer

External interrupt 8 to 11

Watch Timer

N

Y1

N

External interrupt 12 to 15

A/D converter

I/O timer 0

Y1

N

Reserved

N

Reserved

N

Input capture 0 to 3

Reserved

Y1

N

LIN-UART 0 reception

LIN-UART 0 transmission

LIN-UART 1 reception

LIN-UART 1 transmission

Y2

Y1

Y2

Y1

0000BDH

(Continued)

25

MB90960 Series

(Continued)

Interrupt control

register

Interrupt vector

Number Address

EI²OS

corresponding

Interrupt cause

Number

Address

Reserved

N

#39

#40

#41

#42

FFFF60^H

FFFF5CH

FFFF58H

FFFF54H

ICR14

0000BEH

Reserved

Flash memory

ICR15

0000BFH

Delayed interrupt generation module

Y1 : Usable

Y2 : Usable, with EI²OS stop function

N

: Unusable

Notes : • The peripheral resources sharing the ICR register have the same interrupt level.

• When 2 peripheral resources share the ICR register, only one can use extended intelligent I/O service

at a time.

• When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O

service, the other one cannot use interrupts.

26

MB90960 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

VCC

AV^CC

AVR

VI

VSS − 0.3 VSS + 6.0

V

Power supply voltage*¹

VCC = AVCC*²

AVCC ≥ AVR*²

Input voltage*¹

Output voltage*¹

*3

VO

Maximum clamp current

I^CLAMP

Σ|ICLAMP|

I^OL

−2.0

⎯

+2.0

40

mA *4

mW

Total Maximum clamp current

“L” level maximum output current

“L” level average output current

“L” level maximum overall output current

“L” level average overall output current

“H” level maximum output current

“H” level average output current

“H” level maximum overall output current

“H” level average overall output current

Power consumption

⎯

15

IOLAV

ΣI^OL

⎯

4

⎯

125

40

ΣIOLAV

IOH

⎯

−15

−4

I^OHAV

ΣIOH

ΣIOHAV

P^D

⎯

−125

−40

300

+105

+125

+150

⎯

−40

−55

°C

Operating temperature

Storage temperature

T^A

°C *5

°C

T^STG

(Continued)

27

MB90960 Series

(Continued)

*1 : This parameter is based on V^SS= AVSS = 0 V.

*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not exceed AVCC when the power is switched on.

*3 : V^Iand VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximum

current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the

VI rating.

*4 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87

*5 : If used exceeding T^A= +105°C, be sure to contact Fujitsu for reliability limitations.

• Use within recommended operating conditions.

• Use at DC voltage (current) .

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting power supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Sample recommended circuits :

• Input/output equivalent circuits

Protective diode

V^CC

Limiting

P-ch

resistance

+B input (0 V to 16 V)

N-ch

R

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

28

MB90960 Series

2. Recommended Conditions

(VSS = AVSS = 0 V)

Remarks

Value

Typ

Parameter

Symbol

Unit

Min

Max

4.0

5.0

5.5

V

Under normal operation

Under normal operation when not using

the A/D converter and not Flash

programming.

V^CC,

AVCC

Power supply voltage

3.5

3.0

5.0

5.5

V

⎯

Maintains RAM data in stop mode

Use a ceramic capacitor or capacitor of

better AC characteristics for the C pin.

Bypass capacitor at the VCC pin should

be greater than this capacitor.

Smooth capacitor

C^S

T^A

0.1

⎯

1.0

µF

−40

⎯

+105

+125

°C

Operating temperature

*

* : If used exceeding T^A= +105 °C, please contact Fujitsu for reliability limitations.

• C Pin Connection Diagram

C

CS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

29

MB90960 Series

3. DC Characteristics

Sym-

(TA = −40 °C to +125 °C*¹, VCC = 5.0 V 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Condition

Unit

Remarks

bol

Min

Typ

Max

Pin inputs if CMOS

hysteresis levels are

selected (except P82,

P85)

⎯

0.8 VCC

⎯

VCC + 0.3

V

V^IHS

P82, P85 inputs if

CMOS input levels are

selected

⎯

0.7 V^CC

0.8 VCC

⎯

VCC + 0.3

V

Input “H”

voltage

Pin inputs if

Automotive input

levels are selected

V^IHA

RST input pin (CMOS

hysteresis)

V^IHR

V^IHM

⎯

0.8 VCC

⎯

VCC + 0.3

V

VCC − 0.3

MD input pin

Pin inputs if CMOS

hysteresis input levels

are selected (except

P82, P85)

⎯

VSS − 0.3

⎯

0.2 VCC

V

V^ILS

P82, P85 inputs if

CMOS input levels are

selected

⎯

V^SS− 0.3

VSS − 0.3

⎯

0.3 VCC

0.5 VCC

V

Input “L”

voltage

Pin inputs if

Automotive input

levels are selected

V^ILA

RST input pin (CMOS

hysteresis)

V^ILR

V^ILM

V^OH

⎯

VSS − 0.3

V^CC− 0.5

⎯

0.2 VCC

VSS + 0.3

⎯

V

MD input pin

Output “H”

voltage

V^CC= 4.5 V,

I^OH= −4.0 mA

Output “L”

voltage

V^CC= 4.5 V,

I^OL= 4.0 mA

V^OL

I^IL

⎯

−1

25

⎯

50

0.4

+ 1

V

Input leak

current

V^CC= 5.5 V,

V^SS< VI < VCC

µA

kΩ

Pull-up

resistance

P20 to P27,

RST

R^UP

⎯

100

Pull-down

resistance

Except Flash memory

devices

R^DOWN

MD2

(Continued)

30

MB90960 Series

(Continued)

(T^A= −40 °C to +125 °C*¹, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Sym-

bol

Parameter

Condition

Unit

Remarks

Min Typ Max

VCC = 5.0 V,

Internal frequency : 24 MHz,

At normal operation.

⎯

35 45 mA MB90F962(S)

50 60 mA MB90F962(S)

12 20 mA MB90F962(S)

0.3 0.8 mA MB90F962(S)

V^CC= 5.0 V,

Internal frequency : 24 MHz,

At writing Flash memory.

ICC

VCC = 5.0 V,

Internal frequency : 24 MHz,

At erasing Flash memory.

VCC = 5.0 V,

Internal frequency : 24 MHz,

At sleep mode.

I^CCS

VCC = 5.0 V,

Internal frequency : 2 MHz,

At main timer mode

I^CTS

VCC = 5.0 V,

Internal frequency : 24 MHz,

At PLL timer mode,

Power supply

current*²

VCC

I^CTSPLL6

⎯

4

7

mA MB90F962(S)

External frequency = 4 MHz

VCC = 5.0 V,

Internal frequency : 8 kHz,

At sub clock operation mode,

TA = + 25°C

ICCL

40 100 µA MB90F962

VCC = 5.0 V,

Internal frequency : 8 kHz,

At sub clock sleep mode,

T^A= + 25°C

I^CCLS

10 50

µA MB90F962

VCC = 5.0 V,

Internal frequency : 8 kHz,

At watch mode,

T^A= + 25°C

I^CCT

⎯

8

5

30

25

µA MB90F962

VCC = 5.0 V,

At stop mode, T^A= + 25°C

ICCH

µA MB90F962(S)

Other

than

AVCC,

AVSS,

AVR,

VCC,

Input capacity

C^IN

⎯

5

15

pF

VSS, C

*1 : If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

*2 : The power supply current is measured with an external clock.

31

MB90960 Series

4. AC Characteristics

(1) Clock Timing

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Unit

Remarks

Min

Typ

Max

1/2 when PLL stops,

When using an oscillation circuit

3

16

PLL × 1,

4

3

4

16

12

8

When using an oscillation circuit

PLL × 2,

When using an oscillation circuit

X0, X1

⎯

MHz

PLL × 3,

When using an oscillation circuit

PLL × 4,

When using an oscillation circuit

6

PLL × 6,

When using an oscillation circuit

4

f^C

Clock frequency

1/2 when PLL stops,

When using an external clock

24

20

12

8

PLL × 1,

When using an external clock

PLL × 2,

When using an external clock

X0, X1

⎯

MHz

PLL × 3,

When using an external clock

PLL × 4,

When using an external clock

6

PLL × 6,

When using an external clock

4

f^CL

X0A, X1A

X0, X1

⎯

32.768 100

kHz

62.5

⎯

333

⎯

ns When using an oscillation circuit

ns When using an external clock

µs When using sub clock

t^CYL

Clock cycle time

X0, X1 41.67

X0A, X1A 10

tCYLL

30.5

⎯

PWH, PWL

P^WHL, PWLL

X0

10

5

⎯

ns

Input clock pulse width

Duty ratio is about 30% to 70%.

µs

X0A

15.2

⎯

Input clock rise and fall

time

tCR, tCF

X0

⎯

5

ns When using external clock

f^CP

fCPL

t^CP

⎯

1.5

⎯

24

50

MHz When using main clock

kHz When using sub clock

ns When using main clock

µs When using sub clock

Internal operating clock

frequency(machineclock)

8.192

⎯

41.67

20

666

⎯

Internal operating clock

cycle time (machine clock)

tCPL

122.1

*: If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

32

MB90960 Series

• Clock Timing

t

CYL

0.8 VCC

0.2 VCC

X0

P

WH

P

WL

t

CF

tCR

t

CYLL

0.8 VCC

0.2 VCC

X0A

P

WHL

P

WLL

t

CF

tCR

33

MB90960 Series

• Guaranteed PLL Operation Range

Guaranteed operation range

Guaranteed PLL operation range (CS2=1)

5.5

4.5

Guaranteed A/D converter

operation range

3.5

Guaranteed PLL operation range (CS2=0)

1.5

4

8

20

24

Machine clock fCP (MHz)

Guaranteed operation range of MB90960 series

• CS2 (bit 0 in PSCCR register) = 0

x4 (CS=011)

x3 (CS=010)

Guaranteed oscillation frequency range

x1 (CS=000)

x2 (CS=001)

20

16

12

x1/2 (PLL off)

8

6

4

1.5

4

6

8

10 12

16

20

24

3

External clock fC (MHz)*

• CS2 (bit 0 in PSCCR register) = 1

x6 (CS=110)

x4 (CS=101)

x2 (CS=100)

24

Guaranteed oscillation frequency range

16

12

8

x1/2 (PLL off)

4

1.5

4

6

8

10 12

16

20

24

3

External clock f

C

(MHz)*

* : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.

External clock frequency and Machine clock frequency

34

MB90960 Series

(2) Reset Standby Input

Parameter Symbol Pin

Reset input

(T^A= −40 °C to +125 °C*¹, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Unit

Remarks

Min

Max

⎯

500

ns Under normal operation

ns In stop mode

t^RSTL

RST Oscillation time of oscillator*²+ 100 µs

⎯

time

100

⎯

µs In time-base timer mode

*1: If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators,

the oscillation time is between hundreds of µs and several ms. With an external clock, the oscillation time is 0 ms.

• Under normal operation :

tRSTL

RST

0.2 VCC

• In stop mode :

tRSTL

RST

0.2 VCC

90% of

amplitude

X0

Internal operation

clock

100 µs

Oscillation time

of oscillator

Oscillation stabilization

waiting time

Instruction execution

Internal reset

35

MB90960 Series

(3) Power-on Reset

(T^A= −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Remarks

Min

0.05

1

Max

30

Power on rise time

Power off time

t^R

VCC

ms

⎯

t^OFF

⎯

ms Due to repetitive operation

*: If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

tR

2.7 V

V

CC

0.2 V

tOFF

Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you

start up smoothly by restraining voltages when changing the power supply voltage during operation, as

shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within

1 V/s, you can operate while using the PLL clock.

VCC

We recommend a rise of

50 mV/ms maximum.

3 V

Holds RAM data

VSS

36

MB90960 Series

(4) LIN-UART0/1

• Bit setting: ESCR0/1:SCES = 0, ECCR0/1:SCDE = 0

(T^A= −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t^SCYC

t^SLOVI

SCK0, SCK1

5 t^CP

⎯

ns

SCK0, SCK1,

SOT0, SOT1

SCK ↓ → SOT delay time

−50

tCP + 80

0

+50

⎯

Internal shift clock

mode output pins are

CL = 80 pF + 1 TTL.

SCK0, SCK1,

SIN0, SIN1

Valid SIN → SCK ↑

tIVSHI

ns

SCK0, SCK1,

SIN0, SIN1

SCK ↑ → Valid SIN hold time

t^SHIXI

⎯

Serial clock “L” pulse width

Serial clock “H” pulse width

t^SHSL

t^SLSH

SCK0, SCK1

3 t^CP- tR

tCP + 10

⎯

ns

SCK0, SCK1,

SOT0, SOT1

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

tSLOVE

t^IVSHE

t^SHIXE

⎯

30

2 tCP + 60 ns

External shift clock

mode output pins are

CL = 80 pF + 1 TTL.

SCK0, SCK1,

SIN0, SIN1

⎯

ns

SCK0, SCK1,

SIN0, SIN1

SCK ↑ → Valid SIN hold time

tCP + 30

SCK fall time

SCK rise time

tF

SCK0, SCK1

⎯

10

ns

t^R

*: If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

Notes : • AC characteristic in CLK synchronized mode.

• CL is load capacity value of pins when testing.

• tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.

• Internal Shift Clock Mode

t

SCYC

2.4 V

SCK

SOT

0.8 V

t

SLOVI

2.4 V

0.8 V

t

IVSHI

tSHIXI

V

IH

IL

V

IH

IL

SIN

37

MB90960 Series

• External Shift Clock Mode

t

SLSH

t

SHSL

VIH

SCK

V

IL

VIL

t

SLOVE

tF

t

R

2.4 V

0.8 V

SOT

SIN

t

IVSHE

t

SHIXE

V

IH

IL

V

IH

IL

V

• Bit setting: ESCR0/1:SCES = 1, ECCR0/1:SCDE = 0

(T^A= −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t^SCYC

SCK0, SCK1

5 t^CP

⎯

ns

SCK0, SCK1,

SOT0, SOT1

SCK ↑ → SOT delay time

t^SHOVI

−50

tCP + 80

0

+50

⎯

Internal shift clock

mode output pins are

CL = 80 pF + 1 TTL.

SCK0, SCK1,

SIN0, SIN1

Valid SIN → SCK ↓

t^IVSLI

t^SLIXI

ns

SCK0, SCK1,

SIN0, SIN1

SCK ↓ → Valid SIN hold time

⎯

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

SCK0, SCK1

3 t^CP- tR

tCP + 10

⎯

ns

SCK0, SCK1,

SOT0, SOT1

SCK ↑ → SOT delay time

Valid SIN → SCK ↓

t^SHOVE

tIVSLE

tSLIXE

⎯

30

2 tCP + 60

ns

External shift clock

mode output pins are

CL = 80 pF + 1 TTL.

SCK0, SCK1,

SIN0, SIN1

⎯

SCK0, SCK1,

SIN0, SIN1

SCK ↓ → Valid SIN hold time

tCP + 30

SCK fall time

SCK rise time

tF

SCK0, SCK1

⎯

10

ns

tR

* : If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

38

MB90960 Series

• Internal Shift Clock Mode

t

SCYC

2.4 V

SCK

0.8 V

tSHOVI

2.4 V

0.8 V

SOT

SIN

t

IVSLI

t

SLIXI

V

IH

IL

V

IH

IL

• External Shift Clock Mode

t

SHSL

t

SLSH

V

IH

V

IH

SCK

V

IL

V

IL

tSHOVE

t

R

tF

2.4 V

0.8 V

SOT

SIN

tIVSLE

t

SLIXE

V

IH

IL

V

IH

IL

39

MB90960 Series

• Bit setting: ESCR0/1:SCES = 0, ECCR0/1:SCDE = 1

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t^SCYC

SCK0,SCK1

5 t^CP

⎯

ns

SCK0,SCK1

SOT0,SOT1

SCK ↑ → SOT delay time

t^SHOVI

−50

+50

⎯

SCK0,SCK1 Internal clock operation

SIN0,SIN1 output pins are

Valid SIN → SCK ↓

t^IVSLI

t^SLIXI

t^SOVLI

tCP + 80

0

ns

C = 80 pF + 1 TTL.

L

SCK0,SCK1

SIN0,SIN1

SCK ↓ → Valid SIN hold time

SOT → SCK ↓ delay time

⎯

SCK0,SCK1

SOT0,SOT1

3 tCP − 70

⎯

* : If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

Note : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP.

t

SCYC

2.4 V

SCK

SOT

0.8 V

t

SHOVI

t

SOVLI

2.4 V

0.8 V

2.4 V

0.8 V

t

IVSLI

tSLIXI

V

IH

IL

V

IH

IL

SIN

• Bit setting: ESCR0/1:SCES = 1, ECCR0/1:SCDE = 1

(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

Serial clock cycle time

t^SCYC

t^SLOVI

SCK0,SCK1

5 t^CP

⎯

ns

SCK0,SCK1

SOT0,SOT1

SCK ↓ → SOT delay time

−50

tCP + 80

0

+50

⎯

SCK0,SCK1 Internalclockoperation

SIN0,SIN1 output pins are

Valid SIN → SCK ↑

t^IVSHI

t^SHIXI

t^SOVHI

ns

C = 80 pF + 1 TTL.

L

SCK0,SCK1

SIN0,SIN1

SCK ↑ → Valid SIN hold time

SOT → SCK ↑ delay time

⎯

SCK0,SCK1

SOT0,SOT1

3 tCP − 70

⎯

* : If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

40

MB90960 Series

Note : t^CPis the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP.

tSCYC

2.4 V

SCK

SOT

0.8 V

tSLOVI

tSOVHI

2.4 V

0.8 V

2.4 V

0.8 V

tIVSHI

tSHIXI

VIH

VIL

VIH

VIL

SIN

(5) Trigger Input Timing

Parameter

(T^A= −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

Value

Symbol

Condition

Unit

Min

200

Max

⎯

INT8, INT9R

INT10, INT11

INT12R, INT13

INT14R, INT15R

⎯

ns

t^TRGH

tTRGL

Input pulse width

ADTG

t^CP+ 200

⎯

* : If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.

V

IH

VIH

INT8, INT9R

INT10, INT11

INT12R, INT13

INT14R, INT15R

ADTG

V

IL

VIL

t

TRGH

t

TRGL

41

MB90960 Series

(6) Timer Related Resource Input Timing

(T^A= −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

t^TIWH

t^TIWL

TIN2, TIN3

IN0 to IN3

Input pulse width

⎯

4 tCP

⎯

ns

* : If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

Note : t^CPis internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”.

VIH

VIL

TIN2, TIN3

IN0 to IN3

tTIWH

tTIWL

(7) Timer Related Resource Output Timing

(T^A= –40°C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)

Value

Parameter

Symbol

Condition

Unit

Min

Max

TOT2, TOT3

PPGC to PPGF

CLK ↑ → T^OUTchange time

tTO

⎯

30

⎯

ns

* : If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

2.4 V

CLK

2.4 V

TOT2, TOT3

PPGC to PPGF

0.8 V

tTO

42

MB90960 Series

5. A/D Converter

(T

Parameter

Resolution

A

= −40 °C to +125 °C*¹, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

Value

Symbol

Unit

Remarks

Min

⎯

Typ

⎯

Max

10

⎯

bit

Total error

⎯

± 3.0

± 2.5

LSB

Nonlinearity error

⎯

Differential

nonlinearity error

⎯

± 1.9

LSB

Zero reading voltage

V^OT

V^FST

AN0 to AN15 AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB

AN0 to AN15 AVR − 3.5 AVR − 1.5 AVR + 0.5 LSB

1.0

Full scale reading

voltage

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AV^CC< 4.5 V

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AV^CC< 4.5 V

Compare time

Sampling time

⎯

16500

µs

2.0

0.5

1.2

⎯

µs

∞

Analog port input

current

I^AIN

V^AIN

⎯

AN0 to AN15

AVR

−0.3

AVSS

⎯

+0.3

AVR

AVCC

µA

Analog input

voltage

V

Reference

voltage

AV^SS+ 2.7

V

IA

I^AH

I^R

AVCC

AVR

⎯

3.5

⎯

7.5

5

mA

Power supply current

µA *2

µA

600

⎯

900

5

Reference

voltage supply current

I^RH

µA *2

Offset between

input channels

⎯

AN0 to AN15

⎯

4

LSB

*1 : If used exceeding T^A= + 105 °C, please contact Fujitsu for reliability limitations.

*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .

(Continued)

43

MB90960 Series

• About the external impedance of analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion precision.

• Analog input circuit model

R

Comparator

Analog input

C

During sampling : ON

Part number

Analog input

R

C

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AV^CC< 4.5 V

4.5 V ≤ AV^CC≤ 5.5 V

4.0 V ≤ AV^CC< 4.5 V

2.0 kΩ (Max)

8.2 kΩ (Max)

2.0 kΩ (Max)

8.2 kΩ (Max)

16.0 pF (Max)

14.4 pF (Max)

MB90F962(S)

MB90V340E-101/V340-102

Note : The values are reference values.

Use the device with external circuits of the following output impedance for analog inputs:

• Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AV^CC≤ 5.5 V,

sampling period = 0.5 µs)

• If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors

an on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high

as internal capacitor.

• If the output impedance of an external circuit is too high, the sampling period for the analog voltage may be

insufficient.

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

(Continued)

44

MB90960 Series

(Continued)

• The relationship between external impedance and minimum sampling time

• At 4.5 V ≤ AVCC ≤ 5.5 V

(External impedance = 0 kΩ to 20 kΩ)

(External impedance = 0 kΩ to 100 kΩ)

MB90V340E-101/V340-102

20

100

18

16

14

12

10

8

90

80

MB90F962(S)

70

60

50

40

30

20

6

4

2

0

10

0

1

2

3

4

5

6

7

8

0

5

10

15

20

25

30

35

Minimum sampling time [µs]

• At 4.0 V ≤ AV^CC< 4.5 V

(External impedance = 0 kΩ to 20 kΩ)

(External impedance = 0 kΩ to 100 kΩ)

MB90V340E-101/V340-102

20

18

16

14

12

10

8

100

90

80

70

60

50

40

30

20

MB90F962(S)

6

4

10

0

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [µs]

• About errors

As | AVR − AV^SS| becomes smaller, values of relative errors grow larger.

45

MB90960 Series

6. Definition of A/D Converter Terms

Resolution

: Analog variation that is recognized by an A/D converter.

Non linearity

error

: Deviation between a line across zero-transition line ( “00 0000 0000^B” ← → “00 0000 0001B” )

and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion

characteristics.

Differential

linearity error

: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

Total error

: Difference between an actual value and an theoretical value. A total error includes zero

transition error, full-scale transition error, and linear error.

Total error

3FFH

1.5 LSB

3FEH

3FDH

Actual conversion

characteristics

{1 LSB × (N − 1) + 0.5 LSB}

004H

003H

002H

001H

V^NT

(Actually-measured value)

Actual conversion

characteristics

Ideal characteristics

0.5 LSB

AVSS

AVR

Analog input

V^NT− {1 LSB × (N − 1) + 0.5 LSB}

[LSB]

Total error of digital output “N” =

1 LSB

AVR − AV^SS

1 LSB (Ideal value) =

[V]

1024

VOT (Ideal value) = AVSS + 0.5 LSB [V]

VFST (Ideal value) = AVR − 1.5 LSB [V]

V^NT: A voltage at which digital output transits from (N − 1) H to NH.

(Continued)

46

MB90960 Series

(Continued)

Non linearity error

Differential linearity error

Ideal

characteristics

3FF

3FE

3FD

H

Actual conversion

characteristics

(N + 1)

H

Actual conversion

characteristics

{1 LSB × (N − 1)

+ V^OT

}

V

FST (actual

measurement

value)

N

V

NT (actual

measurement value)

004

003

002

001

H

V

(N + 1) T

(actual measurement

Actual conversion

characteristics

(N − 1)

(N − 2)

value)

V

NT

(actual measurement value)

Ideal characteristics

Actual conversion

characteristics

V

OT (actual measurement value)

Analog input

AVSS

AVR

AVSS

AVR

Analog input

V^NT− {1 LSB × (N − 1) + VOT}

[LSB]

Non linearity error of digital output N =

1 LSB

V (^N+1) T − VNT

−1 LSB [LSB]

1 LSB

Differential linearity error of digital output N =

1 LSB =

VFST − VOT

[V]

1022

V^OT: Voltage at which digital output transits from “000H” to “001H.”

VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”

47

MB90960 Series

7. Flash Memory Program/Erase Characteristics

Value

Typ

Parameter

Conditions

Unit

Remarks

Min

Max

Excludes programming

prior to erasure

Sector erase time (60 Kbytes)

Sector erase time (4 Kbytes)

Byte programming time

⎯

1

15

s

T^A= +25 °C

V^CC= 5.0 V

Excludes programming

prior to erasure

⎯

0.2

21

0.5

Except for the overhead

time of the system level

6100

μs

Machine clock frequency f^CPat

Flash programming/erasing

V^CC= 5.0 V

⎯

10000

20

⎯

24

⎯

MHz

cycle

year

Program/Erase cycle

⎯

Flash memory data

retention time

Average

T^A= +85 °C

*

* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature

measurements into normalized value at +85 °C) .

48

MB90960 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F962PMT

48-pin plastic LQFP

FPT-48P-M26

7 mm ❑, 0.50 mm pitch

Flash Memory Product

(64Kbytes)

MB90F962SPMT

MB90V340E-101

MB90V340E-102

299-pin ceramic PGA

PGA-299C-A01

Evaluation product

49

MB90960 Series

■ PACKAGE DIMENSION

48-pin plastic LQFP

Lead pitch

0.50 mm

7 × 7 mm

Package width ×

package length

Lead shape

Sealing method

Mounting height

Weight

Gullwing

Plastic mold

1.70 mm MAX

0.17 g

Code

(Reference)

P-LFQFP48-7×7-0.50

(FPT-48P-M26)

48-pin plastic LQFP

(FPT-48P-M26)

Note 1) * : These dimensions include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

9.00 0.20(.354 .008)SQ

+0.40

7.00 ^–0.10.276 ^–⁺^.^.⁰⁰⁰¹⁴⁶SQ

0.145 0.055

(.006 .002)

*

36

25

37

24

Details of "A" part

0.08(.003)

1.50 ⁺^–0⁰^.^.¹²⁰⁰

(Mounting height)

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

INDEX

48

13

0.10 0.10

(.004 .004)

(Stand off)

"A"

0˚~8˚

1

12

LEAD No.

0.50(.020)

0.25(.010)

0.20 0.05

M

0.08(.003)

(.008 .002)

0.60 0.15

(.024 .006)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2003 FUJITSU LIMITED F48040S-c-2-2

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html

50

MB90960 Series

The information for microcontroller supports is shown in the following homepage.

http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

The company names and brand names herein are the trademarks or

registered trademarks of their respective owners.

Edited

Business Promotion Dept.

F0703


型号：	MB90F962PMT
厂家：	FUJITSU
描述：	16-bit Microcontroller 16位微控制器微控制器
文件：	总51页 (文件大小：781K)
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MB90F962PMT [FUJITSU]

相关型号：

MB90F962S

MB90F962SPMCR-GE1

MB90F962SPMT

MB90F962SPMT

MB90F967SPMT

MB90F983

MB90F983PMC1

MB90F983PMC1

MB90M405

MB90M405_05

MB90M407

MB90M407A