MB90F967SPMT [FUJITSU]
Microcontroller, 16-Bit, FLASH, 24MHz, CMOS, PQFP48, 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48;型号: | MB90F967SPMT |
厂家: | FUJITSU |
描述: | Microcontroller, 16-Bit, FLASH, 24MHz, CMOS, PQFP48, 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48 时钟 微控制器 外围集成电路 |
文件: | 总60页 (文件大小:1876K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13749-2E
16-bit Microcontroller
CMOS
F2MC-16LX MB90960 Series
MB90F962(S), MB90F967(S),
MB90V340E-101/102/103/104
■ DESCRIPTION
The MB90960-series is a 16-bit general-purpose microcontroller. Fujitsu Microelectronics now offers on-chip
Flash-ROM program memory up to 64 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates
a major advantage in terms of EMI and power consumption.
The unit features a 4 channel input capture unit, 1 channel 16-bit free-run timer, 2-channel LIN-UART, and
16-channel 8/10-bit A/D converter as the peripheral resource.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplying circuit
• Machine clock (PLL clock) selectable from frequency division by 2 of oscillation clock or 1 to 6-multiplied
oscillation clock (4 MHz to 24 MHz when oscillation clock is 4 MHz) .
• Sub clock operation : Up to 50 kHz (devices without S-suffix only)
• Minimum instruction execution time : 42 ns (4 MHz oscillation clock and 6-multiplied PLL clock) .
• Clock supervisor (MB90F967 (S) only)
• Main clock or sub clock is monitored independently
(Continued)
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in
system development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2007-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.8
MB90960 Series
• Instruction system optimized controllers
• 16 Mbytes CPU memory space : Internal 24-bit addressing
• Various data types (bit, byte, word, and long word)
• Various addressing modes (23 types)
• Enhanced signed instructions of multiplication/division and RETI
• Enhanced high-accuracy operations by 32-bit accumulator
• Instruction system for high-level language (C language) / multitask
• System stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
• Higher execution speed
• 4-byte instruction queue
• Powerful interrupt function
• Powerful interrupt function with 8 levels and 34 factors
• Corresponds to 8-channel external interrupt
• CPU-independent automatic data transfer function
• Expanded intelligent I/O service function (EI2OS) : 16 channels
• Low-power consumption mode
• Clock mode
PLL clock mode (a PLL clock that is a multiple of the oscillation clock is used to operate the CPU and peripheral
functions.)
Main clock mode (the main clock, with the oscillation clock frequency divided by 2 is used to operate the CPU
and peripheral functions.)
Sub clock mode (the sub clock is used to operate the CPU and peripheral functions.)
• Standby mode
Sleep mode (stops the operation clock to the CPU.)
Watch mode (operates the sub clock and watch timer only.)
Time-base timer mode (operates the oscillation clock, sub clock, time-base timer and watch timer only.)
Stop mode (stops the operates the oscillation clock and sub clock.)
• CPU intermittent operation mode
• I/O port
• General-purpose input/output ports (CMOS output)
- 34 ports (products without S-suffix)
- 36 ports (products with S-suffix)
• Sub clock pin (X0A, X1A)
• Yes : (external oscillator used), products without S-suffix
• No : products with S-suffix
• Timer
• Time-base timer, watch timer (products without S-suffix), watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 4 channels or 16-bit × 2 channels
• 16-bit reload timer : 2 channels
• 16- bit input/output timer
- 16-bit free-run timer : 1 channel
- 16-bit input capture (ICU) : 4 channels
(Continued)
2
DS07-13749-2E
MB90960 Series
(Continued)
• LIN-UART : 2 channels
• Full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transfer
• DTP/External interrupt : 8 channels
• Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external
input.
• Delayed interrupt generator module
• Generates interrupt request for task switching.
• 8/10-bit A/D converter : 16 channels
• 8-bit and 10-bit resolution.
• Start by external trigger input.
• Conversion time : 3 µs (frequency, including sampling time at 24 MHz machine clock)
• Address match detection (program patch) function
• Detects address match for 6 address pointers.
• Changeable port input voltage level
• Automotive input level/CMOS Schmitt input level (initial value in single-chip mode is Automotive level).
DS07-13749-2E
3
MB90960 Series
■ PRODUCT LINEUP
• Product lineup 1
Part number
MB90F962
MB90F962S
MB90V340E-101
MB90V340E-102
Parameter
Type
Flash memory product
Evaluation product
CPU
F2MC-16LX CPU
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)
System clock
Sub clock pin
(X0A, X1A)
Yes
No
No
Yes
Clock supervisor
Flash memory
64 Kbytes (60 Kbytes + 4 Kbytes Sectors)
ROM
External
RAM capacitance
Package
3 Kbytes
30 Kbytes
PGA-299C
LQFP-48P
Power supply for
emulator*1
⎯
Yes
3.5 V to 5.5 V : at normal operation
(not using A/D converter and not doing
flash programming)
Operating
voltage range
5 V ± ±10%
4.0 V to 5.5 V : at normal operation
Operating
temperature range
− 40 °C to + 125°C *2
⎯
2 channels
5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
LIN-UART
16 channels
10-bit or 8-bit resolution
Conversion time: Min. 3 µs includes sample time (per one channel)
24 channels
8/10-bit
A/D Converter
2 channels
4 channels
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function
16-bit Reload Timer
16-bit Free-run Timer
16-bit Input Capture
1 channel
2 channels
Signals an interrupt when overflowing.
Operating clock frequency: fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock frequency)
4 channels
8 channels
Maintains 16-bit free-run timer value by pin input (rising edge, falling edge, or both
edge), and generates interrupt
(Continued)
4
DS07-13749-2E
MB90960 Series
(Continued)
Part number
MB90F962
MB90F962S
MB90V340E-101
MB90V340E-102
Parameter
8 channels (16-bit) /
2 channels (16-bit) / 4 channels (8-bit)
8-bit reload counters × 4
8-bit reload registers for
“L” pulse width × 4
16 channels (8-bit)
8-bit reload counters × 16
8-bit reload registers for
“L” pulse width × 16
8-bit reload registers for
“H” pulse width × 16
8-bit reload registers for
“H” pulse width × 4
8/16-bit
PPG timer
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-
bit prescaler + 8-bit reload counter.
Operating clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24, or 128 µs
@ fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
8 channels
16 channels
External Interrupts
Can be used rising edge, falling edge, starting up by “H”/“L” level input, external
input,extended intelligent I/O services (EI2OS) .
Corresponding
evaluation
product
MB90V340E-102 MB90V340E-101
⎯
*1 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01-E) is used. Please refer to the Emulator
operation manual for the details.
*2 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
DS07-13749-2E
5
MB90960 Series
• Product lineup 2
Part number
MB90F967
MB90F967S
MB90V340E-103
MB90V340E-104
Parameter
Type
Flash memory product
Evaluation product
CPU
F2MC-16LX CPU
PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops)
System clock
Clock supervisor
ROM
Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6)
Yes
Flash memory
64 Kbytes (60 Kbytes + 4 Kbytes Sectors)
External
RAM capacitance
3 Kbytes
30 Kbytes
Yes
Power supply for
emulator*1
⎯
Sub clock pin
(X0A, X1A)
Yes
No
Yes
3.5 V to 5.5 V : at normal operation
(not using A/D converter and not doing
flash programming)
Operating
voltage range
5 V ± ±10%
4.0 V to 5.5 V : at normal operation
Operating
temperature range
− 40 °C to + 125°C *2
⎯
Package
LQFP-48P
2 channels
PGA-299C
5 channels
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
LIN-UART
16 channels
10-bit or 8-bit resolution
Conversion time: Min. 3 µs includes sample time (per one channel)
24 channels
8/10-bit
A/D Converter
2 channels
4 channels
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency)
Supports External Event Count function
16-bit Reload Timer
16-bit Free-run Timer
16-bit Input Capture
1 channel
2 channels
Signals an interrupt when overflowing.
Operating clock frequency: fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = Machine clock frequency)
4 channels
8 channels
Maintains 16-bit free-run timer value by pin input (rising edge, falling edge, or both
edge), and generates interrupt
(Continued)
6
DS07-13749-2E
MB90960 Series
(Continued)
Part number
MB90F967
MB90F967S
MB90V340E-103
MB90V340E-104
Parameter
8 channels (16-bit) /
2 channels (16-bit) / 4 channels (8-bit)
8-bit reload counters × 4
8-bit reload registers for
“L” pulse width × 4
16 channels (8-bit)
8-bit reload counters × 16
8-bit reload registers for
“L” pulse width × 16
8-bit reload registers for
“H” pulse width × 16
8-bit reload registers for
“H” pulse width × 4
8/16-bit
PPG timer
Supports 8-bit and 16-bit operation modes.
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler + 8-bit reload counter.
Operating clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24, or 128 µs
@ fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
8 channels
External Interrupts
Can be used rising edge, falling edge, starting up by “H”/“L” level input, external
input,extended intelligent I/O services (EI2OS) and DMA.
Corresponding evalua-
tion
product
MB90V340E-104
MB90V340E-103
⎯
*1 : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01-E) is used. Please refer to the Emulator
operation manual for the details.
*2 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
DS07-13749-2E
7
MB90960 Series
■ PIN ASSIGNMENT
• MB90F962 (S) /MB90F967 (S)
(TOP VIEW)
(LQFP-48P)
P20
P21
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
AVcc
AVR
P60/AN0
P22/PPGD(C)
P23/PPGF(E)
P24/IN0
P25/IN1
P26/IN2
P27/IN3
X1
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6/PPGC(D)
P67/AN7/PPGE(F)
P80/ADTG/INT12R
P50/AN8
10
11
12
X0
C
Vss
(FPT-48P-M26)
* : MB90F962/MB90F967: X0A, X1A
MB90F962S/MB90F967S: P40, P41
8
DS07-13749-2E
MB90960 Series
■ PIN DESCRIPTION
Pin No.
Pin name
LQFP-48P*
Circuit type
Function
1
AVCC
I
VCC power input pin for analog circuit.
Power (Vref+) input pin for A/D converter.
AVR should not exceed VCC.
2
AVR
⎯
P60 to P65
AN0 to AN5
P66, P67
General-purpose I/O ports.
3 to 8
9, 10
H
H
Analog input pins for A/D converter.
General-purpose I/O ports.
AN6, AN7
Analog input pins for A/D converter.
PPGC (D) ,
PPGE (F)
Output pins for PPG.
P80
General-purpose I/O port.
11
12 to 14
15
ADTG
INT12R
F
H
H
Trigger input pin for A/D converter.
External interrupt request input pin for INT12R.
General-purpose I/O ports (I/O circuit type of P50 is different
from that of MB90V340E) .
P50 to P52
AN8 to AN10
P53
Analog input pins for A/D converter.
General-purpose I/O port.
AN11
Analog input pin for A/D converter.
Event input pin for reload timer 3.
General-purpose I/O port.
TIN3
P54
AN12
Analog input pin for A/D converter.
Output pin for reload timer 3.
16
H
H
TOT3
INT8
External interrupt request input pin for INT8.
General-purpose I/O ports.
P55 to P57
AN13 to AN15
Analog input pins for A/D converter.
17 to 19
INT10, INT11,
INT13
External interrupt request input pins for INT10, INT11, INT13.
20
21, 22
23
MD2
MD1, MD0
RST
D
C
Input pin for selecting operation mode.
Input pins for selecting operation mode.
Reset input.
E
24
VCC
⎯
⎯
Power input pin (3.5 V to 5.5 V) .
Power input pin (0 V) .
25
VSS
Capacity pin for stabilizing power supply. It should be connect-
ed to a higher than or equal to 0.1 µF ceramic capacitor.
26
C
I
27
28
X0
X1
Oscillation input pin.
Oscillation output pin.
A
(Continued)
DS07-13749-2E
9
MB90960 Series
Pin No.
Pin name
Circuit type
Function
LQFP-48P*
General-purpose I/O ports.
P27 to P24
IN3 to IN0
P23, P22
The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
29 to 32
G
Event input pins for input capture 0 to 3.
General-purpose I/O ports.
The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
33, 34
35, 36
G
G
PPGF (E) ,
PPGD (C)
Output pins for PPG.
General-purpose I/O ports.
The register can be set to select whether to use a pull-up resistor.
This function is enabled in single-chip mode.
P21, P20
P85
SIN1
P87
General-purpose I/O port.
37
38
K
F
Serial data input pin for LIN-UART1.
General-purpose I/O port.
SCK1
P86
Clock I/O pin for LIN-UART1.
General-purpose I/O port.
39
40
41
F
F
F
SOT1
P43
Serial data output pin for LIN-UART1.
General-purpose I/O port.
P42
General-purpose I/O port.
INT9R
P83
External interrupt request input pin for INT9R.
General-purpose I/O port.
42
43
SOT0
TOT2
P84
F
F
Serial data output pin for LIN-UART0.
Output pin for reload timer 2
General-purpose I/O port.
SCK0
INT15R
P82
Clock I/O pin for LIN-UART0.
External interrupt request input pin for INT15R.
General-purpose I/O port.
SIN0
INT14R
TIN2
Serial data input pin for LIN-UART0.
External interrupt request input pin for INT14R.
Event input pin for reload timer 2.
44
45
K
F
General-purpose I/O port (I/O circuit type of P44 is different from
that of MB90V340E) .
P44
FRCK0
Free-run timer 0 clock input pin.
(Continued)
10
DS07-13749-2E
MB90960 Series
(Continued)
Pin No.
Pin name
Circuit type
Function
LQFP-48P*
General-purpose I/O ports.
(products with S-suffix and MB90V340E-101/103)
P40, P41
F
46, 47
X0A: Oscillation input pin for sub clock
X0A, X1A
AVSS
B
I
X1A: Oscillation output pin for sub clock
(products without S-suffix and MB90V340E-102/104)
48
VSS power input pin for analog circuit.
* : FPT-48P-M26
DS07-13749-2E
11
MB90960 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
Oscillation circuit
High-speed oscillation feedback
resistor = approx. 1 MΩ
X1
X0
Xout
A
Standby control signal
Oscillation circuit
Low-speed oscillation feedback
resistor = approx. 10 MΩ
X1A
X0A
Xout
B
Standby control signal
CMOS input
R
C
D
CMOS Hysteresis
inputs
• CMOS input
• No Pull-down
R
CMOS Hysteresis
inputs
Pull-down
resistor
CMOS hysteresis input
Pull-up resistor value : approx. 50 kΩ
Pull-up
resistor
E
R
CMOS Hysteresis
inputs
(Continued)
12
DS07-13749-2E
MB90960 Series
Type
Circuit
Remarks
• CMOS level output (IOL = 4 mA,
IOH = − 4 mA)
• CMOS hysteresis input (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
P-ch
N-ch
Pout
Nout
F
R
CMOS hysteresis input
Automotive input
Standby control for
input shutdown
• CMOS level output (IOL = 4 mA,
IOH = − 4 mA)
Pull-up control
Pout
Pull-up
resistor
• CMOS hysteresis input (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
• Programmable pull-up resistor :
approx. 50 kΩ
P-ch
P-ch
N-ch
Nout
G
R
CMOS hysteresis input
Automotive input
Standby control for
input shutdown
• CMOS level output (IOL = 4 mA,
IOH = − 4 mA)
• CMOS hysteresis input (With the
standby-time input shutdown function)
• Automotive input (With the standby-
time input shutdown function)
• A/D analog input
P-ch
N-ch
Pout
Nout
R
H
CMOS hysteresis input
Automotive input
Standby control for
input shutdown
A/D analog input
(Continued)
DS07-13749-2E
13
MB90960 Series
(Continued)
Type
Circuit
Remarks
Power supply input protection circuit
P-ch
N-ch
I
• CMOS level output (IOL = 4 mA,
IOH = − 4 mA)
• CMOS input (With standby-time input
shutdown function)
• Automotive input (With the standby-
time input shutdown function)
P-ch
N-ch
Pout
Nout
R
K
CMOS input
Automotive input
Standby control for
input shutdown
14
DS07-13749-2E
MB90960 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device :
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Notes on during operation of PLL clock mode
• Power supply pins (VCC/VSS)
• Pull-up/down resistors
• Crystal oscillator circuit
• Turning-on sequence of power supply to A/D converter and analog inputs
• Connection of unused pins of A/D converter
• Notes on energization
• Stabilization of power supply voltage
• Initialization
• Correspondence with +105 °C or more
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
When used, note that maximum rated voltage is not exceeded.
For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital
power-supply voltage.
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage of the
device. Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open.
MB90960 Series
X0 (X0A)
X1 (X1A)
Open
DS07-13749-2E
15
MB90960 Series
4. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
5. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential
are connected the inside of the device to prevent such malfunctioning as latch-up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and to keep the recommended DC characteristics specified as the total output current, be sure to connect the
VCC and VSS pins to the power supply and ground externally.
• Connect VCC and VSS to the device from the power supply source with lowest possible impedance.
• It is recommended to connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the
vicinity of VCC and VSS pins of the device.
VCC
VSS
VCC
VSS
VSS
MB90960
Series
VCC
VCC
VSS
VCC
VSS
6. Pull-up/down resistors
The MB90960 series does not support internal pull-up/down resistors (except Port 2 : programmable pull-up
resistors) . Use pull-up/down handling where needed.
7. Crystal oscillator circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly
recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for
stabilizing the operation.
8. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVR) and analog inputs (AN0 to AN15) after turning-
on the digital power supply (VCC) . Turn-off the digital power supply after turning off the A/D converter power
supply and analog inputs. In this case, make sure that the voltage does not exceed AVR or AVCC (turning on/off
the analog and digital power supplies simultaneously is acceptable) .
9. Connection of unused pins of A/D converter if A/D converter is not used
16
DS07-13749-2E
MB90960 Series
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS.
10. Notes on energization
To prevent malfunction of the internal voltage regulator , supply voltage profile while turning on the power supply
should be slower than 50 µs (0.2 V to 2.7 V) .
11. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply
voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization
guide lines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the
commercial frequencies (50 Hz/60 Hz) fall within 10% of the standard VCC power supply voltage and the transient
fluctuation rate becomes 0.1 V/ms or less in instantaneous fluctuation for power supply switching.
12. Serial communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a board so as to avoid noise.
Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of
receiving wrong data due to the noise.
13. Initialization
Inthedevice, thereareinternalregisterswhichareinitializedonlybyapower-onreset. Toinitializetheseregisters,
turn on the power again.
14. Correspondence with +105 °C or more
There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
DS07-13749-2E
17
MB90960 Series
■ BLOCK DIAGRAMS
• MB90F962(S)
X0
X1
RST
X0A*
X1A*
Clock
controller
F2MC-16LX
core
Input
capture
IN0 to IN3
4 channels
16-bit
free-run
timer 0
FRCK0
RAM
3 Kbytes
ROM
64 Kbytes
16-bit
reload
TIN2, TIN3
TOT2, TOT3
timer
Baud rate
generator
2 channels
(2 channels)
SOT0, SOT1
SCK0, SCK1
SIN0, SIN1
LIN-UART
2 channels
AVCC
AVSS
AN15 to AN0
8/10-bit
A/D
converter
16 channels
AVR
ADTG
INT8, INT9R,
DTP/
External
interrupt
INT10, INT11,
INT12R, INT13,
INT14R, INT15R
8/16-bit
PPG timer
4/2 channels
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
* : Only for MB90F962
18
DS07-13749-2E
MB90960 Series
• MB90F967(S)
X0
X1
RST
X0A*
X1A*
Clock
controller
F2MC-16LX
core
CR
oscillation
circuit
Input
capture
IN0 to IN3
4 channels
16-bit
free-run
timer 0
FRCK0
RAM
3 Kbytes
ROM
64 Kbytes
16-bit
reload
TIN2, TIN3
TOT2, TOT3
timer
baud rate
generator
2 channels
(2 channels)
SOT0, SOT1
SCK0, SCK1
SIN0, SIN1
LIN-UART
2 channels
AVCC
AVSS
AN15 to AN0
8/10-bit
A/D
converter
16 channels
AVR
ADTG
INT8, INT9R,
DTP/
External
interrupt
INT10, INT11,
INT12R, INT13,
INT14R, INT15R
8/16-bit
PPG timer
4/2 channels
PPGF(E), PPGD(C),
PPGC(D), PPGE(F)
* : Only for MB90F962
DS07-13749-2E
19
MB90960 Series
• MB90V340E-101/102
X0
X1
RST
X0A*
X1A*
Clock
controller
F2MC-16LX
core
16-bit
free-run
timer 0
FRCK0
Input
capture
IN7 to IN0
8 channels
RAM
30 Kbytes
Output
compare
8 channels
OUT7 to OUT0
FRCK1
baud rate
generator
(5 channels)
16-bit
free-run
timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
LIN-UART
5 channels
16-bit
reload Timer
4 channels
AVCC
AVSS
AN23 to AN0
TIN3 to TIN0
TOT3 to TOT0
8/10-bit
A/D
converter
24 channels
AVRH
AVRL
ADTG
AD15 to AD00
A23 to A16
ALE
RD
10-bit
D/A converter
2 channels
WRL
WRH
HRQ
External
bus
DA01, DA00
8/16-bit
PPG timer
16/8 channels
HAK
RDY
CLK
PPGF to PPG0
I2C
interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DTP/
External
interrupt
DMA
Clock
monitor
CKOT
* : Only for MB90V340E-102
20
DS07-13749-2E
MB90960 Series
• MB90V340E-103/104
X0
X1
RST
X0A*
X1A*
Clock
controller
F2MC-16LX
core
16-bit
free-run
FRCK0
CR
oscillation
circuit
timer 0
Input
capture
IN7 to IN0
8 channels
RAM
30 Kbytes
Output
compare
8 channels
OUT7 to OUT0
FRCK1
baud rate
generator
(5 channels)
16-bit
free-run
timer 1
SOT4 to SOT0
SCK4 to SCK0
SIN4 to SIN0
CAN
controller
3 channels
RX2 to RX0
TX2 to TX0
LIN-UART
5 channels
16-bit
reload Timer
4 channels
AVCC
AVSS
AN23 to AN0
TIN3 to TIN0
TOT3 to TOT0
8/10-bit
A/D
converter
24 channels
AVRH
AVRL
ADTG
AD15 to AD00
A23 to A16
ALE
RD
10-bit
D/A converter
2 channels
WRL
WRH
HRQ
External
bus
DA01, DA00
8/16-bit
PPG timer
16/8 channels
HAK
RDY
CLK
PPGF to PPG0
I2C
interface
2 channels
SDA1, SDA0
SCL1, SCL0
INT15 to INT8
(INT15R to INT8R)
INT7 to INT0
DTP/
External
interrupt
DMA
Clock
monitor
CKOT
* : Only for MB90V340E-104
DS07-13749-2E
21
MB90960 Series
■ MEMORY MAP
MB90V340E-101/102
MB90V340E-103/104
MB90F962(S)
MB90F967(S)
FFFFFFH
FFFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM (FF bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
F90000H
F8FFFFH
F80000H
00FFFFH
010000H
00FFFFH
ROM (image
ROM (image
of FF bank)
of FF bank)
008000H
007FFFH
008000H
007FFFH
Peripheral
Peripheral
007900H
007900H
0078FFH
RAM 30 Kbytes
000CFFH
000100H
RAM 3 Kbytes
000100H
0000FFH
0000F0H
0000EFH
000000H
0000EFH
000000H
Peripheral
Peripheral
: Access prohibited
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using
the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF7FFFH is visible only in bank FF.
22
DS07-13749-2E
MB90960 Series
■ I/O MAP
Address
Register
Abbreviation Access
Resource name Initial value
000000H,
000001H
Reserved
000002H Port 2 Data Register
000003H
PDR2
Reserved
R/W
Port 2
XXXXXXXXB
000004H Port 4 Data Register
000005H Port 5 Data Register
000006H Port 6 Data Register
000007H
PDR4
PDR5
PDR6
R/W
R/W
R/W
Port 4
Port 5
Port 6
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
PDR8
000008H Port 8 Data Register
R/W
Port 8
XXXXXXXXB
000009H,
00000AH
Reserved
00000BH Port 5 Analog Input Enable Register
00000CH Port 6 Analog Input Enable Register
00000DH
ADER5
ADER6
R/W
R/W
Port 5, A/D
Port 6, A/D
11111111B
11111111B
Reserved
00000EH Input Level Select Register 0
00000FH Input Level Select Register 1
ILSR0
ILSR1
R/W
R/W
Port 2, 4, 5, 6
Port 8
X000X0XXB
XXXXXXX0B
0000010H,
000011H
Reserved
000012H Port 2 Direction Register
000013H
DDR2
Reserved
R/W
Port 2
00000000B
000014H Port 4 Direction Register
000015H Port 5 Direction Register
000016H Port 6 Direction Register
000017H
DDR4
DDR5
DDR6
R/W
R/W
R/W
Port 4
Port 5
Port 6
XXX00000B
00000000B
00000000B
Reserved
DDR8
Reserved
DDRA
000018H Port 8 Direction Register
000019H
R/W
W
Port 8
Port A
000000X0B
00001AH Port A Direction Register
XXX00XXXB
00001BH
to
Reserved
00001DH
00001EH Port 2 Pull-up Control Register
00001FH
PUCR2
Reserved
R/W
Port 2
00000000B
(Continued)
DS07-13749-2E
23
MB90960 Series
Address
Register
Abbreviation Access Resource name Initial value
000020H Serial Mode Register 0
000021H Serial Control Register 0
SMR0
SCR0
W, R/W
W, R/W
R/W
00000000B
00000000B
00000000B
00001000B
000022H Reception/Transmission Data Register 0 RDR0/TDR0
000023H Serial Status Register 0
Extended Communication Control
SSR0
R, R/W
LIN-UART0
R, W,
R/W
000024H
ECCR0
000000XXB
Register 0
000025H Extended Status Control Register 0
000026H Baud Rate Generator Register 00
000027H Baud Rate Generator Register 01
000028H Serial Mode Register 1
ESCR0
BGR00
BGR01
SMR1
R/W
00000100B
00000000B
00000000B
00000000B
00000000B
00000000B
00001000B
R/W, R
R/W, R
W, R/W
W, R/W
R/W
000029H Serial Control Register 1
SCR1
00002AH Reception/Transmission Data Register 1 RDR1/TDR1
00002BH Serial Status Register 1
SSR1
R, R/W
LIN-UART1
Extended Communication Control
Register 1
R, W,
R/W
00002CH
ECCR1
000000XXB
00002DH Extended Status Control Register 1
00002EH Baud Rate Generator Register 10
00002FH Baud Rate Generator Register 11
ESCR1
BGR10
BGR11
R/W
00000100B
00000000B
00000000B
R/W, R
R/W, R
000030H
to
00003AH
Reserved
PACSR1
Reserved
Address Match
Detection 1
00003BH Address Detect Control Register 1
R/W
00000000B
00003CH
to
000047H
000048H PPGC Operation Mode Control Register
000049H PPGD Operation Mode Control Register
PPGCC
PPGCD
W, R/W
W, R/W
0X000XX1B
0X000001B
16-bit PPG C/D
16-bit PPG E/F
PPGC/PPGD Count Clock Select
00004AH
Register
PPGCD
R/W
000000X0B
00004BH
Reserved
PPGCE
PPGCF
00004CH PPGE Operation Mode Control Register
00004DH PPGF Operation Mode Control Register
W, R/W
W, R/W
0X000XX1B
0X000001B
PPGE/PPGF Count Clock Select
00004EH
Register
PPGEF
R/W
000000X0B
00004FH
Reserved
(Continued)
24
DS07-13749-2E
MB90960 Series
Address
Register
Abbreviation Access
Resource name
Initial value
00000000B
XXX0X0XXB
00000000B
XXXXXXXXB
000050H Input Capture Control Status 0/1
000051H Input Capture Edge 0/1
ICS01
ICE01
ICS23
ICE23
R/W
R/W, R
R/W
R
Input Capture 0/1
000052H Input Capture Control Status 2/3
000053H Input Capture Edge 2/3
Input Capture 2/3
000054H
to
Reserved
000063H
000064H Timer Control Status 2
000065H Timer Control Status 2
000066H Timer Control Status 3
000067H Timer Control Status 3
000068H A/D Control Status 0
000069H A/D Control Status 1
00006AH A/D Data Register 0
00006BH A/D Data Register 1
00006CH A/D Converter Setting 0
00006DH A/D Converter Setting 1
00006EH
TMCSR2
TMCSR2
TMCSR3
TMCSR3
ADCS0
ADCS1
ADCR0
ADCR1
ADSR0
ADSR1
R/W
R/W
R/W
R/W
R/W
R/W, W
R
00000000B
XXXX0000B
00000000B
XXXX0000B
000XXXX0B
0000000XB
00000000B
XXXXXX00B
00000000B
00000000B
16-bit Reload Timer 2
16-bit Reload Timer 3
A/D Converter
ROM Mirror
R
R/W
R/W
Reserved
00006FH ROM Mirror Function Select
ROMM
W
XXXXXXX1B
000070H
to
Reserved
00009DH
Address Match
Detection 0
00009EH Address Detect Control Register 0
00009FH Delayed Interrupt/Release Register
PACSR0
DIRR
R/W
R/W
00000000B
Delayed Interrupt
generation module
XXXXXXX0B
Low-Power
consumption
Control Circuit
Low-power Consumption Mode
0000A0H
LPMCR
CKSCR
W, R/W
R, R/W
00011000B
11111100B
Control Register
Low-Power
consumption
Control Circuit
0000A1H Clock Selection Register
0000A2H
to
Reserved
0000A7H
0000A8H Watchdog Timer Control Register
0000A9H Time-base Timer Control Register
WDTC
TBTC
R, W
Watchdog Timer
Time-base Timer
XXXXX111B
1XX00100B
(Continued)
W, R/W
DS07-13749-2E
25
MB90960 Series
Address
Register
Abbreviation Access
Resource name
Initial value
0000AAH Watch Timer Control Register
WTC
R, R/W
Watch Timer
1X001000B
0000ABH
to
Reserved
0000ADH
0000AEH Flash Control Status
FMCS
R, R/W
Flash Memory
000X0000B
0000AFH
Reserved
0000B0H Interrupt Control Register 00
0000B1H Interrupt Control Register 01
0000B2H Interrupt Control Register 02
0000B3H Interrupt Control Register 03
0000B4H Interrupt Control Register 04
0000B5H Interrupt Control Register 05
0000B6H Interrupt Control Register 06
0000B7H Interrupt Control Register 07
0000B8H Interrupt Control Register 08
0000B9H Interrupt Control Register 09
0000BAH Interrupt Control Register 10
0000BBH Interrupt Control Register 11
0000BCH Interrupt Control Register 12
0000BDH Interrupt Control Register 13
0000BEH Interrupt Control Register 14
0000BFH Interrupt Control Register 15
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
W, R/W
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
00000111B
Interrupt Control
0000C0H
to
Reserved
0000C9H
0000CAH DTP/External Interrupt Enable 1
0000CBH DTP/External Interrupt Source 1
0000CCH Detection Level Setting 1
ENIR1
EIRR1
ELVR1
ELVR1
EISSR
PSCCR
R/W
R/W
R/W
R/W
R/W
W
00000000B
XXXXXXXXB
00000000B
00000000B
00000000B
XXXX0000B
External Interrupt 1
PLL
0000CDH Detection Level Setting 1
0000CEH External Interrupt factor Select
0000CFH PLL/Sub clock Control Register
0000D0H
to
Reserved
0000FFH
(Continued)
26
DS07-13749-2E
MB90960 Series
Address
Register
Abbreviation
Access
Resource name
Initial value
007900H
to
Reserved
007917H
007918H Reload Register LC
007919H Reload Register HC
00791AH Reload Register LD
00791BH Reload Register HD
00791CH Reload Register LE
00791DH Reload Register HE
00791EH Reload Register LF
00791FH Reload Register HF
007920H Input Capture 0
007921H Input Capture 0
007922H Input Capture 1
007923H Input Capture 1
007924H Input Capture 2
007925H Input Capture 2
007926H Input Capture 3
007927H Input Capture 3
PRLLC
PRLHC
PRLLD
PRLHD
PRLLE
PRLHE
PRLLF
PRLHF
IPCP0
IPCP0
IPCP1
IPCP1
IPCP2
IPCP2
IPCP3
IPCP3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit PPG C/D
16-bit PPG E/F
Input Capture 0/1
Input Capture 2/3
R
R
R
R
R
R
R
007928H
to
Reserved
00793FH
007940H Timer Data 0
TCDT0
TCDT0
R/W
R/W
R/W
R/W
00000000B
00000000B
00000000B
0XXXXXXXB
007941H Timer Data 0
16-bitFree-runTimer
0
007942H Timer Control Status 0
007943H Timer Control Status 0
TCCSL0
TCCSH0
007944H
to
Reserved
00794BH
00794CH
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit Reload
Timer 2
Timer 2/Reload 2
00794DH
TMR2/TMRLR2
TMR3/TMRLR3
00794EH
16-bit Reload
Timer 3
Timer 3/Reload 3
00794FH
007950H
to
Reserved
00795FH
(Continued)
DS07-13749-2E
27
MB90960 Series
(Continued)
Address
Register
Abbreviation Access
Resource name
Initial value
007960H Clock supervisor control register
CSVCR
R,R/W
Clock supervisor
00011100B
007961H
to
Reserved
0079DFH
0079E0H Detect Address Setting 0
0079E1H Detect Address Setting 0
0079E2H Detect Address Setting 0
0079E3H Detect Address Setting 1
0079E4H Detect Address Setting 1
0079E5H Detect Address Setting 1
0079E6H Detect Address Setting 2
0079E7H Detect Address Setting 2
0079E8H Detect Address Setting 2
PADR0
PADR0
PADR0
PADR1
PADR1
PADR1
PADR2
PADR2
PADR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 0
0079E9H
to
Reserved
0079EFH
0079F0H Detect Address Setting 3
0079F1H Detect Address Setting 3
0079F2H Detect Address Setting 3
0079F3H Detect Address Setting 4
0079F4H Detect Address Setting 4
0079F5H Detect Address Setting 4
0079F6H Detect Address Setting 5
0079F7H Detect Address Setting 5
0079F8H Detect Address Setting 5
PADR3
PADR3
PADR3
PADR4
PADR4
PADR4
PADR5
PADR5
PADR5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Address Match
Detection 1
0079F9H
to
Reserved
007FFFH
Notes : • Initial value of “X” represents unknown value.
• Any write access to reserved addresses in I/O map should not be performed. A read access to reserved
addresses results in reading “X”.
28
DS07-13749-2E
MB90960 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt control
Interrupt vector
Number Address
EI2OS
corresponding
register
Interrupt cause
Number
Address
Reset
N
N
#08
#09
#10
#11
#12
#13
#14
#15
#16
#17
#18
#19
#20
#21
#22
#23
#24
#25
#26
#27
#28
#29
#30
#31
#32
#33
#34
#35
#36
#37
#38
FFFFDCH
FFFFD8H
FFFFD4H
FFFFD0H
FFFFCCH
FFFFC8H
FFFFC4H
FFFFC0H
FFFFBCH
FFFFB8H
FFFFB4H
FFFFB0H
FFFFACH
FFFFA8H
FFFFA4H
FFFFA0H
FFFF9CH
FFFF98H
FFFF94H
FFFF90H
FFFF8CH
FFFF88H
FFFF84H
FFFF80H
FFFF7CH
FFFF78H
FFFF74H
FFFF70H
FFFF6CH
FFFF68H
FFFF64H
⎯
⎯
⎯
⎯
⎯
⎯
INT9 instruction
Exception processing
Reserved
N
N
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
Reserved
N
Reserved
N
Reserved
N
Reserved
N
Reserved
N
Reserved
N
Reserved
N
16-bit reload timer 2
16-bit reload timer 3
Reserved
Y1
Y1
N
Reserved
N
PPG C/D
N
PPG E/F
N
Time-base timer
External interrupt 8 to 11
Watch timer
N
Y1
N
External interrupt 12 to 15
A/D converter
16-bit free-run timer 0
Reserved
Y1
Y1
N
N
Reserved
N
Input capture 0 to 3
Reserved
Y1
N
LIN-UART 0 reception
LIN-UART 0 transmission
LIN-UART 1 reception
LIN-UART 1 transmission
Y2
Y1
Y2
Y1
0000BDH
(Continued)
DS07-13749-2E
29
MB90960 Series
(Continued)
Interrupt control
register
Interrupt vector
Number Address
EI2OS
corresponding
Interrupt cause
Number
Address
Reserved
N
N
N
N
#39
#40
#41
#42
FFFF60H
FFFF5CH
FFFF58H
FFFF54H
ICR14
0000BEH
Reserved
Flash memory
ICR15
0000BFH
Delayed interrupt generation module
Y1 : Usable
Y2 : Usable, with EI2OS stop function
N : Unusable
Notes : • The peripheral resources sharing the ICR register have the same interrupt level.
• When 2 peripheral resources share the ICR register, only one can use extended intelligent I/O service
at a time.
• When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O
service, the other one cannot use interrupts.
30
DS07-13749-2E
MB90960 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
AVCC
AVR
VI
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
VSS − 0.3 VSS + 6.0
V
V
V
V
V
Power supply voltage*1
VCC = AVCC*2
AVCC ≥ AVR*2
Input voltage*1
Output voltage*1
*3
*3
VO
Maximum clamp current
ICLAMP
Σ|ICLAMP|
IOL
−2.0
⎯
+2.0
40
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mA *4
mW
Total Maximum clamp current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
“H” level maximum output current
“H” level average output current
“H” level maximum overall output current
“H” level average overall output current
Power consumption
⎯
15
IOLAV
ΣIOL
⎯
4
⎯
125
40
ΣIOLAV
IOH
⎯
⎯
−15
−4
IOHAV
ΣIOH
ΣIOHAV
PD
⎯
⎯
−125
−40
300
+105
+125
+150
⎯
⎯
−40
−40
−55
°C
Operating temperature
Storage temperature
TA
°C *5
°C
TSTG
(Continued)
DS07-13749-2E
31
MB90960 Series
(Continued)
*1 : This parameter is based on VSS = AVSS = 0 V.
*2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the
analog inputs does not exceed AVCC when the power is switched on.
*3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximum
current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the
VI rating.
*4 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Sample recommended circuits :
• Input/output equivalent circuits
Protective diode
VCC
Limiting
P-ch
resistance
+B input (0 V to 16 V)
N-ch
R
*5 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
32
DS07-13749-2E
MB90960 Series
2. Recommended Conditions
(VSS = AVSS = 0 V)
Remarks
Value
Typ
Parameter
Symbol
Unit
Min
Max
4.0
5.0
5.5
V
Under normal operation
Under normal operation when not using
the A/D converter and not Flash
programming.
VCC,
AVCC
Power supply voltage
3.5
3.0
5.0
5.5
5.5
V
V
⎯
Maintains RAM data in stop mode
Use a ceramic capacitor or capacitor of
better AC characteristics for the C pin.
Bypass capacitor at the VCC pin should
be greater than this capacitor.
Smooth capacitor
CS
TA
0.1
⎯
1.0
µF
−40
−40
⎯
⎯
+105
+125
°C
°C
Operating temperature
*
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
• C Pin Connection Diagram
C
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
DS07-13749-2E
33
MB90960 Series
3. DC Characteristics
Sym-
(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Pin
Condition
Unit
Remarks
bol
Min
Typ
Max
Pin inputs if CMOS
hysteresis levels are
selected (except P82,
P85)
⎯
⎯
0.8 VCC
⎯
VCC + 0.3
V
VIHS
P82, P85 inputs if
CMOS input levels are
selected
⎯
⎯
⎯
⎯
0.7 VCC
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
Input “H”
voltage
Pin inputs if
Automotive input
levels are selected
VIHA
RST input pin (CMOS
hysteresis)
VIHR
⎯
⎯
⎯
⎯
0.8 VCC
⎯
⎯
VCC + 0.3
VCC + 0.3
V
V
VIHM
VCC − 0.3
MD input pin
Pin inputs if CMOS
hysteresis input levels
are selected (except
P82, P85)
⎯
⎯
VSS − 0.3
⎯
0.2 VCC
V
VILS
P82, P85 inputs if
CMOS input levels are
selected
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
⎯
⎯
0.3 VCC
0.5 VCC
V
V
Input “L”
voltage
Pin inputs if
Automotive input
levels are selected
VILA
RST input pin (CMOS
hysteresis)
VILR
VILM
VOH
⎯
⎯
⎯
⎯
⎯
VSS − 0.3
VSS − 0.3
VCC − 0.5
⎯
⎯
⎯
0.2 VCC
VSS + 0.3
⎯
V
V
V
MD input pin
Output “H”
voltage
VCC = 4.5 V,
IOH = −4.0 mA
Output “L”
voltage
VCC = 4.5 V,
IOL = 4.0 mA
VOL
IIL
⎯
⎯
⎯
−1
25
25
⎯
⎯
50
50
0.4
+ 1
V
Input leak
current
VCC = 5.5 V,
VSS < VI < VCC
µA
kΩ
kΩ
Pull-up
resistance
P20 to P27,
RST
RUP
⎯
⎯
100
100
Pull-down
resistance
Except Flash memory
devices
RDOWN
MD2
(Continued)
34
DS07-13749-2E
MB90960 Series
(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
VCC = 5.0 V,
Internal frequency : 24 MHz,
At normal operation.
MB90F962(S),
MB90F967(S)
⎯
⎯
⎯
⎯
⎯
35 45 mA
50 60 mA
50 60 mA
12 20 mA
0.3 0.8 mA
VCC = 5.0 V,
Internal frequency : 24 MHz,
At writing Flash memory.
MB90F962(S),
MB90F967(S)
ICC
VCC = 5.0 V,
Internal frequency : 24 MHz,
At erasing Flash memory.
MB90F962(S),
MB90F967(S)
VCC = 5.0 V,
Internal frequency : 24 MHz,
At sleep mode.
MB90F962(S),
MB90F967(S)
ICCS
VCC = 5.0 V,
Internal frequency : 2 MHz,
At main timer mode
MB90F962(S),
MB90F967(S)
ICTS
VCC = 5.0 V,
Internal frequency : 24 MHz,
At PLL timer mode,
MB90F962(S),
MB90F967(S)
ICTSPLL6
⎯
⎯
⎯
⎯
⎯
⎯
4
7
mA
External frequency = 4 MHz
During stop-
ping Clock
supervisor
MB90F962 (S) ,
MB90F967 (S)
VCC = 5.0 V,
Internalfrequency:
8 kHz,
At sub clock opera-
tion mode,
TA = + 25°C
Power supply
current*2
40 100 µA
VCC
ICCL
During
operating
Clock super-
visor
60 150 µA MB90F967 (S)
During stop-
ping Clock
supervisor
MB90F962 (S) ,
MB90F967 (S)
VCC = 5.0 V,
Internalfrequency:
8 kHz,
At sub clock sleep
mode,
10 50
µA
ICCLS
During
operating
Clock super-
visor
30 100 µA MB90F967 (S)
TA = + 25°C
During stop-
ping Clock
supervisor
MB90F962 (S) ,
MB90F967 (S)
8
30
µA
VCC = 5.0 V,
Internalfrequency:
8 kHz,
At watch mode,
TA = + 25°C
ICCT
During
operating
Clock super-
visor
⎯
⎯
30 70
µA MB90F967 (S)
VCC = 5.0 V,
At stop mode, TA = + 25°C
MB90F962(S),
µA
ICCH
5
25
MB90F967(S)
(Continued)
35
DS07-13749-2E
MB90960 Series
(Continued)
(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Sym-
bol
Parameter
Pin
Condition
Unit
Remarks
Min Typ Max
Other
than
AVCC,
AVSS,
AVR,
VCC,
Input capacity
CIN
⎯
⎯
5
15
pF
VSS, C
*1 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
*2 : The power supply current is measured with an external clock.
36
DS07-13749-2E
MB90960 Series
4. AC Characteristics
(1) Clock Timing
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Parameter
Symbol
Pin
Unit
Remarks
Min
Typ
Max
1/2 when PLL stops,
When using an oscillation circuit
3
16
PLL × 1,
4
4
4
4
4
3
4
4
4
4
4
16
12
8
When using an oscillation circuit
PLL × 2,
When using an oscillation circuit
X0, X1
⎯
MHz
PLL × 3,
When using an oscillation circuit
PLL × 4,
When using an oscillation circuit
6
PLL × 6,
When using an oscillation circuit
4
fC
Clock frequency
1/2 when PLL stops,
When using an external clock
24
20
12
8
PLL × 1,
When using an external clock
PLL × 2,
When using an external clock
X0, X1
⎯
MHz
kHz
PLL × 3,
When using an external clock
PLL × 4,
When using an external clock
6
PLL × 6,
When using an external clock
4
fCL
X0A, X1A
X0, X1
⎯
32.768 100
62.5
⎯
⎯
333
333
⎯
ns When using an oscillation circuit
ns When using an external clock
µs When using sub clock
tCYL
Clock cycle time
X0, X1 41.67
X0A, X1A 10
tCYLL
30.5
⎯
PWH, PWL
PWHL, PWLL
X0
10
5
⎯
ns
Input clock pulse width
Duty ratio is about 30% to 70%.
µs
X0A
15.2
⎯
Input clock rise and fall
time
tCR, tCF
X0
⎯
⎯
5
ns When using external clock
fCP
fCPL
tCP
⎯
⎯
⎯
⎯
1.5
⎯
⎯
24
50
MHz When using main clock
kHz When using sub clock
ns When using main clock
µs When using sub clock
Internal operating clock
frequency(machineclock)
8.192
⎯
41.67
20
666
⎯
Internal operating clock
cycle time (machine clock)
tCPL
122.1
*: There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
DS07-13749-2E
37
MB90960 Series
• Clock Timing
t
CYL
0.8 VCC
0.2 VCC
X0
P
WH
P
WL
t
CF
tCR
t
CYLL
0.8 VCC
0.2 VCC
X0A
P
WHL
P
WLL
t
CF
tCR
38
DS07-13749-2E
MB90960 Series
• Guaranteed PLL Operation Range
Guaranteed operation range
Guaranteed PLL operation range (CS2=1)
5.5
4.5
Guaranteed A/D converter
operation range
3.5
Guaranteed PLL operation range (CS2=0)
1.5
4
8
20
24
Machine clock fCP (MHz)
Guaranteed operation range of MB90960 series
• CS2 (bit 0 in PSCCR register) = 0
x4 (CS=011)
x3 (CS=010)
Guaranteed oscillation frequency range
x1 (CS=000)
x2 (CS=001)
20
16
12
x1/2 (PLL off)
8
6
4
1.5
4
6
8
10 12
16
20
24
3
External clock fC (MHz)*
• CS2 (bit 0 in PSCCR register) = 1
x6 (CS=110)
x4 (CS=101)
x2 (CS=100)
24
Guaranteed oscillation frequency range
16
12
8
x1/2 (PLL off)
4
1.5
4
6
8
10 12
16
20
24
3
External clock f
C
(MHz)*
* : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.
External clock frequency and Machine clock frequency
DS07-13749-2E
39
MB90960 Series
(2) Reset Standby Input
Parameter Symbol Pin
Reset input
(TA = −40 °C to +125 °C*1, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Unit
Remarks
Min
Max
⎯
500
ns Under normal operation
µs In stop mode
tRSTL
RST Oscillation time of oscillator*2 + 100 µs
⎯
time
100
⎯
µs In time-base timer mode
*1: There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%.
In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators,
the oscillation time is between hundreds of µs and several ms. With an external clock, the oscillation time is 0 ms.
• Under normal operation :
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode :
tRSTL
RST
0.2 VCC
0.2 VCC
90% of
amplitude
X0
Internal operation
clock
100 µs
Oscillation time
of oscillator
Oscillation stabilization
waiting time
Instruction execution
Internal reset
40
DS07-13749-2E
MB90960 Series
(3) Power-on Reset
Parameter
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Symbol
Pin
Condition
Unit
Remarks
Min
0.05
1
Max
30
Power on rise time
Power off time
tR
VCC
VCC
ms
⎯
tOFF
⎯
ms Due to repetitive operation
*: There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
tR
2.7 V
V
CC
0.2 V
0.2 V
0.2 V
tOFF
Note : If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you
start up smoothly by restraining voltages when changing the power supply voltage during operation, as
shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within
1 V/s, you can operate while using the PLL clock.
VCC
We recommend a rise of
50 mV/ms maximum.
3 V
Holds RAM data
VSS
DS07-13749-2E
41
MB90960 Series
(4) LIN-UART0/1
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 0
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0, SCK1
5 tCP
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↓ → SOT delay time
−50
+50
⎯
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
Valid SIN → SCK ↑
tIVSHI
tCP + 80
0
ns
ns
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
tSHIXI
⎯
Serial clock “L” pulse width
Serial clock “H” pulse width
tSHSL
tSLSH
SCK0, SCK1
SCK0, SCK1
3 tCP - tR
tCP + 10
⎯
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
tSLOVE
tIVSHE
tSHIXE
⎯
30
2 tCP + 60 ns
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
⎯
⎯
ns
ns
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → Valid SIN hold time
tCP + 30
SCK fall time
SCK rise time
tF
SCK0, SCK1
SCK0, SCK1
⎯
⎯
10
10
ns
ns
tR
*: There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing”.
• Internal Shift Clock Mode
t
SCYC
2.4 V
SCK0, SCK1
SOT0, SOT1
0.8 V
0.8 V
t
SLOVI
2.4 V
0.8 V
t
IVSHI
t
SHIXI
V
V
IH
IL
V
V
IH
IL
SIN0, SIN1
42
DS07-13749-2E
MB90960 Series
• External Shift Clock Mode
t
SLSH
t
SHSL
V
IH
V
IH
SCK0, SCK1
VIL
VIL
tSLOVE
t
F
t
R
2.4 V
0.8 V
SOT0, SOT1
SIN0, SIN1
t
IVSHE
t
SHIXE
V
V
IH
IL
V
V
IH
IL
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 0
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0, SCK1
5 tCP
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↑ → SOT delay time
tSHOVI
−50
tCP + 80
0
+50
⎯
Internal shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
Valid SIN → SCK ↓
tIVSLI
tSLIXI
ns
ns
SCK0, SCK1,
SIN0, SIN1
SCK ↓ → Valid SIN hold time
⎯
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK0, SCK1
SCK0, SCK1
3 tCP - tR
tCP + 10
⎯
⎯
ns
ns
SCK0, SCK1,
SOT0, SOT1
SCK ↑ → SOT delay time
Valid SIN → SCK ↓
tSHOVE
tIVSLE
tSLIXE
⎯
30
2 tCP + 60
ns
ns
ns
External shift clock
mode output pins are
CL = 80 pF + 1 TTL.
SCK0, SCK1,
SIN0, SIN1
⎯
⎯
SCK0, SCK1,
SIN0, SIN1
SCK ↓ → Valid SIN hold time
tCP + 30
SCK fall time
SCK rise time
tF
SCK0, SCK1
SCK0, SCK1
⎯
⎯
10
10
ns
ns
tR
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Notes : • CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing”.
DS07-13749-2E
43
MB90960 Series
• Internal Shift Clock Mode
t
SCYC
2.4 V
SCK0, SCK1
SOT0, SOT1
0.8 V
tSHOVI
2.4 V
0.8 V
t
IVSLI
t
SLIXI
V
V
IH
IL
V
V
IH
IL
SIN0, SIN1
• External Shift Clock Mode
t
SHSL
t
SLSH
VIH
VIH
SCK0, SCK1
VIL
V
IL
tSHOVE
t
R
t
F
2.4 V
0.8 V
SOT0, SOT1
SIN0, SIN1
t
IVSLE
t
SLIXE
V
V
IH
IL
V
V
IH
IL
44
DS07-13749-2E
MB90960 Series
• Bit setting: ESCR:SCES = 0, ECCR:SCDE = 1
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0,SCK1
5 tCP
⎯
ns
ns
SCK0,SCK1
SOT0,SOT1
SCK ↑ → SOT delay time
tSHOVI
−50
tCP + 80
0
+50
⎯
SCK0,SCK1 Internal clock operation
SIN0,SIN1 output pins are
Valid SIN → SCK ↓
tIVSLI
tSLIXI
tSOVLI
ns
ns
ns
C = 80 pF + 1 TTL.
L
SCK0,SCK1
SIN0,SIN1
SCK ↓ → Valid SIN hold time
SOT → SCK ↓ delay time
⎯
SCK0,SCK1
SOT0,SOT1
3 tCP − 70
⎯
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Notes : • CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP.
t
SCYC
2.4 V
SCK0, SCK1
SOT0, SOT1
0.8 V
0.8 V
t
SHOVI
t
SOVLI
2.4 V
0.8 V
2.4 V
0.8 V
tIVSLI
tSLIXI
V
V
IH
IL
V
IH
IL
SIN0, SIN1
V
DS07-13749-2E
45
MB90960 Series
• Bit setting: ESCR:SCES = 1, ECCR:SCDE = 1
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOVI
SCK0,SCK1
5 tCP
⎯
ns
ns
SCK0,SCK1
SOT0,SOT1
SCK ↓ → SOT delay time
−50
+50
⎯
SCK0,SCK1 Internalclockoperation
SIN0,SIN1 output pins are
Valid SIN → SCK ↑
tIVSHI
tSHIXI
tSOVHI
tCP + 80
0
ns
ns
ns
C = 80 pF + 1 TTL.
L
SCK0,SCK1
SIN0,SIN1
SCK ↑ → Valid SIN hold time
SOT → SCK ↑ delay time
⎯
SCK0,SCK1
SOT0,SOT1
3 tCP − 70
⎯
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Notes : • CL is load capacity value of pins when testing.
• tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing” rating for tCP.
t
SCYC
2.4 V
2.4 V
SCK0, SCK1
SOT0, SOT1
0.8 V
t
SLOVI
t
SOVHI
2.4 V
0.8 V
2.4 V
0.8 V
t
IVSHI
tSHIXI
V
V
IH
IL
V
V
IH
IL
SIN0, SIN1
46
DS07-13749-2E
MB90960 Series
(5) Trigger Input Timing
Parameter
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Symbol
Pin
Condition
Unit
Min
200
Max
⎯
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
⎯
⎯
ns
ns
tTRGH
tTRGL
Input pulse width
ADTG
tCP + 200
⎯
* : IThere is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing”.
V
IH
VIH
INT8, INT9R
INT10, INT11
INT12R, INT13
INT14R, INT15R
ADTG
V
IL
VIL
t
TRGH
t
TRGL
DS07-13749-2E
47
MB90960 Series
(6) Timer Related Resource Input Timing
(TA = −40 °C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
tTIWH
tTIWL
TIN2, TIN3
IN0 to IN3
Input pulse width
⎯
4 tCP
⎯
ns
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
Note : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock Timing”.
VIH
VIH
VIL
VIL
TIN2, TIN3
IN0 to IN3
tTIWH
tTIWL
(7) Timer Related Resource Output Timing
(TA = –40°C to +125 °C*, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V)
Value
Parameter
Symbol
Pin
Condition
Unit
Min
Max
TOT2, TOT3
PPGC to PPGF
CLK ↑ → TOUT change time
tTO
⎯
30
⎯
ns
* : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
2.4 V
CLK
2.4 V
TOT2, TOT3
PPGC to PPGF
0.8 V
tTO
48
DS07-13749-2E
MB90960 Series
5. A/D Converter
(T
Parameter
Resolution
A
= −40 °C to +125 °C*1, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
Value
Symbol
Pin
Unit
Remarks
Min
⎯
Typ
⎯
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
± 3.0
± 2.5
LSB
LSB
Nonlinearity error
⎯
⎯
Differential
nonlinearity error
⎯
⎯
⎯
⎯
± 1.9
LSB
V
AVSS − 1.5 AVSS + 0.5 AVSS + 2.5
× LSB
Zero reading voltage
VOT
VFST
AN0 to AN15
AN0 to AN15
× LSB
× LSB
Full scale reading
voltage
AVR − 3.5 AVR − 1.5 AVR + 0.5
× LSB
V
× LSB
× LSB
1.0
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
Compare time
Sampling time
⎯
⎯
⎯
⎯
⎯
16500
µs
µs
2.0
0.5
⎯
∞
1.2
Analog port input
current
IAIN
VAIN
⎯
AN0 to AN15
AN0 to AN15
AVR
−0.3
AVSS
⎯
⎯
⎯
+0.3
AVR
AVCC
µA
Analog input
voltage
V
Reference
voltage
AVSS + 2.7
V
IA
IAH
IR
AVCC
AVCC
AVR
AVR
⎯
⎯
⎯
⎯
3.5
⎯
7.5
5
mA
Power supply current
µA *2
µA
600
⎯
900
5
Reference
voltage supply current
IRH
µA *2
Offset between
input channels
⎯
AN0 to AN15
⎯
⎯
4
LSB
*1 : There is limited reliability if the product is used exceeding TA = +105°C. Contact the sales or support
representative for this case.
*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) .
(Continued)
DS07-13749-2E
49
MB90960 Series
• About the external impedance of analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Comparator
Analog input
C
During sampling : ON
Part number
Analog input
R
C
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
4.5 V ≤ AVCC ≤ 5.5 V
4.0 V ≤ AVCC < 4.5 V
2.0 kΩ (Max)
16.0 pF (Max)
16.0 pF (Max)
14.4 pF (Max)
14.4 pF (Max)
MB90F962(S),
MB90F967(S)
8.2 kΩ (Max)
2.0 kΩ (Max)
8.2 kΩ (Max)
MB90V340E-101/102/103/104
Note : The values are reference values.
Use the device with external circuits of the following output impedance for analog inputs:
• Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V,
sampling period = 0.5 µs)
• If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
an on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high
as internal capacitor.
• If the output impedance of an external circuit is too high, the sampling period for the analog voltage may be
insufficient.
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
(Continued)
50
DS07-13749-2E
MB90960 Series
(Continued)
• The relationship between external impedance and minimum sampling time
• At 4.5 V ≤ AVCC ≤ 5.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90F340E-101/102/103/104
MB90F340E-101/102/103/104
100
20
18
16
14
12
10
8
90
80
MB90F962(S),
MB90F967(S)
MB90F962(S),
MB90F967(S)
70
60
50
40
30
20
6
4
10
0
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
Minimum sampling time [µs]
• At 4.0 V ≤ AVCC < 4.5 V
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90F340E-101/102/103/104
MB90F340E-101/102/103/104
20
100
18
16
14
12
10
8
90
80
70
60
50
40
30
20
MB90F962(S),
MB90F967(S)
MB90F962(S),
MB90F967(S)
6
4
2
0
10
0
0
1
2
3
4
5
6
7
8
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
Minimum sampling time [µs]
• About errors
As | AVR − AVSS | becomes smaller, values of relative errors grow larger.
DS07-13749-2E
51
MB90960 Series
6. Definition of A/D Converter Terms
Resolution
: Analog variation that is recognized by an A/D converter.
Non linearity
error
: Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” )
and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion
characteristics.
Differential
linearity error
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
Total error
: Difference between an actual value and an theoretical value. A total error includes zero
transition error, full-scale transition error, and linear error.
Total error
3FFH
1.5 LSB
3FEH
3FDH
Actual conversion
characteristics
{1 LSB × (N − 1) + 0.5 LSB}
004H
003H
002H
001H
VNT
(Actually-measured value)
Actual conversion
characteristics
Ideal characteristics
0.5 LSB
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
Total error of digital output “N” =
1 LSB
AVR − AVSS
1 LSB (Ideal value) =
[V]
1024
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVR − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) H to NH.
(Continued)
52
DS07-13749-2E
MB90960 Series
(Continued)
Non linearity error
Differential linearity error
Ideal
characteristics
3FF
3FE
3FD
H
H
H
Actual conversion
characteristics
(N + 1)
H
H
H
H
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT
}
V
FST (actual
measurement
value)
N
V
NT (actual
measurement value)
004
003
002
001
H
H
H
H
V
(N + 1) T
(actual measurement
Actual conversion
characteristics
(N − 1)
(N − 2)
value)
V
NT
(actual measurement value)
Ideal characteristics
Actual conversion
characteristics
V
OT (actual measurement value)
Analog input
AVSS
AVR
AVSS
AVR
Analog input
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
Non linearity error of digital output N =
1 LSB
V (N+1) T − VNT
−1 LSB [LSB]
1 LSB
Differential linearity error of digital output N =
1 LSB =
VFST − VOT
[V]
1022
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
DS07-13749-2E
53
MB90960 Series
7. Flash Memory Program/Erase Characteristics
Value
Typ
Parameter
Conditions
Unit
Remarks
Min
Max
Excludes programming
prior to erasure
Sector erase time (60 Kbytes)
Sector erase time (4 Kbytes)
Byte programming time
⎯
1
15
s
s
TA = +25 °C
VCC = 5.0 V
Excludes programming
prior to erasure
⎯
⎯
0.2
21
0.5
Except for the overhead
time of the system level
6100
µs
Machine clock frequency fCP at
Flash programming/erasing
VCC = 5.0 V
⎯
10000
20
⎯
⎯
⎯
24
⎯
⎯
MHz
cycle
Year
Program/Erase cycle
⎯
Flash memory data
retention time
Average
TA = +85 °C
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C) .
54
DS07-13749-2E
MB90960 Series
■ ORDERING INFORMATION
Part number
MB90F962PMT
Package
Remarks
48-pin plastic LQFP
FPT-48P-M26
7 mm ❑, 0.50 mm pitch
MB90F962SPMT
Flash Memory Product
(64Kbytes)
MB90F967PMT
MB90F967SPMT
MB90V340E-101CR
MB90V340E-102CR
MB90V340E-103CR
MB90V340E-104CR
299-pin ceramic PGA
PGA-299C-A01
Evaluation product
DS07-13749-2E
55
MB90960 Series
■ PACKAGE DIMENSION
48-pin plastic LQFP
Lead pitch
0.50 mm
7 × 7 mm
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Gullwing
Plastic mold
1.70 mm MAX
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00 0.20(.354 .008)SQ
+0.40
7.00 –0.10 .276 –+..000146 SQ
0.145 0.055
(.006 .002)
*
36
25
37
24
Details of "A" part
0.08(.003)
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
48
13
0.10 0.10
(.004 .004)
(Stand off)
"A"
0˚~8˚
1
12
LEAD No.
0.50(.020)
0.25(.010)
0.20 0.05
M
0.08(.003)
(.008 .002)
0.60 0.15
(.024 .006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F48040S-c-2-3
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
MB90960 Series
■ MAIN CHANGES IN THIS EDITION
Page
⎯
Section
Change Results
Added the part numbers.
(MB90F967 (S) , MB90V340E-103/104)
⎯
1
■ FEATURES
Added the description of Clock supervisor.
■ PRODUCT LINEUP
Added the description of Clock supervisor.
Added the description of MB90F967(S), MB90V340E-103/104
4, 5
Added the product lineup 2
(MB90F967(S), MB90V340E-103/104)
6, 7
19
21
28
Added the Block diagram of MB90F967 (S)
■ BLOCK DIAGRAMS
■ I/O MAP
Added the Block diagram of MB90V340E-103/104
Added the description of Clock supervisor control register (CSVCR)
■ ELECTRICAL
CHARACTERISTICS
3. DC characteristics
For ICCL, ICCLS, ICCT, added the condition of During stopping/operating Clock
supervisor.
35
55
Added the following part numbers:
MB90F967PMT, MB90F967SPMT, MB90V340E-103CR, MB90V340E-
104CR
■ ORDERING
INFORMATION
The vertical lines marked in the left side of the page show the changes.
DS07-13749-2E
57
MB90960 Series
MEMO
58
DS07-13749-2E
MB90960 Series
MEMO
DS07-13749-2E
59
MB90960 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
FUJITSU MICROELECTRONICS ASIA PTE LTD.
151 Lorong Chuan, #05-08 New Tech Park,
Singapore 556741
Tel: +65-6281-0770 Fax: +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm.3102, Bund Center, No.222 Yan An Road(E),
Shanghai 200002, China
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen,
Germany
Tel: +86-21-6335-1560 Fax: +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road
Tsimshatsui, Kowloon
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Hong Kong
Tel: +852-2377-0226 Fax: +852-2376-3269
http://cn.fujitsu.com/fmc/tw
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited Business & Media Promotion Dept.
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