MB90F334APMC_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13734-1E

16-bit Proprietary Microcontroller

CMOS

F²MC-16LX MB90330 Series

MB90333A/F334A/V330A

■ DESCRIPTION

The MB90330 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral

devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but

also Mini-HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices

such as displays and audio devices, and control of mobile devices that support USB communications. While

inheriting the AT architecture of the F²MC* family, the instruction set supports the C language and extended

addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial

collection of improved bit manipulation instructions. In addition, long word processing is now available by intro-

ducing a 32-bit accumulator.

* : F²MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

■ FEATURES

• Clock

• Built-in oscillation circuit and PLL clock frequency multiplication circuit

• Oscillation clock

• The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)

• Clock for USB is 48 MHz

• Machine clock frequency of 6 MHz, 12 MHz, or 24 MHz selectable

• Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock

24 MHz and at operating V^CC= 3.3 V.

(Continued)

■ PACKAGES

120-pin Plastic LQFP

(FPT-120P-M05)

(FPT-120P-M21)

MB90330 Series

(Continued)

• The maximum memory space : 16 MB

• 24-bit addressing

• Bank addressing

• Instruction system

• Data types : Bit, Byte, Word and Long word

• Addressing mode (23 types)

• Enhanced high-precision computing with 32-bit accumulator

• Enhanced Multiply/Divide instructions with sign and the RETI instruction

• Instruction system compatible with high-level language (C language) and multi-task

• Employing system stack pointer

• Instruction set symmetry and barrel shift instructions

• Program Patch Function (2 address pointer)

• 4-byte instruction queue

• Interrupt function

• Priority levels are programmable

• 32 interrupts function

• Data transfer function

• Extended intelligent I/O service function (EI²OS) : Maximum of 16 channels

• µDMAC : Maximum 16 channels

• Low Power Consumption Mode

• Sleep mode (with the CPU operating clock stopped)

• Time-base timer mode (with the oscillator clock and time-base timer operating)

• Stop mode (with the oscillator clock stopped)

• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)

• Watch mode (with 32 kHz oscillator clock and watch timer operating)

• Package

• LQFP-120P (FPT-120P-M05 : 0.40 mm pin pitch)

• LQFP-120P (FPT-120P-M21 : 0.50 mm pin pitch)

• Process : CMOS technology

• Operation guaranteed temperature : − 40 °C to + 85 °C (0 °C to + 70 °C when USB is in use)

2

MB90330 Series

■ INTERNAL PERIPHERAL FUNCTION (RESOURCE)

• I/O port : Max 94 ports

• Time-base timer : 1 channel

• Watchdog timer : 1 channel

• Watch timer : 1channel

• 16-bit reload timer : 3 channels

• Multi-functional timer

• 16-bit free run timer : 1 channel

• Output compare : 4 channels

An interrupt request can be output when the 16-bit free-run timer value matches the compare register value.

• Input capture : 4channels

Upon detection of the effective edge of the signal input to the external input pin, the input capture unit sets the

input capture data register to the 16-bit free-run timer value to output an interrupt request.

• 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) the period and duty of the output pulse can be

set by the program.

• 16-bit PWC timer : 1 channel

Timer function and pulse width measurement function

• UART : 4 channels

• Full-duplex double buffer (8-bit length)

• Asynchronous transfer or clock-synchronous serial (I/O extended serial) transfer can be set.

• I/O extended serial interface : 1 channel

• DTP/External interrupt circuit (8 channels)

• Activate the extended intelligent I/O service by external interrupt input

• Interrupt output by external interrupt input

• Delay interrupt output module

• Output an interrupt request for task switching

• 8/10-bit A/D converter : 16 channels

• 8-bit resolution or 10-bit resolution can be set.

• USB : 1 channel

• USB function (conform to USB2.0 Full Speed)

• Full Speed is supported/Endpoint are specifiable up to six.

• Dual port RAM (The FIFO mode is supported).

• Transfer type : Control, Interrupt, Bulk, or Isochronous transfer possible

• USB Mini-HOST function

• I²C* Interface : 3 channels

• Supports Intel SM bus standard and Phillips I²C bus standards

• Two-wire data transfer protocol specification

• Master and slave transmission/reception

* : I²C license :

Purchase of Fujitsu I²C components conveys a license under the Philips I²C Patent Rights to use, these

components in an I²C system provided that the system conforms to the I²C Standard Specification as defined

by Philips.

3

MB90330 Series

■ PRODUCT LINEUP

Part number

Type

MB90V330A

For evaluation

No

MB90F334A

Built-in Flash memory

384 KB

MB90333A

Built-in Mask ROM

256 KB

ROM capacity

RAM capacity

28 KB

24 KB

16 KB

Emulator-specific power supply *

Used bit

⎯

Number of basic instructions : 351 instructions

Minimum instruction

execution time

: 41.6 ns/at oscillation of 6 MHz

(When 4 times are used : Machine clock of

24 MHz)

CPU functions

Addressing type

: 23 types

Program Patch Function

Maximum memory space

: For 2 address pointers

: 16 MB

Ports

I/O Ports (CMOS) 94 ports

Equipped with full-duplex double buffer

Clock synchronous or asynchronous operation selectable

It can also be used for I/O serial

UART

Built-in special baud-rate generator

Built-in 4 channels

16-bit reload timer operation

Built-in 3 channels

16-bit reload timer

16-bit free run timer × 1 channel

Output compare × 4 channels

Input capture × 4 channels

Multi-functional timer

8/16-bit PPG timer (8-bit mode × 6 channels, 16-bit mode × 3 channels)

16-bit PWC timer × 1 channel

16 channels (input multiplex)

8/10-bit A/D converter

DTP/External interrupt

8-bit resolution or 10-bit resolution can be set.

Conversion time : 7.16 µs at minimum (24 MHz machine clock at maximum)

8 channels

Interrupt factor : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable

I²C

3 channels

1 channel

I/O extended serial interface

1 channel

USB

USB function (conform to USB2.0 Full Speed)

USB Mini-HOST function

External bus interface

For multi-bus/non-multi-bus

Withstand voltage of 5 V

16 ports (excluding VBUS and I/O for I²C)

Sleep mode/Time-base timer mode/Stop mode/CPU intermittent mode/

Watch mode

Low Power Consumption Mode

Process

CMOS

Operating voltage

3.3 V 0.3 V (at maximum machine clock 24 MHz)

* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the

MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.

4

MB90330 Series

■ PACKAGES AND PRODUCT MODELS

Package

MB90333A

MB90F334A

MB90V330A

FPT-120P-M05 (LQFP-0.40 mm)

FPT-120P-M21 (LQFP-0.50 mm)

PGA-299C-A01 (PGA)

: Yes × : No

×

Note : For detailed information on each package, see “■ PACKAGE DIMENSIONS”.

5

MB90330 Series

■ PIN ASSIGNMENT

(TOP VIEW)

P30/A00/TIN1

P31/A01/TOT1

P32/A02/TIN2

P33/A03/TOT2

P34/A04

1

2

3

4

5

6

7

8

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

RST

MD0

MD1

MD2

P55/HAK

P54/HRQ

P53/WRH

P52/WRL

P51/RD

P50/ALE

HCON

Vcc

HVP

HVM

Vss

Vcc

DVP

DVM

Vss

P35/A05

P36/A06

P37/A07

P40/A08/TIN0

P41/A09/TOT0

P42/A10/SIN0

P43/A11/SOT0

X0A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

X1A

Vcc

Vss

P44/A12/SCK0

P45/A13/SIN1

P46/A14/SOT1

P47/A15/SCK1

P60/INT0

VBUS

PB6/PPG5

PB5/PPG4

PB4

PB3/SDA2

PB2/SCL2

PB1/SDA1

PB0/SCL1

PA7/OUT3

PA6/OUT2

PA5/OUT1

P61/INT1

P62/INT2/SIN

P63/INT3/SOT

P64/INT4/SCK

P65/INT5/PWC

P66/INT6/SCL0

P67/INT7/SDA0

P90/SIN2

P91/SOT2

(FPT-120P-M05 / FPT-120P-M21)

6

MB90330 Series

■ PIN DESCRIPTION

Pin no.

Pin name

LQFP

Circuit

type*

Function

Terminals to connect the oscillator.

108, 107

X0, X1

A

When connecting an external clock, leave the X1 pin side unconnected.

13, 14

90

X0A, X1A

RST

A

F

32 kHz oscillation terminals.

External reset input pin.

General purpose input/output port.

The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1)

by the pull-up resistor setting register (RDR0). (When the power output is

set, it is invalid.)

P00 to P07

93 to 100

101 to 104

109 to 112

H

Function as an I/O pin for the low-order external address and data bus in

multiplex mode.

AD00 to AD07

D00 to D07

Function as an output pin for the low-order external data bus in non-

multiplex mode.

General purpose input/output port.

The ports can be set to be added with a pull-up resistor (RD10 to RD13 = 1)

by the pull-up resistor setting register (RDR1). (When the power output is

set, it is invalid.)

P10 to P13

Function as an I/O pin for the high-order external address and data bus in

multiplex mode.

AD08 to AD11

D08 to D11

Function as an output pin for the high-order external data bus in non-

multiplex mode.

General purpose input/output port.

The ports can be set to be added with a pull-up resistor (RD14 to RD17 = 1)

by the pull-up resistor setting register (RDR1). (When the power output is

set, it is invalid.)

P14 to P17

Function as an I/O pin for the high-order external address and data bus in

multiplex mode.

AD12 to D15

D12 to D15

Function as an output pin for the high-order external data bus in non-

multiplex mode.

This is a general purpose I/O port. When the bits of external address output

control register (HACR) are set to “1” in external bus mode, these pins

function as general purpose I/O ports.

P20 to P23

A16 to A19

When the bits of external address output control register (HACR) are set to

“0” in multiplex mode, these pins function as address high output pins (A16

to A19).

113 to 116

D

When the bits of external address output control register (HACR) are set to

“0” in non-multiplex mode, these pins function as address high output pins

(A16 to A19).

(Continued)

7

MB90330 Series

Pin no.

LQFP

Circuit

type*

Pin name

Function

This is a general purpose I/O port. When the bits of external address

output control register (HACR) are set to “1” in external bus mode, these

pins function as general purpose I/O ports.

P24 to P27

When the bits of external address output control register (HACR) are set

to “0” in multiplex mode, these pins function as address high output pins

(A20 to A23).

A20 to A23

117 to 120

D

When the bits of external address output control register (HACR) are set

to “0” in non-multiplex mode, these pins function as address high output

pins (A20 to A23).

PPG0 to PPG3

P30

Function as ch0 to ch3 output pins for the 8-bit PPG timer.

General purpose input/output port.

1

2

3

A00

D

Function as the external address pin in non-multi-bus mode.

Function as an event input pin for 16-bit reload timer ch1.

General purpose input/output port.

TIN1

P31

A01

Function as the external address pin in non-multi-bus mode.

Function as the output pin for 16-bit reload timer ch1.

General purpose input/output port.

TOT1

P32

A02

Function as the external address pin in non-multi-bus mode.

Function as an event input pin for 16-bit reload timer ch2.

General purpose input/output port.

TIN2

P33

4

5 to 8

9

A03

D

G

Function as the external address pin in non-multi-bus mode.

Function as the output pin for 16-bit reload timer ch2.

General purpose input/output port.

TOT2

P34 to P37

A04 to A07

P40

Function as the external address pin in non-multi-bus mode.

General purpose input/output port.

A08

Function as the external address pin in non-multi-bus mode.

Function as an event input pin for 16-bit reload timer ch0.

General purpose input/output port.

TIN0

P41

10

11

12

17

A09

G

Function as the external address pin in non-multi-bus mode.

Function as the output pin for 16-bit reload timer ch0.

General purpose input/output port.

TOT0

P42

A10

Function as the external address pin in non-multi-bus mode.

Function as a data input pin for UART ch0.

SIN0

P43

General purpose input/output port.

A11

Function as the external address pin in non-multi-bus mode.

Function as a data output pin for UART ch0.

General purpose input/output port.

SOT0

P44

A12

Function as the external address pin in non-multi-bus mode.

Function as a clock I/O pin for UART ch0.

SCK0

(Continued)

8

MB90330 Series

Pin no.

LQFP

Circuit

type*

Pin name

Function

General purpose input/output port.

P45

A13

SIN1

P46

A14

SOT1

P47

A15

SCK1

P50

ALE

P51

RD

18

19

20

G

Function as the external address pin in non-multi-bus mode.

Function as a data input pin for UART ch1.

General purpose input/output port.

Function as the external address pin in non-multi-bus mode.

Function as a data output pin for UART ch1.

General purpose input/output port.

Function as the external address pin in non-multi-bus mode.

Function as a clock I/O pin for UART ch1.

General purpose input/output port.

81

82

L

Function as the address latch enable signal (ALE) pin in external bus mode.

General purpose input/output port.

Function as the read strobe output (RD) pin in external bus mode.

General purpose input/output port.

P52

Function as the data write strobe output (WRL) pin on the lower side in

external bus mode. This pin functions as a general-purpose I/O port when

the WRE bit in the EPCR register is “0”.

83

84

85

86

91

L

WRL

P53

General purpose input/output port.

Function as the data write strobe output (WRH) pin on the higher side in bus

width 16-bit external bus mode. This pin functions as a general-purpose

I/O port when the WRE bit in the EPCR register is “0”.

WRH

P54

General purpose input/output port.

Function as the hold request input (HRQ) pin in external bus mode. This pin

functions as a general-purpose I/O port when the HDE bit in the EPCR

register is “0”.

HRQ

P55

General purpose input/output port.

Function as the hold acknowledge output (HAK) pin in external bus mode.

This pin functions as a general-purpose I/O port when the HDE bit in the

EPCR register is “0”.

HAK

P56

General purpose input/output port.

Function as the external ready input (RDY) pin in external bus mode. This

pin functions as a general-purpose I/O port when the RYE bit in the EPCR

register is “0”.

RDY

P57

General purpose input/output port.

Function as the machine cycle clock output (CLK) pin in external bus mode.

This pin functions as a general-purpose I/O port when the CKE bit in the

EPCR register is “0”.

92

L

CLK

P60, P61

General purpose input/output port. (With stand voltage of 5 V)

Function as external interrupt ch0 and ch1 input pins.

(Continued)

21, 22

C

INT0, INT1

9

MB90330 Series

Pin no.

LQFP

Circuit

type*

Pin name

Function

P62

INT2

SIN

General purpose input/output ports. (Withstand voltage of 5 V)

Function as an external interrupt ch2 input pin.

Simple serial I/O data input pin.

23

24

25

26

C

P63

General purpose input/output port. (Withstand voltage of 5 V)

Function as an external interrupt ch3 input pin.

Simple serial I/O data output pin.

INT3

SOT

P64

General purpose input/output port. (Withstand voltage of 5 V)

Function as an external interrupt ch4 input pin.

Simple serial I/O clock input/output pin.

INT4

SCK

P65

General purpose input/output port. (Withstand voltage of 5 V)

Function as an external interrupt ch5 input pin.

Function as the PWC input pin.

INT5

PWC

P66

General purpose input/output port. (Withstand voltage of 5 V)

Function as an external interrupt ch6 input pin.

Function as the ch0 clock I/O pin for the I²C interface. Set port output to High-Z

during I²C interface operations.

INT6

27

28

C

SCL0

P67

General purpose input/output port. (Withstand voltage of 5 V)

Function as an external interrupt ch7 input pin.

Function as the ch0 data I/O pin for the I²C interface. Set port output to High-Z

during I²C interface operations.

INT7

SDA0

P70 to P77

AN0 to AN7

P80 to P87

AN8 to AN15

P90

General purpose input/output port.

39 to 46

48 to 55

29

I

Function as input pins for analog ch0 to ch7.

General purpose input/output port.

I

Function as input pins for analog ch8 to ch15.

General purpose input/output port.

D

SIN2

Function as a data input pin for UART ch2.

General purpose input/output port.

P91

30

SOT2

P92

Function as a data output pin for UART ch2.

General purpose input/output port.

31

SCK2

P93

Function as a clock I/O pin for UART ch2.

General purpose input/output port.

32

SIN3

Function as a data input pin for UART ch3.

General purpose input/output port.

P94

33

SOT3

P95

Function as a data output pin for UART ch3.

General purpose input/output port.

34

SCK3

P96

Function as a clock I/O pin for UART ch3.

General purpose input/output port. (Withstand voltage of 5 V)

Function as the external trigger input pin when the A/D converter is being used.

Function as the external clock input pin when the free-run timer is being used.

35

ADTG

FRCK

C

(Continued)

10

MB90330 Series

Pin no.

LQFP

Circuit

type*

Pin name

Function

PA0 to PA3

IN0 to IN3

PA4 to PA7

OUT0 to OUT3

PB0

General purpose input/output port. (Withstand voltage of 5 V)

Function as the input capture ch0 to ch3 trigger inputs.

General purpose input/output port. (Withstand voltage of 5 V)

Function as the output compare ch0 to ch3 event output pins.

General purpose input/output port. (Withstand voltage of 5 V)

56 to 59

60 to 63

C

Function as the ch1 clock I/O pin for the I²C interface. Set port output to

High-Z during I²C interface operations.

64

65

66

67

C

SCL1

PB1

General purpose input/output port. (Withstand voltage of 5 V)

Function as the ch1 data I/O pin for the I²C interface. Set port output to High-Z

during I²C interface operations.

SDA1

PB2

General purpose input/output port. (Withstand voltage of 5 V)

Function as the ch2 clock I/O pin for the I²C interface. Set port output to High-Z

during I²C interface operations.

SCL2

PB3

General purpose input/output port. (Withstand voltage of 5 V)

Function as the ch2 data I/O pin for the I²C interface. Set port output to High-Z

during I²C interface operations.

SDA2

68

PB4

PB5, PB6

PPG4, PPG5

VBUS

DVM

C

D

General purpose input/output port. (Withstand voltage of 5 V)

General purpose input/output port.

Function as ch4 and ch5 output pins for the 8-bit PPG timer.

Terminal for state detection of USB cable. (Withstand voltage of 5 V)

USB function D− pin.

69, 70

71

73

74

77

78

80

36

37

38

C

K

DVP

K

USB function D+ pin.

HVM

K

USB Mini-HOST D− pin.

HVP

K

USB Mini-HOST D+ pin.

HCON

AVcc

E

External pull-up resistor connect pin.

A/D converter power supply pin.

A/D converter external reference power supply pin.

A/D converter power supply pin.

Operation mode select input pin.

Power supply pin.

⎯

J

AVRH

AVss

⎯

B

87 to 89 MD2 to MD0

15

75

Vcc

Vss

⎯

Power supply pin.

79

Power supply pin.

105

16

Power supply pin.

Power supply pin (GND).

47

Power supply pin (GND).

72

Power supply pin (GND).

76

Power supply pin (GND).

106

Power supply pin (GND).

* : For circuit information, see “■ I/O CIRCUIT TYPE”.

11

MB90330 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• High-rateoscillationfeedbackresistor,

approx.1 MΩ

• Low-rate oscillation feedback resistor,

X1

Clock input

X1A

X0

A

approx.10 MΩ

• With standby control

X0A

Standby control signal

• CMOS hysteresis input

B

C

Hysteresis input

• CMOS hysteresis input

• Nch open drain output

Nch

Nout

Hysteresis input

Standby control signal

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Pch

Nch

Pout

Nout

Notes : • Share one output buffer because

both output of I/O port and

internal resource are used.

• Share one input buffer because

both input of I/O port and internal

resource are used.

D

Hysteresis input

Standby control signal

• CMOS output

Pch

Nch

Pout

E

F

Nout

• CMOS hysteresis input with pull-up

resistor

R

Hysteresis input

(Continued)

12

MB90330 Series

Type

Circuit

Remarks

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

Open drain control

signal

Pch

Nch

Pout

With open drain control signal

Nout

G

Hysteresis input

Standby control

signal

• CMOS output

• CMOS input

CTL

(With input interception function at

standby)

• With input pull-up register control

R

Pch

Nch

Pout

Nout

H

CMOS input

Standby control signal

• CMOS output

• CMOS hysteresis input

(With input interception function at

standby)

• Analog input

Pch

Nch

Pout

Nout

(TheA/Dconverteranaloginputisenabled

when the corresponding bit in the analog

input enable register (ADER) is 1.)

Notes: • Because the output of the I/O port and

the output of internal resources are

used combinedly, one output buffer

is shared.

I

Hysteresis input

Standby control signal

A/D converter analog

input

• Because the input of the I/O port

and the input of internal resources

are used combinedly, one input

buffer is shared.

• A/D converter (AVRH) voltage input pin

Pch

Nch

Pch

Nch

AVRH input

J

A/D converter

analog input

enable signal

(Continued)

13

MB90330 Series

(Continued)

Type

Circuit

Remarks

• USB I/O pin

D + input

D - input

+

D

Differential input

Full D + output

−

D

Full D - output

K

Low D + output

Low D - output

Direction

Speed

• CMOS output

• CMOS input

• With standby control

Pch

Nch

Pout

Nout

L

CMOS input

Standby control signal

14

MB90330 Series

■ HANDLING DEVICES

1. Preventing latchup and turning on power supply

Latchup may occur on CMOS IC under the following conditions:

• If a voltage higher than V^CCor lower than V^SSis applied to input and output pins.

• A voltage higher than the rated voltage is applied between V^CCand V^SS.

• If the AV^CCpower supply is turned on before the V^CCvoltage.

Ensure that you apply a voltage to the analog power supply at the same time as V^CCor after you turn on the

digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as

V^CCand the digital power supply).

If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device.

Use meticulous care not to let any voltage exceed the maximum rating.

2. Treatment of unused pins

Leavingunusedinputpinsunconnectedcancauseabnormaloperationorlatchup,leadingtopermanentdamage.

Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/

output pins may be set to output mode and left open, or set to input mode and treated the same as unused input

pins. If there is unused output pin, make it to open.

3. Treatment of power supply pins on models with A/D converters

Even when the A/D converters are not in use, be sure to make the necessary connections AV^CC= AVRH = V^CC,

and AV^SS= V^SS.

4. About the attention when the external clock is used

• Using external clock

X0

OPEN

X1

5. Treatment of power supply pins (V^CC/V^SS)

In products with multiple V^CCor V^SSpins, the pins of the same potential are internally connected in the device

to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply

and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals

caused by the rise in the ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with the V^CCand V^SSpins of this device at the low impedance.

It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between V^CCand V^SSnear

this device.

6. About Crystal oscillator circuit

Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit

board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass

capacitor to ground are located as close to the device as possible.

It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded

by ground plane because stable operation can be expected with such a layout.

15

MB90330 Series

7. Caution on Operations during PLL Clock Mode

Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the

microcontroller may continue to operate at the free-running frequency of the PLL internal automatic oscillator

circuit. Performance of this operation, however, cannot be guaranteed.

8. Stabilization of supply voltage

A sudden change in the supply voltage may cause the device to malfunction even within the V^CCsupply voltage

operating range. For stabilization reference, the supply voltage should be stabilized so that V^CCripple variations

(peak-to-peak value) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard V^CCsupply

voltage and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply

switching.

9. When the dual-supply is used as a single-supply device

If you are using only a single-system of the MB90330 series that come in the dual-system product, use it with

X0A = VSS : X1A = OPEN.

10. Writing to flash memory

For serial writing to flash memory, always make sure that the operating voltage V^CCis between 3.13 V and 3.6 V.

For normal writing to flash memory, always make sure that the operating voltage V^CCis between 3.0 V and 3.6 V.

16

MB90330 Series

■ BLOCK DIAGRAM

X0, X1

X0A,X1A

RST

Clock control

circuit

F²MC-16LX

CPU

MD0 to MD2

Interrupt

controller

8/16-bit

PPG0 to PPG5

PPG timer

ch0 to ch5*

RAM

ROM

Input capture

ch0 to ch3

IN0 to IN3

FRCK

SIN0 to SIN3

SOT0 to SOT3

SCK0 to SCK3

UART/SIO

ch0 to ch3

I²C

ch0 to ch2

SCL0 to SCL2

SDA0 to SDA2

16-bit free-run

timer

AVCC

AVRH

AVSS

8/10-bit A/D

converter

AN0 to AN15

ADTG

Output compare

ch0 to ch3

OUT0 to OUT3

PWC

16-bit reload

timer

ch0 to ch2

TOT0 to TOT2

TIN0 to TIN2

16-bit PWC

DVP

DVM

HVP

HVM

HCON

VBUS

SIN

SOT

SCK

USB

(Function)

(Mini-HOST)

SIO

µDMAC

External

interrupt

INT0 to INT7

I/O port (port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)

PB0

PB6

P80 P90 PA0

P87 P96 PA7

P00 P10 P20 P30 P40 P50 P60 P70

P07 P17 P27 P37 P47 P57 P67 P77

* : Channel for use in 8-bit mode. 3 channels (ch1, ch3, ch5) are used in 16-bit mode.

Note : I/O ports share pins with peripheral function (resources) .

For details, see “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.

Note also that pins used for peripheral function (resources) cannot serve as I/O ports.

17

MB90330 Series

■ MEMORY MAP

Single chip mode (with ROM mirror function)

MB90V330A

MB90333A

MB90F334A

FFFFFFH

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

ROM (FE bank)

FF0000H

FEFFFFH

FF0000H

FEFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FE0000H

FDFFFFH

FE0000H

FDFFFFH

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (F8 bank)

ROM (FD bank)

FD0000H

FCFFFFH

FD0000H

FCFFFFH

FD0000H

FCFFFFH

FC0000H

FBFFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

FC0000H

FBFFFFH

FC0000H

FBFFFFH

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (FB bank)

FB0000H

FAFFFFH

FA0000H

F9FFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

F90000H

F8FFFFH

F90000H

F8FFFFH

F90000H

F8FFFFH

F80000H

00FFFFH

ROM

(image of FF bank)

008000H

007FFFH

008000H

007FFFH

008000H

007FFFH

Peripheral area

007900H

007100H

006100H

004100H

RAM area

(28KB)

RAM area

(24KB)

RAM area

(16KB)

Register

000100H

0000FBH

000100H

0000FBH

000100H

0000FBH

Peripheral area

000000H

Memory map of MB90330 series (1/3)

18

MB90330 Series

Internal ROM external bus mode (with ROM mirror function)

MB90V330A

MB90333A

MB90F334A

FFFFFFH

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

ROM (FE bank)

ROM (FF bank)

ROM (FE bank)

FF0000H

FEFFFFH

FF0000H

FEFFFFH

FF0000H

FEFFFFH

FE0000H

FDFFFFH

FE0000H

FDFFFFH

FE0000H

FDFFFFH

ROM (FD bank)

ROM (FC bank)

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (F8 bank)

ROM (FD bank)

FD0000H

FCFFFFH

FD0000H

FCFFFFH

FD0000H

FCFFFFH

1

2

FC0000H

FBFFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

FC0000H

FBFFFFH

FC0000H

FBFFFFH

ROM (FB bank)

ROM (FA bank)

ROM (F9 bank)

ROM (FB bank)

FB0000H

FAFFFFH

FA0000H

F9FFFFH

FB0000H

FAFFFFH

FA0000H

F9FFFFH

External area

F90000H

F8FFFFH

F90000H

F8FFFFH

F90000H

F8FFFFH

F80000H

External area

00FFFFH

ROM

(image of FF bank)

008000H

007FFFH

008000H

007FFFH

008000H

007FFFH

Peripheral area

External area

Peripheral area

External area

Peripheral area

External area

007900H

007100H

006100H

004100H

RAM area

(28KB)

RAM area

(24KB)

RAM area

(16KB)

Register

000100H

0000FBH

000100H

0000FBH

000100H

0000FBH

Peripheral area

000000H

*1 : In the area of F80000^Hto F8FFFF^Hand FC0000^Hto FCFFFF^Hat MB90F334, a value of “1” is read at

read operating.

*2 : In the area of FA0000^Hto FAFFFF^Hand FC0000^Hto FCFFFF^Hat MB90333, a value of “1” is read at

read operating.

Memory map of MB90330 series (2/3)

19

MB90330 Series

External ROM external bus mode

MB90V330A

MB90333A

MB90F334A

FFFFFF

H

FFFFFF

H

FFFFFFH

External area

008000

007FFF^H

008000

007FFF^H

008000

007FFF^H

H

Peripheral area

External area

Peripheral area

External area

Peripheral area

External area

007900

H

007900

H

007900H

007100

H

006100

H

RAM area

(28KB)

004100H

RAM area

(24KB)

RAM area

(16KB)

Register

000100

H

000100

H

000100

H

0000FB

Peripheral area

000000

H

000000

H

000000

H

Memory map of MB90330 series (3/3)

Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses

(“FF8000^Hto FFFFFF^H”) of bank FF is visible from the higher addresses (“008000^Hto 00FFFF^H”) of

bank 00.

• The ROM mirror function is effective for using the C compiler small model.

• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in

bank FF exceeds 48 KB, however, the mirror image of all the data in the ROM area cannot be

reproduced in bank 00.

• When the C compiler small model is used, the data table mirror image can be shown at “008000^Hto

00FFFF^H” by storing the data table at “FF8000^Hto FFFFFF^H”. Therefore, data tables in the ROM

area can be referred without declaring the far addressing with the pointer.

20

MB90330 Series

■ F²MC^-16L CPU PROGRAMMING MODEL

• Dedicated register

AH

AL

Accumulator

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

DPR

Direct page register

Program bank register

Data bank register

PCB

DTB

USB

SSB

ADB

User stack bank register

System stack bank register

Additional data bank register

8-bit

16-bit

32-bit

• General purpose register

MSB

LSB

16-bit

000180^H+ RP × 10H

RW0

RW1

RW2

RW3

RL0

RL1

RL2

RL3

R1

R3

R5

R7

R0

R2

R4

R6

RW4

RW5

RW6

RW7

• Processor status

Bit 15

13 12

ILM

8 7

0

PS

RP

CCR

21

MB90330 Series

■ I/O MAP

Register

Address

Read/

Write

Register

Port 0 Data Register

Resource name

Initial Value

abbreviation

000000^H

000001^H

000002^H

000003^H

000004^H

000005^H

000006^H

000007^H

000008^H

000009^H

00000A^H

00000B^H

00000C^H

00000D^H

00000E^H

00000F^H

000010^H

000011^H

000012^H

000013^H

000014^H

000015^H

000016^H

000017^H

000018^H

000019^H

00001A^H

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

PDR8

PDR9

PDRA

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

XXXXXXXX^B

- XXXXXXX^B

XXXXXXXX^B

Port 1 Data Register

Port 2 Data Register

Port 3 Data Register

Port 4 Data Register

Port 5 Data Register

Port 6 Data Register

Port 7 Data Register

Port 8 Data Register

Port 9 Data Register

Port A Data Register

Prohibited

PDRB

DDRB

Port B Data Register

R/W

Port B

- XXXXXXX^B

Port B Direction Register

- 0 0 0 0 0 0 0^B

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

DDR8

DDR9

DDRA

Port 0 Direction Register

Port 1 Direction Register

Port 2 Direction Register

Port 3 Direction Register

Port 4 Direction Register

Port 5 Direction Register

Port 6 Direction Register

Port 7 Direction Register

Port 8 Direction Register

Port 9 Direction Register

Port A Direction Register

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

0 0 0 0 0 0 0 0^B

- 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0^B

Port 4

(opendraincontrol)

00001B^H

ODR4

Port 4 Output Pin Register

R/W

0 0 0 0 0 0 0 0^B

00001C^H

00001D^H

00001E^H

00001F^H

000020^H

000021^H

RDR0

RDR1

Port 0 Pull-up Resistance Register

Port 1 Pull-up Resistance Register

Analog Input Enable Register 0

Analog Input Enable Register 1

Serial Mode Register ch0

R/W

R

Port 0 (PULL-UP) 0 0 0 0 0 0 0 0^B

Port 1 (PULL-UP) 0 0 0 0 0 0 0 0^B

ADER0

ADER1

SMR0

Port 7, 8, A/D

1 1 1 1 1 1 1 1^B

0 0 1 0 0 0 0 0^B

0 0 0 0 0 1 0 0^B

SCR0

Serial Control Register ch0

SIDR0

SODR0

SSR0

Serial Input Data Register ch0

Serial Output Data Register ch0

Serial Status Register ch0

UART0

000022^H

XXXXXXXX^B

W

000023^H

000024^H

000025^H

R/W

0 0 0 0 1 0 0 0^B

0 0 0 0 0 0 0 0^B

0 0 0 0 - 0 0 0^B

UTRLR0

UTCR0

UART Prescaler Reload Register ch0

UART Prescaler Control Register ch0

Communication

Prescaler (UART0)

(Continued)

22

MB90330 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name

Initial Value

000026^H

000027^H

SMR1

SCR1

Serial Mode Register ch1

R/W

R

0 0 1 0 0 0 0 0^B

0 0 0 0 0 1 0 0^B

Serial Control Register ch1

SIDR1

SODR1

SSR1

Serial Input Data Register ch1

Serial Output Data Register ch1

Serial Status Register ch1

UART1

000028^H

XXXXXXXX^B

W

000029^H

00002A^H

00002B^H

00002C^H

00002D^H

R/W

R

0 0 0 0 1 0 0 0^B

0 0 0 0 0 0 0 0^B

0 0 0 0 - 0 0 0^B

0 0 1 0 0 0 0 0^B

0 0 0 0 0 1 0 0^B

UTRLR1

UTCR1

SMR2

UART Prescaler Reload Register ch1

UART Prescaler Control Register ch1

Serial Mode Register ch2

Communication

Prescaler (UART1)

SCR2

Serial Control Register ch2

SIDR2

SODR2

SSR2

Serial Input Data Register ch2

Serial Output Data Register ch2

Serial Status Register ch2

UART2

00002E^H

XXXXXXXX^B

W

00002F^H

000030^H

000031^H

000032^H

000033^H

R/W

R

0 0 0 0 1 0 0 0^B

0 0 0 0 0 0 0 0^B

0 0 0 0 - 0 0 0^B

0 0 1 0 0 0 0 0^B

0 0 0 0 0 1 0 0^B

UTRLR2

UTCR2

SMR3

UART Prescaler Reload Register ch2

UART Prescaler Control Register ch2

Serial Mode Register ch3

Communication

Prescaler (UART2)

SCR3

Serial Control Register ch3

SIDR3

SODR3

SSR3

Serial Input Data Register ch3

Serial Output Data Register ch3

Serial Status Register ch3

UART3

000034^H

XXXXXXXX^B

W

000035^H

000036^H

000037^H

R/W

0 0 0 0 1 0 0 0^B

0 0 0 0 0 0 0 0^B

0 0 0 0 - 0 0 0^B

UTRLR3

UTCR3

UART Prescaler Reload Register ch3

UART Prescaler Control Register ch3

Communication

Prescaler (UART3)

000038^H

to

Prohibited

00003B^H

00003C^H

00003D^H

00003E^H

00003F^H

000040^H

000041^H

000042^H

000043^H

000044^H

ENIR

EIRR

DTP/Interrupt Enable Register

DTP/Interrupt Source Register

Request Level Setting Register Lower

Request Level Setting Register Upper

A/D Control Status Register Lower

A/D Control Status Register Upper

A/D Data Register Lower

R/W

0 0 0 0 0 0 0 0^B

0 0 - - - - - 0^B

DTP/External

Interrupt

ELVR

ADCS0

ADCS1

ADCR0

ADCR1

0 0 0 0 0 0 0 0^B

XXXXXXXX^B

8/10-bit

A/D Converter

A/D Data Register Upper

0 0 1 0 1 XXX^B

Prohibited

A/D Conversion Channel Selection

Register

8/10-bit

A/D Converter

000045^H

000046^H

000047^H

000048^H

ADMR

PPGC0

PPGC1

PPGC2

R/W

0 0 0 0 0 0 0 0^B

0X0 0 0XX1^B

0X0 0 0 0 0 1^B

PPG0 Operation Mode Control

Register

PPG ch0

PPG ch1

PPG ch2

PPG1 Operation Mode Control

Register

PPG2 Operation Mode Control

Register

0X0 0 0XX1^B

(Continued)

23

MB90330 Series

Register

Address

Read/

Write

Register

Resource name Initial Value

abbreviation

000049^H

00004A^H

00004B^H

PPGC3

PPGC4

PPGC5

PPG3 Operation Mode Control Register R/W

PPG4 Operation Mode Control Register R/W

PPG5 Operation Mode Control Register R/W

PPG ch3

PPG ch4

PPG ch5

0X0 0 0 0 0 1^B

0X0 0 0XX1^B

0X0 0 0 0 0 1^B

PPG0 and PPG1 Output Control

Register

00004C^H

00004D^H

00004E^H

00004F^H

000050^H

000051^H

000052^H

PPG01

PPG23

PPG45

R/W

PPG ch0/1

PPG ch2/3

PPG ch4/5

0 0 0 0 0 0XX^B

0 0 0 0 0 0 XX^B

Prohibited

PPG2 and PPG3 Output Control

Register

R/W

Prohibited

PPG4 and PPG5 Output Control

Register

R/W

Prohibited

Input Capture

ch0/1

ICS01

ICS23

OCS0

OCS1

OCS2

OCS3

Input Capture Control Status Register 01 R/W

0 0 0 0 0 0 0 0^B

0 0 0 0 - - 0 0^B

- - - 0 0 0 0 0^B

0 0 0 0 - - 0 0^B

- - - 0 0 0 0 0^B

Input

Capture ch2/3

000053^H

000054^H

000055^H

000056^H

000057^H

Input Capture Control Status Register 23 R/W

Output Compare Control Register ch0

Lower

R/W

Output

Compare ch0/1

Output Compare Control Register ch1

Upper

R/W

Output Compare Control Register ch2

Lower

R/W

Output

Compare ch2/3

Output Compare Control Register ch3

Upper

R/W

000058^H

000059^H

00005A^H

XXXX0 0 0 0^B

0 0 0 0 0 0 1 0^B

XXXXXXXX^B

SMCS

Serial Mode Control Status Register

Serial Data Register

R/W

Extended Serial

I/O

SDR

R/W

Communication Prescaler Control

Register

Communication

Prescaler

00005B^H

SDCR

0XXX0 0 0 0^B

00005C^H

00005D^H

00005E^H

00005F^H

000060^H

000061^H

000062^H

000063^H

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 X^B

0 0 0 0 0 0 0 0^B

- - - - - - 0 0^B

PWCSR

PWC Control Status Register

R/W

16-bit

PWC Timer

PWCR

DIVR

PWC Data Buffer Register

PWC Dividing Ratio Register

R/W

Prohibited

0 0 0 0 0 0 0 0^B

XXXX 0 0 0 0^B

XXXXXXXX^B

TMCSR0

Timer Control Status Register ch0

R/W

TMR0

TMRLR0

TMR0

16-bit Timer Register ch0 Lower

16-bit Reload Register ch0 Lower

16-bit Timer Register ch0 Upper

16-bit Reload Register ch0 Upper

R

W

R

16-bit

Reload Timer ch0

000064^H

000065^H

TMRLR0

W

(Continued)

24

MB90330 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name

Initial Value

000066^H

000067^H

0 0 0 0 0 0 0 0^B

XXXX 0 0 0 0^B

XXXXXXXX^B

0 0 0 0 0 0 0 0^B

XXXX 0 0 0 0^B

XXXXXXXX^B

TMCSR1

Timer Control Status Register ch1

R/W

TMR1

TMRLR1

TMR1

16-bit Timer Register ch1 Lower

16-bit Reload Register ch1 Lower

16-bit Timer Register ch1 Upper

16-bit Reload Register ch1 Upper

R

W

R

16-bit Reload

Timer ch1

000068^H

000069^H

TMRLR1

W

00006A^H

00006B^H

TMCSR2

Timer Control Status Register ch2

R/W

TMR2

TMRLR2

TMR2

16-bit Timer Register ch2 Lower

16-bit Reload Register ch2 Lower

16-bit Timer Register ch2 Upper

16-bit Reload Register ch2 Upper

R

W

R

16-bit Reload

Timer ch2

00006C^H

00006D^H

00006E^H

TMRLR2

W

Prohibited

ROM Mirror

Function

Selection Module

ROM Mirror Function Selection

Register

00006F^H

ROMM

W

- - - - - - 1 1^B

000070^H

000071^H

000072^H

000073^H

000074^H

000075^H

000076^H

000077^H

000078^H

000079^H

00007A^H

00007B^H

00007C^H

00007D^H

00007E^H

00007F^H

000080^H

IBSR0

IBCR0

ICCR0

IADR0

IDAR0

I²C Bus Status Register ch0

I²C Bus Control Register ch0

I²C Bus Clock Selection Register ch0

I²C Bus Address Register ch0

I²C Bus Data Register ch0

Prohibited

I²C Bus Status Register ch1

I²C Bus Control Register ch1

I²C Bus Clock Selection Register ch1

I²C Bus Address Register ch1

I²C Bus Data Register ch1

Prohibited

I²C Bus Status Register ch2

I²C Bus Control Register ch2

I²C Bus Clock Selection Register ch2

I²C Bus Address Register ch2

I²C Bus Data Register ch2

R

0 0 0 0 0 0 0 0^B

XX 0 XXXXX^B

XXXXXXXX^B

R/W

I²C Bus Interface

ch0

IBSR1

IBCR1

ICCR1

IADR1

IDAR1

R

0 0 0 0 0 0 0 0^B

XX 0 XXXXX^B

XXXXXXXX^B

R/W

I²C Bus Interface

ch1

IBSR2

IBCR2

ICCR2

IADR2

IDAR2

R

0 0 0 0 0 0 0 0^B

XX 0 XXXXX^B

XXXXXXXX^B

R/W

I²C Bus Interface

ch2

000081^H

to

Prohibited

000085^H

(Continued)

25

MB90330 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

000086^H

000087^H

000088^H

000089^H

00008A^H

00008B^H

Timer Data Register Lower

R/W

0 0 0 0 0 0 0 0^B

0 - - 0 0 0 0 0^B

XXXXXXXX^B

TCDT

TCCS

Timer Data Register Upper

Timer Control Status Register Lower

Timer Control Status Register Upper

Compare Clear Register Lower

Compare Clear Register Upper

16-bit Free-Run

Timer

CPCLR

XXXXXXXX^B

00008C^H

to

Prohibited

00009A^H

DMA Descriptor Channel

Specification Register

00009B^H

DCSR

R/W

0 0 0 0 0 0 0 0^B

µDMAC

00009C^H

00009D^H

DSRL

DSRH

DMA Status Register Lower

DMA Status Register Upper

R/W

0 0 0 0 0 0 0 0^B

Program Address Detection Control

Status Register

Address Match

Detection

00009E^H

00009F^H

PACSR

DIRR

R/W

0 0 0 0 0 0 0 0^B

- - - - - - - 0^B

Delay Interruption Factor Generation/

Release Register

Delay Interrupt

Low Power

Consumption

Control Circuit

Low Power Consumption Mode

Register

0000A0^H

LPMCR

CKSCR

R/W

0 0 0 1 1 0 0 0^B

1 1 1 1 1 1 0 0^B

0000A1^H

0000A2^H

0000A3^H

0000A4^H

Clock Selection Register

Prohibited

Clock

DSSR

ARSR

DMA Stop Status Register

R/W

W

µDMAC

0 0 0 0 0 0 0 0^B

0 0 1 1- - 0 0^B

Automatic Ready Function Selection

Register

0000A5^H

0000A6^H

External Address Output Control

Register

External Pin

HACR

W

∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ^B

0000A7^H

0000A8^H

0000A9^H

0000AA^H

0000AB^H

0000AC^H

0000AD^H

EPCR

WDTC

TBTC

WTC

Bus Control Signal Control Register

Watchdog Control Register

Time-base Timer Control Register

Watch Timer Control Register

Prohibited

W

1 0 0 0 ∗ 1 0 -^B

Watchdog Timer X - XXX 1 1 1^B

Time-base Timer 1 - - 0 0 1 0 0^B

R/W

Watch Timer

1 0 0 0 1 0 0 0^B

DERL

DERH

DMA Enable Register Lower

DMA Enable Register Upper

R/W

0 0 0 0 0 0 0 0^B

µDMAC

Flash Memory Control Status

Register

Flash Memory

I/F

0000AE^H

0000AF^H

FMCR

R/W

0 0 0 X 0 0 0 0^B

Prohibited

(Continued)

26

MB90330 Series

Register

abbreviation

Read/

Write

Address

Register

Resource name

Initial Value

0000B0^H

0000B1^H

0000B2^H

0000B3^H

0000B4^H

0000B5^H

0000B6^H

0000B7^H

0000B8^H

0000B9^H

0000BA^H

0000BB^H

0000BC^H

0000BD^H

0000BE^H

0000BF^H

0000C0^H

0000C1^H

0000C2^H

0000C3^H

0000C4^H

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

HCNT0

HCNT1

HIRQ

Interrupt Control Register 00

Interrupt Control Register 01

Interrupt Control Register 02

Interrupt Control Register 03

Interrupt Control Register 04

Interrupt Control Register 05

Interrupt Control Register 06

Interrupt Control Register 07

Interrupt Control Register 08

Interrupt Control Register 09

Interrupt Control Register 10

Interrupt Control Register 11

Interrupt Control Register 12

Interrupt Control Register 13

Interrupt Control Register 14

Interrupt Control Register 15

USB Host Control Register 0

USB Host Control Register 1

USB Host Interruption Register

USB Host Error Status Register

USB Host State Status Register

R/W

0 0 0 0 0 1 1 1^B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 1^B

0 0 0 0 0 0 0 0^B

0 0 0 0 0 0 1 1^B

XX 0 1 0 0 1 0^B

Interrupt

Controller

HERR

HSTATE

USB SOF Interrupt FRAME Compare

Register

0000C5^H

HFCOMP

R/W

0 0 0 0 0 0 0 0^B

0000C6^H

0000C7^H

0000C8^H

0000C9^H

0000CA^H

0000CB^H

0000CC^H

0000CD^H

0000CE^H

0000CF^H

0000D0^H

0000D1^H

USB Retry Timer Setting Register 0

USB Retry Timer Setting Register 1

USB Retry Timer Setting Register 2

USB Host Address Register

USB EOF Setting Register 0

USB EOF Setting Register 1

USB FRAME Setting Register 0

USB FRAME Setting Register 1

USB Host Token End Point Register

Prohibited

R/W

0 0 0 0 0 0 0 0^B

XXXXXX 0 0^B

X 0 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0^B

XX 0 0 0 0 0 0^B

0 0 0 0 0 0 0 0^B

XXXXX 0 0 0^B

0 0 0 0 0 0 0 0^B

USB Mini-HOST

HRTIMER

HADR

HEOF

HFRAME

HTOKEN

UDCC

UDC Control Register

R/W

USB Function

1 0 1 0 0 0 0 0^B

Prohibited

(Continued)

27

MB90330 Series

Register

Address

Read/

Write

Register

Resource name

Initial Value

abbreviation

0000D2^H

R/W

R

X 1 0 0 0 0 0 0^B

XXXX 0 0 0 X^B

0 0 0 0 0 0 0 0^B

0 1 1 0 0 0 0 1^B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0^B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0^B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0^B

0 1 0 0 0 0 0 0^B

0 1 1 0 0 0 0 0^B

0 0 0 0 0 0 0 0^B

XXXXXXXX^B

EP0C

EP1C

EP2C

EP3C

EP4C

EP5C

TMSP

EP0 Control Register

EP1 Control Register

EP2 Control Register

EP3 Control Register

EP4 Control Register

EP5 Control Register

Time Stamp Register

0000D3^H

0000D4^H

0000D5^H

0000D6^H

0000D7^H

0000D8^H

0000D9^H

0000DA^H

0000DB^H

0000DC^H

0000DD^H

0000DE^H

0000DF^H

0000E0^H

0000E1^H

0000E2^H

0000E3^H

0000E4^H

0000E5^H

0000E6^H

0000E7^H

0000E8^H

0000E9^H

0000EA^H

0000EB^H

0000EC^H

0000ED^H

0000EE^H

0000EF^H

0000F0^H

0000F1^H

0000F2^H

0000F3^H

0000F4^H

0000F5^H

0000F6^H

0000F7^H

R/W

R

UDCS

UDCIE

UDC Status Register

UDC Interrupt Enable Register

EP0IS

EP0OS

EP1S

EP0I Status Register

EP0O Status Register

EP1 Status Register

EP2 Status Register

EP3 Status Register

EP4 Status Register

EP5 Status Register

EP0 Data Register

EP1 Data Register

EP2 Data Register

EP3 Data Register

1 0 XXX 1 XX^B

XXXXXXXX^B

USB Function

1 0 0 XX 0 0 X^B

XXXXXXXX^B

R/W

R

1 0 0 0 0 0 0 X^B

XXXXXXXX^B

EP2S

R/W

R

1 0 0 0 0 0 0 X^B

XXXXXXXX^B

EP3S

R/W

R

1 0 0 0 0 0 0 X^B

XXXXXXXX^B

EP4S

R/W

R

1 0 0 0 0 0 0 X^B

XXXXXXXX^B

EP5S

R/W

1 0 0 0 0 0 0 X^B

XXXXXXXX^B

EP0DT

EP1DT

EP2DT

EP3DT

XXXXXXXX^B

(Continued)

28

MB90330 Series

Register

abbreviation

Read/

Write

Address

Register

EP4 Data Register

EP5 Data Register

Resource name

Initial Value

0000F8^H

0000F9^H

0000FA^H

0000FB^H

R/W

XXXXXXXX^B

EP4DT

EP5DT

USB Function

0000FC^H

to

0000FF^H

Prohibited

RAM Area

000100^H

to

#^H

Program Address Detection Register

ch0 Lower

001FF0^H

001FF1^H

001FF2^H

001FF3^H

001FF4^H

001FF5^H

R/W

XXXXXXXX^B

Program Address Detection Register

ch0 Middle

PADR0

PADR1

Program Address Detection Register

ch0 Upper

Address Match

Detection

Program Address Detection Register

ch1 Lower

Program Address Detection Register

ch1 Middle

Program Address Detection Register

ch1 Upper

#^H

to

Unused Area

0078FF^H

007900^H

007901^H

007902^H

007903^H

007904^H

007905^H

007906^H

007907^H

007908^H

007909^H

00790A^H

00790B^H

PRLL0

PRLH0

PRLL1

PRLH1

PRLL2

PRLH2

PRLL3

PRLH3

PRLL4

PRLH4

PRLL5

PRLH5

PPG Reload Register Lower ch0

PPG Reload Register Upper ch0

PPG Reload Register Lower ch1

PPG Reload Register Upper ch1

PPG Reload Register Lower ch2

PPG Reload Register Upper ch2

PPG Reload Register Lower ch3

PPG Reload Register Upper ch3

PPG Reload Register Lower ch4

PPG Reload Register Upper ch4

PPG Reload Register Lower ch5

PPG Reload Register Upper ch5

R/W

XXXXXXXX^B

PPG ch0

PPG ch1

PPG ch2

PPG ch3

PPG ch4

PPG ch5

00790C^H

to

Prohibited

00790F^H

(Continued)

29

MB90330 Series

(Continued)

Register

abbreviation

Read/

Write

Address

Register

Resource name Initial Value

007910^H

007911^H

007912^H

007913^H

007914^H

007915^H

007916^H

007917^H

007918^H

007919^H

00791A^H

00791B^H

00791C^H

00791D^H

00791E^H

00791F^H

007920^H

007921^H

007922^H

007923^H

Input Capture Data Register Lower ch0

Input Capture Data Register Upper ch0

Input Capture Data Register Lower ch1

Input Capture Data Register Upper ch1

Input Capture Data Register Lower ch2

Input Capture Data Register Upper ch2

Input Capture Data Register Lower ch3

Input Capture Data Register Upper ch3

Output Compare Register Lower ch0

Output Compare Register Upper ch0

Output Compare Register Lower ch1

Output Compare Register Upper ch1

Output Compare Register Lower ch2

Output Compare Register Upper ch2

Output Compare Register Lower ch3

Output Compare Register Upper ch3

DMA Buffer Address Pointer Lower 8-bit

DMA Buffer Address Pointer Middle 8-bit

DMA Buffer Address Pointer Upper 8-bit

DMA Control Register

R

XXXXXXXX^B

IPCP0

IPCP1

R

XXXXXXXX^B

Input Capture

ch0/1

R

IPCP2

R

Input Capture

ch2/3

R

IPCP3

R

R/W

OCCP0

OCCP1

OCCP2

OCCP3

Output Compare

ch0/1

Output Compare

ch2/3

DBAPL

DBAPM

DBAPH

DMACS

DMA I/O Register Address Pointer

Lower 8-bit

µDMAC

007924^H

007925^H

DIOAL

DIOAH

R/W

XXXXXXXX^B

DMA I/O Register Address Pointer

Upper 8-bit

007926^H

007927^H

DDCTL

DDCTH

DMA Data Counter Lower 8-bit

DMA Data Counter Upper 8-bit

R/W

XXXXXXXX^B

007928^H

to

Prohibited

007FFF^H

• Explanation on read/write

R/W : Readable and Writable

R

: Read only

: Write only

W

• Explanation on initial values

0

1

X

-

: Initial value is “0”.

: Initial value is “1”.

: Initial value is undefined.

: Initial value is undefined (None) .

: Initial value of this bit is “1” or “0”.

∗

Note : No I/O instruction can be used for registers located between 007900^Hand 007FFF^H.

30

MB90330 Series

■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

Interruptcontrol

EI²OS

support

Interrupt vector

register

Interrupt source

µDMAC

Priority

Number* Address ICR Address

Reset

×

#08 08^HFFFFDC^H

#09 09^HFFFFD8^H

#10 0A^HFFFFD4^H

#11 0B^HFFFFD0^H

⎯

High

INT 9 instruction

Exceptional treatment

USB Function1

×

0, 1

ICR00 0000B0^H

ICR01 0000B1^H

ICR02 0000B2^H

ICR03 0000B3^H

ICR04 0000B4^H

ICR05 0000B5^H

ICR06 0000B6^H

ICR07 0000B7^H

ICR08 0000B8^H

ICR09 0000B9^H

ICR10 0000BA^H

ICR11 0000BB^H

ICR12 0000BC^H

ICR13 0000BD^H

ICR14 0000BE^H

ICR15 0000BF^H

USB Function2

2 to 6 #12 0C^HFFFFCC^H

USB Function3

×

#13 0D^HFFFFC8^H

#14 0E^HFFFFC4^H

#15 0F^HFFFFC0^H

#16 10^HFFFFBC^H

#17 11^HFFFFB8^H

#18 12^HFFFFB4^H

#19 13^HFFFFB0^H

#20 14^HFFFFAC^H

#21 15^HFFFFA8^H

#22 16^HFFFFA4^H

#23 17^HFFFFA0^H

#24 18^HFFFF9C^H

#25 19^HFFFF98^H

#26 1A^HFFFF94^H

#27 1B^HFFFF90^H

#28 1C^HFFFF8C^H

#29 1D^HFFFF88^H

#30 1E^HFFFF84^H

#31 1F^HFFFF80^H

#32 20^HFFFF7C^H

#33 21^HFFFF78^H

#34 22^HFFFF74^H

#35 23^HFFFF70^H

#36 24^HFFFF6C^H

#37 25^HFFFF68^H

#38 26^HFFFF64^H

#39 27^HFFFF60^H

#40 28^HFFFF5C^H

#41 29^HFFFF58^H

#42 2A^HFFFF54^H

USB Function4

USB Mini-HOST1

×

USB Mini-HOST2

I²C ch0

×

DTP/External interrupt ch0/1

I²C ch1

×

DTP/Extetrnal interrupt ch2/3

I²C ch2

×

DTP/External interrupt ch4/5

PWC/Reload timer ch0

DTP/External interrupt ch6/7

Input capture ch0/1

Reload timer ch1

×

14

×

7

×

Input capture ch2/3

Reload timer ch2

8

×

Output compare ch0/1

PPG ch0/1

×

Output compare ch2/3

PPG ch2/3

×

UART (Send completed) ch2/3

PPG ch4/5

11

×

UART (Reception completed) ch2/3

A/D converter/Free-run timer

UART (Send completed) ch0/1

Extended serial I/O

UART (Reception completed) ch0/1

Time-base timer/Watch timer

Flash memory status

Delay interrupt output module

10

15

13

9

×

12

×

Low

(Continued)

31

MB90330 Series

(Continued)

: Available, EI²OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.

With a stop request).

: Available (The interrupt request flag is cleared by the interrupt clear signal.)

: Available when any interrupt source sharing ICR is not used.

× : Unavailable

* : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority.

Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI²OS is permitted,

the EI²OS is activated when either of the factors is detected. As any interrupt other than the activation

factor is masked while the EI²OS is running, it is recommended that you should mask either of the interrupt

requests when using the EI²OS.

• The interrupt flag is cleared by the EI²OS interrupt clear signal for the resource that has two interrupt

factors in the same interrupt control register (ICR).

• Ifaresourcehastwointerruptsourcesforthesameinterruptnumber, bothoftheinterruptrequestflagsare

cleared by the µDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the

DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “0” in the

appropriate resource, and take measures by software polling.

• Content of USB interruption factor

USB interrupt factor

Details

End Point0-IN End Point0-OUT

USB function 1

USB function 2

End Point1-5

USB function 3

VOFF VON SUSP SOF BRST WKUP CONF

SPK

USB function 4

USB Mini-HOST1

USB Mini-HOST2

DIRQ CNNIRQ URIRQ RWKIRQ

SOFIRQ CMPIRQ

32

MB90330 Series

■ PERIPHERAL RESOURCES

1. I/O port

The I/O ports are used as general-purpose input/output ports (parallel I/O ports). MB90330 series model is

provided with 12 ports (94 inputs) . The ports function as input/output pins for peripheral functions also.

The port data register (PDR) can be used to send output data to the I/O pin and to receive the signal input to

the I/O port. The port direction register (DDR) can be used to set the I/O direction of the I/O pin in bit units.

The following table lists the I/O ports and the peripheral functions with which they share pins.

Port Pin Name

P00 to P07

P10 to P17

P20 to P23

P24 to P27

P30 to P33

P34 to P37

P40, P41

Pin Name (Peripheral)

Peripheral Function that Shares Pin

(External bus)

Port 0

Port 1

⎯

(External bus)

⎯

PPG0 to PPG3

TIN1, TOT1, TIN2, TOT2

⎯

(External bus)

Port 2

Port 3

8/16-bit PPG timer 0, 1 (External bus)

16-bit Reload timer 1, 2 (External bus)

(External bus)

TIN0, TOT0

16-bit Reload timer 0 (External bus)

Port 4

Port 5

SIN0, SOT0, SCK0,

SIN1, SOT1, SCK1

P42 to P47

UART0, UART1 (External bus)

P50 to P57

P60, P61

⎯

(External bus)

INT0, INT1

External interrupt

INT2 to INT4,

SIN, SOT, SCK

P62 to P64

External interrupt, Serial I/O

Port 6

P65

INT5, PWC

INT6, INT7, SCL0, SDA0

AN0 to AN7

External interrupt, PWC

External interrupt, I²C 0

8/10-bit A/D converter

P66, P67

P70 to P77

P80 to P87

Port 7

Port 8

AN8 to AN15

SIN2, SOT2, SCK2,

SIN3, SOT3, SCK3

P90 to P95

UART2, 3

Port 9

Port A

P96

ADTG, FRCK

IN0 to IN3

8/10-bit A/D converter, Free-run timer

PA0 to PA3

PA4 to PA7

PB0 to PB3

PB4

Input capture 0, 1, 2, 3

Output compare 0, 1, 2, 3

I²C 1, 2

OUT0 to OUT3

SCL1, SDA1, SCL2, SDA2

⎯

Port B

⎯

PB5, PB6

PPG4, PPG5

PPG timer 2

Note : These pins also serve as the analog input pins for ports 7 and 8. To use them as general-purpose ports, be

sure to set the corresponding bits in the analog input enable register (ADER) to 0^B. The ADER is initialized

to FF^Hat a reset.

33

MB90330 Series

• Register list (port data register)

PDR0

Initial Value Access

XXXXXXXX^BR/W*

7

6

5

4

3

2

1

0

Address : 000000^H

P07

P06

P05

P04

P03

P02

P01

P00

PDR1

15

14

13

12

11

10

9

8

Address : 000001H

XXXXXXXX^BR/W*

- XXXXXXX^BR/W*

XXXXXXXX^BR/W*

- XXXXXXX^BR/W*

P17

P16

P15

P14

P13

P12

P11

P10

PDR2

7

6

5

4

3

2

1

0

Address : 000002^H

P27

P26

P25

P24

P23

P22

P21

P20

PDR3

15

14

13

12

11

10

9

8

Address : 000003^H

P37

P36

P35

P34

P33

P32

P31

P30

PDR4

7

6

5

4

3

2

1

0

Address : 000004^H

P47

P46

P45

P44

P43

P42

P41

P40

PDR5

15

14

13

12

11

10

9

8

Address : 000005^H

P57

P56

P55

P54

P53

P52

P51

P50

PDR6

7

6

5

4

3

2

1

0

Address : 000006^H

P67

P66

P65

P64

P63

P62

P61

P60

PDR7

15

14

13

12

11

10

9

8

Address : 000007^H

P77

P76

P75

P74

P73

P72

P71

P70

PDR8

7

6

5

4

3

2

1

0

Address : 000008^H

P87

P85

P86

P84

P83

P82

P81

P80

PDR9

15

14

13

12

11

10

9

8

Address : 000009^H

⎯

P95

P96

P94

P92

P91

P90

P93

PDRA

7

6

5

4

3

2

1

0

Address : 00000A^H

PA7

PA5

PA6

PA4

PA2

PA1

PA0

PA3

PDRB

7

6

5

4

3

2

1

0

Address : 00000C^H

⎯

PB5

PB6

PB4

PB2

PB1

PB0

PB3

* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows :

• Input mode

Read : The level at the relevant pin is read.

Write : Data is written to the output latch.

• Output mode

Read : The data register latch value is read.

Write : Data is output to the relevant pin.

34

MB90330 Series

• Register list (port direction register)

DDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 000010^H

00000000^B

-0000000B

00000000^B

-0000000B

R/W

D07

D06

D05

D04

D03

D02

D01

D00

DDR1

15

14

13

12

11

10

9

8

Address : 000011^H

D17

D16

D15

D14

D13

D12

D11

D10

DDR2

7

6

5

4

3

2

1

0

Address : 000012^H

D27

D26

D25

D24

D23

D22

D21

D20

DDR3

15

14

13

12

11

10

9

8

Address : 000013^H

D37

D36

D35

D34

D33

D32

D31

D30

DDR4

7

6

5

4

3

2

1

0

Address : 000014^H

D47

D46

D45

D44

D43

D42

D41

D40

DDR5

15

14

13

12

11

10

9

8

Address : 000015^H

D57

D56

D55

D54

D53

D52

D51

D50

DDR6

7

6

5

4

3

2

1

0

Address : 000016^H

D67

D66

D65

D64

D63

D62

D61

D60

DDR7

15

14

13

12

11

10

9

8

Address : 000017^H

D75

D74

D73

D72

D71

D70

D77

D76

DDR8

7

6

5

4

3

2

1

0

Address : 000018^H

D84

D83

D82

D81

D80

D87

D85

D86

DDR9

15

14

13

12

11

10

9

8

Address : 000019^H

⎯

D95

D91

D90

D96

D94

D92

D93

DDRA

7

6

5

4

3

2

1

0

Address : 00001A^H

DA7

DA5

DA1

DA0

DA6

DA4

DA2

DA3

DDRB

15

14

13

12

11

10

9

8

Address : 00000D^H

⎯

DB5

DB1

DB0

DB6

DB4

DB2

DB3

• When each pin is serving as a port, the corresponding pin is controlled as follows :

0 : Input mode

1 : Output mode

This bit becomes 0 after a reset.

Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits

manipulated by the instruction are set to prescribed values but those other bits in output registers which

have been set for input are rewritten to current input values of the pins. When switching a pin from input port

to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output.

35

MB90330 Series

• Register list (Analog input enable register)

ADER0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 00001E^H

ADER1

11111111^B

R/W

ADE3

ADE2

ADE1

ADE0

ADE7

ADE6

ADE5

ADE4

15

14

13

12

11

10

9

8

Address : 00001F^H

11111111^B

R/W

ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9

ADE8

This register controls the port 7, 8 pins as follows.

0 : Port input/output mode.

1 : Analog input mode.

This bit becomes 1 after a reset.

• Register list (Port pull-up resistance register)

RDR0

Initial Value Access

7

6

5

4

3

2

1

0

Address : 00001C^H

00000000^B

R/W

RD07

RD06

RD05

RD04

RD03

RD02

RD01

RD00

RDR1

15

14

13

12

11

10

9

8

Address : 00001D^H

00000000^B

R/W

RD17

RD16

RD15

RD14

RD13

RD12

RD11

RD10

Controls the pull-up resistor in input mode.

0 : Without pull-up resistor in input mode.

1 : With pull-up resistor in input mode.

Meaningless in output mode. (Without pull-up resistor)/The input/output mode is decided by the setting of the

port direction register (DDR).

Without pull-up resistor is used in stop mode (SPL = 1). (High-Z) This function is disabled when the external

bus is used. Do not attempt to write to this register.

• Register list (Output pin register)

ODR4

Initial Value Access

00000000^BR/W

7

6

5

4

3

2

1

0

Address : 00001B^H

OD47

OD46

OD45

OD44

OD43

OD42

OD41

OD40

Controls open-drain in output mode.

0 : Serves as a standard output port in output mode.

1 : Serves as an open-drain output port in output mode.

Meaningless in input mode (output High-Z)./The input/output mode is decided by the setting of the port direction

register (DDR). This function is disabled when the external bus is used. Do not attempt to write to this register.

36

MB90330 Series

• Block diagram of port 0 pin and port 1 pin

Pull-up resistor

setting register

(RDRx)

Internal pull-up

resistor

PDRx read

Input

buffer

Port data

register

I/O decision

circuit

Output

buffer

Port

(PDRx)

PDRx

write

Port direction

register

(DDRx)

Standby control (LPMCR : SPL = “1”)

• Block diagram of port 2 pin, port 3 pin, port 4 pin, port 5 pin, port 6 pin, port 9 pin, port A pin and port B pin

Resource input

PDRx read

Input

Port data

register

(PDRx)

buffer

I/O decision

circuit

Output

buffer

Port

PDRx

write

Port direction

register

Standby control (LPMCR : SPL = “1”)

(DDRx)

Resource output control signal

Resource output

37

MB90330 Series

• Block diagram of port 7 pin and port 8 pin

Analog input

enable

register (ADER)

A/D converter

analog input

signal

PDRx read

Input

buffer

Port data

register

(PDRx)

I/O decision

circuit

Output

buffer

Port

PDRx

write

Port direction

register

(DDRx)

Standby control (LPMCR : SPL = “1”)

Notes : • When using as an input port, set " 0 " in the corresponding bit of the port-7 and port-8 direction register

(DDR7 and DDR8) and " 0 " in the related bit of the analog input enable register (ADER).

• When using as an analog input pin, set " 0 " in the corresponding bit of the port-7 and port-8 direction

register (DDR7 and DDR8) and " 1 " in the related bit of the analog input enable register (ADER).

38

MB90330 Series

2. Time-base timer

The time-base timer is an 18-bit free-run counter (time-base timer counter) that counts in synchronization with

the main clock (2 cycles of the oscillation clock HCLK). Four different time intervals can be selected, for each of

which an interrupt request can be generated. Operating clock signals are supplied to peripheral resources such

as the oscillation stabilization wait timer and watchdog timer.

• Interval time of time-base timer

Internal count clock cycle

Interval time

2¹²/HCLK (Approx. 0.68 ms)

2¹⁴/HCLK (Approx. 2.7 ms)

2¹⁶/HCLK (Approx. 10.9 ms)

2¹⁹/HCLK (Approx. 87.4 ms)

2/HCLK (0.33 µs)

Notes : • HCLK : Oscillation clock frequency

• The parenthesized values assume an oscillator clock frequency of 6 MHz.

• Clock cycles supplied from time-base timer

Where to supply clock

Clock cycle

2¹³/HCLK (Approx. 1.36 ms)

2¹⁵/HCLK (Approx. 5.46 ms)

2¹⁷/HCLK (Approx. 21.84 ms)

2¹²/HCLK (Approx. 0.68 ms)

2¹⁴/HCLK (Approx. 2.7 ms)

2¹⁶/HCLK (Approx. 10.9 ms)

2¹⁹/HCLK (Approx. 87.4 ms)

Main clock oscillation

stabilization wait

Watch dog timer

Notes : • HCLK : Oscillation clock frequency

• The parenthesized values assume an oscillator clock frequency of 6 MHz.

• Register list

Time-base timer control register (TBTC)

Initial Value

1 - - 00100^B

15

14

13

12

11

10

9

8

Address : 0000A9^H

RESV

⎯

TBIE

TBOF

TBR

TBC1

TBC0

( R/W )

( ⎯ )

( R/W ) ( R/W )

( W ) ( R/W ) ( R/W )

39

MB90330 Series

• Block Diagram

To PPG timer

To watchdog

timer

Time-base

timer counter

Dividing

HCLK by 2

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

OF

Power-on reset

Stop mode start

To clock controller

oscillation stabilizing

wait time selector

Counter

clear

Hold state start

control

circuit

CKSCR : MCS = 1→0*¹

CKSCR : SCS = 0→1*²

Interval timer selector

TBOF clear

TBOF set

Time-base timer control register (TBTC)

Time-base timer interrupt signal

RESV

⎯

TBIE TBOF TBR TBC1 TBC0

−

: Unused

OF : Overflow

HCLK : Oscillation clock

*1

*2

: Switching the machine clock from main clock or subclock to PLL clock

: Switching the machine clock from subclock to main clock

Actual interrupt request number of time-base timer is as follows :

Interrupt request number : #40 (28^H)

40

MB90330 Series

3. Watchdog timer

The watchdog timer is timer counter provided for measure of program runaway. It is a 2-bit counter operating

with an output of the timebase timer or watch timer as the count clock and resets the CPU when the counter is

not cleared for a preset period of time after start.

• Interval time of watchdog timer

HCLK : Oscillation clock(6 MHz) SCLK : Sub clock(8 KHz)

Min

Max

Clock cycle

2¹⁴2¹¹/HCLK

2¹⁶2¹³/HCLK

2¹⁸2¹⁵/HCLK

2²¹2¹⁸/HCLK

2¹²2⁹/SCLK

2¹⁵2¹²/SCLK

2¹⁶2¹³/SCLK

2¹⁷2¹⁴/SCLK

Approx. 2.39 ms

Approx. 9.56 ms

Approx. 38.23 ms

Approx. 305.83 ms

Approx. 0.448 s

Approx. 3.584 s

Approx. 7.168 s

Approx. 14.336 s

Approx. 3.07 ms

Approx. 12.29 ms

Approx. 49.15 ms

Approx. 393.22 ms

Approx. 0.576 s

Approx. 4.608 s

Approx. 9.216 s

Approx. 18.432 s

Notes : • The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.

• The watchdog timer contains a 2-bit counter that counts the carry-up signal from the time-base timer or

watch timer.

• Interval time of watchdog timer is longer than the set time during the following conditions.

- When clearing the timebase timer during operation on oscillation (HCLK)

- When clearing the watch timer during operation on sub clock (SCLK)

• Events that stop the watchdog timer

• Stop due to a power-on reset

• Watchdog reset

• Clear factor of watchdog timer

• External reset input by RST pin

• Writing “0” to the software reset bit

• Writing “0” to the watchdog timer control bit (second and subsequent times)

• Transition to sleep mode (clearing the watchdog timer to suspend counting)

• Transition to time-base timer mode (clearing the watchdog timer to suspend counting)

• Transition to stop mode (clearing the watchdog timer to suspend counting)

41

MB90330 Series

• Register list

Watchdog timer control register (WDTC)

Initial Value

7

6

5

4

3

2

1

0

Address : 0000A8^H

X-XXX111^B

⎯

PONR

WRST ERST

( R ) ( R )

SRST

WTE

WT1

WT0

( R )

( ⎯ )

( R )

( W )

• Block Diagram

Watchdog timer control register (WDTC)

PONR

⎯

WRST ERST SRST WTE WT1 WT0

WDCS bit of WTC

SCM bit of CKSCR

2

Watch mode start

Time-base timer mode start

Sleep mode start

Hold state start Watchdog timer

CLR and start

CLR

To

internal

reset

generation

circuit

Counter

clear

control

Watchdog

timer reset

generation

circuit

Count

2-bit

counter

selector

clock

circuit

Stop mode start

CLR

4

Clear

(Time-base timer counter)

Main clock

(dividing HCLK by 2)

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

SCLK

× 2¹× 2²

× 2⁸× 2⁹× 2¹⁰× 2¹¹× 2¹²× 2¹³× 2¹⁴× 2¹⁵× 2¹⁶× 2¹⁷× 2¹⁸

HCLK: Oscillation clock

SCLK: Sub clock

42

MB90330 Series

4. Watch timer

The watch timer is a 15-bit timer using the subclock. It can generate interval interrupts. It can also be used as

a clock source for the watchdog timer.

• Register list

Watch timer control register (WTC)

Initial Value

7

6

5

4

3

2

1

0

Address : 0000AA^H

10001000^B

WDCS

SCE

WTIE

WTOF

WTR

WTC2 WTC1

WTC0

( R/W )

( R )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

• Block Diagram

Watch timer control register (WTC)

WDCS

SCE

WTIE

WTOF

WTR

WTC2

WTC1 WTC0

Clear

2⁸

2⁹

Sub clock

2¹⁰

2¹¹

2¹²

2¹³

2¹⁴

Interval

selector

Interrupt

generation

circuit

Watch timer

interrupt

Watch counter

2¹⁰2¹³2¹⁴2¹⁵

To watchdog timer

43

MB90330 Series

5. 16-bit reload timer

The 16-bit reload timer has the internal clock mode to decrement in synchronization with 3 different internal

clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the

external pin. Either can be selected. This timer defines when the count value changes from 0000^Hto FFFF^Has

an underflow. The timer therefore causes an underflow when the count reaches [reload register setting + 1].

Either mode can be selected for the count operation from the reload mode which repeats the count by reloading

the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow

occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC.

• Register list

• TMCSR (Timer control status register 0 to 2)

Timer control status register (upper) (TMCSR0 to TMCSR2)

Initial Value

15

14

13

12

11

10

9

8

Address : 000063^H

000067^H

XXXX0000^B

⎯

CSL1

CSL0

MOD2 MOD1

00006B^H

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W )

Timer control status register (lower) (TMCSR0 to TMCSR2)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 000062^H

000066^H

MOD0 OUTE OUTL

RELD

INTE

UF

CNTE

TRG

00006A^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

• 16-bit timer register/16-bit reload register

TMR0 to TMR2/TMRLR0 to TMRLR2 (upper)

Initial Value

15

14

13

12

11

10

9

8

Address : 000065^H

000069^H

XXXXXXXX^B

D15

D14

D13

D12

D11

D10

D09

D08

00006D^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

TMR0 to TMR2/TMRLR0 to TMRLR2 (lower)

Initial Value

7

6

5

4

3

2

1

0

Address : 000064^H

000068^H

XXXXXXXX^B

D07

D06

D05

D04

D03

D02

D01

D00

00006C^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

44

MB90330 Series

• Block diagram

Internal data bus

TMRLR0^∗1

TMRLR1^∗2

TMRLR2^∗3

16-bit reload register

Reload signal

TMR0^∗1

TMR1^∗2

TMR2^∗3

Reload

control circuit

∗5

UF

16-bit timer register

Count clock

CLK

generation circuit

Gate

input

Valid

clock

decision

circuit

Wait signal

3

Machine

clock φ

Prescaler

Clear

Trigger

Internal

clock

Output control

circuit

CLK

Output signal

generation

circuit

Input

control

circuit

Clock

selector

EN

TOT0^∗1

TOT1^∗2

TOT2^∗3

TIN0^∗1

TIN1^∗2

TIN2^∗3

External clock

Select

signal

3

2

Operating

control

circuit

Select function

⎯

CSL1 CSL0 MOD2MOD1MOD0OUTE OUTL RELD INTE UF CNTE TRG

Timer control status register (TMCSR0 to TMCSR2)

Interrupt request

output

#23 (17^H) *^1,*⁴

#26 (1A^H) *^2,*⁴

#28 (1C^H) *^3,*⁴

*1 : channel 0

*2 : channel 1

*3 : channel 2

*4 : Interrupt number

*5 : Underflow

45

MB90330 Series

6. Multi function timer

The multi-function timer enables the following based on the 16-bit free-run timer.

• Output of independent waveform

• Measurement of input pulse width

• Measurement of external clock cycle

• Configuration of a multi-functional timer

16-bit free-run timer 16-bit Output Compare 16-bit Input Capture 8/16-bit PPG timer 16-bit PWC timer

8-bit × 6 channels

(16-bit × 3 channels)

1 channel

4 channels

1 channel

• 16-bit free-run timer : 1 channel

The 16-bit free-run timer consists of a 16-bit up counter (timer data register (TCDT)), compare clear register

(CPCLR), timer control status register (TCCS), and prescaler.

The counter output value of the 16-bit free-run timer is used as the base timer for the output compare and input

capture units.

• The count clock can be set, selected from among the following eight types.

1/φ, 2/φ, 4/φ, 8/φ, 16/φ, 32/φ, 64/φ, 128/φ

φ : Machine clock frequency

• During the following conditions, the interrupt should be output.

- The counter value of 16-bit free run timer will be overflowed.

- The counter value of 16-bit free run timer will be cleared after the counter value of 16-bit free run timer = the

compare clear register value (CPCLR) (TCCS : ICRE = “1”, MODE = “1”)

• The counter value of 16-bit free run timer should be cleared to “0000^H” during the following conditions.

• Reset

• When setting the clear bit (SCLR) of timer control status register (TCCS) to “1”

• When the counter value of the 16-bit free run timer = the compare clear register value (CPCLR) (TCCS :

MODE = “1”)

• When setting “0000^H” to the timer data register (TCDT)

• Output compare : 4 channels

The output compare unit consists of compare registers (OCCP0 to OCCP3), compare control registers (OCS0

to OCS3), and a compare output latch.

The output compare unit can invert the output level and output an interrupt when a compare register (OCCP0

to OCCP3) value matches the counter value of the 16-bit free-run timer.

• Output compare registers can operate as 4 independent channels. The compare registers (OCCP0 to OCCP3)

of each channel have interrupt request flags of their respective output pins.

• Pin output can be inverted by using 2 channels of compare registers (OCCP0 to OCCP3).

• If the counter value of 16-bit free run timer = the compare register (OCCP0 to OCCP3) (OCS0, OCS2 :

IOP0 = “1”, IOP1 = “1”), the interrupt request should be generated.

• The initial value for pin output of each channel can be set.

• Input capture : 4 channels

The input capture unit consists of the input capture data registers (IPCP0 to IPCP3) corresponding to external

input pins (IN0 to IN3) and input capture control registers (ICS01, ICS23).

The input capture unit can capture the counter value of the 16-bit free-run timer into the input capture data

register (IPCP0 to IPCP3) to generated an interrupt request upon detection of the effective edge of the signal

input through the external input.

46

MB90330 Series

• The input capture unit in each channel can operate independently.

• The effective edge of the external signal can be selected (rising edge, falling edge, both edges).

• An interrupt request can be generated upon detection of the selected effective edge of the external sig-

nal.(ICS01, ICS2 : ICE0 = “1”, ICE1 = “1”, ICE2 = “1”, ICE3 = “1”).

• Register list (16-bit free-run timer)

Compare clear register (CPCLR)

Initial Value

15

14

13

12

11

10

9

8

Address : 00008B^H

XXXXXXXX^B

CL15

CL14

CL13

CL12

CL11

CL10

CL09

CL08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

7

6

5

4

3

2

1

0

Address : 00008A^H

XXXXXXXX^B

CL07

CL06

CL05

CL04

CL03

CL02

CL01

CL00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Timer data register (TCDT)

Address : 000087^H

Initial Value

00000000^B

15

14

13

12

11

10

9

8

T15

T14

T13

T12

T11

T10

T09

T08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 000086^H

T07

T06

T05

T04

T03

T02

T01

T00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Timer control/status register (TCCS)

Initial Value

0--00000^B

15

14

13

12

11

10

9

8

Address : 000089^H

ECKE

⎯

MSI2

MSI1

MSI0

ICLR

ICRE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 000088^H

IVF

IVFE

STOP MODE SCLR

CLK2

CLK1

CLK0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

47

MB90330 Series

• Register list (output compare)

Compare register (OCCP0 to OCCP3)

Address : 007919^H

Initial Value

15

14

13

12

11

10

9

8

00791B^H

00791D^H

00791F^H

XXXXXXXX^B

C15

C14

C13

C12

C11

C10

C09

C08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Address : 007918^H

00791A^H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXX^B

C07

C06

C05

C04

C03

C02

C01

C00

00791C^H

00791E^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Control register (OCS1/OCS3)

Initial Value

---00000^B

15

14

⎯

13

⎯

12

11

10

9

8

Address : 000055^H

⎯

CMOD OTE1

OTE0

OTD1

OTD0

000057^H

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Control register (OCS0/OCS2)

Initial Value

0000--00^B

7

6

5

4

3

2

1

0

Address : 000054^H

ICP1

ICP0

ICE1

ICE0

⎯

CST1

CST0

000056^H

( R/W ) ( R/W ) ( R/W ) ( R/W )

( ⎯ )

( ⎯ ) ( R/W ) ( R/W )

48

MB90330 Series

• Register list (input capture)

Input capture data register (IPCP0 to IPCP3)

Address : 007911^H

Initial Value

15

14

13

12

11

10

9

8

007913^H

007915^H

007917^H

XXXXXXXX^B

CP15

( R )

CP14

( R )

CP13

( R )

CP12

( R )

CP11

( R )

CP10

( R )

CP09

( R )

CP08

( R )

Address : 007910^H

007912^H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXX^B

CP07

( R )

CP06

( R )

CP05

( R )

CP04

( R )

CP03

( R )

CP02

( R )

CP01

( R )

CP00

( R )

007914^H

007916^H

Input capture control status register (ICS23)

Initial Value

00000000^B

15

14

13

12

11

10

9

8

Address : 000053^H

ICP3

ICP2

ICE3

ICE2

EG31

EG30

EG21

EG20

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Input capture control status register (ICS01)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 000052^H

ICP1

ICP0

ICE1

ICE0

EG11

EG10

EG01

EG00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

49

MB90330 Series

• Block diagram of the 16-bit free-run timer, input capture units, and output compare units

To interrupt

#36 (24^H)*

φ

3

8

IVF

IVFE STOP MODE SCLR CLK2

CLK1 CLK0

Divider

Clock

16-bit free-run timer

16

To interrupt

#36 (24^H)*

Compare circuit

16-bit compare clear register

Compare register 0/2

MSI2 to MSI0

ICLR

ICRE

T

Q

OTE0

Compare circuit

OUT0/OUT2

16

4

Compare register 1/3

CMOD

OUT1/OUT3

Q

OTE1

Compare circuit

ICP1

ICP0

IOE1

IOE0

To interrupt

#29 (1D^H)*

#31 (1F^H)*

Edge

detection

IN0/IN2

Capture data register 0/2

Capture data register 1/3

4

EG11 EG10

EG31 EG30

EG01 EG00

EG21 EG20

Edge

detection

IN1/IN3

ICP1

ICP3

ICP0

ICP2

ICE1

ICE3

ICE0

ICE2

To interrupt

#25 (19^H)*

#27 (1B^H)*

* : Interrupt number

φ : Machine clock frequency

50

MB90330 Series

• 8/16-bit PPG timer (8-bit : 6 channels, 16-bit : 3 channels)

8/16-bit PPG timer consists of an 8-bit down counter (PCNT), PPG control register (PPGC0 to PPGC5), PPG

output control register (PPG01, PPG23, PPG45) and PPG reload register (PRLL0 to PRLL5, PRLH0 to PRLH5).

When used as an 8-/16-bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an

arbitrary duty ratio at an arbitrary frequency.

• 8-bit PPG mode

Each channel operates as an independent 8-bit PPG.

• 8-bit prescaler + 8-bit PPG mode

Operates as an arbitrary-cycle 8-bit PPG with PPG0 (PPG2, PPG4) operating as an 8-bit prescaler and PPG1

(PPG3, PPG5) counted by the borrow output of PPG0 (PPG2, PPG4).

• 16-bit PPG mode

Operates as a 16-bit PPG with PPG0 (PPG2, PPG4) and PPG1 (PPG3, PPG5) connected.

• PPG operation

The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level periods of

pulse waveform) at an arbitrary frequency. This can also be used as a D/A converter by an external circuit.

51

MB90330 Series

• Register list

PPG operation mode control register

(PPGC1/PPGC3/PPGC5)

Initial Value

0X000001^B

15

14

13

12

11

10

9

8

Address : 000047^H

000049^H

Reserved

PEN1

( R/W )

⎯

PE10

PIE1

PUF1

MD1

MD0

( ⎯ ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

00004B^H

(PPGC0/PPGC2/PPGC4)

Initial Value

0X000XX1^B

7

6

5

4

3

2

1

0

Address : 000046^H

000048^H

Reserved

PEN0

( R/W )

⎯

PE00

PIE0

PUF0

⎯

( ⎯ ) ( R/W ) ( R/W ) ( R/W )

( ⎯ )

( R/W )

00004A^H

PPG output control register (PPG01/PPG23/PPG45)

Initial Value

000000XX^B

7

6

5

4

3

2

1

0

Address : 00004C^H

00004E^H

Reserved Reserved

PCS2

PCS1

PCS0

PCM2

PCM1

PCM0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

000050^H

PPG reload register

(PRLH0 to PRLH5)

Address : 007901^H

007903^H

Initial Value

15

14

13

12

11

10

9

8

XXXXXXXX^B

D15

D14

D13

D12

D11

D10

D09

D08

007905^H

007907^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

007909^H

00790B^H

(PRLL0 to PRLL5)

Address : 007900^H

007902^H

Initial Value

7

6

5

4

3

2

1

0

XXXXXXXX^B

D07

D06

D05

D04

D03

D02

D01

D00

007904^H

007906^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

007908^H

00790A^H

52

MB90330 Series

• 8/16-bit PPG ch0/2/4 block diagram

PPG0/PPG2/PPG4

output enable

Peripheral clock dividing by 16

PPG0/PPG2/PPG4

Peripheral clock dividing by 8

Peripheral clock dividing by 4

Peripheral clock dividing by 2

Peripheral clock

A/D converteer

PPG0/PPG2/PPG4

output latch

PEN0

To interrupt

#30 (1E^H)*

#32 (20^H)*

#34 (22^H)*

S

R Q

PCNT

(down counter)

IRQ

Count clock

select

ch1/3/5

borrow

L/H selector

Dividing by 512 of timebase

counter output main clock

PUF0

PIE0

L/H select

PRLL

PRLBH

PPGC0 (operating mode control)

L data bus

H data bus

* : Interrupt number

53

MB90330 Series

• 8-bit PPG ch1/3/5 block diagram

PPG1/PPG3/PPG5

output enable

Peripheral clock dividing by 16

PPG1/PPG3/PPG5

Peripheral clock dividing by 8

Peripheral clock dividing by 4

Peripheral clock dividing by 2

Peripheral clock

PPG1/PPG3/PPG5

output latch

PEN1

S

R Q

To interrupt

#30 (1E^H)*

#32 (20^H)*

#34 (22^H)*

PCNT

(down counter)

IRQ

Count clock

select

L/H selector

Dividing by 512 timebase

counter output main clock

PUF1

PIE1

L/H select

PRLL

PRLBH

PPGC1 (operating mode control)

L data bus

H data bus

* : Interrupt number

54

MB90330 Series

• PWC timer

The PWC timer is a 16-bit multi-function up-count timer capable of measuring the input signal pulse width.

• Register list

PWC control status register (PWCSR)

15

14

13

12

11

10

9

8

Initial Value

0000000X^B

Reserved

STRT

STOP

EDIR

EDIE

OVIR

OVIE

ERR

Address : 00005D^H

Address : 00005C^H

( R/W ) ( R/W )

( R )

( R/W ) ( R/W ) ( R/W )

( R )

( R/W )

7

6

5

4

3

2

1

0

Initial Value

00000000^B

CKS1

CKS0

PIS1

PIS0

S/C

MOD2 MOD1 MOD0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

PWC data buffer register (PWCR)

15

14

13

12

11

10

9

8

Initial Value

00000000^B

D15

D14

D13

D12

D11

D10

D9

D8

Address : 00005F^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

7

6

5

4

3

2

1

0

Initial Value

00000000^B

D7

D6

D5

D4

D3

D2

D1

D0

Address : 00005E^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Ratio of dividing frequency control register (DIVR)

7

6

5

4

3

2

1

0

Initial Value

⎯

DIV1

DIV0

------00^B

Address : 000060^H

( ⎯ )

( R/W ) ( R/W )

55

MB90330 Series

• Block Diagram

PWCR read

Error

detection

ERR

PWCR

16

Internal clock

Reload

Data transfer

(machine clock/4)

16

Clock

2²

2³

Overflow

Clock

divider

16-bit up count timer

Timer

CKS1/CKS0

clear

Divider

clear

Control circuit

Count enable

End edge

selection

Start edge

selection

Measurement

starting edge

Input

waveform

comparator

Divider ON/OFF

Edge

detection

PWC

Measurement

termination edge

8-bit

divider

Measurement termination

interrupt request

PIS0/PIS1

Overflow interrupt

request

CKS0/CKS1

ERR

15

Divide ratio select

PWCSR

2

DIVR

56

MB90330 Series

7. UART

UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop syn-

chronization) communications with external devices. It supports bi-directional communication (normal mode)

and master/slave communication (multi-processor mode: supported on master side only). An interrupt can be

generated upon completion of reception, detection of a reception error, or completion of transmission. EI²OS is

supported.

• UART functions

UART, or a generic serial data communication interface that sends and receives serial data to and from other

CPU and peripherals, has the functions listed in following.

Function

Data buffer

Full-duplex double-buffered

• Clock synchronous (without start/stop bit)

• Clock asynchronous (start-stop synchronous)

Transmission mode

• Special-purpose baud-rate generator

Baud rate

It is optional from 8 kinds.

• Baud rate by external clock (SCK0/SCK1/SCK2/SCK3 terminal input)

• 8-bit or 7-bit (in the asynchronous normal mode only)

• 1-bit to 8-bit (synchronous mode only)

Data length

Signal system

Non Return to Zero (NRZ) system

• Framing error

Reception error detection

• Overrun error

• Parity error (Not supported in operation mode 1)

• Receive interrupt (reception completed, reception error detected)

• Transmission interrupt (transmission completed)

• Both the transmission and reception support EI²OS.

Interrupt request

Master/slave type

communication function Capable of 1 (master) to many (slaves) communication (available just as master)

(multi processor mode)

Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added.

• UART operation modes

Data length

Operation mode

Synchronization

Stop bit length

Without parity

With parity

0

1

2

Normal mode

7-bit or 8-bit

Asynchronous

Synchronous

1-bit or 2-bit *²

No

Multi processor mode

Normal mode

8-bit + 1*¹

⎯

1 to 8-bit

⎯ : Setting disabled

*1 : + 1 is an address/data setting bit (A/D) which is used for communication control.

*2 : Only one bit can be detected as a stop bit at reception.

57

MB90330 Series

• Register list

Serial mode register (SMR0 to SMR3)

Initial Value

00100000^B

7

6

5

4

3

2

1

0

Address : 000020^H

000026^H

M2L0

MD1

MD0

SCKL

M2L2

M2L1

SCKE

SOE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

00002C^H

000032^H

Serial control register (SCR0 to SCR3)

Initial Value

00000100^B

15

14

13

12

11

10

9

8

Address : 000021^H

000027^H

PEN

P

SBL

CL

A/D

REC

RXE

TXE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( W )

( R/W ) ( R/W )

00002D^H

000033^H

Serial input/output data register (SIDR0 to SIDR3 / SODR0 to SODR3)

Initial Value

7

6

5

4

3

2

1

0

Address : 000022^H

000028^H

D7

D6

D5

D4

D3

D2

D1

D0

XXXXXXXX^B

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

00002E^H

000034^H

Serial status register (SSR0 to SSR3)

Initial Value

00001000^B

15

14

13

12

11

10

9

8

Address : 000023^H

000029^H

PE

ORE

( R )

FRE

RDRF

TDRE

BDS

RIE

TIE

( R )

( R/W ) ( R/W ) ( R/W )

00002F^H

000035^H

UART prescaler reload register (UTRLR0 to UTRLR3)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 000024^H

00002A^H

D7

D6

D5

D4

D3

D2

D1

D0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

000030^H

000036^H

UART prescaler control register (UTCR0 to UTCR3)

Initial Value

15

14

13

12

11

10

9

8

Address : 000025^H

00002B^H

Reserved

MD

SRST

CKS

⎯

D10

D9

D8

0000-000^B

( R/W ) ( R/W ) ( R/W ) ( R/W )

( ⎯ ) ( R/W ) ( R/W ) ( R/W )

000031^H

000037^H

58

MB90330 Series

• Block Diagram

Control bus

Reception interrupt

signal

Special-purpose

baud-rate generator

(UART prescaler

control register

UTCR0 to UTCR3)

(UART prescaler

reload UTRLR0 to

#39 (27^H)*

Transmission

clock

#35 (23^H)*

Send interrupt

signal

#37 (25^H)*

#33 (21^H)*

Clock

selector

Reception

control

circuit

Reception

clock

Transmission

control circuit

UTRLR3)

Start bit

detection circuit

Transmission

start circuit

SCK0 to SCK3

Reception bit

counter

Transmission

bit counter

Reception parity

counter

Transmission

parity counter

SOT0 to SOT3

Shift register for

reception

Shift register for

transmission

SIN0 to SIN3

Start transmission

SIDR0 to SIDR3

SODR0 to SODR3

Reception

complete

Receive status decision

circuit

Reception error

occurrence signal for

EI²OS • µDMAC (to CPU)

Internal data bus

MD1

MD0

PEN

P

PE

ORE

FRE

RDRF

TDRE

BDS

RIE

SCKL

M2L2

M2L1

M2L0

SCKE

SOE

SBL

CL

A/D

REC

RXE

TXE

SMR0 to

SMR3

SCR0 to

SCR3

SSR0 to

SSR3

TIE

* : Interrupt number

59

MB90330 Series

8. Extended I/O serial interface

The extended I/O serial interface is a serial I/O interface in an 8-bit, single-channel, capable of clock synchronous

data transfer. LSB-first or MSB-first transfer mode can be selected for data transfer.

There are 2 serial I/O operation modes available:

• Internal shift clock mode: Transfer data in synchronization with the internal clock.

• External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK).

By manipulating the general-purpose port sharing the external pin (SCK) in this mode, data can also be

transferred by a CPU instruction.

• Register list

Serial mode control status register (SMCS)

Initial Value

00000010^B

15

14

13

12

11

10

9

8

SMD2 SMD1

SMD0

SIE

SIR

BUSY

STOP

STRT

Address : 000059^H

Address : 000058^H

( R/W ) ( R/W )

( R/W ) ( R/W ) ( R/W )

( R/W )

( R/W ) ( R/W )

Initial Value

XXXX0000^B

7

6

5

4

3

2

1

0

⎯

MODE

BDS

SOE

SCOE

( ⎯ )

( R/W )

( ⎯ )

( R/W )

Serial data register (SDR)

Address : 00005A^H

Initial Value

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

XXXXXXXX^B

( R/W )

( R/W ) ( R/W )

Communication prescaler control register (SDCR)

Initial Value

0XXX0000^B

15

14

13

12

11

10

9

8

Address : 00005B^H

MD

⎯

DIV3

DIV2

DIV1

DIV0

( R/W )

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W )

60

MB90330 Series

• Block Diagram

Internal data bus

Initial value

(MSB fast) D0 to D7

D7 to D0 (LSB fast)

Transfer direction selection

SIN

Read

Write

SDR (serial data register)

SOT

SCK

Shift clock counter

Control circuit

Internal clock

2

1

0

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS SOE SCOE

Interrupt

request

Internal data bus

61

MB90330 Series

9. I²C Interface

The I²C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I²C

bus and has the following features.

• Master/slave sending and receiving

• Arbitration function

• Clock synchronization function

• Slave address and general call address detection function

• Detecting transmitting direction function

• Start condition repeated generation and detection function

• Bus error detection function

• Register list

I²C bus status register (IBSR0 to IBSR2)

7

6

5

4

3

2

1

0

Initial Value

00000000^B

Address : 000070^H

000076^H

BB

RSC

AL

LRB

TRX

AAS

GCA

FBT

00007C^H

( R )

I²C bus control register (IBCR0 to IBCR2)

15

14

13

12

11

10

9

8

Initial Value

00000000^B

Address : 000071^H

000077^H

BER

BEIE

SCC

MSS

ACK

GCAA

INTE

INT

00007D^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus clock selection register (ICCR0 to ICCR2)

7

6

5

4

3

2

1

0

Initial Value

XX0XXXXX^B

Address : 000072^H

000078^H

⎯

EN

CS4

CS3

CS2

CS1

CS0

00007E^H

( ⎯ ) ( ⎯ ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus address register (IADR0 to IADR2)

15

14

A6

13

A5

12

A4

11

A3

10

A2

9

8

Initial Value

XXXXXXXX^B

Address : 000073^H

000079^H

⎯

A1

A0

00007F^H

( ⎯ ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

I²C bus data register (IDAR0 to IDAR2)

7

6

5

4

3

2

1

0

Initial Value

XXXXXXXX^B

Address : 000074^H

00007A^H

D7

D6

D5

D4

D3

D2

D1

D0

000080^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

62

MB90330 Series

• Block Diagram

ICCRx

EN

2

I C enable

Clock divide 1

Peripheral clock

5

6

7

8

ICCRx

CS4

CS3

Clock selector 1

Clock divide 2

CS2

CS1

CS0

Sync

Generating shift clock

2

4

8 16 32 64 128 256

Clock selector 2

Shift clock edge change timing

IBSRx

BB

Bus busy

Repeat start

Last Bit

RSC

LRB

TRX

Start stop

condition detection

Error

Send/receive

First Byte

FBT

AL

Arbitration lost detection

IBCRx

BER

SCLx

SDAx

BEIE

INTE

INT

IRQ

Interrupt request

End

IBCRx

SCC

Start

Master

MSS

ACK

Start stop condition

generation

ACK enable

GC-ACK enable

GCAA

IDAR

IBSRx

AAS

Slave

Slave address

compare

Global call

GCA

IADR

63

MB90330 Series

10. USB Function

The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol.

• Feature of USB function

• Conform to USB2.0 Full Speed

• Full speed (12 Mbps) is supported.

• The device status is auto-answer.

• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16

• Toggle check by data synchronization bit

• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these

3 commands can be processed the same way as the class vendor commands).

• The class vendor commands can be received as data and responded via firmware.

• Supports up to 6 EndPoints (EndPoint0 is fixed to control transfer)

• 2 transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for EndPoint 0)

• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint 0)

• Capable of detection of connection and disconnection by monitoring the USB bus power line

• Register list

UDC control register (UDCC)

7

6

5

4

3

2

1

0

Initial Value

10100000^B

Address : 0000D0^H

Reserved Reserved

RST RESUM HCON USTP

RFBK

PWC

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

EP0 control register (EP0C)

Address : 0000D2^H

7

6

5

4

3

2

1

0

Initial Value

X1000000^B

Reserved

PKS0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XXXX000X^B

Reserved Reserved

Reserved

Address : 0000D3^H

⎯

STAL

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W )

EP1 control register (EP1C)

Address : 0000D4^H

7

6

5

4

3

2

1

0

Initial Value

00000000^B

PKS1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

01100001^B

EPEN

TYPE

DIR

DMAE NULE

STAL

PKS1

Address : 0000D5^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(Continued)

64

MB90330 Series

EP2/3/4/5 control register (EP2C to EP5C)

1

7

6

5

4

3

2

0

Initial Value

01000000^B

Address : 0000D6^H

0000D8^H

Reserved

PKS2 to 5

PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5 PKS2 to 5

PKS2 to 5

0000DA^H

0000DC^H

( R/W )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( R/W )

15

14

13

12

11

10

9

8

Initial Value

01100000^B

Address : 0000D7^H

0000D9^H

Reserved

EPEN

TYPE

DIR

DMAE NULE

STAL

0000DB^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

0000DD^H

Time stamp register (TMSP)

7

6

5

4

3

2

1

0

Initial Value

00000000^B

Address : 0000DE^H

Address : 0000DF^H

TMSP

TMSP TMSP TMSP

TMSP

TMSP TMSP TMSP

( R )

15

14

13

12

11

10

9

8

Initial Value

00000000^B

⎯

TMSP TMSP TMSP

( R ) ( R ) ( R )

( ⎯ )

UDC status register (UDCS)

7

6

5

4

3

2

1

0

Initial Value

00000000^B

Address : 0000E0^H

VOFF

VON

SUSP

SOF

BRST WKUP SETP CONF

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

UDC Interrupt enable register (UDCIE)

15

14

13

12

11

10

9

8

Initial Value

00000000^B

Address : 0000E1^H

VOFFIE VONIE SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( R )

( R/W )

EP0I status register (EP0IS)

Address : 0000E2^H

7

6

5

4

3

2

1

0

Initial Value

XXXXXXXX^B

⎯

( ⎯ )

15

14

13

12

11

10

9

8

Initial Value

10XXX1XX^B

BFINI DRQIIE

( R/W ) ( R/W )

⎯

DRQI

⎯

Address : 0000E3^H

( ⎯ )

( R/W ) ( ⎯ )

( ⎯ )

(Continued)

65

MB90330 Series

(Continued)

EP0O status register (EP0OS)

7

6

5

4

3

2

1

0

Initial Value

Address : 0000E4^H

Address : 0000E5^H

XXXXXXXX^B

⎯

SIZE

( ⎯ )

( R )

15

14

13

12

11

10

9

8

Initial Value

100XX00X^B

BFINI DRQOIE SPKIE

( R/W ) ( R/W ) ( R/W )

⎯

DRQO

SPK

⎯

( ⎯ )

( ⎯ ) ( R/W ) ( R/W )

( ⎯ )

EP1 status register (EP1S)

Address : 0000E6^H

7

6

5

4

3

2

1

0

Initial Value

XXXXXXXX^B

SIZE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

1000000X^B

Address : 0000E7^H

BFINI DRQIE SPKIE

( R/W ) ( R/W ) ( R/W )

⎯

BUSY

DRQ

SPK

SIZE

( ⎯ )

( R )

( R/W ) ( R/W ) ( R/W )

EP2/3/4/5 status register (EP2S to EP5S)

Initial Value

XXXXXXXX^B

Address : 0000E8^H

0000EA^H

7

6

5

4

3

2

1

0

⎯

SIZE

0000EC^H

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

0000EE^H

;

Initial Value

1000000X^B

Address : 0000E9^H

0000EB^H

15

14

13

12

11

10

9

8

BFINI DRQIE SPKIE

( R/W ) ( R/W ) ( R/W )

⎯

BUSY

DRQ

SPK

⎯

0000ED^H

0000EF^H

( ⎯ )

( R )

( R/W ) ( R/W )

( ⎯ )

EP0/1/2/3/4/5 data register (EP0DT to EP5DT)

Address : 0000F0^H

Initial Value

XXXXXXXX^B

7

6

5

4

3

2

1

0

0000F2^H

0000F4^H

0000F6^H

0000F8^H

0000FA^H

BFDT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Address : 0000F1^H

0000F3^H

Initial Value

XXXXXXXX^B

15

14

13

12

11

10

9

8

BFDT

0000F5^H

0000F7^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

0000F9^H

0000FB^H

66

MB90330 Series

11. USB Mini-HOST

USB Mini-HOST provides minimal host operations required and is a function that enables data to be transferred

to and from Device without PC intervention.

• Feature of USB Mini-HOST

• Automatic detection of Low Speed/Full Speed transfer

• Low Speed/Full Speed transfer support

• Automatic detection of connection and cutting device

• Reset sending function support to USB-bus

• Support of IN/OUT/SETUP/SOF token

• In-token handshake packet automatic transmission (excluding STALL)

• Out-token handshake packet automatic detection

• Supports a maximum packet length of 256 bytes.

• Error (CRC error/toggle error/time-out) various supports

• Wake-Up function support

• Differences between the USB HOST and USB Mini-HOST

HOST

Mini-HOST

Hub support

Transfer

×

Bulk transfer

Control transfer

Interrupt transfer

ISO transfer

Low Speed

×

Transfer speed

Full Speed

PRE packet support

SOF packet support

CRC error

Toggle error

Error

Time-out

Maximum packet < receive data

Detection of connection and cutting of device

Transfer speed detection

: Supported

× : Not supported

67

MB90330 Series

• Register list

USB host control register 0 (HCNT0)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 0000C0^H

RWKIRE URIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB host control register 1 (HCNT1)

15

14

13

12

11

10

SOFSTEP CANCEL RETRY

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

9

8

Initial Value

00000001^B

Reserved Reserved Reserved Reserved Reserved

Address : 0000C1^H

USB host interruption register (HIRQ)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 0000C2^H

Reserved

TCAN

RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQ

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB host error status register (HERR)

Initial Value

00000011^B

15

14

13

12

11

10

9

8

Address : 0000C3^H

LSTSOF RERR TOUT

CRC TGERR STUFF

HS

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB host state status register (HSTATE)

7

6

5

4

3

2

1

0

Initial Value

XX010010^B

Address : 0000C4^H

⎯

ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W )

( R )

USB SOF interruption FRAME comparison register (HFCOMP)

15

14

13

12

11

10

9

8

Initial Value

00000000^B

FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME

COMP COMP COMP COMP COMP COMP COMP COMP

Address : 0000C5^H

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

(Continued)

68

MB90330 Series

(Continued)

USB retry timer setting register 0/1/2 (HRTIMER)

7

6

5

4

3

2

1

0

Initial Value

00000000^B

Address : 0000C6^H

RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

00000000^B

Address : 0000C7^H

Address : 0000C8^H

RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

7

6

5

4

3

2

1

0

Initial Value

XXXXXX00^B

⎯

RTIMER2 RTIMER2

( R/W ) ( R/W )

( ⎯ )

USB host address register (HADR)

15

14

13

12

11

10

9

8

Initial Value

X0000000^B

Address : 0000C9^H

⎯

ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( ⎯ )

USB EOF setting register 0/1 (HEOF)

7

6

5

4

3

2

1

0

Initial Value

00000000^B

Address : 0000CA^H

EOF0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XX000000^B

Address : 0000CB^H

⎯

EOF1

( ⎯ )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

USB FRAME setting register (HFRAME)

7

6

5

4

3

2

1

0

Initial Value

00000000^B

Address : 0000CC^H

FRAME0 FRAME0FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

15

14

13

12

11

10

9

8

Initial Value

XXXXX000^B

Address : 0000CD^H

⎯

FRAME1 FRAME1 FRAME1

( ⎯ )

( ⎯ ) ( R/W ) ( R/W ) ( R/W )

USB token end point register (HTOKEN)

7

6

5

4

3

2

1

0

Initial Value

00000000^B

Address : 0000CE^H

TGGL TKNEN TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

69

MB90330 Series

12. 8/10-bit A/D converter

The A/D converter converts analog input voltages into digital values and has the following features.

• RC sequential compare conversion method with sample and hold circuit

• Selectable 8-bit resolution or 10-bit resolution

• Analog input program-selectable from among 16 channels

Single conversion mode : Convert 1 selected channel

Scan conversion mode : Continuous plural channels (maximum 16 channels can be programmed) are converted.

Continuous conversion mode : Repeatedly convert the specified channels.

Stop conversion mode: Convert 1 channel then suspend conversion to remain on standby until the next

activation. (Simultaneous conversion start available.)

• An interrupt request to the CPU can be generated upon completion of A/D conversion. Suitable for continuous

processing as this interrupt activates µDMA to transfer the data resulting from A/D conversion to memory.

• The activation source can be selected from among software, external trigger (falling edge), and timer (rising

edge).

• Register list

AD control status register lower/upper (ADCS0/ADCS1)

Initial Value

7

6

5

4

3

2

1

0

Address : 000040^H

00 - - - - - 0^B

Reserved

MD1

MD0

⎯

( R/W ) ( R/W )

( ⎯ )

( R/W )

Initial Value

00000000^B

15

14

13

12

11

10

9

8

Address : 000041^H

Reserved

BUSY

INT

INTE

PAUS

STS1

STS0

STRT

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

( W )

( R/W )

AD data register lower/upper (ADCR0/ADCR1)

Initial Value

7

6

5

4

3

2

1

0

Address : 000042^H

XXXXXXXX^B

D7

D6

D5

D4

D3

D2

D1

D0

( R )

Initial Value

00101XXX^B

15

14

13

12

11

10

9

8

Address : 000043^H

S10

ST1

ST0

CT1

CT0

⎯

D9

D8

( R/W )

( W )

( ⎯ )

( R )

AD conversion channel selection register (ADMR)

Initial Value

00000000^B

15

14

13

12

11

10

9

8

Address : 000045^H

ANS3

ANS2

ANS1

ANS0

ANE3

ANE2

ANE1

ANE0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

70

MB90330 Series

• Block Diagram

AV^CC

AVRH

AV^SS

Conversion channel

selection

D/A converter

ADMR

MP

AN0

AN1

AN2

Sequential comparison

register

AN3

AN4

AN5

Comparator

Input

AN6

circuit

AN7

AN8

Sample&hold

circuit

AN9

AN10

AN11

AN12

AN13

AN14

AN15

Data register

Decoder

ADCR0, ADCR1

A/D control register upper

A/D control register lower

Trigger start

ADTG

ADCS0, ADCS1

Timer start

Timer

(PPG1 output)

Operating clock

Prescaler

φ

71

MB90330 Series

13. DTP/External interrupt circuit

DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external

interrupt input terminal (INT7 to INT0) , and outputs the interrupt request.

• DTP/External interrupt circuit function

The DTP/External interrupt function outputs an interrupt request upon detection of the edge or level signal input

to the external interrupt input pins (INT7 to INT0).

If CPU accepts the interrupt request, and if the extended intelligent I/O service (EI²OS) is enabled, branches to

the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI²OS.

And if EI²OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer

(DTP function) performed by EI²OS.

• Overview of DTP/External interrupt circuit

External interrupt

DTP function

8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK,

P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0)

Input pin

The detection level or the type of the edge for each terminal can be set in the

request level setting register (ELVR).

Interrupt source

Input of H level/L level/rising edge/falling edge.

#18 (12^H), #20 (14^H), #22 (16^H), #24 (18^H)

Interrupt number

Interrupt control

Enabling/disabling the interrupt request output using the DTP/interrupt enable

register (ENIR)

Interrupt flag

Holding the interrupt causes using the DTP/interrupt cause register (EIRR)

Process setting

Disable EI²OS (ICR: ISE=“0”)

Enable EI²OS (ICR: ISE=“1”)

After an automatic data transfer by

EI²OS, branched to the interrupt

handling routine

Branched to the interrupt handling

routine

Process

72

MB90330 Series

• Register list

DTP/Interrupt enable register (ENIR)

Initial Value

7

6

5

4

3

2

1

0

Address : 00003CH

00000000^B

EN7

(R/W)

EN6

(R/W)

EN5

(R/W)

EN4

(R/W)

EN3

(R/W)

EN2

(R/W)

EN1

EN0

(R/W)

DTP/Interrupt source register (EIRR)

Initial Value

00000000^B

15

14

13

12

11

10

9

8

Address : 00003D^H

ER7

(R/W)

ER6

(R/W)

ER5

(R/W)

ER4

(R/W)

ER3

(R/W)

ER2

(R/W)

ER1

(R/W)

ER0

(R/W)

Request level setting register (ELVR)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 00003E^H

LB3

LA3

LB2

LA2

LB1

LA1

LB0

LA0

(R/W)

Initial Value

00000000^B

15

14

13

12

11

10

9

8

Address : 00003F^H

LB7

LA7

LB6

LA6

LB5

LA5

LB4

LA4

(R/W)

73

MB90330 Series

• Block Diagram

Request level setting register (ELVR)

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

2

DTP/external interrupt input

detection circuit

Selector

P67/INT7

SDA0

P60/INT0

Selector

P66/INT6

SCL0

P61/INT1

Selector

P65/INT5

PWC

P62/INT2

SIN

Selector

P63/INT3

SOT

P64/INT4

SCK

DTP/interrupt

source register

(EIRR)

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

Interrupt request signal

*

#18(12

#20(14

#22(16

#24(18

H)

*

DTP/interrupt

enable register

(ENIR)

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

* : Interrupt number

74

MB90330 Series

14. Interrupt controller

The interrupt control register is located inside the interrupt controller; it exists for every I/O having an interrupt

function. This register has the following functions.

• Setting of the interrupt levels of relevant resources

• Register list

Interrupt control register (ICR01, ICR03, ICR05, ICR07, ICR09, ICR11, ICR13, ICR15)

Initial Value

Address : ICR01 : 0000B1^H

ICR03 : 0000B3^H

ICR05 : 0000B5^H

ICR07 : 0000B7^H

ICR09 : 0000B9^H

ICR11 : 0000BB^H

ICR13 : 0000BD^H

ICR15 : 0000BF^H

00000111^B

15

14

13

12

11

10

9

8

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

( W )

( R/W ) ( R/W ) ( R/W ) ( R/W )

Interrupt control register (ICR00, ICR02, ICR04, ICR06, ICR08, ICR10, ICR12, ICR14)

Address : ICR00 : 0000B0^H

Initial Value

00000111^B

7

6

5

4

3

2

1

0

ICR02 : 0000B2^H

ICR04 : 0000B4^H

ICR06 : 0000B6^H

ICR08 : 0000B8^H

ICR10 : 0000BA^H

ICR12 : 0000BC^H

ICR14 : 0000BE^H

ICS3

ICS2

ICS1

ICS0

ISE

IL2

IL1

IL0

( W )

( R/W ) ( R/W ) ( R/W ) ( R/W )

Note : Do not access interrupt control registers using any read modify write instruction because it causes a

malfunction.

• Block Diagram

3

32

Interrupt request

(peripheral resource)

IL2

IL1

IL0

3

Determine

priority

of

interrupt

3

(CPU)

Interrupt level

75

MB90330 Series

15. µDMAC

µDMAC is simple DMA with the function equal with EI²OS. It has 16 channels DMA transfer channels with the

following features.

• Performs automatic data transfer between the peripheral resource (I/O) and memory

• The program execution of CPU stops in the DMA start-up

• Capable of selecting whether to increment the transfer source and destination addresses

• DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register, and

descriptor.

• A STOP request is available for stopping DMA transfer from the resource.

Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA

status register is set and a termination interrupt is output to the transfer controller.

• Register list

DMA enable register upper (DERH)

Initial Value

15

14

13

12

11

10

9

8

Address : 0000AD^H

00000000^B

EN15

EN14

EN13

EN12

EN11

EN10

EN9

EN8

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA enable register lower (DERL)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 0000AC^H

EN7

EN6

EN5

EN4

EN3

EN2

EN1

EN0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA stop status register (DSSR)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

STP7

STP6

STP5

STP4

STP3

STP2

STP1

STP0

STP8

Address : 0000A4^H

STP15 STP14 STP13 STP12 STP11 STP10 STP9

*

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA status register upper (DSRH)

Initial Value

00000000^B

15

14

13

12

11

10

9

8

Address : 00009D^H

DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9

DTE8

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA status register lower (DSRL)

Initial Value

00000000^B

7

6

5

4

3

2

1

0

Address : 00009C^H

DTE7

DTE6

DTE5

DTE4

DTE3

DTE2

DTE1

DTE0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA descriptor channel specification register (DCSR)

Initial Value

00000000^B

15

14

13

12

11

10

9

8

Address : 00009B^H

Reserved Reserved Reserved

STP

DCSR3 DCSR2 DCSR1 DCSR0

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

* : The DSSR is lower when the STP bit of DCSR in the DSSR is “0”.

The DSSR is upper when the STP bit of DCSR in the DSSR is “1”.

(Continued)

76

MB90330 Series

(Continued)

DMA buffer address pointer lower 8-bit (DBAPL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007920^H

XXXXXXXX^B

DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA buffer address pointer middle 8-bit (DBAPM)

Initial Value

15

14

13

12

11

10

9

8

Address : 007921^H

XXXXXXXX^B

DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA buffer address pointer upper 8-bit (DBAPH)

Initial Value

7

6

5

4

3

2

1

0

Address : 007922^H

XXXXXXXX^B

DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA control register (DMACS)

Initial Value

15

14

13

12

IF

11

10

9

8

Address : 007923^H

XXXXXXXX^B

RDY2

RDY1 BYTEL

BW

BF

DIR

SE

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA I/O register address pointer lower 8-bit (DIOAL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007924^H

XXXXXXXX^B

A07

A06

A05

A04

A03

A02

A01

A00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA I/O register address pointer upper 8-bit (DIOAH)

Initial Value

15

14

13

12

11

10

9

8

Address : 007925^H

XXXXXXXX^B

A15

A14

A13

A12

A11

A10

A09

A08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA data counter lower 8-bit (DDCTL)

Initial Value

7

6

5

4

3

2

1

0

Address : 007926^H

XXXXXXXX^B

B07

B06

B05

B04

B03

B02

B01

B00

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

DMA data counter upper 8-bit (DDCTH)

Initial Value

15

14

13

12

11

10

9

8

Address : 007927^H

XXXXXXXX^B

B15

B14

B13

B12

B11

B10

B09

B08

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

Note : The above register is switched for each channel depending on the DCSR.

77

MB90330 Series

16. External bus pin control circuit

The external bus pin control circuit controls external bus pins to extend the CPU address and data buses to

externals.

• Register list

• Automatic ready function selection register (ARSR)

Initial Value

15

14

13

12

11

10

9

8

Address : 0000A5^H

0011- - 00^B

ICR1

ICR0

HMR1 HMR0

⎯

LMR1

LMR0

(W)

(⎯)

(W)

• External address output control register (HACR)

Initial Value

7

6

5

4

3

2

1

0

Address : 0000A6^H

* * * * * * * * ^B

E23

E22

E21

E20

E19

E18

E17

E16

(W)

• Bus control signal selection register (EPCR)

Initial Value

1000*10 -^B

15

14

13

12

Reserved

(W)

11

9

8

10

Address : 0000A7^H

CKE

RYE

HDE

HMBS

LMBS

⎯

(W)RE

(W)

(⎯)

(W)

W :Write only

−

*

:Unused

:“1” or “0”

• Block Diagram

P5

P4

P3

P5

P2

P1

P0

P0 data

P0 direction

RB

Data control

Address control

Access control

Access

control

78

MB90330 Series

17. Address matching detection function

When the address is equal to the value set in the address detection register, the instruction code to be read into

the CPU is forcibly replaced with the INT9 instruction code (01^H). As a result, the CPU executes the INT9

instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the

program patch function is enabled.

2 address detection registers are provided, for each of which there is an interrupt enable bit. When the address

matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code

to be read into the CPU is forcibly replaced with the INT9 instruction code.

• Register list

• Program address detect register 0 to 2 (PADR0)

PADR0 (lower)

7

6

5

4

3

2

1

0

Initial Value

XXXXXXXX^B

Address : 001FF0^H

(R/W)

PADR0 (middle)

Address : 001FF1^H

15

14

13

12

11

10

9

8

Initial Value

XXXXXXXXB

(R/W)

PADR0 (upper)

Address : 001FF2^H

7

6

5

4

3

2

1

0

Initial Value

XXXXXXXXB

(R/W)

• Program address detect register 3 to 5 (PADR1)

PADR1 (lower)

15

14

13

12

11

10

9

8

Initial Value

XXXXXXXXB

Address : 001FF3^H

(R/W)

PADR1 (middle)

Address : 001FF4^H

7

6

5

4

3

2

1

0

Initial Value

XXXXXXXXB

(R/W)

PADR1 (upper)

Address : 001FF5^H

15

14

13

12

11

10

9

8

Initial Value

XXXXXXXXB

(R/W)

• Program address detection control status register (PACSR)

PACSR

7

6

5

4

3

2

1

0

Initial Value

00000000B

Address : 00009E^HReserved Reserved Reserved Reserved

Reserved

ADIE

(R/W)

ADDE

(R/W)

R/W : Readable and Writable

X

: Undefined

79

MB90330 Series

18. Delay interrupt generator module

The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware

interrupt can be generated by software.

• Delay interrupt generator module function

Function and control

• Setting the R0 bit in the delayed interrupt request generation/release register to 1

(DIRR: R0 = 1) generates a delayed interrupt request.

• Setting the R0 bit in the delayed interrupt request generation/release register to 0

(DIRR: R0 = 0) cancels the delayed interrupt request.

Interrupt source

Interrupt control

Interrupt flag

No setting of permission register is provided.

Set in bit R0 of the delayed interrupt request generation /clear register (DIRR : R0)

Not ready for extended intelligent I/O service (EI²OS).

EI²OS support

• Block Diagram

Internal data bus

⎯

R0

S Interrupt

request

Interrupt

request

signal

Delay interrupt factor generation/release

register(DIRR)

R latch

⎯ : Undefined

80

MB90330 Series

19. ROM mirror function selection module

The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read

by accessing bank 00.

• ROM mirroring function selection module function

Description

FFFFFF^Hto FF8000^Hin the FF bank can be read through 00FFFF^Hto 008000^Hin

Mirror setting address

the 00 bank.

Interrupt source

EI²OS support

None.

Not ready for extended intelligent I/O service (EI²OS) .

• Block Diagram

ROM mirror function selection register (ROMM)

Re-

served

⎯

MI

Address

Address area

00 bank

FF bank

Data

ROM

81

MB90330 Series

20. Low power consumption (standby) mode

TheF²MC-16LXcanbesettosavepowerconsumptionbyselectingandsettingthelowpowerconsumptionmode.

• CPU operation mode and functional description

CPU

operating

clock

Operation

Description

mode

Normal run

Sleep

The CPU and peripheral resources operate at the clock frequency obtained by PLL

multiplication of oscillator clock (HCLK) frequency.

Only peripheral resources operate at the clock frequency obtained by PLL multiplica-

tion of the oscillator clock (HCLK) .

PLL clock

Main clock

Sub clock

Time-base Only the time-base timer operates at the clock frequency obtained by PLL multiplica-

timer

tion of the oscillator clock (HCLK) frequency.

Stop

The CPU and peripheral resources are suspended with the oscillator clock stopped.

The CPU and peripheral resources operate at the clock frequency obtained by divid-

ing the oscillator clock (HCLK) frequency by two.

Normal run

Sleep

Only peripheral resources operate at the clock frequency obtained by dividing the

oscillator clock (HCLK) frequency by two.

Time-base Only the time-base timer operates at the clock frequency obtained by dividing the

timer

oscillator clock (HCLK) frequency by two.

Stop

The CPU and peripheral resources are suspended with the oscillator clock stopped.

The CPU and peripheral resources operate at the clock frequency obtained by

dividing the subclock (SCLK) frequency by four.

Normal run

Sleep

Only peripheral resources operate at the clock frequency obtained by dividing the

subclock (SCLK) frequency by four.

Watch

mode

Only the watch timer operates at the clock frequency obtained by dividing the

subclock (SCLK) frequency by four.

Stop

The CPU and peripheral resources are suspended with the subclock stopped.

CPU

intermittent

operation

mode

The halved or PLL-multiplied oscillator clock (HCLK) frequency or the subclock

(SCLK) frequency is used for operation while being decimated in a certain period.

Normal run

• Register list

Low power consumption mode control register (LPMCR)

Initial Value

00011000^B

7

6

5

4

3

2

1

0

Address : 0000A0^H

Reserved

STP

SLP

SPL

RST

TMD

CG1

CG0

( W )

( R/W )

( W )

( R/W ) ( R/W ) ( R/W ) ( R/W )

82

MB90330 Series

21. Clock

The clock generator controls the internal clock as the operating clock for the CPU and peripheral resources. The

internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The clock based on

source oscillation is referred to as oscillator clock while the clock based on internal PLL oscillation is referred to

as PLL clock.

• Register list

Clock selection register (CKSCR)

Initial Value

11111100^B

15

14

13

12

11

10

9

8

Address : 0000A1^H

SCM

MCM

WS1

WS0

SCS

MCS

CS1

CS0

( R )

( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )

83

MB90330 Series

22. 3 Mbits flash memory

The description that follows applies to the flash memory built in the MB90F334A; it is not applicable to evaluation

ROM or masked ROM.

The flash memory is located in bank FF in the CPU memory map.

• Function to flash memory

Description

Memory capacity

Memory configuration

Sector configuration

Sector protect function

Program algorithm

3072 Kbits (384 KB)

384 Kwords × 8 bits/192 Kwords × 16 bits

64 KB × 5 + 32 KB + 8 KB × 2 + 16 KB

Possibility that set up with a recommendation parallel writer

Automatic program algorithm (Embedded Algorithm* : Similar to MBM29LV400TC)

• Compatibility with the JEDEC standard-type command

• Built-in deletion pause/deletion resume function

• Detection of programming/erasure completion using data polling and the toggle bit

• Capable of erasing data sector by sector (in arbitrary combination of sectors)

Operation command

Program/Erase cycle

At least 10,000 times guaranteed

• Parallel programmer available for programming and erasure

(Ando Denki : AF9708, AF9709, AF9709B)

• Can be written and erased using a dedicated serial writer

(Yokogawa Digital Computer Corporation : AF220/AF210/AF120/AF110)

• Write/delete operation by program execution

How to program and

erase memory

Interrupt source

EI²OS supports

Programming/erasure completion sources

Not ready for expanded intelligent I/O service (EI²OS).

* : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

84

MB90330 Series

• Sector configuration of flash memory

Flash Memory CPU address

Writer address *

F80000^H

F8FFFFH

F90000H

F9FFFFH

FA0000H

FAFFFFH

FB0000H

FBFFFFH

FC0000^H

FCFFFFH

FD0000H

FDFFFFH

FE0000H

FEFFFFH

FF0000H

FF7FFFH

FF8000^H

FF9FFFH

FFA000H

FFBFFFH

FFC000H

FFFFFFH

00000H

0FFFFH

10000H

1FFFFH

20000H

2FFFFH

30000H

3FFFFH

40000H

4FFFFH

50000H

5FFFFH

60000H

6FFFFH

70000H

77FFFH

78000H

79FFFH

7A000H

7BFFFH

7C000H

7FFFFH

Prohibited

SA0 (64 KB)

SA1 (64 KB)

SA2 (64 KB)

Prohibited

SA3 (64 KB)

SA4 (64 KB)

SA5 (32 KB)

SA6 (8 KB)

SA7 (8 KB)

SA8 (16 KB)

* : The writer address is relative to the CPU address when data is programmed into flash memory by a

parallel programmer. Programming and erasing by the general-purpose parallel programmer are

executed based on writer addresses.

• Register list

Flash memory control register (FMCS)

Initial Value

000X0000^B

7

6

5

4

3

2

1

0

Address : 0000AE^H

Reserved

INTE RDYINT

WE

RDY

LPM1

LPM0

( R/W ) ( R/W ) ( R/W )

( R )

( W )

( R/W )

( W )

( R/W )

85

MB90330 Series

• Standard configuration for Fujitsu standard serial on-board writing

The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Cor-

poration is used for Fujitsu standard serial on-board writing.

Host interface cable (AZ201)

General-purpose common cable (AZ210)

Flash

CLK synchronous

RS232C

microcontroller

programmer

+

serial

MB90F334A

user system

Memory card

Can operate stand alone

Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the

AF220, AF210, AF120 and AF110 flash microcontroller programmer, general-purpose common cable for

connection (AZ210) and connectors.

• Pins Used for Fujitsu Standard Serial On-board Programming

Function

Description

MD2,

The device enters the serial program mode by setting MD2=1, MD1=1

and MD0 =0.

Mode input pin

MD1, MD0

X0, X1

Because the internal CPU operation clock is set to be the 1 multiplication

PLL clock in the serial write mode, the internal operation clock frequency

is the same as the oscillation clock frequency.

Oscillation pin

Programming program

start pins

P60, P61

Input a Low level to P60 and a High level to P61.

RST

Reset input pin

⎯

SIN0

SOT0

SCK0

Serial data input pin.

Serial data output pin

Serial clock input pin

UART0 is used as CLK synchronous mode.

In program mode, the pins used for the UART0 CLK synchronous mode

are SIN0, SOT0 and SCK0.

When supplying the write voltage (MB90F334A : 3.3 V 0.3 V) from the

user system, connection with the flash microcontroller programmer is not

necessary.

V^CC

V^SS

Power source input pin

GND Pin

When connecting, do not short-circuit with the user power supply.

Share GND with the flash microcontroller programmer.

86

MB90330 Series

The control circuit shown in the figure is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the

user system. Isolate the user circuit during serial on-boardwriting, with the TICS signal of the flash microcontroller

programmer.

AF220/AF210/AF120/AF110

program control pin

MB90F334A program control

10 kΩ

AF220/AF210/AF120/AF110/

TICS pin

User

Control circuit

The MB90F334A serial clock frequency that can be input is determined by the following expression:

Use the flash microcontroller programmer to change the serial clock input frequency setting depending on the

oscillator clock frequency to be used.

Inputable serial clock frequency = 0.125 × oscillation clock frequency.

• Maximum serial clock frequency

Maximum serial clock

frequency acceptable to the

microcontroller

Maximum serial clock

frequency that can be set

with the AF200

Oscillation

clock frequency

frequency that can be set

with the AF220, AF210,

AF120 or AF110

At 6 MHz

750 kHz

500 kHz

• System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa Digital

Computer Corporation)

Part number

AF220/AC4P

AF210/AC4P

AF120/AC4P

AF110/AC4P

Function

Model with internal Ethernet interface

Standard model

/100 V to 220 V power adapter

Unit

Single key internal Ethernet interface mode

Single key model

AZ221

AZ210

FF201

AZ290

/P4

PC/AT RS232C cable for writer

Standard target probe (a) length : 1 m

Control module for Fujitsu F²MC-16LX flash microcontroller control module

Remote controller

4 MB PC Card (option) Flash memory capacity to 512 KB correspondence

Contact to : Yokogawa Digital Computer Corporation TEL : 81-423-33-6224

Note : The AF200 flash microcontroller programmer is a retired product, but it can be supported using control

module FF201.

87

MB90330 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Rating

Parameter

Symbol

Unit

Remarks

Min

Max

V^CC

V^SS− 0.3

V^SS+ 4.0

V

Power supply voltage*¹

AV^CC

AVRH

V^CC≥ AV^CC*²

AV^CC≥ AVR ≥ 0 V*³

*4

Nch open-drain

(Withstand voltage of

5 V I/O)*⁵

Input voltage*¹

V^I

V^SS− 0.3

V^SS+ 6.0

V

− 0.5

V^SS− 0.3

− 0.5

− 2.0

⎯

V^SS+ 4.5

V^SS+ 4.0

V^SS+ 4.5

+2.0

20

V

USB I/O

V

*4

Output voltage*¹

V^O

V

USB I/O

Maximum clamp current

I^CLAMP

Σ⏐I^CLAMP⏐

I^OL1

mA

mW

°C

*6

Total maximum clamp current

*6

⎯

10

Other than USB I/O*⁷

USB I/O*⁷

“L” level maximum output current

I^OL2

⎯

43

“L” level average output current

I^OLAV

ΣI^OL

⎯

3

*8

“L” level maximum total output current

“L” level average total output current

⎯

60

ΣI^OLAV

I^OH1

⎯

30

*9

⎯

− 10

− 43

− 3

Other than USB I/O*⁷

USB I/O*⁷

“H” level maximum output current

I^OH2

⎯

“H” level average output current

“H” level maximum total output current

“H” level average total output current

Power consumption

I^OHAV

ΣI^OH

⎯

*8

⎯

− 60

− 30

340

ΣI^OHAV

Pd

⎯

*9

⎯

Operating temperature

T^A

− 40

− 55

+ 85

+ 150

+ 125

°C

Storage temperature

Tstg

°C

USB I/O

*1 : The parameter is based on V^SS= AV^SS= 0.0 V.

*2 : Be careful not to let AV^CCexceed V^CC, for example, when the power is turned on.

*3 : Be careful not to let AVRH exceed AVcc.

*4 : V^Iand V^Omust not exceed Vcc + 0.3 V. However, if the maximum current to/from an input is limited by some

means with external components, the I^CLAMPrating supersedes the V^Irating.

*5 : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, VBUS

*6 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77,

P80 to P87, P90 to P95, PB5, PB6

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

88

MB90330 Series

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to

the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input

potential may pass through the protective diode and increase the potential at the V^CCpin, and this may affect

other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power

supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the

resulting supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Note that analog system input/output pins other than P60 to P67, P96, PA0 to PA7, PB0 to PB4, DVP, DVM,

HVP, HVM, VBUS, HCON

• Sample recommended circuits:

• Input/output equivalent circuits

Protective diode

V^CC

Limiting

resistance

Pch

Nch

+B input (0 V to 16 V)

R

*7 : A peak value of an applicable one pin is specified as a maximum output current.

*8 : The average output current specifies the mean value of the current flowing in the relevant single pin during a

period of 100 ms.

*9 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during

a period of 100 ms.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

89

MB90330 Series

2. Recommended Operating Conditions

(V^SS= AV^SS= 0.0 V)

Remarks

Value

Parameter

Symbol

Unit

Min

3.0

Max

3.6

V

At normal operation (when using USB)

At normal operation (when not using USB)

Hold state of stop operation

CMOS input pin

Power supply voltage

V^CC

2.7

3.6

1.8

V^IH

0.7 V^CC

0.8 V^CC

V^CC+ 0.3

V^IHS1

CMOS hysteresis input pin

Nch open-drain

(Withstand voltage of 5 V I/O)*

Input “H” voltage

Input “L” voltage

V^IHS2

0.8 V^CC

V^SS+ 5.3

V

V^IHM

V^IHUSB

V^IL

V^CC− 0.3

2.0

V^CC+ 0.3

0.3 V^CC

0.2 V^CC

V^SS+ 0.3

0.8

V

MD pin input

USB pin input

V^SS− 0.3

V^SS

CMOS input pin

CMOS hysteresis input pin

MD pin input

V^ILS

V^ILM

V^ILUSB

USB pin input

Differential input

sensitivity

V^DI

0.2

⎯

V

USB pin input

Differential common

mode input voltage

range

V^CM

0.8

2.5

V

USB pin input

Series resistance

R^S

T^A

25

− 40

0

30

Ω

Recommended value = 27 Ω at using USB

When not using USB

+ 85

+ 70

°C

Operating

temperature

When using USB

* : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, VBUS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

90

MB90330 Series

3. DC Characteristics

Sym

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Parameter

Pin name

Conditions

Unit Remarks

bol

Min Typ Max

Output pins other than

P60 to P67, P96,

PA0 to PA7, PB0 to PB4,

HVP, HVM, DVP, DVM

V^CC−

I^OH= − 4.0 mA

⎯

Vcc

3.6

V

Output “H”

voltage

0.5

V^OH

HVP, HVM, DVP, DVM RL = 15 kΩ 5%

Output pins other than

HVP, HVM, DVP, DVM

2.8

Vss

0

⎯

V

Vss

+ 0.4

0.3

I^OL= 4.0 mA

Output “L”

voltage

V^OL

HVP, HVM, DVP, DVM RL = 1.5 kΩ 5%

Output pins other than

P60 to P67, P96,

PA0 to PA7,

PB0 to PB4, HVP, HVM,

V^CC= 3.3 V,

Vss < V^I< V^CC

− 10

⎯

+ 10 µA

Input leak

current

I^IL

DVP, DVM

HVP, HVM, DVP, DVM

⎯

− 5

⎯

+ 5

µA

Pull-up

resistance

V^CC= 3.3 V,

T^A= + 25 °C

R^PULLP00 to P07, P10 to P17

25

50 100 kΩ

Opendrain

output

current

P60 to P67, P96,

I^LIOD

⎯

0.1

10

µA

PA0 to PA7, PB0 to PB4,

V^CC= 3.3 V,

Internal frequency 24 MHz,

At normal operating

⎯

75

65

85

75

mA MB90F334A

mA MB90333A

At USB operating (USTP = 0)

I^CC

V^CC= 3.3 V,

⎯

70

60

80

70

mA MB90F334A

mA MB90333A

Internal frequency 24 MHz,

At normal operating

At non-operating USB

(USTP = 1)

V^CC= 3.3 V,

Internal frequency 24 MHz,

At sleep mode

Power

supply

current

I^CCS

⎯

27

3.5

1

40

10

2

mA

V^CC

V^CC= 3.3 V,

Internal frequency 24 MHz,

At timer mode

I^CTS

V^CC= 3.3 V,

Internal frequency 3 MHz,

At timer mode

V^CC= 3.3 V,

Internal frequency 8 kHz,

At subclock operation,

(T^A= +25 °C)

I^CCL

⎯

25 150 µA

(Continued)

91

MB90330 Series

(Continued)

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Conditions

Unit

Remarks

Min

Typ

Max

V^CC= 3.3 V,

Internal frequency 8 kHz,

At sub clock,

I^CCLs

⎯

10

50

µA

At sleep operating,

(T^A= + 25 °C)

V^CC= 3.3 V,

Internal frequency 8 kHz,

Watch mode,

Power

supply

current

V^CC

I^CCT

⎯

1.5

40

µA

(T^A= + 25 °C)

T^A= + 25 °C,

I^CCH

⎯

25

1

5

40

15

µA

pF

kΩ

At stop

Input

capacitance

OtherthanAVcc,

AVss, Vcc, Vss

C^IN

⎯

Pull-up

resistor

R^upRST

50

100

Note : P60 to P67, P96, PA0 to PA7, and PB0 to PB4 are Nch open-drain pins usually used as CMOS.

92

MB90330 Series

4. AC Characteristics

(1)Clock input timing

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

Parameter

Pin name

Unit

Remarks

Min

⎯

Typ

6

Max

⎯

MHz External crystal oscillation

MHz External clock input

kHz

f^CH

f^CL

t^HCYL

t^LCYL

X0, X1

X0A, X1A

X0, X1

Clock frequency

6

⎯

24

⎯

166.7

⎯

32.768

166.7

⎯

41.7

⎯

ns External crystal oscillation

ns External clock input

s

Clock cycle time

X0A, X1A

X0

30.5

P^WH

P^WL

A reference duty ratio is

30% to 70%.

10

⎯

15.2

⎯

5

ns

Input clock pulse width

P^WHL

P^WLL

X0A

X0

s

Input clock rise time and fall

time

tcr

tcf

ns At external clock

f^CP

f^CPL

t^CP

⎯

3

⎯

8.192

⎯

24

⎯

333

⎯

MHz When main clock is used

kHz When sub clock is used

ns When main clock is used

Internal operating clock

frequency

⎯

42

⎯

Internal operating clock

cycle time

t^CPL

122.1

s

When sub clock is used

• Clock Timing

tHCYL

0.8 VCC

0.2 VCC

X0

PWH

PWL

tcr

tcf

tLCYL

0.8 VCC

0.2 VCC

X0A

PWLH

PWLL

tcr

tcf

93

MB90330 Series

• PLL operation guarantee range

Relation between internal operation clock frequency and power supply voltage

PLL operation guarantee range

3.6

3.0

2.7

Normal Operation

Assurance Range

3

6

12

24

Internal clock F^CP(MHz)

Note : When the USB is used, operation is guaranteed at voltages between 3.0 V and 3.6 V.

Relation between oscillation frequency and internal operation clock frequency

24

Multiplied by 4

Multiplied by 2

12

External clock

6

Multiplied by 1

3

6

24

Oscillation clock Fc (MHz)

94

MB90330 Series

The AC standards assume the following measurement reference voltages.

• Input signal waveform

• Output signal waveform

Hysteresis input pin

Output pin

0.8 VCC

2.4 V

0.2 VCC

0.8 V

Hysteresis input/other than MD input pin

0.7 VCC

0.3 VCC

95

MB90330 Series

(2)Clock output timing

(V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Parameter

Cycle time

Symbol Pin name

Conditions

Unit

Remarks

Min

t^CP

Max

⎯

t^CYC

CLK

⎯

ns

t^CP/2 − 15

t^CP/2 + 15

t^CP/2 + 20

t^CP/2 + 64

At f^cp= 24 MHz

At f^cp= 12 MHz

At f^cp= 6 MHz

CLK↑→CLK↓

t^CHCL

V^CC= 3.0 V to 3.6 V t^CP/2 − 20

t^CP/2 − 64

Note : t^CP: See “ (1) Clock input timing”.

t

CYC

t

CHCL

2.4 V

0.8 V

CLK

96

MB90330 Series

(3) Reset

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

bol

name

Condi-

tions

Parameter

Unit

Remarks

Min

Max

At normal operating,

At time base timer mode,

At main sleep mode,

At PLL sleep mode

500

⎯

ns

Reset input time

t^RSTL

RST

⎯

At stop mode,

Oscillation time

of oscillator* +

500 ns

At sub clock mode,

At sub sleep mode,

At watch mode

⎯

µs

* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several

dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a

FAR/ceramic oscillator, and 0 milliseconds on an external clock.

• During normal operation, time-base timer mode, main sleep mode and PLL sleep mode

t

RSTL

RST

0.2 Vcc

• During stop mode, subclock mode, sub-sleep mode and watch mode

t

RSTL

RST

X0

0.2 Vcc

90% of

amplitude

Internal

operation

clock

Oscillation time

of oscillator

500 ns

Oscillation stabilization wait time

Execute

instruction

Internal reset

97

MB90330 Series

(4) Power-on reset

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to +85 °C)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

Max

Power supply rising time

t^R

V^CC

⎯

30

ms

⎯

Power supply shutdown

time

t^OFF

1

⎯

ms For repeated operation

Notes : • V^CCmust be lower than 0.2 V before the power supply is turned on.

• The above standard is a value for performing a power-on reset.

• In the device, there are internal registers which is initialized only by a power-on reset.

When the initialization of these items is expected, turn on the power supply according to the standards.

tR

2.7 V

0.2 V

VCC

0.2 V

t^OFF

Sudden change of power supply voltage may activate the power-on reset function.

When changing the power supply voltage during operation as illustrated below, voltage fluctuation

should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not

use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.

VCC

The rising edge should be 50 mV/ms

or less.

3.0 V

RAM data hold

VSS

98

MB90330 Series

(5) UART0, 1, 2, 3 I/O extended serial timing

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym

bol

Parameter

Pin name

Conditions

Unit Remarks

Min

Max

Serial clock cycle time

t^SCYC

t^SLOV

SCKx

8 t^CP

⎯

ns

SCKx,

SOTx

SCK↓→SOT delay time

− 80

100

60

+ 80

⎯

Internal shift clock

mode output pin is :

C^L= 80 pF + 1TTL

SCKx,

SINx

Valid SIN→SCK↑

t^IVSH

t^SHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

ns

SCKx,

SINx

SCK↑→valid SIN hold time

Serial clock H pulse width

Serial clock L pulse width

SCK↓→SOT delay time

Valid SIN→SCK↑

⎯

SCKx,

SINx

4 t^CP

⎯

SCKx,

SINx

⎯

External shift clock

modeoutputpinis:

C^L= 80 pF + 1TTL

SCKx,

SOTx

150

⎯

SCKx,

SINx

60

SCKx,

SINx

SCK↑→valid SIN hold time

60

⎯

Notes : • Above rating is the case of CLK synchronous mode.

• C^Lis a load capacitance value on pins for testing.

• t^CP: See “ (1) Clock input timing”.

99

MB90330 Series

• Internal shift clock mode

tSCYC

SCK

2.4 V

0.8 V

tSLOV

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

• External shift clock mode

tSLSH

tSHSL

SCK

0.8 VCC

0.2 VCC

tSLOV

0.2 VCC

2.4 V

0.8 V

SOT

SIN

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

100

MB90330 Series

2

(6) I C timing

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Parameter

Symbol

Conditions

Unit

Min

Max

SCL clock frequency

t^SCL

0

100

kHz

(Repeat) [start] condition hold

time

SDA ↓ → SCL ↓

t^HDSTA

4.0

⎯

µs

Power-supply voltage of external pull-up

resistor at 5.0 V.

R = 1.2 kΩ, C = 50 pF*²

SCL clock “L” width

SCL clock “H” width

t^LOW

t^HIGH

4.7

4.0

⎯

µs

Power-supply voltage of external pull-up

resistor at 3.6 V.

R = 1.0 kΩ, C = 50 pF*²

Repeat [start] condition setup time

SCL ↑ → SDA ↓

t^SUSTA

t^HDDAT

4.7

0

⎯

µs

Data hold time

SCL ↓ → SDA ↓ ↑

3.45*³

Power-supply voltage of external pull-up

resistor at 5.0 V.

f^CP*¹≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*²

Power-supply voltage of external pull-up

resistor at 3.6 V.

250

200

⎯

f^CP*¹≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*²

Data setup time

SDA ↓ ↑ → SCL ↑

t^SUDAT

ns

Power-supply voltage of external pull-up

resistor at 5.0 V.

f^CP*¹> 20 MHz, R = 1.2 kΩ, C = 50 pF*²

Power-supply voltage of external pull-up

resistor at 3.6 V.

f^CP*¹> 20 MHz, R = 1.0 kΩ, C = 50 pF*²

[Stop] condition setup time

SCL ↑ → SDA ↑

Power-supply voltage of external pull-up

resistor at 5.0 V.

t^SUSTO

4.0

4.7

⎯

µs

R = 1.2 kΩ, C = 50 pF*²

Power-supply voltage of external pull-up

resistor at 3.6 V.

R = 1.0 kΩ, C = 50 pF*²

Bus free time between [stop]

condition and [start] condition

t^BUS

*1 : f^CPis internal operating clock frequency. See “ (1) Clock input timing”.

*2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance.

*3 : The maximum t^HDDATonly has to be met if the device does not stretch the “L” width (t^LOW) of the SCL signal.

SDA

tBUS

tHDSTA

tLOW

tSUDAT

SCL

tHDSTA

tHDDAT

tHIGH

tSUSTA

tSUSTO

101

MB90330 Series

(7) Timer input timing

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

Max

FRCK,

INx, TINx

PWC

t^TIWH

t^TIWL

Input pulse width

⎯

4 t^CP

⎯

ns

Note : t^CP: See “ (1) Clock input timing”.

0.8 VCC

0.2 VCC

PWC

TINx

INx

0.2 VCC

FRCK

tTIWH

tTIWL

(8) Timer output timing

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Sym-

Condi-

tions

Parameter

bol

Pin name

Unit

Remarks

Min

Max

CLK↑→T^OUTchange time

PPG0 to PPG5 change time

OUT0 to OUT3 change time

TOTx,

PPGx,

OUTx

t^TO

⎯

30

⎯

ns

2.4 V

t^TO

CLK

PPGx

OUTx

2.4 V

0.8 V

(9) Trigger input timing

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Condi-

tions

Parameter

Symbol Pin name

Unit

Remarks

Min

5 t^CP

1

Max

⎯

ns At normal operating

t^TRGH

t^TRGL

INTx,

ADTG

Input pulse width

⎯

µs In Stop mode

Note : t^CP: See “ (1) Clock input timing”.

0.8 VCC

0.2 VCC

INTx

ADTGx

tTRGH

tTRGL

102

MB90330 Series

(10) Bus read timing

Parameter

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= 0 °C to + 70 °C)

Value

Sym

bol

Condi-

tions

Pin name

Unit

Remarks

Min

Max

⎯

t^CP/2 − 15

t^CP/2 − 20

t^CP/2 − 35

t^CP/2 − 17

t^CP/2 − 40

ns At f^cp= 24 MHz

ns At f^cp= 12 MHz

ns At f^cp= 6 MHz

ns

ALE pulse width

t^LHLL

ALE

⎯

Address,

ALE

Valid address→ALE↓time t^AVLL

ALE↓→Address valid time t^LLAX

⎯

ns At f^cp= 6 MHz

ALE,

⎯

t^CP/2 − 12

t^CP− 25

⎯

ns

Address

RD,

Valid address→RD↓time

t^AVRL

Address

⎯

5 t^CP/2 − 55

5 t^CP/2 − 80

⎯

ns

Valid address→valid data

Address/

data

t^AVDV

⎯

input

⎯

3 t^CP/2 − 25

3 t^CP/2 − 20

⎯

ns At f^cp= 6 MHz

ns At f^cp= 24 MHz

ns At f^cp= 12 MHz

ns

RD pulse width

t^RLRH

RD

⎯

3 t^CP/2 − 55

3 t^CP/2 − 80

RD,

Data

RD↓→valid data input

t^RLDV

⎯

ns At f^cp= 6 MHz

RD,

Data

RD↓→data hold time

RD↑→ALE↑time

t^RHDX

t^RHLH

t^RHAX

⎯

0

⎯

ns

RD, ALE

t^CP/2 − 15

t^CP/2 − 10

Address,

RD

RD↑→address valid time

Address,

CLK

Valid address→CLK↑time t^AVCH

⎯

t^CP/2 − 17

⎯

ns

RD↓→CLK↑time

ALE↓→RD↓time

t^RLCH

t^LLRL

RD, CLK

RD, ALE

⎯

t^CP/2 − 17

t^CP/2 − 15

⎯

ns

Note : t^CP: See “ (1) Clock input timing”.

103

MB90330 Series

tAVCH

tRLCH

2.4 V

CLK

tRHLH

2.4 V

0.8 V

2.4 V

ALE

tLHLL

tAVLL

tRLRH

2.4 V

RD

tLLAX

tLLRL

0.8 V

In multiplex mode

tAVRL

tRLDV

tRHAX

2.4 V

0.8 V

A23 to A16

0.8 V

tAVDV

tRHDX

2.4 V

0.8 V

2.4 V

0.8 V

0.7 VCC

0.3 V^CC

0.7 VCC

0.3 VCC

AD15 to AD00

Read data

Address

tRHAX

In non-multiplex mode

A23 to A00

2.4 V

0.8 V

2.4 V

0.8 V

tRLDV

tRHDX

tAVDV

0.7 VCC

0.3 V^CC

0.7 VCC

0.3 VCC

D15 to D00

Read data

104

MB90330 Series

(11) Bus write timing

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= 0 °C to + 70 °C)

Value

Sym-

bol

Condi-

tions

Parameter

Pin name

Unit

Remarks

Min

Max

Address,

WR

Valid address→WR↓time

t^AVWL

⎯

t^CP− 15

⎯

ns

⎯

3 t^CP/2 − 25

3 t^CP/2 − 20

3 t^CP/2 − 15

10

⎯

ns At f^cp= 24 MHz

ns At f^cp= 12 MHz

ns

WR pulse width

t^WLWH

t^DVWH

WRL, WRH

Data, WR

Valid data output→WR↑time

ns At f^cp= 24 MHz

ns At f^cp= 12 MHz

ns At f^cp= 6 MHz

WR,

Data

WR↑→data hold time

t^WHDX

20

30

WR,

Address

WR↑→address valid time

t^WHAX

⎯

t^CP/2 − 10

⎯

ns

WR↑→ALE↑time

WR↓→CLK↑time

t^WHLH

t^WLCH

WR, ALE

WR, CLK

⎯

t^CP/2 − 15

t^CP/2 − 17

⎯

ns

Note : t^CP: See “ (1) Clock input timing”.

t

WLCH

2.4 V

CLK

ALE

t

WHLH

2.4 V

t

WLWH

2.4 V

WR

(WRL, WRH)

0.8 V

In multiplex mode

t

AVWL

t

WHAX

2.4 V

0.8 V

2.4 V

0.8 V

A23 to A16

t

DVWH

t

WHDX

2.4 V

0.8 V

AD15 to AD00

2.4 V

0.8 V

Write data

Address

0.8 V

In non-multiplex mode

A23 to A00

t

WHAX

2.4 V

0.8 V

2.4 V

0.8 V

t

DVWH

t

WHDX

2.4 V

0.8 V

D15 to D00

2.4 V

0.8 V

Write data

105

MB90330 Series

(12) Ready input timing

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= 0 °C to + 70 °C)

Value

Parameter

Symbol

Pin name Conditions

Unit

Remarks

Min

35

70

0

Max

⎯

ns

RDY set-up time

RDY hold time

t^RYHS

t^RYHH

RDY

⎯

f^cp= 6 MHz

⎯

Notes : • If the RDY set-up time is insufficient, use the auto-ready function.

• For input from the RDY pin, be careful as failure to satisfy AC standards may cause the chip to run out of

control.

2.4 V

CLK

ALE

RD/WR

tRYHS

tRYHH

RDY

wait not

applied

0.8 VCC

RDY

wait applies

(1cycle)

0.2 VCC

0.2 V^CC

tRYHS

106

MB90330 Series

(13) Hold timing

Parameter

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= 0 °C to + 70 °C)

Value

Condi-

tions

Symbol Pin name

Unit

Remarks

Min

30

Max

t^CP

Pin floating→HAK↓time

HAK↓→pin valid time

t^XHAL

t^HAHV

HAK

ns

⎯

t^CP

2 t^CP

Notes : • It takes one cycle or more for HAK to change after the HRQ pin is captured.

• t^CP: See “ (1) Clock input timing”.

HAK

2.4 V

0.8 V

tXHAL

tHAHV

High-Z

2.4 V

0.8 V

2.4 V

0.8 V

Each pin

107

MB90330 Series

5. Electrical Characteristics for the A/D Converter

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= − 40 °C to + 85 °C)

Value

Typ

⎯

Sym

bol

Parameter

Resolution

Pin name

Unit

Remarks

Min

⎯

Max

10

⎯

bit

Total error

⎯

3.0

2.5

1.9

LSB

Nonlinear error

Differential linear error

⎯

AV^SS− 1.5 AV^SS+ 0.5 AV^SS+ 2.5

Zero transition voltage V^OTAN0 to AN15

mV

LSB

1 LSB = AVRH/1024

Full-scale transition

V^FSTAN0 to AN15

voltage

AVRH −

1.5 LSB

AVRH +

0.5 LSB

3.5 LSB

*1

Conversion time

Sampling time

⎯

176 t^CP

⎯

ns

*1

64 t^CP

Analog port input

current

I^AIN

AN0 to AN15

⎯

10

µA

Analog input voltage

Reference voltage

V^AIN

⎯

I^A

AN0 to AN15

AVRH

0

2.7

⎯

1.4

⎯

95

⎯

AVRH

AV^CC

3.5

5

V

AV^CC

mA

Power supply current

I^AH

I^R

AV^CC

µA *2

µA

AVRH

170

5

Reference voltage

supplying current

I^RH

⎯

AVRH

µA *2

LSB

Interchannel disparity

AN0 to AN15

4

*1 : t^CP: See “ (1) Clock input timing”.

*2 : The current when the CPU is in stop mode and the A/D converter is not operating (For V^CC= AV^CC= AVRH = 3.3 V).

108

MB90330 Series

Notes :

• About the external impedance of the analog input and its sampling time

• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling

time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting

A/D conversion presicion.

• Analog input circuit model

R

Comparator

R

Analog input

C

During sampling : ON

C

MB90333A

MB90F334A

MB90V330A

1.9 kΩ (Max)

32.3 pF (Max)

25.0 pF (Max)

32.3 pF (Max)

Note : The values are reference values.

• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance

and minimum sampling time and either adjust the resistor value and operating frequency or decrease the

external impedance so that the sampling time is longer than the minimum value.

• The relationship between the external impedance and minimum sampling time

(External impedance = 0 kΩ to 100 kΩ)

(External impedance = 0 kΩ to 20 kΩ)

MB90333A/

MB90V330A

MB90F333A/

MB90V330A

MB90F334A

100

90

80

70

60

50

40

30

20

10

0

20

18

16

14

12

10

8

6

4

2

0

5

10

15

20

25

30

35

0

1

2

3

4

5

6

7

8

Minimum sampling time [µs]

• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.

• About errors

^As|^AVRH| ^{becomes smaller, values of relative errors grow larger.}

109

MB90330 Series

6. USB characteristics

(V^CC= AV^CC= 3.3 V 0.3 V, V^SS= AV^SS= 0.0 V, T^A= 0 °C to + 70 °C)

Value

Sym

Parameter

Unit

Remarks

bol

Min

2.0

⎯

Max

⎯

Input High level voltage

V^IH

V^IL

V^DI

V

Input Low level voltage

0.8

⎯

Input

characteristics

Differential input sensitivity

0.2

0.8

2.8

0.0

1.3

4

V

Differential common mode range V^CM

2.5

3.6

0.3

2.0

20

V

Output High level voltage

Output Low level voltage

Cross over voltage

V^OH

V^OL

V^CRS

t^FR

V

I^OH= − 200 µA

I^OL= 2 mA

V

ns

%

Ω

Full Speed

Low Speed

Full Speed

Low Speed

(T^FR/T^FF)

Rise time

Fall time

t^LR

75

4

300

20

Output

characteristics

t^FF

t^LF

75

90

80

28

300

111.11

125

44

t^RFM

t^RLM

Z^DRV

Rising/falling time matching

Output resistance

(T^LR/T^LF)

Including Rs = 27 Ω

• Data signal timing (Full Speed)

Fall time

Rise time

DVP/HVP

DVM/HVM

90%

Vcrs

10%

tFF

tFR

• Data signal timing (Low Speed)

Rise time

Fall time

HVP

HVM

90%

Vcrs

10%

tLF

tLR

110

MB90330 Series

• Load condition (Full Speed)

RS = 27 Ω

Testing point

DVP/HVP

DVM/HVM

C

= 50 pF

Testing point

C

= 50 pF

• Load condition (Low Speed)

RS = 27 Ω

Testing point

HVP

HVM

C

= 50 pF to 150 pF

RS = 27 Ω

Testing point

C

= 50 pF to 150 pF

111

MB90330 Series

7. Flash memory write/erase characteristics

Value

Typ

Parameter

Condition

Unit

Remarks

Min

Max

Excludes 00^Hprogramming

prior to erasure.

Sector erase time

Chip erase time

⎯

1

9

15

s

T^A= + 25 °C

V^CC= 3.0 V

Excludes 00^Hprogramming

prior to erasure.

⎯

Word (16-bit width)

programming time

Except for over head time of

system level

⎯

10,000

20

16

⎯

3,600

⎯

µs

Programming/erase cycle

⎯

cycle

year

Flash memory data

retaining period

Average

T^A= + 85 °C

⎯

*

* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature

measurements into normalized value at + 85 °C)

112

MB90330 Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90F334APFF

MB90333APFF

120-pin Plastic LQFP

(FPT-120P-M05)

MB90F334APMC

MB90333APMC

120-pin Plastic LQFP

(FPT-120P-M21)

299-pin Ceramic PGA

(PGA-299C-A01)

MB90V330A

For evaluation

113

MB90330 Series

■ PACKAGE DIMENSIONS

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

120-pin Plastic LQFP

(FPT-120P-M05)

16.00±0.20(.630±.008)SQ

*

14.00±0.10(.551±.004)SQ

90

61

91

60

0.08(.003)

Details of "A" part

1.50 ⁺^–0⁰^.^.¹²⁰⁰

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

(Mounting height)

INDEX

120

31

"A"

0~8˚

1

30

LEAD No.

0.10±0.10

(.004±.004)

(Stand off)

0.16±0.03

(.006±.001)

0.145±0.055

(.006±.002)

0.50±0.20

(.020±.008)

M

0.07(.003)

0.40(.016)

0.60±0.15

(.024±.006)

0.25(.010)

C

2003 FUJITSU LIMITED F120006S-c-4-5

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

(Continued)

114

MB90330 Series

(Continued)

120-pin Plastic LQFP

Note 1) * : These dimensions do not include resin protrusion.

Resin protrusion is +0.26 (.010) MAX (each side) .

Note 2) Pins width and pins thickness include plating thickness.

Note 3) Pins width do not include tie bar cutting remainder.

(FPT-120P-M21)

18.00±0.20(.709±.008)SQ

+0.40

16.00 –0.10 .630 ^–⁺^.^.⁰⁰⁰¹⁴⁶SQ

*

90

61

91

60

0.08(.003)

Details of "A" part

1.50 –⁺0⁰.^.1²0⁰

(Mounting height)

.059 –⁺.^.0⁰0⁰4⁸

INDEX

0~8˚

"A"

120

31

0.10±0.05

(.004±.002)

(Stand off)

1

30

LEAD No.

0.145 ⁺–0⁰.^.0⁰3⁵

.006 ⁺^–.^.⁰⁰⁰⁰¹²

0.60±0.15

(.024±.006)

0.22±0.05

(.009±.002)

M

0.08(.003)

0.50(.020)

0.25(.010)

C

2002 FUJITSU LIMITED F120033S-c-4-4

Dimensions in mm (inches)

Note : The values in parentheses are reference values.

115

MB90330 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0411


型号：	MB90F334APMC
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器外围集成电路时钟
文件：	总116页 (文件大小：1306K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB90F334APMC [FUJITSU]

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