MB90F334APMC1 [FUJITSU]
16-bit microcontrollers; 16位微控制器型号: | MB90F334APMC1 |
厂家: | FUJITSU |
描述: | 16-bit microcontrollers |
文件: | 总72页 (文件大小:404K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13734-9E
16-bit Microcontroller
CMOS
F2MC-16LX MB90330A Series
MB90333A/F334A/F335A/V330A
■ DESCRIPTION
The MB90330A series are 16-bit microcontrollers designed for applications, such as personal computer peripheral
devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but
also HOST operation. It is equipped with functions that are suitable for personal computer peripheral devices
such as displays and audio devices, and control of mobile devices that support USB communications. While
inheriting the AT architecture of the F2MC family, the instruction set supports the C language and extended
addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial
collection of improved bit manipulation instructions. In addition, long word processing is now available by intro-
ducing a 32-bit accumulator.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
• Built-in oscillation circuit and PLL clock frequency multiplication circuit
• Oscillation clock
• The main clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz)
• Clock for USB is 48 MHz
• Machine clock frequency of 6 MHz, 12 MHz, or 24 MHz selectable
• Minimum execution time of instruction : 41.7 ns (6 MHz oscillation clock, 4-time multiplied : machine clock
24 MHz and at operating VCC = 3.3 V).
• The maximum memory space : 16 Mbytes
• 24-bit addressing
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2004-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.7
MB90330A Series
(Continued)
• Bank addressing
• Instruction system
• Data types : Bit, Byte, Word and Long word
• Addressing mode (23 types)
• Enhanced high-precision computing with 32-bit accumulator
• Enhanced Multiply/Divide instructions with sign and the RETI instruction
• Instruction system compatible with high-level language (C language) and multi-task
• Employing system stack pointer
• Instruction set symmetry and barrel shift instructions
• Program Patch Function (2 address pointer)
• 4-byte instruction queue
• Interrupt function
• Priority levels are programmable
• 32 interrupts function
• Data transfer function
• Extended intelligent I/O service function (EI2OS) : Maximum of 16 channels
• μDMAC : Maximum 16 channels
• Low Power Consumption Mode
• Sleep mode (with the CPU operating clock stopped)
• Time-base timer mode (with the oscillator clock and time-base timer operating)
• Stop mode (with the oscillator clock stopped)
• CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles)
• Watch mode (with 32 kHz oscillator clock and watch timer operating)
• Package
• LQFP-120P (FPT-120P-M24 : 0.40 mm pin pitch)
• LQFP-120P (FPT-120P-M21 : 0.50 mm pin pitch)
• Process : CMOS technology
• Operation guaranteed temperature : − 40 °C to + 85 °C (0 °C to + 70 °C when USB is in use)
2
DS07-13734-9E
MB90330A Series
■ INTERNAL PERIPHERAL FUNCTION (RESOURCE)
• I/O port : Max 94 ports
• Time-base timer : 1 channel
• Watchdog timer : 1 channel
• Watch timer : 1 channel
• 16-bit reload timer : 3 channels
• Multi-functional timer
• 16-bit free run timer : 1 channel
• Output compare : 4 channels
An interrupt request can be output when the 16-bit free-run timer value matches the compare register value.
• Input capture : 4 channels
Upon detection of the effective edge of the signal input to the external input pin, the input capture unit sets the
input capture data register to the 16-bit free-run timer value to output an interrupt request.
• 8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels) the period and duty of the output pulse can be
set by the program.
• 16-bit PWC timer : 1 channel
Timer function and pulse width measurement function
• UART : 4 channels
• Full-duplex double buffer (8-bit length)
• Asynchronous transfer or clock-synchronous serial (Extended I/O serial) transfer can be set.
• Extended I/O serial interface : 1 channel
• DTP/External interrupt circuit (8 channels)
• Activate the extended intelligent I/O service by external interrupt input
• Interrupt output by external interrupt input
• Delay interrupt output module
• Output an interrupt request for task switching
• 8/10-bit A/D converter : 16 channels
• 8-bit resolution or 10-bit resolution can be set.
• USB : 1 channel
• USB function (correspond to USB Full Speed)
• Full Speed is supported/Endpoint are specifiable up to six.
• Dual port RAM (The FIFO mode is supported).
• Transfer type : Control, Interrupt, Bulk, or Isochronous transfer possible
• USB HOST function
• I2C Interface : 3 channels
• Supports Intel SM bus standard and Phillips I2C bus standards
• Two-wire data transfer protocol specification
• Master and slave transmission/reception
DS07-13734-9E
3
MB90330A Series
■ PRODUCT LINEUP
Part number
MB90V330A
MB90F334A
MB90F335A
MB90333A
Built-in Flash
memory
Built-in Flash
memory
Built-in MASK
ROM
Type
For evaluation
ROM capacity
No
28 Kbytes
Yes
384 Kbytes
24 Kbytes
512 Kbytes
30 Kbytes
⎯
256 Kbytes
16 Kbytes
RAM capacity
Emulator-specific power supply *
Number of basic instructions
Minimum instruction execution time : 41.7 ns/at oscillation of 6 MHz
(When 4 times are used : Machine clock
: 351 instructions
CPU functions
of 24 MHz)
: 23 types
Addressing type
Program Patch Function
Maximum memory space
: For 2 address pointers
: 16 Mbytes
Ports
I/O Ports (CMOS) 94 ports
Equipped with full-duplex double buffer
Clock synchronous or asynchronous operation selectable
It can also be used for I/O serial
UART
Built-in special baud-rate generator
Built-in 4 channels
16-bit reload timer operation
Built-in 3 channels
16-bit reload timer
16-bit free run timer × 1 channel
Output compare × 4 channels
Input capture × 4 channels
Multi-functional timer
8/16-bit PPG timer (8-bit mode × 6 channels, 16-bit mode × 3 channels)
16-bit PWC timer × 1 channel
16 channels (input multiplex)
8/10-bit A/D converter
DTP/External interrupt
8-bit resolution or 10-bit resolution can be set.
Conversion time : 7.16 μs at minimum (24 MHz machine clock at maximum)
8 channels
Interrupt factor : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable
I2C
3 channels
1 channel
Extended I/O serial interface
1 channel
USB
USB function (correspond to USB Full Speed)
USB HOST function
External bus interface
For multi-bus/non-multi-bus
Withstand voltage of 5 V
16 ports (excluding UTEST and I/O for I2C)
Sleep mode/Time-base timer mode/Stop mode/CPU intermittent mode/
Watch mode
Low Power Consumption Mode
Process
CMOS
Operating voltage
3.3 V 0.3 V (at maximum machine clock 24 MHz)
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the
MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
4
DS07-13734-9E
MB90330A Series
■ PACKAGES AND PRODUCT MODELS
Package
MB90333A
MB90F334A
MB90F335A
MB90V330A
FPT-120P-M24 (LQFP-0.40 mm)
FPT-120P-M21 (LQFP-0.50 mm)
PGA-299C-A01 (PGA)
×
×
×
×
×
: Yes × : No
Note : For detailed information on each package, refer to “■ PACKAGE DIMENSIONS”.
DS07-13734-9E
5
MB90330A Series
■ PIN ASSIGNMENT
(TOP VIEW)
P30/A00/TIN1
P31/A01/TOT1
P32/A02/TIN2
P33/A03/TOT2
P34/A04
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
MD0
MD1
MD2
P55/HAK
P54/HRQ
P53/WRH
P52/WRL
P51/RD
P50/ALE
HCON
P35/A05
P36/A06
P37/A07
P40/A08/TIN0
P41/A09/TOT0
P42/A10/SIN0
P43/A11/SOT0
X0A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
HVP
HVM
X1A
VCC
VSS
VSS
VCC
P44/A12/SCK0
P45/A13/SIN1
P46/A14/SOT1
P47/A15/SCK1
P60/INT0
DVP
DVM
VSS
UTEST
PB6/PPG5
PB5/PPG4
PB4
PB3/SDA2
PB2/SCL2
PB1/SDA1
PB0/SCL1
PA7/OUT3
PA6/OUT2
PA5/OUT1
P61/INT1
P62/INT2/SIN
P63/INT3/SOT
P64/INT4/SCK
P65/INT5/PWC
P66/INT6/SCL0
P67/INT7/SDA0
P90/SIN2
P91/SOT2
(FPT-120P-M24 / FPT-120P-M21)
6
DS07-13734-9E
MB90330A Series
■ PIN DESCRIPTION
I/O
Circuit
type*
Pin no.
Pin name
Function
Terminals to connect the oscillator.
108, 107
X0, X1
A
When connecting an external clock, leave the X1 pin side unconnected.
13, 14
90
X0A, X1A
RST
A
F
32 kHz oscillation terminals.
External reset input pin.
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1)
by the pull-up resistor setting register (RDR0). (When the power output is
set, it is invalid.)
P00 to P07
93 to 100
H
Function as an I/O pin for the low-order external address and data bus in
multiplex mode.
AD00 to AD07
D00 to D07
Function as an output pin for the low-order external data bus in non-
multiplex mode.
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD10 to RD13 = 1)
by the pull-up resistor setting register (RDR1). (When the power output is
set, it is invalid.)
P10 to P13
101 to 104
H
Function as an I/O pin for the high-order external address and data bus in
multiplex mode.
AD08 to AD11
D08 to D11
Function as an output pin for the high-order external data bus in non-
multiplex mode.
General purpose input/output port.
The ports can be set to be added with a pull-up resistor (RD14 to RD17 = 1)
by the pull-up resistor setting register (RDR1). (When the power output is
set, it is invalid.)
P14 to P17
109 to 112
H
D
Function as an I/O pin for the high-order external address and data bus in
multiplex mode.
AD12 to D15
D12 to D15
Function as an output pin for the high-order external data bus in non-
multiplex mode.
This is a general purpose I/O port. When the bits of external address output
control register (HACR) are set to “1” in external bus mode, these pins
function as general purpose I/O ports.
P20 to P23
A16 to A19
113 to 116
When the bits of external address output control register (HACR) are set to
“0” in multiplex mode, these pins function as address high output pins.
When the bits of external address output control register (HACR) are set to
“0” in non-multiplex mode, these pins function as address high output pins.
(Continued)
DS07-13734-9E
7
MB90330A Series
I/O
Circuit
type*
Pin no.
Pin name
Function
This is a general purpose I/O port. When the bits of external address
output control register (HACR) are set to “1” in external bus mode, these
pins function as general purpose I/O ports.
P24 to P27
When the bits of external address output control register (HACR) are set
to “0” in multiplex mode, these pins function as address high output pins.
117 to 120
D
A20 to A23
When the bits of external address output control register (HACR) are set
to “0” in non-multiplex mode, these pins function as address high output
pins.
PPG0 to PPG3
P30
Function as ch.0 to ch.3 output pins for the 8-bit PPG timer.
General purpose input/output port.
1
2
3
A00
D
D
D
Function as the external address pin in non-multi-bus mode.
Function as an event input pin for 16-bit reload timer ch.1.
General purpose input/output port.
TIN1
P31
A01
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.1.
General purpose input/output port.
TOT1
P32
A02
Function as the external address pin in non-multi-bus mode.
Function as an event input pin for 16-bit reload timer ch.2.
General purpose input/output port.
TIN2
P33
4
5 to 8
9
A03
D
D
G
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.2.
General purpose input/output port.
TOT2
P34 to P37
A04 to A07
P40
Function as the external address pin in non-multi-bus mode.
General purpose input/output port.
A08
Function as the external address pin in non-multi-bus mode.
Function as an event input pin for 16-bit reload timer ch.0.
General purpose input/output port.
TIN0
P41
10
11
12
17
A09
G
G
G
G
Function as the external address pin in non-multi-bus mode.
Function as the output pin for 16-bit reload timer ch.0.
General purpose input/output port.
TOT0
P42
A10
Function as the external address pin in non-multi-bus mode.
Function as a data input pin for UART ch.0.
SIN0
P43
General purpose input/output port.
A11
Function as the external address pin in non-multi-bus mode.
Function as a data output pin for UART ch.0.
General purpose input/output port.
SOT0
P44
A12
Function as the external address pin in non-multi-bus mode.
Function as a clock I/O pin for UART ch.0.
SCK0
(Continued)
8
DS07-13734-9E
MB90330A Series
I/O
Circuit
type*
Pin no.
Pin name
Function
General purpose input/output port.
P45
A13
SIN1
P46
A14
SOT1
P47
A15
SCK1
P50
ALE
P51
RD
18
G
G
G
Function as the external address pin in non-multi-bus mode.
Function as a data input pin for UART ch.1.
General purpose input/output port.
19
20
Function as the external address pin in non-multi-bus mode.
Function as a data output pin for UART ch.1.
General purpose input/output port.
Function as the external address pin in non-multi-bus mode.
Function as a clock I/O pin for UART ch.1.
General purpose input/output port.
81
82
L
L
Function as the address latch enable signal pin in external bus mode.
General purpose input/output port.
Function as the read strobe output pin in external bus mode.
General purpose input/output port.
P52
Function as the data write strobe output pin on the lower side in external
bus mode. This pin functions as a general-purpose I/O port when the WRE
bit in the EPCR register is “0”.
83
84
85
86
91
L
L
L
L
L
WRL
P53
General purpose input/output port.
Function as the data write strobe output pin on the higher side in bus width
16-bit external bus mode. This pin functions as a general-purpose I/O port
when the WRE bit in the EPCR register is “0”.
WRH
P54
General purpose input/output port.
Function as the hold request input pin in external bus mode. This pin
functions as a general-purpose I/O port when the HDE bit in the EPCR
register is “0”.
HRQ
P55
General purpose input/output port.
Function as the hold acknowledge output pin in external bus mode. This pin
functions as a general-purpose I/O port when the HDE bit in the EPCR
register is “0”.
HAK
P56
General purpose input/output port.
Function as the external ready input pin in external bus mode. This pin
functions as a general-purpose I/O port when the RYE bit in the EPCR
register is “0”.
RDY
P57
General purpose input/output port.
Function as the machine cycle clock output pin in external bus mode. This
pin functions as a general-purpose I/O port when the CKE bit in the EPCR
register is “0”.
92
L
CLK
P60, P61
General purpose input/output port. (With stand voltage of 5 V)
Function as external interrupt ch.0 and ch.1 input pins.
(Continued)
21, 22
C
INT0, INT1
DS07-13734-9E
9
MB90330A Series
I/O
Pin no.
Pin name Circuit
type*
Function
P62
General purpose input/output ports. (Withstand voltage of 5 V)
Function as an external interrupt ch.2 input pin.
Extended I/O serial interface data input pin.
23
INT2
SIN
C
C
C
C
P63
General purpose input/output port. (Withstand voltage of 5 V)
Function as an external interrupt ch.3 input pin.
Extended I/O serial interface data output pin.
24
25
26
INT3
SOT
P64
General purpose input/output port. (Withstand voltage of 5 V)
Function as an external interrupt ch.4 input pin.
Extended I/O serial interface clock input/output pin.
General purpose input/output port. (Withstand voltage of 5 V)
Function as an external interrupt ch.5 input pin.
Function as the PWC input pin.
INT4
SCK
P65
INT5
PWC
P66
General purpose input/output port. (Withstand voltage of 5 V)
Function as an external interrupt ch.6 input pin.
INT6
27
28
C
C
Function as the ch.0 clock I/O pin for the I2C interface. Set port output to
SCL0
High-Z during I2C interface operations.
P67
General purpose input/output port. (Withstand voltage of 5 V)
Function as an external interrupt ch.7 input pin.
INT7
Function as the ch.0 data I/O pin for the I2C interface. Set port output to
SDA0
High-Z during I2C interface operations.
P70 to P77
AN0 to AN7
P80 to P87
AN8 to AN15
P90
General purpose input/output port.
39 to 46
48 to 55
29
I
Function as input pins for analog ch.0 to ch.7.
General purpose input/output port.
I
Function as input pins for analog ch.8 to ch.15.
General purpose input/output port.
D
D
D
D
D
D
SIN2
Function as a data input pin for UART ch.2.
General purpose input/output port.
P91
30
SOT2
P92
Function as a data output pin for UART ch.2.
General purpose input/output port.
31
SCK2
P93
Function as a clock I/O pin for UART ch.2.
General purpose input/output port.
32
SIN3
Function as a data input pin for UART ch.3.
General purpose input/output port.
P94
33
SOT3
P95
Function as a data output pin for UART ch.3.
General purpose input/output port.
34
SCK3
P96
Function as a clock I/O pin for UART ch.3.
General purpose input/output port. (Withstand voltage of 5 V)
Function as the external trigger input pin when the A/D converter is being used.
Function as the external clock input pin when the free-run timer is being used.
35
ADTG
FRCK
C
(Continued)
10
DS07-13734-9E
MB90330A Series
(Continued)
I/O
Circuit
type*
Pin no.
Pin name
Function
PA0 to PA3
IN0 to IN3
PA4 to PA7
General purpose input/output port. (Withstand voltage of 5 V)
Function as the input capture ch.0 to ch.3 trigger inputs.
General purpose input/output port. (Withstand voltage of 5 V)
Function as the output compare ch.0 to ch.3 event output pins.
General purpose input/output port. (Withstand voltage of 5 V)
56 to 59
60 to 63
C
C
OUT0 to OUT3
PB0
Function as the ch.1 clock I/O pin for the I2C interface. Set port output to
64
65
66
67
C
C
C
C
SCL1
PB1
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
Function as the ch.1 data I/O pin for the I2C interface. Set port output to
SDA1
PB2
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
Function as the ch.2 clock I/O pin for the I2C interface. Set port output to
SCL2
PB3
High-Z during I2C interface operations.
General purpose input/output port. (Withstand voltage of 5 V)
Function as the ch.2 data I/O pin for the I2C interface. Set port output to
SDA2
High-Z during I2C interface operations.
68
PB4
PB5, PB6
PPG4, PPG5
UTEST
DVM
C
D
General purpose input/output port. (Withstand voltage of 5 V)
General purpose input/output port.
Function as ch.4 and ch.5 output pins for the 8-bit PPG timer.
USB test pin. Connect this to a pull-down resistor during normal usage.
USB function D− pin.
USB function D+ pin.
USB HOST D− pin.
USB HOST D+ pin.
External pull-up resistor connect pin.
A/D converter power supply pin.
69, 70
71
73
74
77
78
80
36
37
38
C
K
DVP
K
HVM
K
HVP
K
HCON
AVcc
E
⎯
J
AVRH
AVss
A/D converter external reference power supply pin.
A/D converter power supply pin.
⎯
B
87 to 89 MD2 to MD0
Operation mode select input pin.
15, 75,
Vcc
⎯
Power supply pin.
79, 105
16, 47,
72, 76,
106
Vss
⎯
Power supply pin (GND).
* : For circuit information, refer to “■ I/O CIRCUIT TYPE”.
DS07-13734-9E
11
MB90330A Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• High-rateoscillationfeedbackresistor,
approx.1 MΩ
• Low-rate oscillation feedback resistor,
X1
Clock input
X1A
X0
approx.10 MΩ
• With standby control
X0A
Standby control signal
B
C
CMOS hysteresis input
CMOS hysteresis
input
• CMOS hysteresis input
• N-ch open drain output
N-ch
Nout
CMOS hysteresis input
Standby control signal
D
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
P-ch
N-ch
Pout
Nout
Notes : • Share one output buffer because
both output of I/O port and
internal resource are used.
• Share one input buffer because
both input of I/O port and internal
resource are used.
CMOS hysteresis input
Standby control signal
E
F
CMOS output
P-ch
N-ch
Pout
Nout
CMOS hysteresis input with pull-up resistor
R
CMOS hysteresis
input
(Continued)
12
DS07-13734-9E
MB90330A Series
Type
Circuit
Remarks
G
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
Open drain control
signal
P-ch
N-ch
Pout
With open drain control signal
Nout
CMOS hysteresis
input
Standby control
signal
H
• CMOS output
• CMOS input
CTL
(With input interception function at
standby)
• With input pull-up register control
R
P-ch
N-ch
Pout
Nout
CMOS input
Standby control signal
I
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
• Analog input
P-ch
N-ch
Pout
Nout
(TheA/Dconverteranaloginputisenabled
when the corresponding bit in the analog
input enable register (ADER) is 1.)
Notes: • Because the output of the I/O port and
the output of internal resources are
used combinedly, one output buffer
is shared.
CMOS hysteresis
input
Standby control signal
A/D converter analog
input
• Because the input of the I/O port
and the input of internal resources
are used combinedly, one input
buffer is shared.
J
A/D converter (AVRH) voltage input pin
P-ch
N-ch
P-ch
N-ch
AVRH input
A/D converter
analog input
enable signal
(Continued)
DS07-13734-9E
13
MB90330A Series
(Continued)
Type
Circuit
Remarks
K
USB I/O pin
D + input
D - input
+
D
Differential input
Full D + output
−
D
Full D - output
Low D + output
Low D - output
Direction
Speed
L
• CMOS output
• CMOS input
• With standby control
P-ch
N-ch
Pout
Nout
CMOS input
Standby control signal
14
DS07-13734-9E
MB90330A Series
■ HANDLING DEVICES
1. Preventing latch-up and turning on power supply
Latch-up may occur on CMOS IC under the following conditions:
• If a voltage higher than VCC or lower than VSS is applied to input and output pins.
• A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
• If the AVCC power supply is turned on before the VCC voltage.
Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the
digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as
VCC and the digital power supply).
If latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device.
Use meticulous care not to let any voltage exceed the maximum rating.
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent
damage.
Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/
output pins may be set to output mode and left open, or set to input mode and treated the same as unused input
pins. If there is unused output pin, make it to open.
3. Treatment of power supply pins on models with A/D converters
Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC,
and AVSS = VSS.
4. About the attention when the external clock is used
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or
when recovering from sub clock or stop mode. When suing an external clock, 25 MHz should be the upper
frequency limit.
The following figure shows a sample use of external clock signals.
• Using external clock
X0
OPEN
X1
5. Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the
current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC pin and VSS pin
near this device.
DS07-13734-9E
15
MB90330A Series
6. About Crystal oscillator circuit
Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass
capacitor to ground are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded
by ground plane because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
7. Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
8. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage
operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations
(peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard VCC supply voltage
and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply switching.
9. When the dual-supply is used as a single-supply device
If you are using only a single-system of the MB90330A series that come in the dual-system product, use it with
X0A = VSS : X1A = OPEN.
10. Writing to flash memory
For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V.
For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V.
11. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore,
design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error.
If an error is detected, retransmit the data.
16
DS07-13734-9E
MB90330A Series
■ BLOCK DIAGRAM
X0, X1
X0A,X1A
RST
F2MC-16LX
CPU
Clock control
circuit
MD0 to MD2
Interrupt
controller
8/16-bit
PPG0 to PPG5
IN0 to IN3
PPG timer
ch.0 to ch.5*
RAM
ROM
Input capture
ch.0 to ch.3
SIN0 to SIN3
SOT0 to SOT3
SCK0 to SCK3
UART/SIO
ch.0 to ch.3
I2C
ch.0 to ch.2
SCL0 to SCL2
SDA0 to SDA2
16-bit free-run
FRCK
timer
AVCC
AVRH
AVSS
8/10-bit A/D
converter
AN0 to AN15
ADTG
Output compare
ch.0 to ch.3
OUT0 to OUT3
PWC
16-bit reload
timer
ch.0 to ch.2
TOT0 to TOT2
TIN0 to TIN2
16-bit PWC
DVP
DVM
HVP
HVM
HCON
UTEST
SIN
SOT
SCK
USB
(Function)
(HOST)
SIO
µDMAC
External
interrupt
INT0 to INT7
I/O port (port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)
PB0
PB6
P80 P90 PA0
P87 P96 PA7
P00 P10 P20 P30 P40 P50 P60 P70
P07 P17 P27 P37 P47 P57 P67 P77
* : Channel for use in 8-bit mode. 3 channels (ch.1, ch.3, ch.5) are used in 16-bit mode.
Note : I/O ports share pins with peripheral function (resources) .
For details, refer to “■ PIN ASSIGNMENT” and “■ PIN DESCRIPTION”.
Note also that pins used for peripheral function (resources) cannot serve as I/O ports.
DS07-13734-9E
17
MB90330A Series
■ MEMORY MAP
Memory map of MB90330A series (1/3)
Single chip mode (with ROM mirror function)
MB90V330A
MB90F334A
MB90F335A
MB90333A
FFFFFF
H
FFFFFF
H
FFFFFF
H
FFFFFF
H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FF bank)
ROM (FE bank)
FF0000
FF0000
FF0000
FEFFFFH
FF0000
FEFFFFH
FEFFFFH
H
FEFFFFH
H
H
H
FE0000
FE0000
FE0000
FDFFFFH
FE0000
FDFFFFH
FDFFFFH
H
FDFFFFH
H
H
H
ROM (FD bank)
FD0000
H
H
FD0000
H
H
FD0000
FCFFFF
FC0000
FBFFFFH
H
H
FD0000
FCFFFF
FC0000
FBFFFFH
H
H
FCFFFF
FCFFFF
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
FC0000
FC0000
FBFFFFH
H
FBFFFFH
H
H
H
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (FB bank)
FB0000
H
FB0000
H
FB0000
FAFFFF
FA0000
F9FFFF
H
H
FB0000
FAFFFF
FA0000
F9FFFF
H
H
FAFFFF
H
FAFFFF
H
FA0000
H
H
FA0000
F9FFFF
H
H
H
H
H
H
F9FFFF
F90000
H
H
F90000
H
H
F90000
F8FFFF
H
H
F90000
F8FFFF
H
H
F8FFFF
F8FFFF
ROM (F8 bank)
F80000
H
F80000
H
F80000
H
F80000
H
00FFFF
008000
H
00FFFF
008000
H
00FFFF
008000
H
00FFFF
008000
H
ROM
(image of FF bank)
ROM
(image of FF bank)
ROM
(image of FF bank)
ROM
(image of FF bank)
007FFFH
H
007FFFH
H
007FFFH
H
007FFFH
H
Peripheral area
Peripheral area
Peripheral area
Peripheral area
007900
H
007900
H
007900
H
007900H
007100
H
RAM area
(30 Kbytes)
006100
H
004100
H
RAM area
RAM area
RAM area
(28 Kbytes)
(24 Kbytes)
(16 Kbytes)
Register
Register
Register
Register
000100
H
H
000100
H
H
000100
H
H
000100
H
H
0000FB
0000FB
0000FB
0000FB
Peripheral area
Peripheral area
Peripheral area
Peripheral area
000000
H
000000
H
000000
H
000000
H
18
DS07-13734-9E
MB90330A Series
Memory map of MB90330A series (2/3)
Internal ROM external bus mode (with ROM mirror function)
MB90V330A
MB90F334A
MB90F335A
MB90333A
FFFFFFH
FFFFFFH
FFFFFFH
FFFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FF bank)
ROM (FE bank)
ROM (FF bank)
ROM (FE bank)
ROM (FF bank)
ROM (FE bank)
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FE0000H
FDFFFFH
FE0000H
FDFFFFH
FE0000H
FDFFFFH
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM (FD bank)
ROM (FD bank)
ROM (FC bank)
ROM (FD bank)
FD0000H
FCFFFFH
FD0000H
FCFFFFH
FD0000H
FCFFFFH
FD0000H
FCFFFFH
*1
*2
FC0000H
FBFFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
FC0000H
FBFFFFH
FC0000H
FBFFFFH
FC0000H
FBFFFFH
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (F8 bank)
ROM (FB bank)
FB0000H
FAFFFFH
FA0000H
F9FFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
FB0000H
FAFFFFH
FA0000H
F9FFFFH
*2
External area
External area
F90000H
F8FFFFH
F90000H
F8FFFFH
F90000H
F8FFFFH
F90000H
F8FFFFH
*1
F80000H
F80000H
F80000H
F80000H
External area
External area
External area
External area
00FFFFH
00FFFFH
00FFFFH
00FFFFH
ROM
ROM
ROM
ROM
(image of FF bank)
(image of FF bank)
(image of FF bank)
(image of FF bank)
008000H
007FFFH
008000H
007FFFH
008000H
007FFFH
008000H
007FFFH
Peripheral area
External area
Peripheral area
External area
Peripheral area
Peripheral area
External area
007900H
007900H
007900H
007900H
007100H
RAM area
(30 Kbytes)
006100H
004100H
RAM area
RAM area
RAM area
(28 Kbytes)
(24 Kbytes)
(16 Kbytes)
Register
Register
Register
Register
000100H
0000FBH
000100H
0000FBH
000100H
0000FBH
000100H
0000FBH
Peripheral area
Peripheral area
Peripheral area
Peripheral area
000000H
000000H
000000H
000000H
*1 : In the area of F80000H to F8FFFFH and FC0000H to FCFFFFH at MB90F334A, a value of “1” is read at
read operating.
*2 : In the area of FA0000H to FAFFFFH and FC0000H to FCFFFFH at MB90333A, a value of “1” is read at
read operating.
DS07-13734-9E
19
MB90330A Series
Memory map of MB90330A series (3/3)
External ROM external bus mode
MB90V330A
MB90F334A
MB90F335A
MB90333A
FFFFFF
H
FFFFFF
H
FFFFFF
H
FFFFFFH
External area
External area
External area
External area
008000
008000
008000
008000
007FFFH
H
007FFFH
H
007FFFH
H
007FFFH
H
Peripheral area
External area
Peripheral area
External area
Peripheral area
Peripheral area
External area
007900
H
007900
H
007900
H
007900H
007100
H
006100
H
RAM area
(30 Kbytes)
004100
H
RAM area
(28 Kbytes)
RAM area
RAM area
(16 Kbytes)
(24 Kbytes)
Register
Register
Register
Register
000100
0000FB
H
H
000100
0000FB
H
H
000100
0000FB
H
H
000100
0000FB
H
H
Peripheral area
Peripheral area
Peripheral area
Peripheral area
000000
H
000000
H
000000
H
000000
H
Notes: • When the ROM mirror function register has been set, the mirror image data at higher addresses
(“FF8000H to FFFFFFH”) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of
bank 00.
• The ROM mirror function is effective for using the C compiler small model.
• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in
bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be
reproduced in bank 00.
• When the C compiler small model is used, the data table mirror image can be shown at “008000H to
00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM
area can be referred without declaring the far addressing with the pointer.
• MB90F335A has the larger size of RAM area than MB90V330A, so that the emulation memory area needs
to be set in the tools for a larger size of emulation area than 007100H.
For details of setting, please refer to “Notes on Debug Environment Setting for MB90330A Series” by
clicking "Application note" at the following URL.
http://edevice.fujitsu.com/micom/en-support/
• 3 cycles are required to access to the emulation memory area (007100H to 0078FFH), which is 1 cycle
more than to the mounted RAM area.
20
DS07-13734-9E
MB90330A Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated register
AH
AL
Accumulator
USP
SSP
PS
User stack pointer
System stack pointer
Processor status
Program counter
PC
DPR
Direct page register
Program bank register
Data bank register
PCB
DTB
USB
SSB
ADB
User stack bank register
System stack bank register
Additional data bank register
8-bit
16-bit
MSB
32-bit
• General purpose register
LSB
16-bit
000180H + RP × 10H
RW0
RW1
RW2
RW3
RL0
RL1
RL2
RL3
R1
R3
R5
R7
R0
R2
R4
R6
RW4
RW5
RW6
RW7
• Processor status
Bit 15
13 12
ILM
8 7
0
PS
RP
CCR
DS07-13734-9E
21
MB90330A Series
■ I/O MAP
Register
Address
Read/
Write
Register
Port 0 Data Register
Resource name
Initial Value
abbreviation
000000H
000001H
000002H
000003H
000004H
000005H
000006H
000007H
000008H
000009H
00000AH
00000BH
00000CH
00000DH
00000EH
00000FH
000010H
000011H
000012H
000013H
000014H
000015H
000016H
000017H
000018H
000019H
00001AH
PDR0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
- XXXXXXXB
XXXXXXXXB
Port 1 Data Register
Port 2 Data Register
Port 3 Data Register
Port 4 Data Register
Port 5 Data Register
Port 6 Data Register
Port 7 Data Register
Port 8 Data Register
Port 9 Data Register
Port A Data Register
Prohibited
Prohibited
PDRB
DDRB
Port B Data Register
R/W
R/W
Port B
Port B
- XXXXXXXB
Port B Direction Register
- 0 0 0 0 0 0 0B
DDR0
DDR1
DDR2
DDR3
DDR4
DDR5
DDR6
DDR7
DDR8
DDR9
DDRA
Port 0 Direction Register
Port 1 Direction Register
Port 2 Direction Register
Port 3 Direction Register
Port 4 Direction Register
Port 5 Direction Register
Port 6 Direction Register
Port 7 Direction Register
Port 8 Direction Register
Port 9 Direction Register
Port A Direction Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Port 4
(opendraincontrol)
00001BH
ODR4
Port 4 Output Pin Register
R/W
0 0 0 0 0 0 0 0B
00001CH
00001DH
00001EH
00001FH
000020H
000021H
RDR0
RDR1
Port 0 Pull-up Resistance Register
Port 1 Pull-up Resistance Register
Analog Input Enable Register 0
Analog Input Enable Register 1
Serial Mode Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R
Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B
Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B
ADER0
ADER1
SMR0
Port 7, 8, A/D
Port 7, 8, A/D
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
SCR0
Serial Control Register 0
SIDR0
SODR0
SSR0
Serial Input Data Register 0
Serial Output Data Register 0
Serial Status Register 0
UART0
000022H
XXXXXXXXB
W
000023H
000024H
000025H
R/W
R/W
R/W
0 0 0 0 1 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 - 0 0 0B
UTRLR0
UTCR0
UART Prescaler Reload Register 0
UART Prescaler Control Register 0
Communication
Prescaler (UART0)
(Continued)
22
DS07-13734-9E
MB90330A Series
Register
abbreviation
Read/
Write
Address
Register
Resource name
Initial Value
000026H
000027H
SMR1
SCR1
Serial Mode Register 1
R/W
R/W
R
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
Serial Control Register 1
SIDR1
SODR1
SSR1
Serial Input Data Register 1
Serial Output Data Register 1
Serial Status Register 1
UART1
000028H
XXXXXXXXB
W
000029H
00002AH
00002BH
00002CH
00002DH
R/W
R/W
R/W
R/W
R/W
R
0 0 0 0 1 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 - 0 0 0B
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
UTRLR1
UTCR1
SMR2
UART Prescaler Reload Register 1
UART Prescaler Control Register 1
Serial Mode Register 2
Communication
Prescaler (UART1)
SCR2
Serial Control Register 2
SIDR2
SODR2
SSR2
Serial Input Data Register 2
Serial Output Data Register 2
Serial Status Register 2
UART2
00002EH
XXXXXXXXB
W
00002FH
000030H
000031H
000032H
000033H
R/W
R/W
R/W
R/W
R/W
R
0 0 0 0 1 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 - 0 0 0B
0 0 1 0 0 0 0 0B
0 0 0 0 0 1 0 0B
UTRLR2
UTCR2
SMR3
UART Prescaler Reload Register 2
UART Prescaler Control Register 2
Serial Mode Register 3
Communication
Prescaler (UART2)
SCR3
Serial Control Register 3
SIDR3
SODR3
SSR3
Serial Input Data Register 3
Serial Output Data Register 3
Serial Status Register 3
UART3
000034H
XXXXXXXXB
W
000035H
000036H
000037H
R/W
R/W
R/W
0 0 0 0 1 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 - 0 0 0B
UTRLR3
UTCR3
UART Prescaler Reload Register 3
UART Prescaler Control Register 3
Communication
Prescaler (UART3)
000038H
to
Prohibited
00003BH
00003CH
00003DH
00003EH
00003FH
000040H
000041H
000042H
000043H
000044H
ENIR
EIRR
DTP/Interrupt Enable Register
DTP/Interrupt Source Register
Request Level Setting Register Lower
Request Level Setting Register Upper
A/D Control Status Register Lower
A/D Control Status Register Upper
A/D Data Register Lower
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 - - - - - 0B
DTP/External
Interrupt
ELVR
ADCS0
ADCS1
ADCR0
ADCR1
0 0 0 0 0 0 0 0B
XXXXXXXXB
8/10-bit
A/D Converter
A/D Data Register Upper
0 0 1 0 1 XXXB
Prohibited
A/D Conversion Channel Selection
Register
8/10-bit
A/D Converter
000045H
000046H
000047H
000048H
ADMR
PPGC0
PPGC1
PPGC2
R/W
R/W
R/W
R/W
0 0 0 0 0 0 0 0B
0X0 0 0XX1B
0X0 0 0 0 0 1B
PPG0 Operation Mode Control
Register
PPG ch.0
PPG ch.1
PPG ch.2
PPG1 Operation Mode Control
Register
PPG2 Operation Mode Control
Register
0X0 0 0XX1B
(Continued)
DS07-13734-9E
23
MB90330A Series
Register
Address
Read/
Write
Register
Resource name Initial Value
abbreviation
000049H
00004AH
00004BH
PPGC3
PPGC4
PPGC5
PPG3 Operation Mode Control Register R/W
PPG4 Operation Mode Control Register R/W
PPG5 Operation Mode Control Register R/W
PPG ch.3
PPG ch.4
PPG ch.5
0X0 0 0 0 0 1B
0X0 0 0XX1B
0X0 0 0 0 0 1B
PPG0 and PPG1 Output Control
Register
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
PPG01
PPG23
PPG45
R/W
PPG ch.0/ch.1 0 0 0 0 0 0XXB
PPG ch.2/ch.3 0 0 0 0 0 0 XXB
PPG ch.4/ch.5 0 0 0 0 0 0 XXB
Prohibited
PPG2 and PPG3 Output Control
Register
R/W
Prohibited
PPG4 and PPG5 Output Control
Register
R/W
Prohibited
Input Capture
0 0 0 0 0 0 0 0B
ch.0/ch.1
ICS01
ICS23
OCS0
OCS1
OCS2
OCS3
Input Capture Control Status Register 01 R/W
Input
000053H
000054H
000055H
000056H
000057H
Input Capture Control Status Register 23 R/W
0 0 0 0 0 0 0 0B
Capture ch.2/ch.3
Output Compare Control Register ch.0
Lower
R/W
0 0 0 0 - - 0 0B
- - - 0 0 0 0 0B
0 0 0 0 - - 0 0B
- - - 0 0 0 0 0B
Output
Compare
ch.0/ch.1
Output Compare Control Register ch.1
Upper
R/W
Output Compare Control Register ch.2
Lower
R/W
Output
Compare
ch.2/ch.3
Output Compare Control Register ch.3
Upper
R/W
000058H
000059H
00005AH
XXXX0 0 0 0B
0 0 0 0 0 0 1 0B
XXXXXXXXB
SMCS
Serial Mode Control Status Register
R/W
Extended Serial
I/O
SDR
Serial Data Register
R/W
R/W
Communication Prescaler Control
Register
Communication
Prescaler
00005BH
SDCR
0XXX0 0 0 0B
00005CH
00005DH
00005EH
00005FH
000060H
000061H
000062H
000063H
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 XB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
- - - - - - 0 0B
PWCSR
PWC Control Status Register
R/W
16-bit
PWC Timer
PWCR
DIVR
PWC Data Buffer Register
R/W
R/W
PWC Dividing Ratio Control Register
Prohibited
0 0 0 0 0 0 0 0B
XXXX 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
TMCSR0
Timer Control Status Register 0
R/W
16-bit
Reload Timer
ch.0
TMR0
TMRLR0
TMR0
16-bit Timer Register 0 Lower
16-bit Reload Register 0 Lower
16-bit Timer Register 0 Upper
16-bit Reload Register 0 Upper
R
W
R
000064H
000065H
TMRLR0
W
(Continued)
24
DS07-13734-9E
MB90330A Series
Register
abbreviation
Read/
Write
Address
Register
Resource name
Initial Value
000066H
000067H
0 0 0 0 0 0 0 0B
XXXX 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
XXXX 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
TMCSR1
Timer Control Status Register 1
R/W
TMR1
TMRLR1
TMR1
16-bit Timer Register 1 Lower
16-bit Reload Register 1 Lower
16-bit Timer Register 1 Upper
16-bit Reload Register 1 Upper
R
W
R
16-bit Reload
Timer ch.1
000068H
000069H
TMRLR1
W
00006AH
00006BH
TMCSR2
Timer Control Status Register 2
R/W
TMR2
TMRLR2
TMR2
16-bit Timer Register 2 Lower
16-bit Reload Register 2 Lower
16-bit Timer Register 2 Upper
16-bit Reload Register 2 Upper
R
W
R
16-bit Reload
Timer ch.2
00006CH
00006DH
00006EH
TMRLR2
W
Prohibited
ROM Mirror
Function
Selection Module
ROM Mirror Function Selection
Register
00006FH
ROMM
W
- - - - - - 1 1B
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
000080H
IBSR0
IBCR0
ICCR0
IADR0
IDAR0
I2C Bus Status Register 0
I2C Bus Control Register 0
I2C Bus Clock Control Register 0
I2C Bus Address Register 0
I2C Bus Data Register 0
R
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XX 0 XXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
I2C Bus Interface
ch.0
Prohibited
IBSR1
IBCR1
ICCR1
IADR1
IDAR1
I2C Bus Status Register 1
I2C Bus Control Register 1
I2C Bus Clock Control Register 1
I2C Bus Address Register 1
I2C Bus Data Register 1
R
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XX 0 XXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
I2C Bus Interface
ch.1
Prohibited
IBSR2
IBCR2
ICCR2
IADR2
IDAR2
I2C Bus Status Register 2
I2C Bus Control Register 2
I2C Bus Clock Control Register 2
I2C Bus Address Register 2
I2C Bus Data Register 2
R
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XX 0 XXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
R/W
R/W
R/W
I2C Bus Interface
ch.2
000081H
to
Prohibited
000085H
(Continued)
DS07-13734-9E
25
MB90330A Series
Register
Address
Read/
Write
Register
Resource name
Initial Value
abbreviation
000086H
000087H
000088H
000089H
00008AH
00008BH
Timer Data Register Lower
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 - - 0 0 0 0 0B
XXXXXXXXB
TCDT
TCCS
Timer Data Register Upper
Timer Control Status Register Lower
Timer Control Status Register Upper
Compare Clear Register Lower
Compare Clear Register Upper
16-bit Free-Run
Timer
CPCLR
XXXXXXXXB
00008CH
to
Prohibited
00009AH
DMA Descriptor Channel
Specification Register
00009BH
DCSR
R/W
0 0 0 0 0 0 0 0B
μDMAC
00009CH
00009DH
DSRL
DSRH
DMA Status Register Lower
DMA Status Register Upper
R/W
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Program Address Detection Control
Status Register
Address Match
Detection
00009EH
00009FH
PACSR
DIRR
R/W
R/W
0 0 0 0 0 0 0 0B
- - - - - - - 0B
Delay Interruption Factor Generation/
Release Register
Delay Interrupt
Low Power
Consumption
Control Circuit
Low Power Consumption Mode
Control Register
0000A0H
LPMCR
CKSCR
R/W
R/W
0 0 0 1 1 0 0 0B
1 1 1 1 1 1 0 0B
0000A1H
0000A2H
0000A3H
0000A4H
Clock Selection Register
Prohibited
Clock
DSSR
ARSR
DMA Stop Status Register
R/W
W
μDMAC
0 0 0 0 0 0 0 0B
0 0 1 1- - 0 0B
Automatic Ready Function Selection
Register
0000A5H
0000A6H
External Address Output Control
Register
External Pin
HACR
W
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ B
1 0 0 0 ∗ 1 0 -B
0000A7H
0000A8H
0000A9H
0000AAH
0000ABH
0000ACH
0000ADH
EPCR
WDTC
TBTC
WTC
Bus Control Signal Selection Register
Watchdog Timer Control Register
Time-base Timer Control Register
Watch Timer Control Register
Prohibited
W
R/W
R/W
R/W
Watchdog Timer X - XXX 1 1 1B
Time-base Timer 1 - - 0 0 1 0 0B
Watch Timer
1 0 0 0 1 0 0 0B
DERL
DERH
DMA Enable Register Lower
DMA Enable Register Upper
R/W
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
μDMAC
Flash Memory Control Status
Register
Flash Memory
I/F
0000AEH
0000AFH
FMCS
R/W
0 0 0 X 0 0 0 0B
Prohibited
(Continued)
26
DS07-13734-9E
MB90330A Series
Register
abbreviation
Read/
Write
Address
Register
Resource name
Initial Value
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
0000B5H
0000B6H
0000B7H
0000B8H
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
0000C0H
0000C1H
0000C2H
0000C3H
0000C4H
ICR00
ICR01
ICR02
ICR03
ICR04
ICR05
ICR06
ICR07
ICR08
ICR09
ICR10
ICR11
ICR12
ICR13
ICR14
ICR15
HCNT0
HCNT1
HIRQ
Interrupt Control Register 00
Interrupt Control Register 01
Interrupt Control Register 02
Interrupt Control Register 03
Interrupt Control Register 04
Interrupt Control Register 05
Interrupt Control Register 06
Interrupt Control Register 07
Interrupt Control Register 08
Interrupt Control Register 09
Interrupt Control Register 10
Interrupt Control Register 11
Interrupt Control Register 12
Interrupt Control Register 13
Interrupt Control Register 14
Interrupt Control Register 15
Host Control Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 1B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 1 1B
XX 0 1 0 0 1 0B
Interrupt
Controller
Host Control Register 1
Host Interruption Register
Host Error Status Register
Host State Status Register
HERR
HSTATE
SOF Interrupt FRAME Compare Reg-
ister
0000C5H
HFCOMP
R/W
0 0 0 0 0 0 0 0B
0000C6H
0000C7H
0000C8H
0000C9H
0000CAH
0000CBH
0000CCH
0000CDH
0000CEH
0000CFH
0000D0H
0000D1H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXX 0 0B
X 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XX 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXX 0 0 0B
0 0 0 0 0 0 0 0B
USB HOST
HRTIMER
Retry Timer Setting Register
HADR
HEOF
Host Address Register
EOF Setting Register
HFRAME
HTOKEN
FRAME Setting Register
Host Token End Point Register
Prohibited
R/W
R/W
1 0 1 0 0 0 0 0B
0 0 0 0 0 0 0 0B
UDCC
UDC Control Register
USB Function
(Continued)
DS07-13734-9E
27
MB90330A Series
Register
Address
Read/
Write
Register
Resource name
Initial Value
abbreviation
0000D2H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0 1 0 0 0 0 0 0B
XXXX 0 0 0 0B
0 0 0 0 0 0 0 0B
0 1 1 0 0 0 0 1B
0 1 0 0 0 0 0 0B
0 1 1 0 0 0 0 0B
0 1 0 0 0 0 0 0B
0 1 1 0 0 0 0 0B
0 1 0 0 0 0 0 0B
0 1 1 0 0 0 0 0B
0 1 0 0 0 0 0 0B
0 1 1 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXX0 0 0B
XX0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
EP0C
EP1C
EP2C
EP3C
EP4C
EP5C
TMSP
EP0 Control Register
EP1 Control Register
EP2 Control Register
EP3 Control Register
EP4 Control Register
EP5 Control Register
Time Stamp Register
0000D3H
0000D4H
0000D5H
0000D6H
0000D7H
0000D8H
0000D9H
0000DAH
0000DBH
0000DCH
0000DDH
0000DEH
0000DFH
0000E0H
0000E1H
0000E2H
0000E3H
0000E4H
0000E5H
0000E6H
0000E7H
0000E8H
0000E9H
0000EAH
0000EBH
0000ECH
0000EDH
0000EEH
0000EFH
0000F0H
0000F1H
0000F2H
0000F3H
0000F4H
0000F5H
0000F6H
0000F7H
R
UDCS
UDCIE
UDC Status Register
R/W
R/W, R
R/W
R/W
R/W, R
R/W
R
UDC Interrupt Enable Register
EP0IS
EP0OS
EP1S
EP0I Status Register
EP0O Status Register
EP1 Status Register
EP2 Status Register
EP3 Status Register
EP4 Status Register
EP5 Status Register
EP0 Data Register
EP1 Data Register
EP2 Data Register
EP3 Data Register
1 0 XXX 1 XXB
0 XXXXXXXB
1 0 0 XX 0 0 0B
XXXXXXXXB
USB Function
R/W, R
R
1 0 0 0 0 0 0 XB
XXXXXXXXB
EP2S
R/W, R
R
1 0 0 0 0 0 0 0B
XXXXXXXXB
EP3S
R/W, R
R
1 0 0 0 0 0 0 0B
XXXXXXXXB
EP4S
R/W, R
R
1 0 0 0 0 0 0 0B
XXXXXXXXB
EP5S
R/W, R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 0 0 0 0 0 0 0B
XXXXXXXXB
EP0DT
EP1DT
EP2DT
EP3DT
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
28
DS07-13734-9E
MB90330A Series
Register
Read/
Write
Address
Register
EP4 Data Register
EP5 Data Register
Resource name
Initial Value
abbreviation
0000F8H
0000F9H
0000FAH
0000FBH
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
EP4DT
EP5DT
USB Function
0000FCH
to
0000FFH
Prohibited
RAM Area
000100H
to
#H
Program Address Detection Register
ch.0 Lower
001FF0H
001FF1H
001FF2H
001FF3H
001FF4H
001FF5H
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Program Address Detection Register
ch.0 Middle
PADR0
PADR1
Program Address Detection Register
ch.0 Upper
Address Match
Detection
Program Address Detection Register
ch.1 Lower
Program Address Detection Register
ch.1 Middle
Program Address Detection Register
ch.1 Upper
#H
to
Unused Area
0078FFH
007900H
007901H
007902H
007903H
007904H
007905H
007906H
007907H
007908H
007909H
00790AH
00790BH
PRLL0
PRLH0
PRLL1
PRLH1
PRLL2
PRLH2
PRLL3
PRLH3
PRLL4
PRLH4
PRLL5
PRLH5
PPG Reload Register Lower ch.0
PPG Reload Register Upper ch.0
PPG Reload Register Lower ch.1
PPG Reload Register Upper ch.1
PPG Reload Register Lower ch.2
PPG Reload Register Upper ch.2
PPG Reload Register Lower ch.3
PPG Reload Register Upper ch.3
PPG Reload Register Lower ch.4
PPG Reload Register Upper ch.4
PPG Reload Register Lower ch.5
PPG Reload Register Upper ch.5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
PPG ch.0
PPG ch.1
PPG ch.2
PPG ch.3
PPG ch.4
PPG ch.5
00790CH
to
Prohibited
00790FH
(Continued)
DS07-13734-9E
29
MB90330A Series
(Continued)
Register
abbreviation
Read/
Write
Address
Register
Resource name Initial Value
007910H
007911H
007912H
007913H
007914H
007915H
007916H
007917H
007918H
007919H
00791AH
00791BH
00791CH
00791DH
00791EH
00791FH
007920H
007921H
007922H
007923H
Input Capture Data Register Lower ch.0
Input Capture Data Register Upper ch.0
Input Capture Data Register Lower ch.1
Input Capture Data Register Upper ch.1
Input Capture Data Register Lower ch.2
Input Capture Data Register Upper ch.2
Input Capture Data Register Lower ch.3
Input Capture Data Register Upper ch.3
Output Compare Register Lower ch.0
Output Compare Register Upper ch.0
Output Compare Register Lower ch.1
Output Compare Register Upper ch.1
Output Compare Register Lower ch.2
Output Compare Register Upper ch.2
Output Compare Register Lower ch.3
Output Compare Register Upper ch.3
DMA Buffer Address Pointer Lower 8-bit
DMA Buffer Address Pointer Middle 8-bit
DMA Buffer Address Pointer Upper 8-bit
DMA Control Register
R
XXXXXXXXB
IPCP0
IPCP1
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Input Capture
ch.0/ch.1
R
R
R
IPCP2
R
Input Capture
ch.2/ch.3
R
IPCP3
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OCCP0
OCCP1
OCCP2
OCCP3
Output Compare
ch.0/ch.1
Output Compare
ch.2/ch.3
DBAPL
DBAPM
DBAPH
DMACS
DMA I/O Register Address Pointer
Lower 8-bit
μDMAC
007924H
007925H
DIOAL
DIOAH
R/W
R/W
XXXXXXXXB
XXXXXXXXB
DMA I/O Register Address Pointer
Upper 8-bit
007926H
007927H
DDCTL
DDCTH
DMA Data Counter Lower 8-bit
DMA Data Counter Upper 8-bit
R/W
R/W
XXXXXXXXB
XXXXXXXXB
007928H
to
Prohibited
007FFFH
• Explanation on read/write
R/W : Readable / Writable
R
W
: Read only
: Write only
• Explanation on initial values
0
1
X
-
: Initial value is “0”.
: Initial value is “1”.
: Initial value is undefined.
: Initial value is undefined (None) .
: Initial value of this bit is “1” or “0”.
∗
Note : No I/O instruction can be used for registers located between 007900H and 007FFFH.
30
DS07-13734-9E
MB90330A Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interruptcontrol
EI2OS
support
Interrupt vector
register
Interrupt source
μDMAC
Priority
Number*1 Address ICR Address
Reset
×
×
×
×
×
×
×
×
×
×
×
×
#08 08H FFFFDCH
#09 09H FFFFD8H
#10 0AH FFFFD4H
#11 0BH FFFFD0H
⎯
⎯
⎯
⎯
⎯
⎯
High
INT 9 instruction
Exceptional treatment
USB Function1
×
0, 1
ICR00 0000B0H
ICR01 0000B1H
ICR02 0000B2H
ICR03 0000B3H
ICR04 0000B4H
ICR05 0000B5H
ICR06 0000B6H
ICR07 0000B7H
ICR08 0000B8H
ICR09 0000B9H
ICR10 0000BAH
ICR11 0000BBH
ICR12 0000BCH
ICR13 0000BDH
ICR14 0000BEH
ICR15 0000BFH
USB Function2
2 to 6*2 #12 0CH FFFFCCH
USB Function3
×
×
#13 0DH FFFFC8H
#14 0EH FFFFC4H
#15 0FH FFFFC0H
#16 10H FFFFBCH
#17 11H FFFFB8H
#18 12H FFFFB4H
#19 13H FFFFB0H
#20 14H FFFFACH
#21 15H FFFFA8H
#22 16H FFFFA4H
#23 17H FFFFA0H
#24 18H FFFF9CH
#25 19H FFFF98H
#26 1AH FFFF94H
#27 1BH FFFF90H
#28 1CH FFFF8CH
#29 1DH FFFF88H
#30 1EH FFFF84H
#31 1FH FFFF80H
#32 20H FFFF7CH
#33 21H FFFF78H
#34 22H FFFF74H
#35 23H FFFF70H
#36 24H FFFF6CH
#37 25H FFFF68H
#38 26H FFFF64H
#39 27H FFFF60H
#40 28H FFFF5CH
#41 29H FFFF58H
#42 2AH FFFF54H
USB Function4
USB HOST1
×
USB HOST2
I2C ch.0
×
×
DTP/External interrupt ch.0/ch.1
I2C ch.1
×
×
×
×
DTP/External interrupt ch.2/ch.3
I2C ch.2
×
×
DTP/External interrupt ch.4/ch.5
PWC/Reload timer ch.0
DTP/External interrupt ch.6/ch.7
Input capture ch.0/ch.1
Reload timer ch.1
×
14
×
7
×
Input capture ch.2/ch.3
Reload timer ch.2
8
×
Output compare ch.0/ch.1
PPG ch.0/ch.1
×
×
×
×
×
Output compare ch.2/ch.3
PPG ch.2/ch.3
×
×
UART (Send completed) ch.2/ch.3
PPG ch.4/ch.5
11
×
UART (Reception completed) ch.2/ch.3
A/D converter/Free-run timer
UART (Send completed) ch.0/ch.1
Extended serial I/O
10
15
13
9
×
UART (Reception completed) ch.0/ch.1
Time-base timer/Watch timer
Flash memory status
Delay interrupt output module
12
×
×
×
×
×
×
Low
(Continued)
DS07-13734-9E
31
MB90330A Series
(Continued)
: Available, EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal.
With a stop request).
: Available (The interrupt request flag is cleared by the interrupt clear signal.)
: Available when any interrupt source sharing ICR is not used.
× : Unavailable
*1:Ifthesamelevelinterruptisoutputsimultaneously, thelowerinterruptfactorofinterruptvectornumberhaspriority.
*2 : ch.2 and 3 can also be used during USB HOST operation.
Notes : • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted,
the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation
factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt
requests when using the EI2OS.
• The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt
factors in the same interrupt control register (ICR).
• Ifaresourcehastwointerruptsourcesforthesameinterruptnumber, bothoftheinterruptrequestflagsare
cleared by the μDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the
DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to “0” in the
appropriate resource, and take measures by software polling.
• Content of USB interruption factor
USB interrupt factor
USB function 1
USB function 2
USB function 3
USB function 4
USB HOST1
Details
End Point0-IN End Point0-OUT
End Point1-5 *
SUSP SOF BRST WKUP CONF
SPK
DIRQ CNNIRQ URIRQ RWKIRQ
SOFIRQ CMPIRQ
USB HOST2
* : Endpoints 1 and 2 can also be used during USB HOST operation.
32
DS07-13734-9E
MB90330A Series
■ USB
1. USB Function
The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol.
• Feature of USB function
• Correspond to USB Full Speed
• Full speed (12 Mbps) is supported.
• The device status is auto-answer.
• Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16
• Toggle check by data synchronization bit
• Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these
3 commands can be processed the same way as the class vendor commands).
• The class vendor commands can be received as data and responded via firmware.
• Supports up to 6 EndPoints (EndPoint0 is fixed to control transfer)
• 2 transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for EndPoint 0)
• Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint 0)
DS07-13734-9E
33
MB90330A Series
2. USB HOST
USB HOST provides the minimal host operations required and is a function that enables data to be transferred
to and from a device without PC intervention.
• Feature of USB HOST
• Automatic detection of Low Speed/Full Speed transfer
• Low Speed/Full Speed transfer support
• Automatic detection of connection and cutting device
• Reset sending function support to USB-bus
• Support of IN/OUT/SETUP/SOF token
• In-token handshake packet automatic transmission (excluding STALL)
• Out-token handshake packet automatic detection
• Supports a maximum packet length of 256 bytes.
• Error (CRC error/toggle error/time-out) various supports
• Wake-Up function support
• Restrictions of USB HOST
USB HOST
HUB support
Transfer
*
Bulk transfer
Control transfer
Interrupt transfer
Isochronous transfer
Low Speed
×
Transfer speed
Full Speed
PRE packet support
SOF packet support
×
CRC error
Toggle error
Error
Time-out
Maximum packet < receive data
Detection of connection and cutting of device
Transfer speed detection
: Supported
× : Not supported
* : It corresponds to Full Speed only, and the HUB supports up to one step.
34
DS07-13734-9E
MB90330A Series
■ SECTOR CONFIGURATION OF FLASH MEMORY
• Sector configuration of 3Mbit flash memory
3 Mbits flash memory is located in F9H to FFH bank on the CPU memory map.
Flash Memory CPU address
Writer address *
F80000
H
00000
H
Prohibited
F8FFFF
H
0FFFF
H
H
H
H
H
H
H
H
F90000
H
10000
H
SA0 (64 Kbytes)
SA1 (64 Kbytes)
F9FFFF
H
1FFFF
FA0000
FAFFFF
FB0000
FBFFFF
FC0000
FCFFFF
H
20000
H
H
2FFFF
H
30000
H
SA2 (64 Kbytes)
Prohibited
H
3FFFF
H
40000
H
H
H
H
H
4FFFF
FD0000
H
50000
H
SA3 (64 Kbytes)
SA4 (64 Kbytes)
FDFFFF
5FFFF
FE0000
H
60000
H
FEFFFF
6FFFF
FF0000
H
70000
H
SA5 (32 Kbytes)
SA6 (8 Kbytes)
SA7 (8 Kbytes)
FF7FFF
77FFF
FF8000
H
78000
H
FF9FFF
H
79FFF
H
FFA000
FFBFFF
FFC000
FFFFFF
H
7A000
7BFFF
7C000
7FFFF
H
H
H
H
H
SA8 (16 Kbytes)
H
H
* : The writer address is relative to the CPU address when data is programmed into flash memory by a
parallel programmer. Programming and erasing by the general-purpose parallel programmer are
executed based on writer addresses.
DS07-13734-9E
35
MB90330A Series
• Sector configuration of 4Mbit flash memory
4 Mbits flash memory is located in F8H to FFH bank on the CPU memory map.
Flash Memory
CPU address
Writer address *
F80000H
00000H
SA0 (64 Kbytes)
SA1 (64 Kbytes)
SA2 (64 Kbytes)
SA3 (32 Kbytes)
SA4 (8 Kbytes)
SA5 (8 Kbytes)
SA6 (16 Kbytes)
SA7 (64 Kbytes)
SA8 (64 Kbytes)
SA9 (64 Kbytes)
SA10 (32 Kbytes)
SA11 (8 Kbytes)
SA12 (8 Kbytes)
SA13 (16 Kbytes)
F8FFFFH
F90000H
0FFFFH
10000H
1FFFFH
20000H
F9FFFFH
FA0000H
FAFFFFH
FB0000H
2FFFFH
30000H
FB7FFFH
FB8000H
37FFFH
38000H
FB9FFFH
FBA000H
39FFFH
3A000H
3BFFFH
3C000H
FBBFFFH
FBC000H
FBFFFFH
FC0000
3FFFFH
40000H
4FFFFH
50000H
FCFFFF
FD0000
FDFFFF
FE0000H
5FFFFH
60000H
FEFFFFH
FF0000H
6FFFFH
70000H
77FFFH
78000H
FF7FFFH
FF8000H
FF9FFFH
FFA000H
79FFFH
7A000H
7BFFFH
7C000H
FFBFFFH
FFC000H
7FFFFH
FFFFFFH
* : The writer address is relative to the CPU address when data is programmed into flash memory by a
parallel programmer. Programming and erasing by the general-purpose parallel programmer are
executed based on writer addresses.
36
DS07-13734-9E
MB90330A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS + 4.0
VSS + 4.0
VSS + 4.0
VSS + 4.0
V
V
V
V
Power supply voltage*1
AVCC
AVRH
VCC ≥ AVCC*2
AVCC ≥ AVR ≥ 0 V*3
*4
N-ch open-drain
(Withstand voltage of
5 V I/O)*5
Input voltage*1
VI
VSS − 0.3
VSS + 6.0
V
− 0.5
VSS − 0.3
− 0.5
− 2.0
⎯
VSS + 4.5
VSS + 4.0
VSS + 4.5
+2.0
V
USB I/O
V
*4
Output voltage*1
VO
V
USB I/O
Maximum clamp current
ICLAMP
Σ⏐ICLAMP⏐
IOL1
mA
mA
mA
mA
mA
*6
Total maximum clamp current
20
*6
⎯
10
Other than USB I/O*7
USB I/O*7
“L” level maximum output current
IOL2
⎯
43
IOLAV1
⎯
4
*8
“L” level average output current
USB-IO (Full speed/
Low speed) *8
IOLAV2
⎯
15/4.5
mA
“L” level maximum total output current
“L” level average total output current
ΣIOL
ΣIOLAV
IOH1
⎯
⎯
⎯
⎯
⎯
100
50
mA
mA
mA
mA
mA
*9
− 10
− 43
− 4
Other than USB I/O*7
USB I/O*7
“H” level maximum output current
IOH2
IOHAV1
*8
“H” level average output current
USB-IO (Full speed/
Low speed) *8
IOHAV2
⎯
−15/−4.5
mA
“H” level maximum total output current
“H” level average total output current
Power consumption
ΣIOH
ΣIOHAV
Pd
⎯
⎯
− 100
− 50
mA
mA
mW
°C
*9
⎯
340
Operating temperature
TA
− 40
− 55
− 55
+ 85
+ 150
+ 125
°C
Storage temperature
Tstg
°C
USB I/O
*1 : The parameter is based on VSS = AVSS = 0.0 V.
*2 : Be careful not to let AVCC exceed VCC, for example, when the power is turned on.
*3 : Be careful not to let AVRH exceed AVcc.
*4 : VI and VO must not exceed Vcc + 0.3 V. However, if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
*5 : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST
(Continued)
DS07-13734-9E
37
MB90330A Series
(Continued)
*6 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77,
P80 to P87, P90 to P95, PB5, PB6
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than P60 to P67, P96, PA0 to PA7, PB0 to PB4, DVP, DVM,
HVP, HVM, UTEST, HCON
• Sample recommended circuits:
• Input/output equivalent circuits
Protective diode
VCC
Limiting
P-ch
resistance
+B input (0 V to 16 V)
N-ch
R
*7 : A peak value of an applicable one pin is specified as a maximum output current.
*8 : The average output current specifies the mean value of the current flowing in the relevant single pin during a
period of 100 ms.
*9 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during
a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
DS07-13734-9E
MB90330A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Value
Parameter
Symbol
Unit
Remarks
Min
3.0
Max
3.6
V
V
V
V
V
At normal operation (when using USB)
At normal operation (when not using USB)
Hold state of stop operation
CMOS input pin
Power supply voltage
VCC
2.7
3.6
1.8
3.6
VIH
0.7 VCC
0.8 VCC
VCC + 0.3
VCC + 0.3
VIHS1
CMOS hysteresis input pin
N-ch open-drain
(Withstand voltage of 5 V I/O)*
Input “H” voltage
Input “L” voltage
VIHS2
0.8 VCC
VSS + 5.3
V
VIHM
VIHUSB
VIL
VCC − 0.3
2.0
VCC + 0.3
VCC + 0.3
0.3 VCC
0.2 VCC
VSS + 0.3
0.8
V
V
V
V
V
V
MD pin input
USB pin input
VSS − 0.3
VSS − 0.3
VSS − 0.3
VSS
CMOS input pin
CMOS hysteresis input pin
MD pin input
VILS
VILM
VILUSB
USB pin input
Differential input
sensitivity
VDI
0.2
0.8
⎯
V
USB pin input
Differential common
mode input voltage
range
VCM
2.5
V
USB pin input
− 40
+ 85
+ 70
°C
°C
When not using USB
Operating
temperature
TA
When using USB, at external bus
operation
0
* : Applicable to pins : P60 to P67, P96, PA0 to PA7, PB0 to PB4, UTEST
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13734-9E
39
MB90330A Series
3. DC Characteristics
Sym-
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Pin name
Conditions
Unit Remarks
bol
Min Typ Max
Output pins other than
P60 to P67, P96,
PA0 to PA7, PB0 to PB4,
HVP, HVM, DVP, DVM
VCC
− 0.5
IOH = − 4.0 mA
⎯
Vcc
V
Output “H”
voltage
VOH
HVP, HVM, DVP, DVM RL = 15 kΩ 5%
2.8
Vss
0
⎯
⎯
⎯
3.6
V
V
V
Output pins other than
HVP, HVM, DVP, DVM
Vss
+ 0.4
0.3
IOL = 4.0 mA
Output “L”
voltage
VOL
HVP, HVM, DVP, DVM RL = 1.5 kΩ 5%
Output pins other than
P60 to P67, P96,
PA0 to PA7,
PB0 to PB4, HVP, HVM,
VCC = 3.3 V,
Vss < VI < VCC
− 10
⎯
+ 10 μA
+ 5 μA
Input leak
current
IIL
DVP, DVM
HVP, HVM, DVP, DVM
⎯
⎯
− 5
⎯
Pull-up
resistance
VCC = 3.3 V,
TA = + 25 °C
RPULL P00 to P07, P10 to P17
25
50 100 kΩ
Opendrain
output
current
P60 to P67, P96,
ILIOD
⎯
⎯
⎯
⎯
⎯
0.1
75
65
70
60
10
μA
PA0 to PA7, PB0 to PB4
VCC = 3.3 V,
MB90F334A
MB90F335A
85 mA
Internal frequency 24 MHz,
At normal operating
At USB operating
(USTP = 0)
75 mA MB90333A
ICC
VCC = 3.3 V,
MB90F334A
80 mA
Internal frequency 24 MHz,
At normal operating
At non-operating USB
(USTP = 1)
MB90F335A
70 mA MB90333A
40 mA
VCC = 3.3 V,
Power
supply
current
ICCS
Internal frequency 24 MHz,
At sleep mode
⎯
⎯
⎯
27
3.5
1
VCC
VCC = 3.3 V,
Internal frequency 24 MHz,
At timer mode
10 mA
ICTS
VCC = 3.3 V,
Internal frequency 3 MHz,
At timer mode
2
mA
VCC = 3.3 V,
Internal frequency 8 kHz,
At sub clock operation,
(TA = +25 °C)
ICCL
⎯
25 150 μA
(Continued)
40
DS07-13734-9E
MB90330A Series
(Continued)
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
bol
Parameter
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
VCC = 3.3 V,
Internal frequency 8 kHz,
At sub clock,
ICCLS
⎯
10
50
μA
At sleep operating,
(TA = + 25 °C)
Power
supply
current
VCC
VCC = 3.3 V,
Internal frequency 8 kHz,
Watch mode,
ICCT
⎯
1.5
40
μA
(TA = + 25 °C)
TA = + 25 °C,
ICCH
⎯
⎯
25
1
5
40
15
μA
pF
kΩ
At stop
Input
capacitance
OtherthanAVcc,
AVss, Vcc, Vss
CIN
⎯
⎯
Pull-up
resistor
Rup RST
50
100
USB I/O
output
impedance
DVP, DVM
HVP, HVM
ZUSB
⎯
3
⎯
14
Ω
Note : P60 to P67, P96, PA0 to PA7, and PB0 to PB4 are N-ch open-drain pins usually used as CMOS.
DS07-13734-9E
41
MB90330A Series
4. AC Characteristics
(1)Clock input timing
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym-
Parameter
bol
Pin name
Unit
Remarks
Min
⎯
6
Typ
6
Max
⎯
24
MHz When oscillator is used
MHz External clock input
kHz
fCH
X0, X1
X0A, X1A
X0, X1
Clock frequency
⎯
fCL
⎯
⎯
166.7
⎯
32.768
166.7
⎯
⎯
⎯
41.7
⎯
ns When oscillator is used
ns External clock input
s
tHCYL
Clock cycle time
tLCYL
X0A, X1A
X0
30.5
PWH
A reference duty ratio is
30% to 70%.
10
⎯
⎯
⎯
15.2
⎯
⎯
⎯
5
ns
PWL
Input clock pulse width
PWHL
X0A
X0
s
PWLL
Input clock rise time and fall
time
tcr
tcf
ns At external clock
fCP
fCPL
tCP
⎯
⎯
⎯
⎯
3
⎯
8.192
⎯
24
⎯
333
⎯
MHz When main clock is used
kHz When sub clock is used
ns When main clock is used
Internal operating clock
frequency
⎯
42
⎯
Internal operating clock
cycle time
tCPL
122.1
s
When sub clock is used
• Clock Timing
t
HCYL
0.8 VCC
0.2 VCC
X0
P
WH
PWL
t
cr
tcf
tLCYL
0.8 VCC
0.2 VCC
X0A
PWHL
PWLL
tcr
tcf
42
DS07-13734-9E
MB90330A Series
• PLL operation guarantee range
Relation between power supply voltage and internal operation clock frequency
PLL operation guarantee range
3.6
3.0
2.7
Normal Operation
Assurance Range
3
6
12
24
Internal clock FCP (MHz)
Note : When the USB is used, operation is guaranteed at voltages between 3.0 V and 3.6 V.
Relation between internal operation clock frequency and external clock frequency
24
Multiplied by 4
Multiplied by 2
12
External clock
6
Multiplied by 1
3
6
24
External clock Fc (MHz)
DS07-13734-9E
43
MB90330A Series
The AC standards assume the following measurement reference voltages.
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Hysteresis input/other than MD input pin
0.7 VCC
0.3 VCC
44
DS07-13734-9E
MB90330A Series
(2)Clock output timing
(VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Cycle time
Symbol Pin name
Conditions
Unit
Remarks
Min
tCP
Max
⎯
tCYC
CLK
CLK
⎯
ns
ns
ns
ns
tCP/2 − 15
tCP/2 + 15
tCP/2 + 20
tCP/2 + 64
At fcp = 24 MHz
At fcp = 12 MHz
At fcp = 6 MHz
CLK↑→CLK↓
tCHCL
VCC = 3.0 V to 3.6 V tCP/2 − 20
tCP/2 − 64
Note : tCP : Refer to “ (1) Clock input timing”.
tCYC
tCHCL
2.4 V
2.4 V
0.8 V
CLK
DS07-13734-9E
45
MB90330A Series
(3) Reset
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
At normal operating,
At time base timer mode,
At main sleep mode,
At PLL sleep mode
500
⎯
ns
Reset input time
tRSTL
RST
⎯
At stop mode,
Oscillation time
of oscillator* +
500 ns
At sub clock mode,
At sub sleep mode,
At watch mode
⎯
μs
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. It takes several milliseconds to several
dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a
ceramic oscillator, and 0 milliseconds on an external clock.
• During normal operation, time-base timer mode, main sleep mode and PLL sleep mode
t
RSTL
RST
0.2 Vcc
0.2 Vcc
• During stop mode, sub clock mode, sub-sleep mode and watch mode
t
RSTL
RST
X0
0.2 Vcc
0.2 Vcc
90% of
amplitude
Internal
operation
clock
Oscillation time
of oscillator
500 ns
Oscillation stabilization wait time
Execute
instruction
Internal reset
46
DS07-13734-9E
MB90330A Series
(4) Power-on reset
Parameter
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to +85 °C)
Value
Symbol Pin name Conditions
Unit
Remarks
Min
Max
Power supply rising
time
tR
VCC
VCC
0.05
30
ms
ms
⎯
Powersupplyshutdown
time
Waiting time until
power-on
tOFF
1
⎯
tR
2.7 V
0.2 V
VCC
0.2 V
0.2 V
tOFF
Notes : • VCC must be lower than 0.2 V before the power supply is turned on.
• The above standard is a value for performing a power-on reset.
• In the device, there are internal registers which is initialized only by a power-on reset.
When the initialization of these items is expected, turn on the power supply according to the standards.
• Sudden change of power supply voltage may activate the power-on reset function.
When changing the power supply voltage during operation as illustrated below, voltage fluctuation should
be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL
clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.
VCC
The rising edge should be 50 mV/ms
or less.
1.8 V
RAM data hold
VSS
DS07-13734-9E
47
MB90330A Series
(5) UART0, UART1, UART2, UART3 I/O extended serial timing
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
Serial clock cycle time
tSCYC
tSLOV
SCKx
8 tCP
⎯
ns
ns
SCKx,
SOTx
SCK↓→SOT delay time
− 80
100
60
+ 80
⎯
Internal shift clock
mode output pin is :
CL = 80 pF + 1TTL
SCKx,
SINx
Valid SIN→SCK↑
tIVSH
ns
ns
SCKx,
SINx
SCK↑→valid SIN hold time
tSHIX
⎯
Serial clock H pulse width
Serial clock L pulse width
tSHSL
tSLSH
SCKx, SINx
SCKx, SINx
4 tCP
⎯
⎯
ns
ns
4 tCP
SCKx,
SOTx
SCK↓→SOT delay time
Valid SIN→SCK↑
tSLOV
tIVSH
tSHIX
External shift clock
mode output pin is :
CL = 80 pF + 1TTL
⎯
60
60
150
⎯
ns
ns
ns
SCKx,
SINx
SCKx,
SINx
SCK↑→valid SIN hold time
⎯
Notes : • Above rating is the case of CLK synchronous mode.
• CL is a load capacitance value on pins for testing.
• tCP : Refer to “ (1) Clock input timing”.
48
DS07-13734-9E
MB90330A Series
• Internal shift clock mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
0.2 VCC
2.4 V
0.8 V
SOT
SIN
tIVSH
tSHIX
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
DS07-13734-9E
49
MB90330A Series
2
(6) I C timing
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Conditions
Unit
Min
Max
SCL clock frequency
fSCL
0
100
kHz
(Repeat) [start] condition hold
time
SDA ↓ → SCL ↓
tHDSTA
4.0
⎯
μs
Power-supply voltage of external pull-up
resistor at 5.0 V.
R = 1.2 kΩ, C = 50 pF*2
SCL clock “L” width
SCL clock “H” width
tLOW
tHIGH
4.7
4.0
⎯
⎯
μs
μs
Power-supply voltage of external pull-up
resistor at 3.6 V.
Repeat [start] condition setup time
SCL ↑ → SDA ↓
tSUSTA
R = 1.0 kΩ, C = 50 pF*2
4.7
0
⎯
μs
μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
3.45*3
Power-supply voltage of external pull-up
resistor at 5.0 V.
fCP*1 ≤ 20 MHz, R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
250*4
200*4
⎯
⎯
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
ns
Power-supply voltage of external pull-up
resistor at 5.0 V.
fCP*1 > 20 MHz, R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
fCP*1 > 20 MHz, R = 1.0 kΩ, C = 50 pF*2
[Stop] condition setup time
SCL ↑ → SDA ↑
Power-supply voltage of external pull-up
resistor at 5.0 V.
tSUSTO
4.0
4.7
⎯
⎯
μs
μs
R = 1.2 kΩ, C = 50 pF*2
Power-supply voltage of external pull-up
resistor at 3.6 V.
Bus free time between [stop]
condition and [start] condition
tBUS
R = 1.0 kΩ, C = 50 pF*2
*1 : fCP is internal operating clock frequency. Refer to “ (1) Clock input timing”.
*2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “• Note of SDA, SCL set-up time”.
50
DS07-13734-9E
MB90330A Series
• Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending
on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating
of the input data set-up time cannot be satisfied.
•Timing definition
SDA
tBUS
tHDSTA
tLOW
tSUDAT
SCL
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
DS07-13734-9E
51
MB90330A Series
(7) Timer input timing
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
FRCK,
INx, TINx,
PWC
tTIWH
tTIWL
Input pulse width
⎯
4 tCP
⎯
ns
Note : tCP : Refer to “ (1) Clock input timing”.
0.8 VCC
0.8 VCC
0.2 VCC
PWC
TINx
INx
0.2 VCC
FRCK
t
TIWH
t
TIWL
(8) Timer output timing
Parameter
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Pin name
Conditions
Unit
Min
Max
CLK↑→TOUT change time
PPG0 to PPG5 change time
OUT0 to OUT3 change time
TOTx,
PPGx,
OUTx
tTO
⎯
30
⎯
ns
2.4 V
CLK
t
TO
PPGx
OUTx
2.4 V
0.8 V
(9) Trigger input timing
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Parameter
Symbol Pin name Conditions
Unit
Remarks
Min
5 tCP
1
Max
⎯
ns At normal operating
tTRGH
INTx,
Input pulse width
⎯
tTRGL
ADTG
⎯
μs In Stop mode
Note : tCP : Refer to “ (1) Clock input timing”.
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
INTx
ADTG
tTRGH
tTRGL
52
DS07-13734-9E
MB90330A Series
(10) Bus read timing
Parameter
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Sym-
bol
Pin name Conditions
Unit
Remarks
Min
Max
⎯
tCP/2 − 15
tCP/2 − 20
tCP/2 − 35
tCP/2 − 17
tCP/2 − 40
ns At fcp = 24 MHz
ns At fcp = 12 MHz
ns At fcp = 6 MHz
ns
ALE pulse width
tLHLL
ALE
⎯
⎯
⎯
⎯
⎯
Address,
ALE
Valid address→ALE↓time
tAVLL
⎯
ns At fcp = 6 MHz
ALE,
Address
ALE↓→Address valid time tLLAX
⎯
⎯
tCP/2 − 15
tCP − 25
⎯
⎯
ns
ns
RD,
Address
Valid address→RD↓time
tAVRL
⎯
5 tCP/2 − 55
5 tCP/2 − 80
⎯
ns
Valid address→valid data
Address/
data
tAVDV
⎯
⎯
⎯
input
⎯
3 tCP/2 − 25
3 tCP/2 − 20
⎯
ns At fcp = 6 MHz
ns At fcp = 24 MHz
ns At fcp = 12 MHz
ns
RD pulse width
tRLRH
tRLDV
RD
⎯
3 tCP/2 − 55
3 tCP/2 − 80
RD,
Data
RD↓→valid data input
⎯
ns At fcp = 6 MHz
RD,
Data
RD↓→data hold time
RD↑→ALE↑time
tRHDX
tRHLH
tRHAX
⎯
⎯
⎯
0
⎯
⎯
⎯
ns
ns
ns
RD, ALE
tCP/2 − 15
tCP/2 − 10
Address,
RD
RD↑→address valid time
Address,
CLK
Valid address→CLK↑time tAVCH
⎯
tCP/2 − 17
⎯
ns
RD↓→CLK↑time
ALE↓→RD↓time
tRLCH
tLLRL
RD, CLK
RD, ALE
⎯
⎯
tCP/2 − 17
tCP/2 − 15
⎯
⎯
ns
ns
Note : tCP : Refer to “ (1) Clock input timing”.
DS07-13734-9E
53
MB90330A Series
tAVCH
tRLCH
2.4 V
2.4 V
CLK
ALE
RD
tRHLH
2.4 V
0.8 V
2.4 V
2.4 V
tLHLL
tAVLL
tRLRH
2.4 V
tLLAX
tLLRL
0.8 V
In multiplex mode
A23 to A16
tAVRL
tRLDV
tRHAX
2.4 V
2.4 V
0.8 V
0.8 V
tAVDV
tRHDX
2.4 V
0.8 V
2.4 V
0.8 V
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
AD15 to AD00
Read data
Address
tRHAX
In non-multiplex mode
A23 to A00
2.4 V
0.8 V
2.4 V
0.8 V
tRLDV
tRHDX
tAVDV
0.7 VCC
0.3 VCC
0.7 VCC
D15 to D00
Read data
0.3 VCC
54
DS07-13734-9E
MB90330A Series
(11) Bus write timing
Parameter
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Symbol Pin name Conditions
Unit
Remarks
Min
Max
Valid address→WR↓
Address,
tAVWL
tWLWH
tDVWH
⎯
tCP − 15
⎯
ns
time
WR
⎯
⎯
3 tCP/2 − 25
3 tCP/2 − 20
⎯
⎯
ns At fcp = 24 MHz
ns At fcp = 12 MHz
WR pulse width
WRL, WRH
Valid data output→WR↑
time
Data, WR
⎯
3 tCP/2 − 15
⎯
ns
⎯
⎯
⎯
10
20
30
⎯
⎯
⎯
ns At fcp = 24 MHz
ns At fcp = 12 MHz
ns At fcp = 6 MHz
WR,
Data
WR↑→data hold time
tWHDX
WR,
Address
WR↑→address valid time
tWHAX
⎯
tCP/2 − 10
⎯
ns
WR↑→ALE↑time
WR↓→CLK↑time
tWHLH
tWLCH
WR, ALE
WR, CLK
⎯
⎯
tCP/2 − 15
tCP/2 − 17
⎯
⎯
ns
ns
Note : tCP : Refer to “ (1) Clock input timing”.
tWLCH
2.4 V
CLK
ALE
tWHLH
2.4 V
tWLWH
2.4 V
WR
(WRL, WRH)
0.8 V
In multiplex mode
tAVWL
tWHAX
2.4 V
2.4 V
0.8 V
A23 to A16
0.8 V
tDVWH
tWHDX
2.4 V
0.8 V
2.4 V
0.8 V
AD15 to AD00
2.4 V
0.8 V
Write data
Address
tWHAX
In non-multiplex mode
2.4 V
0.8 V
2.4 V
0.8 V
A23 to A00
tDVWH
tWHDX
2.4 V
0.8 V
D15 to D00
2.4 V
0.8 V
Write data
DS07-13734-9E
55
MB90330A Series
(12) Ready input timing
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Parameter
Symbol
Pin name Conditions
Unit
Remarks
Min
35
70
0
Max
⎯
⎯
ns
ns
ns
RDY set-up time
RDY hold time
tRYHS
RDY
⎯
⎯
⎯
fcp = 6 MHz
tRYHH
⎯
2.4 V
2.4 V
CLK
ALE
RD/WR
t
RYHS
t
RYHH
RDY
wait not
applied
0.8 VCC
0.8 VCC
RDY
wait applies
(1cycle)
0.2 VCC
0.2 VCC
t
RYHS
56
DS07-13734-9E
MB90330A Series
(13) Hold timing
Parameter
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Symbol
Pin name
Conditions
Unit
Min
30
Max
tCP
Pin floating → HAK ↓ time
HAK ↓ → pin valid time
tXHAL
tHAHV
HAK
HAK
ns
ns
⎯
tCP
2 tCP
Notes : • It takes one cycle or more for HAK to change after the HRQ pin is captured.
• tCP : Refer to “ (1) Clock input timing”.
HAK
2.4 V
0.8 V
tXHAL
tHAHV
High-Z
2.4 V
0.8 V
2.4 V
0.8 V
Each pin
DS07-13734-9E
57
MB90330A Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Typ
⎯
Sym-
bol
Parameter
Resolution
Pin name
Unit
Remarks
Min
⎯
Max
10
⎯
⎯
⎯
⎯
⎯
⎯
bit
Total error
⎯
⎯
3.0
2.5
LSB
LSB
Nonlinear error
⎯
⎯
Differential linear
error
⎯
⎯
⎯
⎯
1.9
LSB
V
Zero transition
voltage
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
VOT
AN0 to AN15
1 LSB = (AVRH −
AVSS)/1024
Full-scale transition
voltage
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
VFST AN0 to AN15
V
*1
Conversion time
Sampling time
⎯
⎯
⎯
⎯
⎯
⎯
176 tCP
⎯
⎯
ns
ns
*1
64 tCP
Analog port input
current
IAIN
VAIN
⎯
AN0 to AN15
AN0 to AN15
AVRH
⎯
0
⎯
⎯
⎯
10
μA
Analog input
voltage
AVRH
AVCC
V
Reference
voltage
2.7
V
IA
IAH
IR
AVCC
AVCC
⎯
⎯
⎯
⎯
1.4
⎯
3.5
5
mA
Power supply
current
μA *2
μA
AVRH
AVRH
95
⎯
170
5
Reference voltage
supplying current
IRH
μA *2
Interchannel
disparity
⎯
AN0 to AN15
⎯
⎯
4
LSB
*1 : tCP : Refer to “ 4. AC Characteristics (1) Clock input timing”.
*2 : The current when the CPU is in stop mode and the A/D converter is not operating (For VCC = AVCC = AVRH = 3.3 V).
58
DS07-13734-9E
MB90330A Series
Notes :
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Comparator
R
Analog input
C
During sampling : ON
C
MB90333A
MB90F334A
MB90F335A
MB90V330A
1.9 kΩ (Max)
32.3 pF (Max)
25.0 pF (Max)
25.0 pF (Max)
32.3 pF (Max)
1.9 kΩ (Max)
1.9 kΩ (Max)
1.9 kΩ (Max)
Note : The values are reference values.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
MB90333A/
MB90333A/
MB90V330A
MB90V330A
100
20
90
18
MB90F334A
MB90F334A
80
16
MB90F335A
MB90F335A
70
14
12
10
8
60
50
40
30
20
10
0
6
4
2
0
0
5
10
15
20
25
30
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
Minimum sampling time [μs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• About errors
As |AVRH| becomes smaller, values of relative errors grow larger.
DS07-13734-9E
59
MB90330A Series
A/D Converter Glossary
Resolution :
Analog changes that are identifiable with the A/D converter.
Linearity error :
The deviation of the straight line connecting the zero transition point
(“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics.
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Total error :
The total error is defined as a difference between the actual value and the theoretical
value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FF
3FE
3FD
H
Actual conversion
value
H
H
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
004
H
H
VNT
(Measured value)
003
002
001
Actual conversion
value
H
H
Theoretical
characteristics
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
Total error for digital output N =
1 LSB (Theoretical value) =
[LSB]
1 LSB
AVRH − AVss
[V]
1024
VOT (Theoretical value) = AVss + 0.5 LSB [V]
VFST (Theoretical value) = AVRH − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
60
DS07-13734-9E
MB90330A Series
(Continued)
Linearity error
Differential linearity error
Theoretical
characteristics
Actual conversion
3FF
H
H
H
value
Actual conversion
value
3FE
3FD
N + 1
{1 LSB × (N − 1)
+ VOT
}
V
FST
(Measured
value)
N
V
(N + 1) T
(Measured
N − 1
V
NT
004
003
H
H
value)
(Measured value)
VNT
Actual conversion
value
(Measured value)
002
H
H
N − 2
Actual conversion
value
Theoretical
characteristics
OT (Measured value)
001
V
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
Linearity error of
digital output N
VNT − {1 LSB × (N − 1) + VOT}
=
=
[LSB]
1 LSB
Differential linearity error
of digital output N
V (N + 1) T − VNT
− 1 [LSB]
1 LSB
VFST − VOT
[V]
1 LSB =
1022
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
DS07-13734-9E
61
MB90330A Series
6. USB characteristics
(VCC = AVCC = 3.3 V 0.3 V, VSS = AVSS = 0.0 V, TA = 0 °C to + 70 °C)
Value
Sym-
bol
Parameter
Unit
Remarks
Min
2.0
⎯
Max
⎯
Input High level voltage
VIH
VIL
VDI
V
V
Input Low level voltage
0.8
⎯
Input
characteristics
Differential input sensitivity
0.2
0.8
2.8
0.0
1.3
4
V
Differential common mode range VCM
2.5
3.6
0.3
2.0
20
V
Output High level voltage
Output Low level voltage
Cross over voltage
VOH
VOL
VCRS
tFR
V
IOH = − 200 μA
IOL = 2 mA
V
V
ns
ns
ns
ns
%
%
Ω
Full Speed
Low Speed
Full Speed
Low Speed
(TFR/TFF)
Rise time
Fall time
tLR
75
4
300
20
Output
characteristics
tFF
tLF
75
90
80
28
300
tRFM
tRLM
ZDRV
111.11
125
Rising/falling time matching
Output impedance
(TLR/TLF)
44
Including Rs = 27 Ω
Recommended value =
27 Ω at using USB*
Series resistance
RS
25
30
Ω
* : Arrange the series resistance RS values in order to set the impedance value within the output impedance ZSRV.
• Data signal timing (Full Speed)
Rise time
Fall time
DVP/HVP
DVM/HVM
90%
90%
Vcrs
10%
10%
t
FF
tFR
• Data signal timing (Low Speed)
Rise time
Fall time
HVP
90%
90%
Vcrs
10%
10%
HVM
tLF
tLR
62
DS07-13734-9E
MB90330A Series
• Load condition (Full Speed)
Z
USB
R
S
= 27 Ω
= 27 Ω
Testing point
DVP/HVP
DVM/HVM
C
L
= 50 pF
Z
USB
RS
Testing point
C
L
= 50 pF
• Load condition (Low Speed)
ZUSB
RS = 27 Ω
RS = 27 Ω
Testing point
HVP
CL = 50 pF to 150 pF
ZUSB
Testing point
HVM
CL = 50 pF to 150 pF
DS07-13734-9E
63
MB90330A Series
7. Flash memory write/erase characteristics
Value
Typ
Parameter
Condition
Unit
Remarks
Min
Max
Excludes 00H programming
prior to erasure.
Sector erase time
⎯
1
15
s
*:MB90F334A (384 Kbytes)
Excludes 00H programming
prior to erasure.
⎯
⎯
9
⎯
⎯
TA = + 25 °C
VCC = 3.0 V
Chip erase time
s
*:MB90F335A (512 Kbytes)
Excludes 00H programming
prior to erasure.
14
Word (16-bit width)
programming time
Except for over head time of
system level
⎯
10000
20
16
⎯
⎯
3600
⎯
μs
Programming/erase cycle
⎯
cycle
year
Flash memory data
retaining period
Average
TA = + 85 °C
⎯
*
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C)
64
DS07-13734-9E
MB90330A Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB90F334APMC1
MB90F335APMC1
MB90333APMC1
120-pin plastic LQFP
(FPT-120P-M24)
MB90F334APMC
MB90F335APMC
MB90333APMC
120-pin plastic LQFP
(FPT-120P-M21)
299-pin ceramic PGA
(PGA-299C-A01)
MB90V330ACR
For evaluation
DS07-13734-9E
65
MB90330A Series
■ PACKAGE DIMENSIONS
120-pin plastic LQFP
Lead pitch
0.40 mm
14.0 mm × 14.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.70 mm MAX
Code
(Reference)
P-LFQFP120-14×14-0.40
(FPT-120P-M24)
120-pin plastic LQFP
(FPT-120P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00 0.20(.630 .008)SQ
*14.00 0.10(.551 .004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
120
31
"A"
0~8
°
1
30
LEAD No.
0.10 0.10
(.004 .004)
(Stand off)
0.16 0.05
(.006 .002)
0.145 0.055
(.006 .002)
0.50 0.20
(.020 .008)
M
0.07(.003)
0.40(.016)
0.60 0.15
(.024 .006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2006-2010 FUJITSU SEMICONDUCTOR LIMITED F120036S-c-1-3
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
66
DS07-13734-9E
MB90330A Series
(Continued)
120-pin plastic LQFP
Lead pitch
0.50 mm
16.0 × 16.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.88 g
Code
(Reference)
(FPT-120P-M21)
P-LFQFP120-16×16-0.50
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 0.20(.709 .008)SQ
+0.40
16.00 –0.10 .630 –+..000146 SQ
*
90
61
91
60
0.08(.003)
Details of "A" part
1.50 +–00..1200
(Mounting height)
.059 +–..000048
INDEX
0~8
°
"A"
120
31
0.10 0.05
(.004 .002)
(Stand off)
1
30
LEAD No.
0.145 +–00..0035
0.60 0.15
(.024 .006)
0.22 0.05
(.009 .002)
M
0.50(.020)
0.08(.003)
.006 +–..000012
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F120033S-c-4-7
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13734-9E
67
MB90330A Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
■ ELECTRICAL CHARACTERISTICS Corrected the remarks for operating temperature as follows;
39
2. Recommended Operating Condi-
tions
When using USB → When using USB, at external bus opera-
tion
The vertical lines marked in the left side of the page show the changes.
68
DS07-13734-9E
MB90330A Series
MEMO
DS07-13734-9E
69
MB90330A Series
MEMO
70
DS07-13734-9E
MB90330A Series
MEMO
DS07-13734-9E
71
MB90330A Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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