MB90623PFS_技术文档

FUJITSU SEMICONDUCTOR

CONTROLLER MANUAL

CM43-10105-1E

F²MC-16L FAMILY

16-BIT MICROCONTROLLERS

MB90620 SERIES

HARDWARE MANUAL

2

PREFACE

Thank you for your interest in Fujitsu Semiconductor products.

The MB90620 Series has been developed as a series of general-purpose products for the F²MC*-16L

Family of proprietary 16-bit single-chip microcontrollers.

This manual is intended for engineers who will actually use this semiconductor in product designs, and

describes the functions and operations of the MB90620 Series products. For details concerning

instructions, refer to the MB90700 Series Programming Manual.

*"F²MC" stands for "Fujitsu Flexible Microcontroller".

The organization of this manual is described below:

Chapter 1 General

This chapter describes the product lineup of the various models in the MB90620 Series, and provides

an overview of those models.

Chapter 2 Hardware

This chapter describes the internal configuration of the F²MC*-16L Series CPU, and also describes the

specifications for the MB90620 Series hardware.

Chapter 3 Operation

This chapter describes how to use the MB90620 Series, resets, interrupts, memory access modes, low

power consumption modes, etc.

Chapter 4 Instructions

This chapter describes the F²MC*-16L Series instructions.

1. The products described in this manual and the specifications thereof may be changed without prior

notice. To obtain up-to-date information and/or specifications, contact your Fujitsu sales

representative or Fujitsu authorized dealer.

2. Fujitsu will not be liable for infringement of copyright, industrial property right, or other rights of a third

party caused by the use of information or drawings described in this manual.

3. The contents of this manual may not be transferred or copied without the express permission of

Fujitsu.

4. The products contained in this document are not intended for use with equipments which require

extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control

systems or medical equipments for life support.

5. Some of the products described in this manual may be strategic materials (or special technology) as

defined by the Foreign Exchange and Foreign Trade Control Law. In such cases, the products or

portions thereof must not be exported without permission as defined under the Law.

ã

1996 FUJITSU LIMITED Printed in Japan

CONTENTS

CHAPTER 1

GENERAL ................................................................................... 1

1.1 Features ...................................................................................................... 1

1.2 Model Expansion (Planned Model Expansion).......................................... 3

1.3 Block Diagram ........................................................................................... 4

1.4 Pin Assignment .......................................................................................... 5

1.5 External Dimensions .................................................................................. 6

1.6 Pin Descriptions ......................................................................................... 7

1.7 Notes On Handling The Device ............................................................... 15

CHAPTER 2

HARDWARE...................................................................................... 16

2.1 CPU.......................................................................................................... 16

2.2 Map........................................................................................................... 50

2.3 Parallel Ports ............................................................................................ 59

2.4 UART....................................................................................................... 66

2.5 I/O Extended Serial Interface................................................................... 82

2.6 A/D Converter.......................................................................................... 93

2.7 16-bit Timer (with Event Counter Function) ......................................... 109

2.8 16-bit Free-running Timer...................................................................... 119

2.9 PPG (Programmable Pulse Generator) Timer........................................ 124

2.10 LCD Controller/Driver........................................................................... 133

2.11 DTP/External Interrupts ......................................................................... 143

2.12 Clock Output Module............................................................................. 150

2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions.......... 151

2.14 Delay Interrupt Generation Module....................................................... 161

2.15 Low Power Consumption Control Circuit ............................................. 163

2.16 Interrupt Controller ................................................................................ 172

CHAPTER 3

OPERATION.................................................................................... 177

3.1 Clock Generation Block......................................................................... 177

3.2 Resets ..................................................................................................... 178

3.3 Interrupts ................................................................................................ 181

3.4 Memory Access Modes.......................................................................... 199

3.5 Low Power Consumption Modes........................................................... 204

3.6 Pin States for Sleep, Stop, Hold, and Reset ........................................... 219

Chapter

4

INSTRUCTIONS............................................................................. 220

4.1 Addressing.............................................................................................. 220

4.2 Instruction Set ........................................................................................ 225

4.3 Instruction Map ...................................................................................... 245

i

1.1 Features

Chapter 1:

GENERAL

The MB90620 Series is a series of high-performance general-purpose 16-bit microcontrollers designed for

applications that demand high-speed real-time processing suited for industrial applications, OA equipment,

process control, and other applications.

The instruction set is built on the AT architecture of the F²MC-8/16/16H family, with additional

instructions for high-level language support, expanded addressing modes, enhanced multiplication and

division instructions, and improved bit processing instructions. In addition, long-word data can now be

processed due to the inclusion of a 32-bit accumulator.

As peripheral resources, the MB90620 Series includes on chip an LCD control driver (32 segments, 4

common), communications functions (UART, extended serial I/O), three types of timers (16-bit reload

timer × three channels, 16-bit free-run timer × two channels, and 16-bit PPG timer × two channels), a four-

channel 8/10-bit A/D converter, and eight channels for external interrupts.

1.1 Features

î

ï

í

ï

ì

(1) Minimum instruction execution time:........ 83.3 ns (at 4-MHz source

oscillation multiplied by 3)

Uses PLL clock multiplier

method

(2) Instruction set optimized for controller applications

•

Variety of data types: bit, byte, word, long-word

Expanded addressing modes: 23 types

High coding efficiency

Improvement of high-precision operations through use of 32-bit accumulator

(3) Enhanced instruction set supporting high-level language

(C language) and multitasking

•

Inclusion of system stack pointer

Enhanced indirect pointer instructions

Barrel shift instruction

(4) Improved execution speed: ......................4-byte instruction queue

(5) Powerful interrupt functions with 8 levels and 32 sources

(6) Automatic transfer function independent of CPU (EI²OS)

Common

throughout the

2

F MC-16 family

(7) General-purpose ports: ...........................................................................A maximum of 59

(8) UART: ..................................................................................................................... 1 channel

•

Can be used for asynchronous transfer or for synchronous transfer with clock

(9) Extended I/O serial interface: .............................................................................. 1 channel

Can be used for 8-bit synchronous transfer

•

(10) A/D converter (8-/10-bit resolution): ............................................................... 4 channels

(11) PPG (Programmable Pulse Generator):........................................................... 2 channels

1

1.1 Features

(12) 16-bit reload timer: ........................................................................................... 3 channels

(13) 16-bit free-run timer: ........................................................................................ 2 channels

With compare register for 2 channels

(14) LCD controller/driver

32 segments, 4 common (no built-in voltage booster circuit) MB90620 Series

•

(15) External interrupts

(16) 18-bit timebase timer

•

Watchdog timer function

(17) PLL clock multiplier function

(18) CPU intermittent operation function

(19) Various standby modes

(20) Package: SQFP-100

(21) CMOS technology

2

Chapter 1: GENERAL

1.2 Model Expansion (Planned Model Expansion)

Table 1.2.1 lists the models in the MB90620 Series.

Aside from the ROM size and the RAM size all functions are common to all models in the series.

Table 1.2.1 List of Models in the MB90620 Series

MB90622

32 KB

MB90623

48 KB

MB90P623

48 KB

MB90W623

48 KB

MB90V620

ROM size

RAM size

–

1.64 KB

2 KB

3 KB

Mask ROM

product

Mask ROM

product

One-time

PROM product

EPROM

product

Evaluation

product

Applications

3

1.3 Block Diagram

î

X0,X1

6

CPU

F MC-16L Series

Clock controller

í

ì

2

RSTX

X0A,X1A

CLK

RAM

ROM

UART

Interrupt controller

Timer × 3

TIN0-2

TOT0-2

SIN0

SOT0

SCK0

Free-run timer × 2

+

Compare register

Communications

prescaler

PPG0,1

TRG

PPG × 2

SIN1

SOT1

SCK1

Extended I/O

serial interface

8

INT0 to 7

External interrupts

AVCC

AVRH.L

AV,

LCD controller

/driver

SEG00

to

A/D converter

ATGX

AN0 to 3

SEG31

V0-V3

COM0-3

I/O ports

8

7

4

8

P00 P10 P20 P30 P40 P50 P60 P70

to to to to to to to to

P07 P17 P27 P37 P46 P53 P67 P77

• Pins for which the input pull-up resistor can be set: 24 pins (P00 to P27)

• Open drain pins: 18 pins (P45, P46, P60 to P77)

4

Chapter 1: GENERAL

1.4 Pin Assignment

P22

P23

1

2

3

4

5

6

7

8

9

75 RSTX

74 SEG30/P76

73 SEG29/P75

72 SEG28/P74

71 SEG27/P73

70 SEG26/P72

69 SEG25/P71

68 SEG24/P70

67 SEG23/P67

66 SEG22/P66

65 SEG21/P65

64 SEG20/P64

63 SEG19/P63

62 SEG18/P62

61 SEG17/P61

60 SEG16/P60

59 SEG15

P24/SIN0

P25/SOT0

P26/SCK0

P27/CKOT

P30/SIN1

P31/SOT1

VSS

P32/SCK1 10

P33 11

SQFP-100

MB90620 Series

(Top view)

P34 12

P35 13

P36 14

P37/TRG/ATGX 15

P40/PPG0 16

P41/PPG1 17

P42/INT7/TIO0 18

P43/TIO1 19

P44/TIO2 20

VCC 21

58 SEG14

57 SEG13

56 SEG12

55 SEG11

P45 22

P46 23

54 SEG10

53 SEG09

V0 24

V1 25

52 SEG08

51 SEG07

•

Pins for which the input pull-up resistor can be set: 24 pins (ports 0, 1, and 2)

Open drain pins: 18 pins (ports 6, and 7, and pins 45 and 46)

5

1.5 External Dimensions

■ SQFP-100

FPT-100P-M05

EIAJ code: *QFP100-P-1414-1

Lead pitch

0.50 mm

100-pin plastic SQFP

Package width x package

length

14 × 14 mm

Lead shape

Gull-wing

Sealing method

Plastic molding

(FPT-100P-M05)

100-pin plastic SQFP

(FPT-100P-M05)

6

Chapter 1: GENERAL

1.6 Pin Descriptions

Table 1.6.1 Table of Pin Descriptions (1)

Pin No. Pin name

Circuit type

Function

77 78

X1A X0A A (Oscillation)

Crystal oscillator pins (32 kHz).

Digital circuit ground level.

FAR oscillator pins (4 MHz).

Digital circuit power supply.

79

Vss

Power supply

A (Oscillation)

Power supply

M (CMOS/H)

80 81

82

X0 X1

Vcc

83 to

89

P00 to

P06

General-purpose I/O ports. This function is valid only in single-chip

mode.

INT0 to

INT6

External interrupt request input pins. When external interrupts are

enabled, these inputs may be used at any time; therefore, it is neces-

sary to stop output by other functions on these pins, except when

using them for output deliberately.

90

P07

G (CMOS)

F (CMOS/H)

General-purpose I/O port. This function is valid only in single-chip

mode.

91 to

98

P10 to

P17

General-purpose I/O ports. This function is valid only in single-chip

mode.

99 100 P20 to

1 2

General-purpose I/O ports. This function is valid either in single-

chip mode or when the upper address control register is set to "port."

P23

3

P24

General-purpose I/O port. This function is always valid.

SIN0

UART0 serial data input pin. During UART0 input operations, this

input may be used at any time; therefore, it is necessary to stop out-

put by other functions on this pin, except when using it for output

deliberately.

4

5

P25

G (CMOS)

General-purpose I/O port. This function is always valid.

SOT0

UART0 serial data output. This function is valid when the UART0

serial data output specification is "enabled."

P26

F (CMOS/H)

General-purpose I/O port. This function is always valid.

SCK0

UART0 clock I/O pin. This function is valid when the UART0 clock

output specification is "enabled." During UART0 input operations,

this input may be used at any time; therefore, it is necessary to stop

output by other functions on this pin, except when using it for output

deliberately.

6

P27

G (CMOS)

General-purpose I/O port. This function is always valid.

CKOT

Clock output pin. This function is valid when the clock output speci-

fication is "enabled."

7

1.6 Pin Descriptions

Pin No. Pin name

Table 1.6.1 Table of Pin Descriptions (2)

Circuit type

E (CMOS/H)

Function

7

P30

General-purpose I/O port. This function is valid only in single-chip

mode.

SIN1

Extended I/O serial data input pin. During input operations, this

input may be used at any time; therefore, it is necessary to stop out-

put by other functions on this pin, except when using it for output

deliberately.

8

9

P31

D (CMOS)

General-purpose I/O port. This function is valid only in single-chip

mode.

SOT1

Extended I/O serial data output. This function is valid when the

serial data output specification is "enabled."

Vss

P32

Power supply

E (CMOS/H)

Digital circuit ground level.

10

5

General-purpose I/O port. This function is valid in single-chip mode

or when WR pin output is disabled.

SCK1

Extended I/O serial interface clock I/O pin. This function is valid

when the clock output specification is "enabled." During input oper-

ations, this input may be used at any time; therefore, it is necessary

to stop output by other functions on this pin, except when using it for

output deliberately.

11

P33

D (CMOS)

General-purpose I/O port. This function is valid in single-chip

mode, in external bus 8-bit mode, or when WR pin output is dis-

abled.

12

13

14

15

P34

D (CMOS)

E (CMOS/H)

General-purpose I/O port. This function is valid in single-chip mode

and when the hold function is disabled.

P35

General-purpose I/O port. This function is valid in single-chip mode

and when the hold function is disabled.

P36

General-purpose I/O port. This function is valid in single-chip mode

and when the external ready function is disabled.

P37

General-purpose I/O port. This function is valid in single-chip mode

and when the CLK output specification is "disabled."

ATGX

A/D converter trigger input pin. During A/D converter input opera-

tions, this input may be used at any time; therefore, it is necessary to

stop output by other functions on this pin, except when using it for

output deliberately.

TRG

P40

PPG0, PPG1 external trigger input pin.

16

D (CMOS)

General-purpose I/O port. This function is valid when the PPG timer

1 output specification is "disabled."

PPG0

PPG timer 0 output pin. This function is valid when the PPG timer 0

waveform output specification is "enabled."

8

Chapter 1: GENERAL

1.6 Pin Descriptions

Table 1.6.1 Table of Pin Descriptions (3)

Pin No. Pin name

Circuit type

Function

17

P41

D (CMOS)

General-purpose I/O port. This function is valid when the PPG timer

1 output specification is "disabled."

PPG1

P42

PPG timer 1 output pin. This function is valid when the PPG timer 1

waveform output specification is "enabled."

18

L (CMOS/H)

General-purpose I/O port. This function is valid when the timer 0

timer output specification is "disabled."

TIN0

TOT0

INT7

Timer input pin. The data on this pin serves as the timer 0 event

counter signal.

Timer output pin. This function is valid when the timer 0 output

specification is "enabled."

External interrupt request input pin. When external interrupts are

enabled, this input may be used at any time; therefore, it is necessary

to stop output by other functions on this pin, except when using it for

output deliberately.

19

20

P43

E (CMOS/H)

General-purpose I/O port. This function is valid when the timer 1

timer output specification is "disabled."

TIN1

TOT1

P44

Timer input pin. The data on this pin serves as the timer 1 event

counter signal.

Timer output pin. This function is valid when the timer 1 output

specification is "enabled."

E (CMOS/H)

General-purpose I/O port. This function is valid when the timer 2

timer output specification is "disabled."

TIN2

TOT2

Timer input pin. The data on this pin serves as the timer 2 event

counter signal.

Timer output pin. This function is valid when the timer 2 output

specification is "enabled."

21

22

23

V^CC

P45

P46

Power supply

Digital circuit power supply.

H

General-purpose I/O port. Functions for the MB90620 Series.

LCDC reference power supply pins.

24 to

27

V0 to V3 Power supply

28 to

31

COM0 to

COM3

K

LCDC common pins.

32

AVCC

Power supply

Analog circuit power supply. This power supply must only be turned

on or off when electric potential of AVCC or greater is applied to

VCC.

9

1.6 Pin Descriptions

Pin No. Pin name

Table 1.6.1 Table of Pin Descriptions (4)

Circuit type

Function

33

AVR+

Power supply

Analog circuit reference voltage input. This pin must only be turned

on or off when electric potential of AVR+ or greater is applied to

AVCC.

34

35

AVR-

AVSS

Power supply

I (AD)

Analog circuit reference voltage input.

Analog circuit ground level.

36 to

39

P50 to

P53

General-purpose I/O ports. This function is valid when the analog

input enable register specification is "port."

AN0 to

AN3

A/D converter analog input pins. This function is valid when the

analog input enable register specification is "AD."

40

V^SS

Power supply

K

Digital circuit ground level.

41 to

46

SEG00 to

SEG05

LCDC segment dedicated pins.

47 to

49

MD0 to

MD2

C (CMOS)

Operation mode specification input pins. Connect these pins directly

to VCC or VSS.

50 to

59

SEG06 to

SEG15

K

J

LCDC segment dedicated pins.

60 to

67

P60 to

P63

General-purpose I/O ports. Valid when enabled by LCR2.

LCDC segment pins.

SEG16 to

SEG23

68 to

74

P70 to

P76

J

General-purpose I/O ports. Valid when enabled by LCR2.

LCDC segment pins.

SEG24 to

SEG30

75

76

RSTX

P77

B (CMOS/H)

J

External reset request input.

General-purpose I/O ports. Valid when enabled by LCR2.

LCDC segment pins.

SEG31

10

Chapter 1: GENERAL

1.6 Pin Descriptions

Table 1.6.2 I/O Circuit Types (1)

Type

Circuit

Remarks

• Oscillation feedback resistor:

X1

X0

Approximately 1 MW

A

Standby control

• Hysteresis input with pull-up resis-

tor

B

C

• CMOS input port

• CMOS-level input/output

D

CMOS

Standby control

11

1.6 Pin Descriptions

Table 1.6.2 I/O Circuit Types (2)

Type

Circuit

Remarks

• CMOS-level output

• Hysteresis input

E

Standby control

• With input pull-up resistor control

• CMOS-level output

Pull-up control

• Hysteresis input

F

• With input pull-up resistor control

• CMOS-level input/output

Pull-up control

G

CMOS

12

Chapter 1: GENERAL

1.6 Pin Descriptions

Table 1.6.2 I/O Circuit Types (3)

Type

Circuit

Remarks

• Open-drain input/output

H

CMOS

Standby control

• CMOS-level input/output

• Analog input

I

Analog input

CMOS

Standby control

• Open-drain output

• CMOS input

• Also serves as LCD output

LCD output

J

CMOS

Standby control

13

1.6 Pin Descriptions

Table 1.6.2 I/O Circuit Types (4)

Type

Circuit

Remarks

• LCD output pin

LCD output

K

• CMOS output

• Hysteresis input

L

• With input pull-up resistor control

• CMOS-level output

Pull-up control

• Hysteresis input

M

14

Chapter 1: GENERAL

1.7 Notes On Handling The Device

(1) Preventing latch-up

The latch-up phenomenon may occur if a voltage higher than V^CC, or a voltage lower than VSS is applied to

the input or output pins of a CMOS IC or a voltage exceeding the ratings is applied between V^CCand VSS

pins.

When latch-up occurs, the supply current spikes up rapidly to the point where thermal damage to the

device can result; therefore, when using CMOS ICs, it is important not to exceed the maximum ratings.

In addition, for the same reasons it is also important to ensure that the analog power supply does not

exceed the digital power supply.

(2) Treatment of unused pins

The IC may not operate correctly if input pins that are not used are left open; therefore, connect pull-up

or pull-down resistors to unused input pins.

(3) Notes for using an external clock

When using an external clock, drive X0 and leave X1 open. Fig. 1.7.1 shows an example of how to use

an external clock.

X0

X1

MB90620

Fig. 1.7.1 Example of Using an External Clock

(4) Power supply pins

When there are multiple VCC and VSS pins, those pins that should have the same electric potential are

connected within the device when the device is designed in order to malfunctions, such as latchup.

However, all of those pins must be connected to the power supply and ground pins externally in order

to gradually reduce unnecessary emissions, prevent misoperation of strobe signals due to an increase in

the ground level, and to observe the total output current standards.

In addition, the power supply should be connected to V^CCand VSS on this device with the minimum

impedance possible.

Finally, connecting a ceramic capacitor of about 1 µF between VCC and VSS near this device as a

bypass capacitor is recommended.

(5) Crystal oscillator circuit

Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the

printed circuit board so that the bypass capacitors connected to X0, X1, the crystal oscillator (or

ceramic oscillator) and to ground should be located as close to the device as possible.

In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is

surrounded by ground provides stable operation, such an arrangement is strongly recommended.

15

2.1 CPU

Chapter 2:

HARDWARE

2.1 CPU

The F²MC-16L CPU core is a high-performance 16-bit CPU designed for applications that demand high-

speed real-time processing suited for industrial applications, OA applications and automotive equipment.

The F²MC-16L instruction set is optimized for controller applications, and can handle control processing

efficiently and at high speed. In addition, while the F²MC-16L CPU is highly suited for 16-bit data

processing, it also includes an on-chip 32-bit accumulator to permit the handling of 32-bit data; as a result,

a number of instructions are able to process 32-bit data. The memory space can be expanded up to a

maximum of 16 Mbytes, and can be accessed through either linear pointers or banks method. Finally, the

instruction set is based on the F²MC-8 A-T architecture, but has been improved with added functions for

high-level language support, expanded addressing modes, enhanced multiplication and division

instructions, and more comprehensive bit manipulation instructions.

The features of the F²MC-16L CPU core are listed below:

•

Minimum instruction execution time: .................83.3 ns (4-MHz oscillation multiplied by 3)

Large memory space: ...........................................16 Mbytes Can be accessed through linear/bank

methods

•

Instruction set optimized for controller applications

Wider variety of data types: .................................bit, byte, word, long-word

Expanded addressing modes: ...............................23 types

Higher coding efficiency

Enhanced high-precision arithmetic operations (32-bit length) through use of 32-bit accumulator

•

Powerful interrupt functions

Priority levels: .....................................................8 levels (programmable)

Automatic transfer function independent of CPU

Extended intelligent I/O service: ..........................Up to 16 channels

Improved instruction set support for high-level language (C language) and multitasking

Inclusion of system stack pointer

Variety of pointers

High instruction set symmetry

Barrel shift instruction

•

Improved execution speed: ..................................4-byte queue

16

Chapter 2: HARDWARE

2.1 CPU

2.1.1 Memory Space

■ Overview of the CPU memory space

The data, programs, and I/O controlled by the F²MC-16L CPU are all located in the F²MC-16L CPU's 16-

Mbyte memory space. The CPU can access each resource by expressing the addresses through the 24-bit

address bus (Fig. 2.1.1).

FFFFFFH

ì

ï

Program area

í

ï

î

FF8000H

Peripheral circuits

2

F MC-16L

CPU

General-purpose

ports

810000H

Data area

ì

ï

í

Interrupts

Data

ï

î

800000H

0000C0H

ì

ï

í

Interrupt controller

Peripheral circuits

ï

î

0000B0H

ì

ï

í

ï

î

Programs

000020H

000000H

ì

ï

General-purpose

ports

í

[Device]

ï

î

Fig. 2.1.1 Example of Relationship between the F²MC-16L System and the Memory Map

17

2.1 CPU

■ Address generation systems

There are basically two systems for generating addresses: the linear system, in which all 24 bits of the

address are specified by the instruction; and the bank system, in which the upper 8 bits of the address

are specified by the bank register according to the application, and the lower 16 bits of the address are

specified by the instruction.

The linear system can be further divided into two methods: one in which the 24-bit address is specified

directly in the operand, and one in which the lower 24 bits of a 32-bit general-purpose register are

referenced as the address (Fig. 2.1.2).

Example 1. 24-bit operand specification in the linear system

JMPP 123456^H

Memory space

17452D^H

123456H

JMPP 123456^H

Old program counter

+ program bank

17

12

452D

3456

Next instruction

New program counter

+ program bank

Example 2. 32-bit register indirect specification in the linear system

MOV A,@RL1+7

Memory space

3A

Old AL

(accumulator)

XXXX

003A

090700^H

+7

New AL

(accumulator)

RL1

(Upper 8 bits are ignored)

240906F9

Fig. 2.1.2 Examples of Address Generation in the Linear System

18

Chapter 2: HARDWARE

2.1 CPU

■ Addressing methods in the bank system

In the bank system, the 16MB space is divided into 256 banks of 64 Kbytes each, and the following five

bank registers specify the bank that corresponds to each associated space.

•

Program bank register (PCB)

Data bank register (DTB)

User stack bank register (USB)

System stack bank register (SSB)

Additional bank register (ADB)

The 64-Kbyte bank specified by the PCB is called the program (PC) space; primarily instruction codes,

vector tables, and immediate data reside here.

The 64-Kbyte bank specified by the DTB is called the data (DT) space; primarily readable/writable data

and internal/external resource control registers/data registers reside here.

The 64-Kbyte banks specified by the USP and the SSP are called the stack (SP) space; the stack is the

area that is accessed when a stack access operation is generated at a push/pop instruction or when

saving the contents of registers due to an interrupt. Which space is used depends on the value of the S

flag in the condition code register.

The 64-Kbyte bank specified by the ADB is called the additional (AD) space; primarily data that did

not fit in the DT space resides here.

In order to improve instruction coding efficiency, the default space for each instruction is

predetermined in each addressing mode as shown in Table 2.1.1. In addition, to use a space other than

the default space for a given addressing mode, it is possible to specify a prefix code corresponding to

each bank before executing an instruction so that any bank corresponding to the prefix code is accessed.

The DTB, USB, SSB, and ADB registers are initialized to 00^Hby a reset, while the PCB register is

initialized to FF^H. After a reset, the DT, SP and AD spaces are allocated into bank 00H (000000H to

00FFFF^H), while the PC space is allocated into bank FFH (FF0000H to FFFFFFH).

Table 2.1.1 Default Spaces

Default space

Program space

Data space

Addressing modes

PC indirect, program access, branch instructions

Addressing modes that use @RW0, @RW1, @RW4, @RW5; @A, addr16, dir

Addressing modes that use PUSHW, POPW, @RW3, @RW7

Stack space

Additional space Addressing modes that use @RW2, @RW6

19

2.1 CPU

Fig. 2.1.3 shows an example of a memory space divided into banks and each register bank.

FFFFFFH

Program space

:PCB (Program bank register)

FFH

FF0000H

B3FFFFH

B30000H

92FFFFH

920000H

Additional space

User stack space

:ADB (Additional bank register)

:USB (User stack bank register)

B3H

92H

68FFFFH

680000H

Data space

:DTB (Data bank register)

68H

4BH

4BFFFFH

System stack space

:SSB (System stack bank register)

4B0000H

000000H

Fig. 2.1.3 Example of Each Space and Their Physical Addresses

20

Chapter 2: HARDWARE

2.1 CPU

■ Memory space arrangement for multiple-byte data lengths

Fig. 2.1.4 shows the data configuration in memory for multiple-byte data lengths. The lower 8 bits of

data are stored in address n, and the remaining data bits are stored in address n + 1, address n + 2,

address n + 3, and so on.

MSB

01010101

LSB

00010100

11001100

11111111

H

01010101

11001100

11111111

00010100

Address n

L

Fig. 2.1.4 Example of Memory Space Arrangement for Multiple-byte Data Lengths

Writes to memory are performed starting from the lower address. Therefore, in the case of 32-bit data,

the lower 16 bits are transferred first, followed by the upper 16 bits.

Note that if a reset signal is input immediately after the lower data is written, the upper data may not be

written.

■ Accessing multiple-byte data lengths

Basically, all accesses are conducted within a bank, but in the case of an instruction that accesses

multiple-byte data lengths, the address that follows the address FFFF^His 0000H in the same bank. Fig.

2.1.5 shows an example of the execution of a multiple-byte data access instruction.

H

AL before execution

AL after execution

??

80FFFFH

01H

23H

01H

800000^H

L

Fig. 2.1.5 Execution of MOVW A, 080FFFF

H

21

2.1 CPU

2.1.2 Registers

The registers in the F²MC-16L can be broadly classified into two types: dedicated registers within the CPU

and general-purpose registers in memory. The dedicated registers exist as dedicated hardware in the CPU,

and the purposes for which they are used are limited by the CPU architecture. Conversely, the general-

purpose registers reside in the CPU address space with RAM; while they are the same as the dedicated

registers in that they can be accessed without specifying an address, they are like normal memory in that

they can be used for any purpose specified by the user.

22

Chapter 2: HARDWARE

2.1 CPU

■ Dedicated registers

The thirteen dedicated registers in the F²MC-16L are indicated below.

•

Accumulator

(A = AH:AL): This accumulator consists of two 16-bit registers. They

can also be used as one 32-bit accumulator.

•

User stack pointer

System stack pointer

Processor status

(USP): This is a 16-bit pointer that points to the user stack area.

(SSP): This is a 16-bit pointer that points to the system stack area.

(PS): This is a 16-bit register that shows the system status.

Program counter

(PC): This is a 16-bit register that contains the address where the

next program instruction is stored.

•

Program bank register

Data bank register

(PCB): This is an 8-bit register that points to the PC space.

(DTB): This is an 8-bit register that points to the DT space.

(USB): This is an 8-bit register that points to the user stack space.

User stack bank register

System stack bank register

(SSB): This is an 8-bit register that points to the system stack

space.

•

Additional bank register

Direct page register

(ADB): This is an 8-bit register that points to the AD space.

(DPR): This is an 8-bit register that points to the direct page.

Fig. 2.1.6 shows an image of the dedicated registers.

AL

Accumulator

AH

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

Direct page register

DPR

PCB

DTB

USB

SSB

ADB

Program bank register

Data bank register

User stack bank register

System stack bank register

Additional data bank register

8bit

16bit

32bit

Fig. 2.1.6 Dedicated Registers

23

2.1 CPU

■ General-purpose registers

The F²MC-16L general-purpose registers reside in the area from 000180H to 00037FH (when using

maximum area available); the register bank pointer (RP) indicates which portion of that address space

is the register bank in current use. The following three types of registers exist in each bank. These

registers are not independent; rather, they exist in the relationship illustrated in Fig. 2.1.7.

•

R0 to R7:

8-bit general-purpose register

RW0 to RW7: 16-bit general-purpose register

RL0 to RL3: 32-bit general-purpose register

MSB

LSB

16bit

RW0

RW1

RW2

RW3

*

î

í

ì

î

í

ì

î

í

ì

î

í

ì

000180H+RP 10H

Low oder

Top address of

general-purpose register

RL0

RL1

RL2

RL3

R1

R3

R5

R7

R0

R2

R4

R6

RW4

RW5

RW6

RW7

High oder

Fig. 2.1.7 General-purpose Registers

The relationship between the byte registers and the upper/lower bytes of the word registers can be

expressed as follows:

RW(i+4) = R(i*2+1) * 256 + R(i*2) [i = 0 to 3]

While the relationship between the low order/high order RLi and RW can be expressed as follows:

RL(i) = RW(i*2+1) * 65536 + RW(i*2) [i = 0 to 3]

■ Program counter (PC)

The PC is a 16-bit counter that indicates the lower 16 bits of the memory address where the next

instruction code that should be executed by the CPU resides. The upper 8 bits of that address are

indicated by the PCB. The contents of the PC are updated by conditional branching instructions,

subroutine call instructions, interrupts, resets, etc. The PC is also used as the base pointer when

performing an operand access.

PC ABCDH

PCB FEH

Next instruction

to be executed

FEABCD^H

Fig. 2.1.8 Program Counter

24

Chapter 2: HARDWARE

2.1 CPU

■ Accumulator (A)

The accumulator (A) consists of two 16-bit arithmetic registers AH and AL. These registers are used

for purposes such as temporary storage of arithmetic results or when transferring data. When

processing 32-bit data, AH and AL are linked and used together; when processing 16-bit data words or

8-bit data bytes, only AL is used (see Fig. 2.1.9 and Fig. 2.1.10). The data in the accumulator can be

used in all types of arithmetic operations with data in memory or registers (Ri, RWi, RLi).

Furthermore, just as in the case of the F²MC-8, if data of the basic word length or less is transferred to

the AL in the F²MC-16L, any data that was already in the AL prior to the transfer is automatically

transferred to the AH (data retention function). This data retention function and arithmetic operations

between the AL and the AH make improved efficiency possible in all types of processing (See Fig.

2.1.10).

When byte-length or shorter data is transferred to the AL, the data is given a sign extension or a zero

extension so that it is 16 bits long before it is stored in the AL. In addition, data in the AL can be

handled as if it were word length or byte length. If a byte-processing arithmetic operation instruction is

performed using the contents of the AL, the upper 8 bits of the AL prior to the operation are ignored

and the upper 8 bits of the results of the operation are all zero.

MOVL A, @RW1+6

MSB

LSB

8FH

2BH

74H

52H

A61540^H

Old A

XXXXH

A6153EH

+6

DTB

A6H

15H

38H

RW1

New A

8F74H

AH

2B52H

AL

Fig. 2.1.9 32-bit Data Transfer Example

MOVW A, @RW1+6

MSB

LSB

8FH

2BH

74H

52H

A61540^H

Old A

XXXXH

1234H

A6153EH

+6

DTB

A6H

15H

38H

RW1

New A

1234H

AH

2B52H

AL

Fig. 2.1.10 AL-AH Transfer Example

25

2.1 CPU

■ User stack pointer (USP) and system stack pointer (SSP)

The USP and SSP are 16-bit registers that indicate the memory addresses for saving and recovering

data when executing push/pop instructions and subroutines. The USP and SSP are used in similar

manners by the stack system instructions, but the USP register is enabled when the S flag in the process

status register is "0" and the SSP register is enabled when the S flag is "1" (see Fig. 2.1.11). In addition,

because the S flag is set when an interrupt is received, whenever the contents of registers are saved

during an interrupt, they are saved in memory pointed to by the SSP. The SSP is used for stack

processing in normal interrupt routines, while the USP is used for stack processing outside of interrupt

routines. Users that have no need to divide the stack space should only use the SSP.

The upper eight bits of the addresses used for stacks are indicated by the SSB in the case of the SSP,

and by the USB in the case of the USP.

Example 1. PUSHW A when the S flag is "0"

MSB

LSB

Before execution Þ

AL A624H

S flag

USB C6H

SSB 56H

USP

SSP

F328H

1234H

XX

C6F326H

0

Ü User stack is used because S flag is '0'

After execution Þ

AL A624H

S flag

USB C6H

SSB 56H

USP

SSP

F326H

1234H

0

A6H

24H

C6F326H

Example 2. PUSHW A when the S flag is "1"

Before execution Þ

AL A624H

S flag

USB C6H

SSB 56H

USP

SSP

F328H

1234H

XX

561232^H

1

After execution Þ

A6H

24H

AL A624H

S flag

USB C6H

SSB 56H

USP

SSP

F328H

1232H

561232H

Ü User stack is used because S flag is '1'

1

Fig. 2.1.11 Stack Manipulation Instructions and the Stack Pointers

Note: As a general rule, even addresses should be set in the stack pointers.

26

Chapter 2: HARDWARE

2.1 CPU

■ Processor status (PS)

The PS consists of various bits that control operations and that show the status of the CPU. As shown

in Fig. 2.1.12, the upper bytes of the PS consist of the register bank pointer (RP), which shows the top

address of the register bank, and the interrupt level mask register (ILM). The lower bytes of the PS

consist of the condition code register (CCR), which consists of various flags that are set/reset according

to the results of instruction execution and the occurrence of interrupts.

15

13 12

8 7

0

PS

ILM

RP

CCR

Fig. 2.1.12 Configuration of the PS

(1) Condition code register (CCR)

Fig. 2.1.13 shows the configuration of the condition code register.

7

–

6

5

4

T

3

2

Z

1

0

I

S

N

V

C

:CCR

Fig. 2.1.13 Configuration of the Condition Code Register

I (Interrupt enable flag): For all interrupt requests (aside from software interrupts), when I is "1",

interrupts are enabled; when I is "0" interrupts are masked. This flag is

cleared by a reset.

S (Stack flag):

When S is "0", the USP is enabled as the pointer used for stack operations.

When S is "1", the SSP is enabled. This flag is set when an interrupt is

received and when a reset is executed.

T (Sticky bit flag):

This flag is set to "1" if there is at least one "1" in data that was shifted out by

a carry when a logical right/arithmetic right shift instruction was executed;

otherwise, this bit is "0". This bit is also "0" when the shift amount was

zero.

N (Negative flag):

Z (Zero flag):

This flag is set if the MSB of an operation result was "1", and is cleared if

the MSB was "0".

This flag is set if the an operation result was all zeros, and is cleared in any

other case.

V (Overflow flag):

C (Carry flag):

This flag is set if an overflow occurred as a signed value when an operation

was executed, and is cleared if no overflow occurred.

This flag is set if a digit was carried in or out from the MSB when an

operation was executed, and is cleared if no carry occurred.

27

2.1 CPU

(2) Register bank pointer (RP)

The RP register indicates the relationship between the F²MC-16L's general-purpose registers and the

internal RAM addresses where they reside, indicating the top memory address of the register bank

currently being used through the conversion formula [000180^H+ (RP) × 10H] (see Fig. 2.1.7). The RP

consists of five bits and thus can express a value from 00^Hto 1FH, and the register banks can be

allocated into memory from 000180^Hto 00037FH. However, even if the address is within this range, it

must be part of internal RAM, or else it cannot be used as a general-purpose register.

An 8-bit immediate value can be transferred to the RP by an instruction, but only the lower five bits of

that data are actually used.

B4 B3 B2 B1 B0 :RP

Fig. 2.1.14 Register Bank Pointer

(3) Interrupt level mask register (ILM)

The ILM consists of three bits and indicates the CPU interrupt mask level. Only interrupt requests of a

stronger (higher priority) level than the level indicated by these three bits are accepted. Level 0 is

defined as the strongest (highest priority) level, and level 7 is defined as the weakest (lowest priority)

level (see Table 2.1.2). Therefore, for an interrupt to be accepted, it must be a request of a level that is

a smaller value than the value currently stored in the ILM. When an interrupt is accepted, the value of

the interrupt level is set in the ILM, and subsequent interrupts with the same or lower priority ranking

than that interrupt level are not accepted. When reset, all ILM bits are initialized to "0". An 8-bit

immediate value can be transferred to the ILM by an instruction, but only the lower three bits of that

data are actually used.

ILM2

ILM1 ILM0

:ILM

Fig. 2.1.15 Interrupt Level Register

Table 2.1.2 Comparative Strength of Levels Indicated by the Interrupt Level Mask Register (ILM)

ILM2

ILM1

ILM0

Level value

Enabled interrupt levels

Interrupts disabled

0 only

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

Level 1 or smaller

Level 2 or smaller

Level 3 or smaller

Level 4 or smaller

Level 5 or smaller

Level 6 or smaller

28

Chapter 2: HARDWARE

2.1 CPU

■ Register bank

The register bank consists of eight words. Byte registers R0 to R7, word registers RW0 to RW7, and

long-word registers RL0 to RL3 can be used as general-purpose registers for various arithmetic

operations and as pointers for various instructions. RL0 to RL3 can also be used as linear pointers for

direct access of all of memory. Table 2.1.3 shows the function of each register, and Table 2.1.4 shows

the relationships among the registers.

Table 2.1.3 Function of Each Register

Used as operands for various functions.

R0 to R7

Note: R0 is also used as a counter for barrel shifts and as a counter for the

normalize instruction.

Used as pointers.

RW0 to RW7 Used as operands for various instructions.

Note: RW0 is also used as a counter for string instructions.

Used as long pointer.

Used as operands for various instructions.

RL0 to RL3

Table 2.1.4 Relationships Among Registers

RW0

RL0

RW1

RW2

RL1

RW3

R0

RW4

R1

R2

R3

RL2

RW5

R4

RW6

R5

R6

R7

RL3

RW7

29

2.1 CPU

■ Program counter bank register (PCB),

data bank register (DTB),

user stack bank register (USB),

system stack bank register (SSB),

and additional data bank register (ADB)

These bank registers indicate the memory banks where the PC space, DT space, SP space (user), SP

space (system), and AD space are located respectively. All of the bank registers are byte length. A reset

initializes the PCB to 0FF^Hand the others are initialized to 00H. All of the bank registers except for

PCB can be read and written. Although the PCB can be read, it cannot be written. The PCB is updated

with an interrupt or with a JMPP, CALLP, RETP, RETI, or RETF instruction that branches to another

location within the entire 16MB space. For details on the operation of each register, refer to section

2.1.1, "Memory Space."

■ Direct page register (DPR)

The DPR specifies addr8 to addr15 of the operand for a direct addressing instruction as shown in Fig.

2.1.16. The DPR is eight bits long, and is initialized to 01^Hby a reset. This register can be read/written

by instructions.

DTB register

DPR register

Direct address within instruction

a a a a a a a a

bbbbbbbb

gggggggg

MSB

LSB

24-bit

physical address

a a a a a a a a bbbbbbbbgggggggg

Fig. 2.1.16 Generation of Physical Addresses through Direct Addressing

30

Chapter 2: HARDWARE

2.1 CPU

2.1.3 Prefix Codes

By placing a prefix code in front of an instruction, it is possible to partially alter the operation of that

instruction. There are three types of prefixes: bank select prefix, common register bank prefixes, and flag

change suppression prefixes.

■ Bank select prefixes

The memory space used for data access is specified for each addressing operation. By placing a bank

select prefix before the instruction, it is possible to select the memory space in which data is to be

accessed by that instruction regardless of the addressing mode. The bank select prefixes and the

memory spaces that they select are shown in Table 2.1.5.

Table 2.1.5 Bank Select Prefixes

Bank select prefixes

Space selected

PC space

PCB

DTB

ADB

Data space

AD space

Either the SSP space or the USP space,

whichever is selected by the S flag, is used.

SPB

However, the special cases indicated below must be noted when using a bank select prefix with the

following instructions:

(1) String instructions

MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW

The bank register specified by the operand is used, regardless of whether a prefix is specified or not.

(2) Stack manipulation instructions

PUSHW, POPW

Either the SSB or the USB is used, in accordance with the S flag, regardless of whether a prefix is

specified or not.

(3) I/O access instructions

MOV A, io; MOV io, A; MOVX A, io; MOVW A, io; MOVW io, A; MOV io, #imm8; MOVW io,

#imm16; MOVB A, io:bp; MOVB io:bp, A; SETB io:bp; CLRB io:bp; BBC io:bp, rel; BBS io:bp, rel;

WBTC; WBTS

The bank I/O space is accessed, regardless of whether a prefix is specified or not.

31

2.1 CPU

(4) Flag change instructions

AND CCR, #imm8; OR CCR, #imm8

The operation indicated by the instruction itself is performed normally. The effect of the prefix extends

to the next instruction.

(5) POPW ps

Either the SSB or the USB is used, in accordance with the S flag, regardless of whether the prefix is

specified or not. The effect of the prefix extends to the next instruction.

(6) MOV ILM, #imm8

The operation indicated by the instruction itself is performed normally. The effect of the prefix extends

to the next instruction.

(7) RETI

The SSB is used, regardless of whether a prefix is specified or not.

■ Common register bank prefix (CMR)

In order to permit the easy exchange of data between multiple tasks, a comparatively easy means for

accessing the same specified register bank is required, no matter what the current value of the RP is. By

placing CMR before the instruction that will access the register bank, it is possible to change all the

registers accessed by that instruction to the common bank located between 000180^Hto 00018FH (the

register bank selected when RP = 0), regardless of what the current value of the RP is. However, the

special cases indicated below must be noted when using the common register bank prefix with the

following instructions:

(1) String instructions

MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW

If an interrupt request is generated during the execution of a string instruction to which a prefix code

has been added, the instruction will function incorrectly since prefixes are invalid for string instructions

after recovery from an interrupt. Do not add the CMR prefix to the string instructions listed above.

(2) Flag change instructions

AND CCR, #imm8; OR CCR, #imm8; POPW PS

The operation indicated by the instruction itself is performed normally. The effect of the prefix extends

to the next instruction.

(3) MOV ILM, #imm8

The operation indicated by the instruction itself is performed normally. The effect of the prefix extends

to the next instruction.

32

Chapter 2: HARDWARE

2.1 CPU

■ Flag change suppression prefix

The flag change suppression prefix code (NCC) is used to suppress unnecessary flag changes. Flag

changes that accompany the execution of an given instruction can be suppressed by placing the NCC

prefix in front of the instruction in question. However, the special cases indicated below must be noted

when using the flag change suppression prefix with the following instructions:

(1) String instructions

MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW

If an interrupt request is generated during the execution of a string instruction to which a prefix code

has been added, the instruction will function incorrectly since prefixes are invalid for string instructions

after recovery from an interrupt. Do not add the NCC prefix to the string instructions listed above.

(2) Flag change instructions

AND CCR, #imm8; OR CCR, #imm8; POPW PS

CCR changes the flags according to the specifications of the instruction, regardless of whether the

prefix is specified or not. The effect of the prefix extends to the next instruction.

(3) Interrupts

INT #vct8, INT9, INT addr16, INTP addr24, RETI

CCR changes the flags according to the specifications of the instruction, regardless of whether the

prefix is specified or not.

(4) JCTX @A

CCR changes the flags according to the specifications of the instruction, regardless of whether the

prefix is specified or not.

(5) MOV ILM, imm8

The operation indicated by the instruction itself is performed normally. The effect of the prefix extends

to the next instruction.

■ Interrupt suppression instructions

The following ten instructions do not sample interrupt requests.

•

MOV ILM, #imm8

AND CCR, #imm8

OR CCR, #imm8

POPW PS

•

PCB

ADB

NCC

DTB

•

SPB

CMR

Therefore, as shown in Fig. 2.1.17, even if a valid interrupt request is generated while one of these

instructions is being executed, the interrupt processing is executed subsequent to this instruction after

the first instruction that is not one of the types listed above is executed.

33

2.1 CPU

Interrupt suppression instruction

…………

……

(a) Normal instruction

(a)

•

Interrupt request generated

Interrupt accepted

Fig. 2.1.17 Interrupt Suppression Instruction

■ Restrictions regarding interrupt suppression instructions and prefix instructions

If a prefix code is assigned to an interrupt suppression instruction as shown in Fig. 2.1.18, the effect of

the prefix code extends to the first instruction other than an interrupt suppression instruction that

appears after the prefix code.

Interrupt suppression instruction

…

MOV A, FFH

NCC

MOV ILM, #imm8

ADD A, 01^H

CCR:XXX10XX

CCR is not changed due to NCC

Fig. 2.1.18 Interrupt Suppression Instructions and Prefix Codes

■ Consecutive prefix codes

When conflicting prefix codes follow one another, the later prefix code takes precedence.

Prefix codes

……

ADB

DTB

PCB

ADD A, 01H

• PCB is the valid prefix code

Fig. 2.1.19 Consecutive Prefix Codes

The conflicting prefix codes are PCB, ADB, DTB, and SPB.

34

Chapter 2: HARDWARE

2.1 CPU

2.1.4 Interrupts, Extended Intelligent I/O Service, Exceptions

In the F²MC-16L, interrupt processing or the extended intelligent I/O service started up in response to

interrupt requests from an internal resource. In interrupt processing, processing in accordance with the

interrupt request is performed by the interrupt processing program. In the extended intelligent I/O service,

data transfers are performed automatically between internal resources and memory. There are also

functions that, for example, interrupt the execution of the extended intelligent I/O service in response to a

request from a resource.

■ Interrupts

(1) Hardware interrupts

Internal resources that are able to issue hardware interrupt requests to the F²MC-16L CPU require an

interrupt request flag and an interrupt enable flag. The interrupt request flag is reset by the occurrence

of events unique to internal resources. The interrupt request flag indicates that there is an interrupt

request, and when the interrupt request flag is enabled, a hardware interrupt request is generated by the

internal resource. For those internal resources that need to start up the extended intelligent I/O service

by generating a hardware interrupt request, an extended intelligent I/O service enable flag (ISE) is

provided in the interrupt control register (ICR) in the interrupt controller corresponding to that resource.

when that flag is "1", the extended intelligent I/O service is started up by the generation of an interrupt

request. Set the ISE to "0" to start up a normal interrupt in response to a hardware interrupt.

It is possible to specify interrupt levels for groups of a uniform type of request. The interrupt level

specification is made by the interrupt level setting bits (IL0, IL1, and IL2) in the interrupt controller.

The interrupt level can be set to one of eight levels, from 0 to 7. Interrupt level 0 is the strongest

(highest priority) level, while interrupt level 6 is the weakest (lowest priority). An interrupt source

group for which interrupt level 7 is set does not issue interrupt requests. In addition, hardware interrupt

requests can be masked through the I flag and the ILM (ILM0, ILM1, ILM2) register in the PS. If an

interrupt request that is not masked is generated, the CPU saves the twelve bytes of the PS, PC, PCB,

DTB, ADB, DPR and A to the location in memory indicated by the SSB and SSP, fetches the three

bytes of the interrupt vector, loads them into the PC and the PCB, updates the ILM in the PS with the

level of the interrupt request that was accepted, sets the S flag, and begins to execute instructions

starting at the address indicated by the interrupt vector.

As a special case, hardware interrupt requests are not accepted during writes to the I/O area. This is

done in order to avoid malfunctions of the CPU in regards to interrupts as a result of an interrupt request

occurring while the interrupt control registers for each resource are being overwritten.

(2) Software interrupts

There is no interrupt request flag or enable flag for interrupt requests generated by executing the INT

instruction (software interrupt); when the INT instruction is executed, an interrupt request is always

generated.

The INT instruction has no interrupt levels. Therefore, when an INT instruction is executed, the ILM

register is not updated, the I flag is cleared, and continuing interrupt requests are put on hold.

35

2.1 CPU

The interrupt vectors are shared by hardware interrupts and software interrupts. For example, interrupt

request number INT 42 is used by both the delay interrupt of hardware interrupt as well as the software

interrupt INT #42. As a result, both the delay interrupts and INT #42 call the same interrupt processing

routine. The interrupt vectors are located in FFFC00^Hto FFFFFFH, as shown in Table 2.1.6.

Table 2.1.6 Interrupt Vector Table

Lower vector

addresses

Higher vector

addresses

Vector address

bank

Interrupt request

Mode register

INT 0 *1

INT 1 *1

FFFFFC^H

FFFFF8^H

FFFFFDH

FFFFF9H

FFFFFEH

FFFFFAH

Not used

.

INT 7 *1

INT 8 *2

INT 9

FFFFE0^H

FFFFDC^H

FFFFD8H

FFFFD4^H

FFFFD0^H

FFFFE1H

FFFFDDH

FFFFD9H

FFFFD5H

FFFFD1H

FFFFE2H

FFFFDEH

FFFFDAH

FFFFD6H

FFFFD2H

Not used

FFFFDFH

Not used

INT 10 *3

INT 11

.

INT 254

INT 255

FFFC04^H

FFFC00^H

FFFC05H

FFFC01H

FFFC06H

FFFC02H

Not used

*1: Because the CALLV instruction vector area when the PCB is FFH and the INT #vct8 (#0 to #7)

vector area are shared, caution is required when using the vector for the CALLV instruction.

*2: This vector is the reset vector.

*3: This vector is the exception processing vector.

36

Chapter 2: HARDWARE

2.1 CPU

■ Interrupt flow chart

I:

Flag in CCR

ILM: CPU level register

IF:

IE:

Internal resource interrupt request

Internal resource interrupt enable flag

ISE: EI²OS enable flag

IL:

S:

Internal resource interrupt request level

Flag in CCR

I & IF & IE = 1

AND

YES

ILM > IL

NO

YES

ISE = 1

Fetch and decode next instruction

Save PS, PC, PCB, DTB, ADB,

DPR, and A to the SSP stack;

afterwards, ILM = IL

Extended intelligent I/O

service processing

YES

INT instruction?

Save PS, PC, PCB, DTB, ADB,

DPR, and A to the SSP stack;

afterwards, I = 0, ILM = IL

NO

Execute instruction normally

End of

repeated string

instructions?

NO

S ¬ 1

Fetch interrupt vector

YES

Update PC

37

2.1 CPU

Saving of registers upon an interrupt

Word (16 bits)

MSB

LSB

H

SSP

(value of SSP prior to occurrence of interrupt)

A H

A L

ADB

PCB

DPR

DPB

P C

P S

SSP

L

(value of SSP after occurrence of interrupt)

38

Chapter 2: HARDWARE

2.1 CPU

■ Extended intelligent I/O service (EI²OS)

The EI²OS is a function that automatically transfers data between the I/O area and memory. This

function makes it possible to handle as DMA transfers the data exchanges with I/O performed in

conventional interrupt processing programs. This function offers the following benefits compared to

the method used in conventional interrupt processing:

•

Because there is no need to write a transfer program, program size can be reduced.

Because the internal registers are not used during transfers, the necessity of saving the contents

of registers is eliminated, making transfers faster.

•

It is possible to stop transfers according to the I/O status, eliminating transfers of unnecessary

data.

•

It is possible to select whether to increment the buffer address or to not update it.

It is possible to select whether to increment the I/O register address or to not update it.

In addition, when the EI²OS terminates, it branches automatically to the interrupt processing routine

after the termination condition is set; this allows the user to determine what the termination condition

was.

The hardware for implementing the EI²OS is divided into two separate parts, and each block contains

the following register and descriptor.

•

Interrupt control register:

In the interrupt controller; shows the ISD

address.

•

Extended intelligent I/O service descriptor (ISD):

In RAM; stores the transfer mode, the I/O

address and number of transfers, and the

buffer address.

Fig. 2.1.20 shows an overview of the extended intelligent I/O service.

Memory space

by IOA

Peripheral

ice

I/O register

dev

Interrupt request

(1)

CPU

(3)

by ICS

ISD

(2)

Interrupt control register

Interrupt controller

(1) I/O requests transfer

(2) Interrupt controller selects descriptor.

by BAP

(3) Reads the transfer origin/destination

from descriptor.

Buffer

(4)

(4) Transfer is made between I/ O and

memory.

Fig. 2.1.20 Overview of Extended Intelligent I/O Service

39

2.1 CPU

■ Interrupt control register (ICR)

The interrupt control register is located in the interrupt controller, and supports all I/O that has an

interrupt function. This register has the following three functions:

•

Setting of the interrupt level for the corresponding peripheral devices

Selection of whether to handle interrupts from the corresponding peripheral devices as normal

interrupts or through the extended intelligent I/O service

•

Selection of the extended intelligent I/O service channel

Do not access this register with a read-modify-write instruction, since doing so can cause malfunctions.

Fig. 2.1.21 shows the bit configuration of the interrupt control register.

7

6

5

4

3

2

1

0

ICS1

or S1

ICS0

or S0

Interrupt control register

When reset: 00000111^B

ICS3

W

ICS2

W

ISE

R/W

IL2

R/W

IL1

R/W

IL0

R/W

*

Note1: ICSS to ICS0 are valid only when starting up the EI²OS. When starting up the EI²OS, set ISE to

"1"; when not starting it up, set ISE to "0". If EI²OS is not being started up, the settings of ICS3 to

ICS0 do not matter.

* When read, "1" is returned.

Note2: ICS1 and ICS0 are write-only bits; S1 and S0 are read-only bits.

Fig. 2.1.21 Interrupt Control Register (ICR)

The meanings of all of the bits in the interrupt control register are shown on the following pages.

40

Chapter 2: HARDWARE

2.1 CPU

■ Interrupt level setting bits: IL0, IL1, IL2

These bits can be read and written, and specify the interrupt levels for the corresponding internal

resources. When reset, the interrupt levels are initialized to level 7 (no interrupts). The relationship

between the interrupt level setting bits and each interrupt level is shown in Table 2.1.7.

Table 2.1.7 Correspondence between Interrupt Level Setting Bits and Interrupt Levels

IL2

0

IL1

0

IL0

0

Level value

0 (Strongest (highest priority) interrupt)

0

1

0

1

0

2

0

1

3

1

0

4

1

0

1

5

1

0

6 (Weakest (lowest priority interrupt)

7 (No interrupts)

1

■ Extended intelligent I/O service enable bit: ISE

This bit can be read and written. If this bit is "1" when an interrupt request is generated, EI²OS is

started up; when "0", the interrupt sequence is started up. In addition, when EI²OS terminates, the ISE

bit is cleared to "0". If the corresponding peripheral device does not support the EI²OS, it is necessary

to set the ISE bit to "0" via software.

When reset, this bit is initialized to "0".

41

2.1 CPU

■ Extended intelligent I/O service channel select bits: ICS3 to ICS0

These write-only bits are used to set the EI²OS channel. The value set here determines the address of

the extended intelligent I/O service descriptor in memory (described later). The ICS bits are initialized

by a reset.

Table 2.1.8 shows the correspondence between the ICS bits, the channel numbers, and the descriptor

addresses.

Table 2.1.8 Correspondence between ICS Bits, Channel Numbers, and Descriptor Addresses

ICS3

ICS2

ICS1

ICS0

Selected channel

Descriptor address

000100^H

000108H

000110H

000118H

000120H

000128H

000130H

000138H

000140H

000148H

000150H

000158H

000160H

000168H

000170H

000178H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

42

Chapter 2: HARDWARE

2.1 CPU

■ Extended intelligent I/O service termination status: S0, S1

These are read-only bits. By checking the value of these bits when EI²OS terminates, it is possible to

determine what the termination condition was. After a reset, these bits are set to "00".

Table 2.1.9 shows the relationship between the S bits and the termination conditions.

Table 2.1.9 S Bits and Termination Conditions

S1

0

S0

0

Termination conditions

Reserved

0

1

By count termination

Reserved

1

0

1

By request from resource

■ Extended intelligent I/O service descriptors (ISD)

The extended intelligent I/O service descriptors reside in internal RAM from 000100^Hto 00017FH, and

consist of the following elements:

•

Control data for data transfers

Status data

Buffer address pointer

Fig. 2.1.22 shows the configuration of an extended intelligent I/O service descriptor.

ISD top address

Lower 8 bits of buffer address pointer (BAPL)

Middle 8 bits of buffer address pointer (BAPM)

Upper 8 bits of buffer address pointer (BAPH)

L

2

EI OS status (ISCS)

Lower 8 bits of I/O address pointer (IOAL)

Higher 8 bits of I/O address pointer (IOAH)

Lower 8 bits of data counter (DCTL)

Higher 8 bits of data counter (DCTH)

H

Fig. 2.1.22 Extended Intelligent I/O Service Descriptor Configuration

43

2.1 CPU

■ Data counter (DCT)

This 16-bit register is a counter that counts the transfer data. Before data is transferred, the counter is

2

decremented by one. When the count reaches zero, EI OS terminates. Fig. 2.1.23 shows the

configuration of the data counter.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

: DCT

(undecided

when reset)

B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

Fig. 2.1.23 Data Counter Configuration

■ I/O register address pointer (IOA)

This 16-bit I/O register address pointer indicates the lower addresses (A15 to A0) for the buffer and

data transfer I/O register. The higher addresses (A23 to A16) are all zeroes, so I/O anywhere from

000000^Hto 00FFFFH can be specified. Fig. 2.1.24 shows the configuration of the IOA.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 : IOA

(undecided

when reset)

Fig. 2.1.24 I/O Register Address Pointer Configuration

44

Chapter 2: HARDWARE

2.1 CPU

■ EI²OS status register (ISCS)

This 8-bit register indicates the update direction (increment/decrement) for the buffer address pointer

and the I/O register address pointer, the transfer data format (byte/word), the transfer direction, the

buffer address pointer, and whether the buffer address pointer and I/O register address pointer are

updated or fixed. Fig. 2.1.25 shows the configuration of the ISCS.

7

6

5

4

3

2

1

0

Reserved Reserved Reserved

BW

BF

DIR SE

IF

:ISCS (undecided when reset)

Fig. 2.1.25 ISCS Configuration

The meaning of individual bits is described below.

[Bit 4] IF: Specifies whether the I/O register address pointer is updated or fixed.

0: The I/O register address pointer is updated after data transfers.

1: The I/O register address pointer is not updated after data transfers.

Note: Only incrementing is possible.

[Bit 3] BW: Specifies the transfer data length.

0: Byte

1: Word

[Bit 2] BF: Specifies whether the buffer address pointer is updated or fixed.

0: The buffer address pointer is updated after data transfers.

1: The buffer address pointer is not updated after data transfers.

Note: On updating, the buffer address pointer varies by the lower 16 bits only.

Only incrementing is possible.

[Bit 1] DIR: Specifies the data transfer direction.

0: I/O to buffer

1: Buffer from I/O

[Bit 0] SE: Controls termination of the extended intelligent I/O service in response to a request from a

resource.

0: Does not terminate upon request by a resource.

1: Does terminate upon request by a resource.

45

2.1 CPU

■ Buffer address pointer (BAP)

This 24-bit register holds the address to be used next for a transfer by the EI²OS. Because there is a

separate BAP for each EI²OS channel, each EI²OS can be used to transfer data to any space within the

16MB area. If updating is specified by the BF bit in the ISCS, only the lower 16 bits in the BAP are

changed; the BAPH is not changed.

Fig. 2.1.26 shows a flow chart of EI²OS operations, while Fig. 2.1.27 shows a flow chart of the

procedure for using EI²OS.

46

Chapter 2: HARDWARE

2.1 CPU

Interrupt request generated

by internal resource

BAP: Buffer address pointer

I/OA: I/O address pointer

ISD: EI²OS descriptor

ISCS: EI²OS status

NO

ISE=1

YES

DCT: Data counter

ISE: EI²OS enable bit

S1,S0: EI²OS termination status

Read ISD/ISCS

Interrupt sequence

Termination

request

YES

from resource?

YES

SE=1

NO

DIR=1

NO

Transfer data indicated

by IOA to memory

indicated by BAP

Transfer data indicated

by BAP to memory

indicated by IOA

YES

IF=0

NO

Update value

indicated

by BW

Update IOA

Update BAP

YES

BF=0

NO

Update value

indicated

by BW

(-1)

Decrement DCT

DCT=00

YES

Set "01" in S1, S0

Set "11" in S1, S0

NO

Set "00" in S1, S0

Clear resource

Clear ISE to "0"

interrupt request

Recovery of CPU operation

Interrupt sequence

Fig. 2.1.26 Flow of EI²OS Operations

47

2.1 CPU

Processing by CPU

Initial setting of I²OS

Processing by EI²OS

(Interrupt requests) AND (ISE = 1)

Normal termination status

Execute job

Transfer data

Count out or interrupt generated by

termination request from resource

Reset extended

intelligent I/O service

(channel switching)

Process data in buffer

Fig. 2.1.27 Flow of Procedure for Using EI²OS

48

Chapter 2: HARDWARE

2.1 CPU

■ Exceptions

In the F²MC-16L, exceptions are generated and exception processing is executed in response to the

causes described below.

(1) Execution of undefined instruction

Exception processing is basically the same as an interrupt. When the occurrence of an exception is

detected between instructions, normal processing is exited and exception processing is performed.

Generally, exception processing occurs as a result of an unforeseen operation, and should only be used

for debugging and for starting up recovery software in an emergency.

■ Generation of an exception by execution of an undefined instruction

In the F²MC-16L, any code that is not defined in the instruction map is treated as an undefined

instruction. If an undefined instruction is executed, processing that is equivalent to software interrupt

instruction "INT 10" is executed. In other words, the contents of AL, AH, DPR, DTB, ADB, PCB, PC,

and PS are all saved to the system stack, and then processing branches to the routine indicated by the

vector for interrupt number 10. In addition, the I flag is cleared and the S flag is set. The value of the

PC that was saved in the stack is the address containing the undefined instruction. In the case of an

instruction code consisting of two bytes or more, the value of the PC that was saved to the stack is the

address containing the code that was identified as being undefined. Therefore, while it is possible to

use the RETI instruction to return from the interrupt, doing so is meaningless since the exception will

occur again.

49

2.2 Map

This section explains the MB90620 memory space, I/O space, and interrupt number assignments.

2.2.1 Memory Space

The MB90620 memory space is shown in Fig. 2.2.1.

Single chip

FFFFFFH

ROM area

Address #1

FF0000H

010000H

ROM area

(FF bank image)

Address #2

004000H

002000H

: Internal

: No access

Address #3

RAM

Registers

000100H

0000C0H

000000H

Peripherals

Model

Address #1

Address #2

008000H

Address #3

MB90622

FF8000^H

FF4000H

(FE0000H)

000780H

000900H

000D00H

MB90623

004000H

MB90W623

MB90V620

004000H

Fig. 2.2.1 Memory Space Assignment by Mode in the MB90620

50

Chapter 2: HARDWARE

2.2 Map

Although the ROM image of the FF bank is visible above the 00 bank, this is in order to use the C

compiler's small model effectively. Although the least-significant 16 bits will be the same, tables in ROM

can be referenced without the "far" specification in the pointer declaration.

Because the ROM area in the FF bank exceeds 48 Kbytes, the entire area cannot be shown in the 00 bank

image.

In the MB90V620, the image from FF4000^Hto FFFFFFH can be seen in the 00 bank, but FE0000H to

FF3FFF^Hcan only be seen in the FE and FF banks.

51

2.2 Map

2.2.2 I/O Map

The MB90620 I/O map is shown below.

Table 2.2.2 MB90620 I/O Map (1)

Address

000000^H

000001^H

000002^H

000003^H

000004^H

000005^H

000006^H

000007^H

Register

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Symbol Access

Resource name

Initial value

XXXXXXXX

-XXXXXXX

----XXXX

PDR0

PDR1

PDR2

PDR3

PDR4

PDR5

PDR6

PDR7

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

XXXXXXXX

000008^Hto

00000F^H

Reserved area (Note 3)

000010^H

000011^H

000012^H

000013^H

000014^H

000015^H

000016^H

000017^H

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

DDR0

DDR1

DDR2

DDR3

DDR4

DDR5

DDR6

DDR7

R/W

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

00000000

-0000000

----0000

00000000

000018^Hto

000019^H

Reserved area (Note 3)

Port 0 pull-up resistor set-

ting register

00001A^H

00001B^H

00001C^H

RDR0

RDR1

RDR2

R/W

Port 0

Port 1

Port 2

00000000

Port 1 pull-up resistor set-

ting register

Port 2 pull-up resistor set-

ting register

00001D^H

00001E^H

00001F^H

Analog input enable register

Clock output enable register

Reserved area (Note 3)

ADER

CKOT

R/W

A/D

----1111

----0000

Clock output (CKOT)

52

Chapter 2: HARDWARE

2.2 Map

Table 2.2.2 MB90620 I/O Map (2)

Address

000020H

000021^H

Register

Serial mode register

Serial control register

Symbol Access

Resource name

Initial value

00000000

SMR

SCR

R/W

00000100

UART

Serial input register/serial

output register

SIDR/

SODR

000022^H

R/W

XXXXXXXX

000023^H

000024^H

000025^H

000026^H

Serial status register

SSR

0001--00

----00000

Serial mode control status

register

SMCS

R/W

Extended I/O serial

interface

00000010

XXXXXXXX

Serial data register

SDR

R/W

Communications prescaler

register

000027^H

000028^H

000029^H

CDCR

UART, I/O serial

0---1111

00000000

Interrupt/DTP source regis-

ter

ENIR

EIRR

R/W

Interrupt/DTP enable regis-

ter

DTP/external interrupt

00002A^H

00002B^H

00002C^H

00002D^H

00002E^H

00002F^H

000030^H

000031^H

000032^H

000033^H

000034^H

000035^H

00000000

Request level setting regis-

ter

ELVR

R/W

00000000

ADCS0

ADCS1

ADCR0

ADCR1

00000000

AD control status register

AD data register

R/W

00000000

8-/10-bit A/D con-

verter

XXXXXXXX

000000XX

XXXXXXXX

00000000

Periodic setting register

Duty setting register

PCSR0

PDUT0

W

16-bit PPG timer 0

PCNL0

PCNH0

Control status register

Reserved area (Note 3)

R/W

0000000-

000036^Hto

000037^H

53

2.2 Map

Table 2.2.2 MB90620 I/O Map (3)

Address

Register

Symbol Access

Resource name

Initial value

XXXXXXXX

00000000

000038H

000039^H

00003A^H

00003B^H

00003C^H

00003D^H

Periodic setting register

PCSR1

PDUT1

W

Duty setting register

16-bit PPG timer 1

PCNL1

PCNH1

Control status register

Reserved area (Note 3)

Control status register

R/W

0000000

00003E^H

to 00003F^H

000040^H

000041^H

000042^H

000043^H

000044^H

000045^H

000046^H

000047^H

000048^H

000049^H

00004A^H

00004B^H

00000000

----0000

TMCSR0

TMR0

R/W

XXXXXXXX

00000000

16-bit timer register

16-bit reload register

Control status register

16-bit timer register

16-bit reload timer 0

TMRLR0

TMCSR1

TMR1

----0000

XXXXXXXX

16-bit reload timer 1

16-bit reload register

Reserved area (Note 3)

Control status register

TMRLR1

00004C^H

to 00004F^H

000050^H

000051^H

000052^H

000053^H

000054^H

000055^H

00000000

----0000

TMCSR2

TMR2

R/W

XXXXXXXX

16-bit timer register

16-bit reload register

16-bit reload timer 2

TMRLR2

54

Chapter 2: HARDWARE

2.2 Map

Table 2.2.2 MB90620 I/O Map (4)

Address

000056H

000057^H

000058^H

000059^H

00005A^H

00005B^H

00005C^H

00005D^H

00005E^H

00005F^H

000060^H

000061^H

000062^H

000063^H

000064^H

000065^H

000066^H

000067^H

Register

Symbol Access

Resource name

Initial value

00000000

Timer data register

TCDT0

R

16-bit free-run timer 0 00000000

Control status register

TCS0

CCS0

R/W

00000000

0000--00

XXXXXXXX

Compare register 0

Compare register 1

TCRL0

TCRH0

R/W

Compare

register block

Reserved area (Note 3)

00000000

Timer data register

TCDT1

R

16-bit free-run timer 1 00000000

Control status register

TCS1

CCS1

R/W

00000000

0000--00

XXXXXXXX

Compare register 0

Compare register 1

TCRL1

TCRH1

R/W

Compare

register block

XXXXXXXX

000068^Hto

00006F^H

XXXXXXXX

00010000

000070H to

00007F^H

Display data RAM

VRAM

R/W

LCD controller/driver

000080^H

000081^H

LCR0

LCR1

Control status register

0--00000

000082^Hto

00008F^H

Reserved area (Note 3)

System reserved area

000090^Hto

00009E^H

Note 1

R/W

Delayed interrupt source

generation/release register

Delayed interrupt gen-

eration module

00009F^H

DIRR

-------0

55

2.2 Map

Table 2.2.2 MB90620 I/O Map (5)

Address

Register

Symbol Access

Resource name

Initial value

Low power consumption

mode control register

Low power consump-

tion

0000A0H

0000A1^H

LPMCR

CKSCR

R/W

00011000

Low power consump-

tion

Clock selection register

Reserved area (Note 3)

11111100

0000A2^H

to 0000A7^H

Watchdog timer control reg-

ister

0000A8^H

0000A9^H

0000AA^H

WDTC

TBTC

WTC

R/W

Watchdog timer

Timebase timer

Timeclock timer

XXXXXXXX

1--00000

Timebase timer control reg-

ister

Timeclock timer control

register

1X-00000

0000AB^H

to 0000AF^H

Reserved area (Note 3)

0000B0^H

0000B1^H

0000B2^H

0000B3^H

0000B4^H

0000B5^H

0000B6^H

0000B7^H

0000B8^H

0000B9^H

Timeclock timer 00

Timeclock timer 01

Timeclock timer 02

Timeclock timer 03

Timeclock timer 04

Timeclock timer 05

Timeclock timer 06

Timeclock timer 07

Timeclock timer 08

Timeclock timer 09

ICR00

ICR01

ICR02

ICR03

ICR04

ICR05

ICR06

ICR07

ICR08

ICR09

ICR10

ICR11

ICR12

ICR13

ICR14

ICR15

R/W

00000111

Interrupt controller

0000BA^HTimeclock timer 10

0000BB^HTimeclock timer 11

0000BC^HTimeclock timer 12

0000BD^HTimeclock timer 13

0000BE^HTimeclock timer 14

0000BF^H

Timeclock timer 15

0000C0^H

to 0000FF^H

External area (Note 2)

56

Chapter 2: HARDWARE

2.2 Map

Note1: Access prohibited.

Note2: This is the only area below address 0000FFH that is an external access area. Accesses to these

addresses are handled as accesses to an external I/O area.

Note3: Do not access registers indicated as reserved areas on the I/O map.

Note4: Only bit 15 can be written. Writes to other bits are used as a test function. If bits 10 to 15 are read,

"0" is returned.

Explanation of initial values:

0:

1:

The initial value of this bit is "0".

The initial value of this bit is "1".

X: The initial value of this bit is undecided.

-: This bit is unused. The initial value is undecided.

57

2.2 Map

2.2.3 Interrupt Vector Assignments

The interrupt vector assignments in the MB90620 are shown below.

Table 2.2.3 MB90620 Interrupt Vector Assignment Table

Interrupt control

register

I²OS

support

Interrupt vector

Number Address

Interrupt source

ICR

Address

Reset

×

#08

#09

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#35

#36

#37

#39

#42

08H

09H

0AH

0B^H

0CH

0DH

0EH

0FH

10H

11H

12H

13H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

23H

24H

25H

27H

2AH

FFFFDCH

FFFFD8H

FFFFD4H

FFFFD0H

FFFFCCH

FFFFC8H

FFFFC4H

FFFFC0H

FFFFBCH

FFFFB8H

FFFFB4H

–

INT 9 instruction

Exception

External interrupt #0

ICR00

ICR01

ICR02

ICR03

0000B0H

0000B1H

0000B2H

External interrupt #1

External interrupt #2

External interrupt #3

External interrupt #4

External interrupt #5

External interrupt #6

0000B3H

0000B4H

0000B5H

External interrupt #7

Extended I/O serial interface

Free-run timer 0 overflow

Free-run timer 1 overflow

Free-run timer 0 compare register 0 match

Free-run timer 0 compare register 1 match

Free-run timer 1 compare register 0 match

Free-run timer 1 compare register 1 match

PPG timer #0

FFFFB0H ICR04

FFFFA8H

ICR05

FFFFA4H

FFFFA0H

ICR06

0000B6H

0000B7H

0000B8H

0000B9H

0000BAH

FFFF9CH

FFFF98H

ICR07

FFFF94H

FFFF90H

ICR08

PPG timer #1

FFFF8CH

16-bit reload timer #0

FFFF88H

ICR09

16-bit reload timer #1

FFFF84H

16-bit reload timer #2

FFFF80H

ICR10

Wakeup interrupt

FFFF7CH

A/D converter measurement complete

Timeclock prescaler

FFFF78H

FFFF70H

ICR11

ICR12

0000BBH

0000BCH

0000BDH

0000BEH

0000BFH

×

Timebase timer interval interrupt

UART transmission end

UART reception end

FFFF6CH ICR12

FFFF68H

FFFF60H

FFFF54H

ICR13

ICR14

ICR15

Delayed interrupt generation module

×

Note:

indicates support for I²OS (no stop request),

indicates I²OS support (with stop request), ×

indicates no I²OS support. Do not make the I²OS startup settings for ICRxx if I²OS is not

supported.

58

Chapter 2: HARDWARE

2.3 Parallel Ports

The MB90620 Series has 59 I/O pins.

The 24 I/O ports in ports 0 to 2 permit the setting of the input pull-up resistor; the pull-up resistor is applied

when in the input state by setting the resistor setting register.

P45, P46, and ports 6 and 7 are open drain ports that also serve as the LCD segment pins.

2.3.1 Register List

Port data register

15

14

13

12

11

10

9

8

Ü Bit no.

î

í

ì

Address : PDR1 000001H

PDR3 000003H

PDR

PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

PDR5 000005H

PDR7 000007H

Read/writeÞ

Initial valueÞ

(X)

Port data register

7

6

5

4

3

2

1

0

î

Ü Bit no.

Address : PDR0 000000H

PDR2 000002H

í

PDR

ì

PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

PDR4 000004H

PDR6 000006H

Read/writeÞ

Initial valueÞ

(X)

Note: There is no register bit for bit 7 of port 4.

There are no register bits for bits 4 to 7 of port 5.

Port direction register

15

14

13

12

11

10

9

8

Ü Bit no.

î

í

ì

Address : DDR1 000011H

DDR3 000013H

DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

DDR5 000015H

DDR7 000017H

Read/write Þ

Initial value Þ

(0)

Port direction register

î

í

ì

7

6

5

4

3

2

1

0

Ü Bit no.

Address : DDR0 000010H

DDR2 000012H

DDR

DDR4 000014H

DDR6 000016H

DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/write Þ

Initial value Þ

(0)

Note: There is no register bit for bit 7 of port 4.

There are no register bits for bits 4 to 7 of port 5.

Analog input enable register

Address : ADER 00001DH

15

14

13

12

11

10

9

8

Ü Bit no.

ADE3 ADE2 ADE1 ADE0

–

ADER

(R/W) (R/W) (R/W) (R/W)

(1)

Read/write Þ

Initial value Þ

–

(1)

59

2.3 Parallel Ports

2.3.2 Block Diagrams

■ Input/output ports

Internal data bus

Data register read

Data register

Data register write

Direction register

Direction register write

Direction register read

Fig. 2.3.1 Input/Output Port Block Diagram

■ Open-drain ports

Internal data bus

RMW

(Read-modify-write instruction)

Data register read

Data register

Data register write

Fig. 2.3.2 Open Drain Port Block Diagram

■ Ports also used by the A/D converter

Internal data bus

RMW

(read-modify-write instruction)

Data register read

Data register

Data register write

Direction register

A D E R

Direction register write

ADER register write

ADER register read

Fig. 2.3.3 Block Diagram of Ports Also Used by A/D Converter

60

Chapter 2: HARDWARE

2.3 Parallel Ports

2.3.3 Explanation of Register Details

(1) Port data registers (PDR0, 1, 2, 3, 4, 5)

■ Register arrangement

Port data register

15

14

13

12

11

10

9

8

Ü Bit no.

î

í

ì

Address : PDR1 000001H

PDR3 000003H

PDR

PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

PDR5 000005H

PDR7 000007H

Read/writeÞ

Initial valueÞ

(X)

Port data register

7

6

5

4

3

2

1

0

î

Ü Bit no.

Address : PDR0 000000H

PDR2 000002H

í

ì

PDR

PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

PDR4 000004H

PDR6 000006H

Read/writeÞ

Initial valueÞ

(X)

Note: There is no register bit for bit 7 of port 4.

There are no register bits for bits 4 to 7 of port 5.

■ Register contents

When the corresponding peripheral is not set to use the output pins, each pin of a port can be

individually specified as an input or output according to the direction register settings. When specified

as an input, whenever the data register is read, the value is read according to the pin level; when

specified as an output, if the data register is read, the latched value is read. This also applied to the read

portion of read-modify-write instructions.

If the data register is read while the pin is used as a control output, the level output as the control output

is read, regardless of the setting of the direction register.

Note: If this register is accessed using a read-modify-write instruction (a bit set instruction, etc.), the

bit that is the target of the instruction becomes the prescribed value, but the contents of the

output register are overwritten with the current input value of the corresponding pin for other

bits that are set for input. Therefore, when switching to output a pin that was used for input, first

write the desired value to the PDR and then set the DDR to switch the pin to output.

Note: The operation for reading/writing ports differs from the operation for reading/writing memory;

port reads/writes are as follows:

Input mode

Reads:

The read data is the level of the corresponding pin.

Writes: The write data is stored in the output latch. The data is not output to the pin.

Output mode

Reads:

The read data is the value stored in the PDR.

Writes: The write data is stored in the output latch and is output to the pin.

The pins of port 5 (P53 to P50) are also used as analog input pins. When used as a general-purpose

ports, be certain to set the corresponding bits in the ADER to "0".

When a pin corresponding to a bit set to "1" in the analog input enable register is read, "0" is read.

61

2.3 Parallel Ports

(2) Port direction registers (DDR0, 1, 2, 3, 4, 5, 6, 7)

■ Register arrangement

Port direction register

15

14

13

12

11

10

9

8

Ü Bit no.

î

í

ì

Address : DDR1 000011H

DDR3 000013H

DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

DDR5 000015H

DDR7 000017H

Read/write Þ

Initial value Þ

(0)

Port direction register

î

í

ì

7

6

5

4

3

2

1

0

Ü Bit no.

Address : DDR0 000010H

DDR2 000012H

DDR

DDR4 000014H

DDR6 000016H

DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/write Þ

Initial value Þ

(0)

Note: There is no register bit for bit 7 of port 4.

There are no register bits for bits 4 to 7 of port 5.

■ Register contents

When an individual pin functions as a port, the corresponding pin is controlled as follows:

0: Input mode

1: Output mode

These bits are set to "0" by a reset.

62

Chapter 2: HARDWARE

2.3 Parallel Ports

(3) Pull-up resistor setting register (RDR0, RDR1, RDR2)

■ Register arrangement

Pull-up data register

15

14

13

12

11

10

9

8

Ü Bit no.

Address :RDR1 00001BH

RDx7 RDx6 RDx5 RDx4 RDx3 RDx2 RDx1 RDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

RDR

Read/write Þ

Initial value Þ

(0)

Pull-up data register

7

6

5

4

3

2

1

0

Ü Bit no.

Address : RDR0 00001AH

RDR2 00001CH

RDR

RDx7 RDx6 RDx5 RDx4 RDx3 RDx2 RDx1 RDx0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/write Þ

Initial value Þ

(0)

Pull-up resistor (approximately 50 kW)

Port input/output

Data register

Direction register

Resistor register

Bus

Fig. 2.3.4 Block Diagram

* Input resistor register R/W

Controls the pull-up resistor in input mode.

0: No pull-up resistor in input mode.

1: Pull-up resistor in input mode.

This register has no meaning in output mode. (No pull-up resistors.)

* When stopped (SPL = 1), the no pull-up resistor setting is in effect, regardless of the value of this

register. (The pins go to high impedance.)

* This function is prohibited when the device is used with an external bus. Do not write to this register.

63

2.3 Parallel Ports

(4) Analog input enable register (ADER)

Analog input enable register

Address : ADER 00001DH

Read/write Þ

Initial value Þ

15

14

13

12

11

10

9

8

Ü Bit no.

ADE3 ADE2 ADE1 ADE0

–

ADER

(R/W) (R/W) (R/W) (R/W)

(1)

–

(1)

■ Register contents

Each pin of port 5 is controlled as follows:

0: Port input/output mode

1: Analog input mode

These bits are set to "1" by a reset. To use as a pin as a port, set the corresponding bit to "0".

64

Chapter 2: HARDWARE

2.3 Parallel Ports

2.3.4 Port Pin Assignments

In the MB90620 Series, ports 0 to 3 share pins with the external bus. The function of the pins can be

selected according to the bus mode and the register settings. Table 2.3.1 shows the assignment of the port

pins in each mode.

Table 2.3.1 Port Pin Assignment in Each Mode

Function

Pin name

External bus extension

EPROM writing

Single chip

8 bits

16 bits

P07 to P00

P17 to P10

P23 to P20

P27 to P24

P30

AD07 to AD00

D07 to D00

A15 to A08

A03 to A00

A07 to A04

A16

A15 to A08

AD15 to AD08

A19 to A16

ALE

RDX

P31

CEX

Port

P32

WRX

WRLX

WRHX

OEX

P33

P34

HRQ

HAKX

RDY

P35

Not used

P36

P37

CLK

Note: The upper address bits and WRX, WRLX, WRHX, HAKX, HRQ, RDY, and CLK can be used as

ports, depending on the function selection.

65

2.4 UART

UART is a serial I/O port used for asynchronous (start-stop synchronization) communications and CLK

synchronized communications that has the following features:

•

Full-duplex double buffer

Permits asynchronous (start-stop synchronization) communications and CLK synchronized

communications

•

Support for multiprocessor mode

Internal dedicated baud rate generator

Asynchronous: 9615/ 31250/ 4808/ 2404/ and 1202 bps

CLK synchronization: IM, 500K, 250K,125K, 62.5K bps

î

í

ì

(internal machine clock: 6, 8, 10, 12, or 16 MHz)

•

Baud rate can be set freely when using an external clock

Error detection function (parity, framing, overrun)

NRZ encoding for transfer signals

Intelligent I/O service support

2.4.1 Register List

15

8

7

0

–

CDCR

SCR

SSR

8bit

(R/W)

SMR

SIDR(R)/SODR(W)

8bit

(R/W)

7

6

5

4

3

2

1

0

Serial mode register

(SMR)

Reserved

MD1 MD0 CS2 CS1 CS0

SCKE SOE

Address : 000020H

Address : 000021H

Address : 000022H

Address : 000023H

Address : 000027H

15

14

P

13

12

11

10

9

8

Serial control register

(SCR)

PEN

SBL CL

A/D REC RXE TXE

7

6

5

4

3

2

1

0

Serial input register 1

Serial output register

(SIDR/SODR)

D7

D6

D5

D4

D3

D2

D1

D0

15

14

13

12

11

10

–

9

8

Serial status register

(SSR)

PE ORE FRE RDRF TDRE

RIE TIE

15

14

–

13

–

12

–

11

10

9

8

Communications prescaler

control register

MD

DIV3 DIV2 DIV1 DIV0

(CDCR)

66

Chapter 2: HARDWARE

2.4 UART

2.4.2 Block Diagram

Control signals

Reception interrupt

(to CPU)

Dedicated baud

rate generator

SCK0

Transmission clock

Clock

selection

circuit

Transmission

interrupt

(to CPU)

16-bit timer 0

(internal connection)

External clock

Reception clock

Reception control circuit

Transmission control circuit

SINO

Start bit detection circuit

Reception bit counter

Reception parity counter

Transmission start circuit

Transmission bit counter

Transmission parity counter

SOT0

Reception status evaluation circuit

Reception shifter

Transmission shifter

Reception end

SIDR

transmission

Start

SODR

2

I OS reception error

generation signal (to CPU)

FFMC-16 BUS

MD1

MD0

CS2

CS1

CS0

PEN

P

SBL

PE

ORE

FRE

RDRF

TDRE

SMR

register

SCR

register

SSR

register

CL

A/D

REC

RXE

TXE

SCKE

SOE

RIE

TIE

Control signals

Fig. 2.4.1 Overall Block Diagram

67

2.4 UART

2.4.3 Explanation of Register Details

(1) Serial mode register (SMR)

7

6

5

4

3

2

1

0

Initial value

00000000B

SMR

Address : 000020H

Reserved

MD1 MD0 CS2 CS1 CS0

SCKE SOE

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

The SMR specifies the UART operation mode. The operation mode is set while operation is halted; do not

write to this register while in operation.

[Bits 7, 6] MD1, MD0 (Mode select):

These bits select the UART operation mode.

Table 2.4.1 Operation Mode Selection

Mode

MD1

MD0

Operation mode

Asynchronous (start-stop synchronization) normal mode

Asynchronous (start-stop synchronization) multiprocessor mode

CLK synchronization mode

0

1

2

–

0

1

0

1

0

1

Setting prohibited

Note: Mode 1, the CLK asynchronous mode (multiprocessor), is used when multiple slave CPUs

are connected to one host CPU. With this resource, the data format of reception data cannot

be determined. As a result, only the master multiprocessor mode is supported.

In addition, because the parity check function cannot be used, set PEN in the SCR register to

"0".

[Bits 5 to 3] CS2, CS1, CS0 (Clock Select):

These bits select the baud rate clock source. When the dedicated baud rate generator is selected, the

baud rate is determined simultaneously.

Table 2.4.2 Clock Input Selection

CS2 to CS0

000^Bto 100B

101^B

Clock input

Dedicated baud rate generator

Reserved

110^B

Internal timer

111^B

External clock

Note: When the internal timer is selected, in the MB90620 Series, timer 0 (of the three 16-bit

timers) is selected.

[Bit 2] Reserved bit

Be sure to always write "0" to this bit.

68

Chapter 2: HARDWARE

2.4 UART

[Bit 1] SCKE (SCLK Enable):

This bit specifies whether to use the SCK0 pin as the clock input pin or as the clock output pin when

performing communications in CLK synchronization mode (mode 2).

Set this pin to "0" in CLK asynchronous mode or external clock mode.

0: Functions as clock input pin.

1: Functions as clock output pin

Note: When the SCK0 pin is used as a clock input pin, the external clock source must be selected.

[Bit 0] SOE (Serial Output Enable):

This bit specifies whether to use the external pin (SOT0), which also serves as a general-purpose I/O

port, as either a serial output pin or as an I/O port pin.

0: Functions as a general-purpose I/O port pin.

1: Functions as a serial data output pin (SOT0).

(2) Serial control register (SCR)

15

14

P

13

12

11

10

9

8

Initial value

00000100B

SCR

Address : 000021H

PEN

SBL CL

A/D REC RXE TXE

(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W)

SCR controls the transfer protocol when performing serial communications.

[Bit 15] PEN (Parity Enable)

This bit specifies whether or not to use parity checking in serial communications.

0: Parity off

1: Parity on

Note: Parity checking can only be used with the normal mode in the asynchronous (start-stop

synchronization) communications mode (mode 0). Parity checking cannot be used in

multiprocessor mode (mode 1) and CLK synchronized communications (mode 2).

[Bit 14] P (Parity):

This bit specifies either odd or even parity when using parity checking for data communications.

0: Even parity

1: Odd parity

[Bit 13] SBL (Stop Bit Length):

This bit specifies the number of stop bits, which are used to mark the end of a frame in asynchronous

(start-stop synchronization) communications.

0: One stop bit

1: Two stop bits

69

2.4 UART

[Bit 12] CL (Character Length):

This bit specifies the data length of one frame for transmission or reception.

0: 7-bit data

1: 8-bit data

Note: 7-bit data can only be used with the normal mode in the asynchronous (start-stop

synchronization) communications mode (mode 0). Use 8-bit data in multiprocessor mode

(mode 1) and CLK synchronized communications (mode 2).

[Bit 11] A/D (Address/Data):

This bit specifies the data format for transmission/reception frames in multiprocessor mode (mode

1) during asynchronous (start-stop) communications.

0: Data frame

1: Address frame

[Bit 10] REC (Receiver Error Clear):

This bit clears the error flags (PE, ORE, and FRE) in the SSR register.

Writing a "1" is invalid, and the value read from this bit is always "1".

[Bit 9] RXE (Receiver Enable):

This bit controls the UART receive operation.

0: Receive operation prohibited.

1: Receive operation enabled.

Note: If the receive operation is disabled (prohibited) in the midst of a reception (while data is

being input to the reception shift register), receive of that frame is completed, and then the

receive operation is halted once the receive data is stored in the SIDR register of the receive

data buffer.

[Bit 8] TXE (Transmitter Enable):

This bit controls the UART transmit operation.

0: Transmit operation disabled.

1: Transmit operation enabled.

Note: If the transmit operation is disabled (prohibited) in the midst of a transmission (while data is

being output from the transmit register), the transmit operation is halted once the data stored

in the SODR register of the transmit data buffer has all been output.

70

Chapter 2: HARDWARE

2.4 UART

(3) Serial input data register (SIDR)

Serial output data register (SODR)

7

6

5

4

3

2

1

0

Initial value

Undecided

SIDR

Address : 000022H

D7

D6

D5

D4

D3

D2

D1

D0

R

7

6

5

4

3

2

1

0

Initial value

Undecided

SODR

Address : 000022H

D7

D6

D5

D4

D3

D2

D1

D0

W

These registers are data buffer registers for transmit/receive.

When the data length is 7 bits, the upper bit (D7) becomes invalid data. Write to the SODR register

when TDRE in the SSR register is "1".

Note: Writes to this address are writes to the SODR register, while reading this address reads the SIDR

register.

(4) Serial status register (SSR)

15

14

13

12

11

10

9

8

Initial value

00001-00B

SSR

PE ORE FRE RDRF TDRE

RIE TIE

–

Address : 000023H

R

R/W R/W

The SSR consists of flags that indicate the UART operating state.

[Bit 15] PE (Parity Error):

This bit is an interrupt request flag that is set when a parity error occurs during reception.

To clear the flag once it has been set, write a "0" to the REC bit (bit 10) in the SCR register.

When this bit has been set, the SIDR data becomes invalid.

0: No parity error

1: Parity error

[Bit 14] ORE (Overrun Error):

This bit is an interrupt request flag that is set when an overrun error occurs during reception.

To clear the flag once it has been set, write a "0" to the REC bit (bit 10) in the SCR register.

When this bit has been set, the SIDR data becomes invalid.

0: No overrun error

1: Overrun error

71

2.4 UART

[Bit 13] FRE (Framing Error):

This bit is an interrupt request flag that is set when a framing error occurs during reception.

To clear the flag once it has been set, write a "0" to the REC bit (bit 10) in the SCR register.

When this bit has been set, the SIDR data becomes invalid.

0: No framing error

1: Framing error

[Bit 12] RDRF (Receiver Data Register Full):

This bit is an interrupt request flag that indicates that there is reception data in the SIDR register.

This flag is set when reception data is loaded in the SIDR register, and is cleared automatically when

the SIDR register is read.

0: No reception data

1: Reception data

[Bit 11] TDRE (Transmitter Data Register Empty):

This bit is an interrupt request flag that indicates transmit data can be written to the SODR.

This flag is cleared when transmit data is written to the SODR register. When the data that was

written to the SODR register is loaded into the transmission shifter and transfer begins, this flag is

set again, indicating that the next transmit data can be written to the register.

0: Writing of transmit data disabled

1: Writing of transmit data enabled

[Bit 9] RIE (Receiver Interrupt Enable):

This bit controls reception interrupts.

0: Interrupts disabled.

1: Interrupts enabled.

Note: In addition to errors generated by PE, ORE, and FRE, normal reception by RDRF is the source

of reception interrupts.

[Bit 8] TIE (Transmitter Interrupt Enable):

This bit controls transmission interrupts.

0: Interrupts disabled.

1: Interrupts enabled.

Note: A transmission request by TDRE is the source of transmission interrupts.

72

Chapter 2: HARDWARE

2.4 UART

(5) Transmission prescaler control register (CDCR)

15

14

13

12

11

10

9

8

Initial value

0---1111B

CDCR

Address : 000027H

MD

DIV3 DIV2 DIV1 DIV0

R/W R/W R/W R/W

–

R/W

The UART operation clock is derived from the machine clock being divided. This communications

prescaler allows a constant baud rate from various machine clocks. The CDCR register controls the

division of the machine clock.

[Bit 15] MD (Machine Clock Divide Mode Select):

This bit enables the operation of the communications prescaler.

0: The communications prescaler is stopped.

1: The communications prescaler is in operation.

[Bits 11, 10, 9, 8] DIV3-DIV0 (Divide 3 to 0):

These bits determine the machine clock division ratio.

Table 2.4.3 Machine Clock Division Ratio

DIV3 to DIV0

1101^B

Division ratio

3 divisions

4 divisions

5 divisions

6 divisions

8 divisions

1100^B

1011^B

1010^B

1001^B

Note: If the division ratio is changed, wait for two cycles to allow for clock stabilization before

beginning communications.

The output from this communications prescaler is also used as the operation clock for the extended

I/O serial interface.

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2.4 UART

2.4.4 Explanation of Operation

(1) Operation mode

UART has the operation modes shown in Table 2.4.4; the mode can be switched by setting the

appropriate value in the SMR register and the SCR register.

Table 2.4.4 UART Operation Modes

Data

Mode

Parity

Operation mode

Stop bit length

length

On/off

7

8

Asynchronous (start-stop synchronization);

normal mode

0

one bit or two bits

None

Asynchronous (start-stop synchronization);

multiprocessor mode

1

2

Off

8 + 1

8

CLK synchronized mode

However, in asynchronous (start-stop synchronization) mode, the stop bit length can only be specified

for the transmit operation. The number of stop bits is always one bit for the receive operation. Because

the stop bits are not used in any other mode, do not set them.

(2) UART clock selection

a) Dedicated baud rate generator

When the dedicated baud rate generator is selected, the baud rate is determined as follows:

Table 2.4.5 Baud Rates (f : machine clock)

In asynchronous mode

(start-stop synchronization)

CS2

CS1

CS0

Formula

0

1

0

1

0

1

0

1

0

9615

4808

2404

1202

31250

(f ÷ div)/(8 × 13 × 2)

(f ÷ div)/(8 × 13 × 2²)

(f ÷ div)/(8 × 13 × 2³)

(f ÷ div)/(8 × 13 × 2⁴)

(f ÷ div)/2⁶

CS2

CS1

CS0

In CLK synchronized mode

Formula

0

1

0

1

0

1

0

1

0

1 M

(f ÷ div)/2

(f ÷ div)/2²

(f ÷ div)/2³

(f ÷ div)/2⁴

(f ÷ div)/2⁵

500 K

250 K

125 K

62.5 K

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Chapter 2: HARDWARE

2.4 UART

Communications prescaler settings

MD

1

DIV3

DIV2

DIV1

DIV0

div

3

Recommended machine clock

1

0

1

0

1

0

1

0

6 MHz

8 MHz

1

4

1

5

10 MHz

12 MHz

16 MHz

1

6

1

8

b) Internal timer

When CS2 to CS0 are set to "110" and the internal timer is selected, the 16-bit timer (timer 0)

operates in reload mode. In this case, the baud rate formulas are as follows:

Asynchronous mode (start-stop synchronization): (f ¸ N)/(16 × 2 × (n + 1))

CLK synchronized mode:

N: Timer count clock source

n: Timer reload value

(f ¸ N)/(2 × (n + 1))

Fig. 2.4.6 shows the relationship between the baud rate and the reload value (decimal value) when

the machine clock is 7.3728 MHz.

Table 2.4.6 Baud Rates and Reload Values

N = 2¹

N = 2³

Reload value

Baud rate

(divide-by-2 output from machine clock) (divide-by-8 output from machine clock)

38400

19200

9600

4800

2400

1200

600

2

5

–

11

23

47

95

191

383

2

5

11

23

47

95

300

When an internal timer (16-bit timer 0) is selected as the baud rate clock source, the 16-bit timer 0

output TOUT0 is already connected within this controller. Therefore, there is no need to externally

connect the 16-bit timer 0 external pin TOT0 to the UART external clock input pin SCK0. In

addition, as long as the timer 0 output pin is not used for another purpose, it can be used as an I/O

port pin.

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2.4 UART

c) External clock

When CS2 to CS0 are set to "111" and the external clock is selected, the baud rate is as follows,

assuming the frequency of the external clock as "f":

Asynchronous mode (start-stop synchronization):

CLK synchronized mode:

f/16

f

However, the maximum for "f" is 1 MHz.

(3) Asynchronous (start-stop synchronization) mode

a) Transfer data format

UART only handles data in NRZ (Non Return to Zero) format. Fig. 2.4.2 shows the data format.

SIN0,SOT0

0

1

0

1

0

1

0

1

Start LSB

MSB Stop........(Mode 0)

A/D Stop........(Mode 1)

The transferred data is 01001101B

Fig. 2.4.2 Transfer Data Format (Mode 0, 1)

As shown in Fig. 2.4.2, the transfer data always starts with a start bit (low level data), followed by an

LSB-first transfer of the specified data bit length, and then ends with a stop bit (high level data).

When the external clock is selected, input the clock continuously.

In normal mode (mode 0), it is possible to set the data length as 7 bits or 8 bits, but in multiprocessor

mode (mode 1), the data length must be 8 bits. In addition, it is not possible to add a parity bit in

multiprocessor mode. On the other hand, an A/D bit is always added.

b) Receive operation

Whenever the RXE bit (bit 9) in the SCR register is "1", the receive operation is being performed.

If the start bit appears on the reception line, one frame of data is received according to the data

format determined by the SCR register. Once one frame is received, then if an error occurred, the

error flag is set, and then the RDRF flag (bit 12 of the SSR register) is set. In this case, if the RIE bit

(bit 9) of the SSR register is set to "1", a reception interrupt is sent to the CPU. The CPU should

check each flag in the SSR register, and if reception was completed normally, the CPU should then

read the SIDR register; if an error occurred, the CPU should perform the necessary processing.

The RDRF flag and the SIDR register are cleared when they are read.

c) Transmit operation

Whenever the TDRE flag (bit 11) of the SSR register is "1", transmit data is written into the SODR

register. Then, if the TXE bit (bit 8) of the SCR register is "1", the data is sent.

Once the data that was set in the SODR register is loaded into the transmission shift register and

transmission is started, the TDRE flag is set again so that the next transmit data can be set in the

SODR register. In this case, if the TIE bit (bit 8) of the SSR register is set to "1", a transmission

interrupt is sent to the CPU, requesting that the transmit data be set in the SODR register.

The TDRE flag is cleared once the data is set in the SODR register.

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2.4 UART

(4) CLK synchronization mode

a) Transfer data format

UART only handles data in NRZ (Non Return to Zero) format. Fig. 2.4.3 shows the relationship

between the transmit/receive clock and the data.

SODR

Mark

SCLK

RXE,TXE

SIN0,SOT0

1

0

1

0

1

0

LSB

MSB...................(Mode 2)

The transferred data is 01001101B

Fig. 2.4.3 Transfer Data Format (Mode 2)

When the internal clock (dedicated baud rate generator or internal timer) is selected, the data receive

synchronization clock is generated automatically once the data is transmitted.

When the external clock is selected, after confirming that there is data in the UART transmit data

buffer SODR register on the transmission side (the TDRE flag is "0"), it is necessary to accurately

supply the clock signal for one byte. In addition, the clock signal must be kept at the mark level

before the start and after completion of transmission.

The data bit length can only be 8 bits, and a parity bit cannot be added. In addition, because there is

not start or stop bit, no errors other than overrun errors are detected.

b) Initialization

The settings for each control register when using the CLK synchronized mode are shown below.

(1) SMR register

MD1, MD0:

CS2, CS1, CS0:

SCKE:

10

Specify clock input

For dedicated baud rate generator or internal timer: 1

For external clock: 0

SOE:

(2) SCR register

PEN:

Transmission: 1; reception only: 0

0

P, SBL, A/D:

These bits have no meaning in this instance.

CL:

REC:

1

0 (for initialization)

RXE, TXE:

(3) SSR register

RIE:

At least one or the other: 1

When using interrupts: 1; when not using interrupts: 0

0

TIE:

77

2.4 UART

c) Communications start

Communications are started by writing the data to the SODR register. Even for reception only, it is

necessary to write hypothetical transmission data to the SODR register.

d) Communications end

The end of communications can be confirmed when the RDRF flag in the SSR register changes to

"1". Use the ORE bit in the SSR register to determine whether communications were completed

normally.

(5) Timing of generation of interrupts and setting of flags

UART has five flags and two interrupt sources.

The five flags are: PE/ ORE/ FRE/ RDRF/ and TDRE. PE is used for parity errors, ORE is used for

overrun errors, and FRE is used for framing errors; these flags are set if the corresponding error occurs

during reception, and are cleared by writing "0" to the REC bit in the SCR register. RDRF is set when

the reception data is loaded into the SIDR register, and is cleared by reading the SIDR register. Note

that mode 1 does not have a parity detection function, and mode 2 does not have a parity detection

function and a framing error detection function. TDRE is set when the SODR register is empty and

ready for writing, and is cleared when the SODR register is written.

There are two interrupt sources: one for reception and one for transmission. During reception, an

interrupt is requested in response to PE/ ORE/ FRE, or RDRF. During transmission, an interrupt is

requested in response to TDRE. The timing by which the interrupt flags are set is shown below for

each of the operating modes.

a) Receive in mode 0

The PE, ORE, FRE, and RDRF flags are set when reception ends and the final stop bit is detected,

and then an interrupt request is sent to the CPU. If PE, ORE, or FRE is active, the data in the SIDR

becomes invalid data.

D6

D7

Stop

Data

PE,ORE,FRE

RDRF

Reception interrupt

Fig. 2.4.4 Timing for Setting ORE, FRE, and RDRF (Mode 0)

b) Receive in mode 1

The ORE, FRE, and RDRF flags are set when reception ends and the final stop bit is detected, and

then an interrupt request is sent to the CPU. In addition, because the data length that can be received

is 8 bits, the last, nineth bit indicating address/data becomes invalid data. If ORE or FRE is active,

the data in the SIDR becomes invalid data.

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Chapter 2: HARDWARE

2.4 UART

D7

Address/ data

Stop

Data

ORE,FRE

RDRF

Reception interrupt

Fig. 2.4.5 Timing for Setting ORE, FRE, and RDRF (Mode 1)

c) Receive in mode 2

The ORE and RDRF flags are set when reception ends and the final data (D7) is detected, and then

an interrupt request is sent to the CPU. If ORE is active, the data in the SIDR becomes invalid data.

D5

D6

D7

Data

ORE

RDRF

Reception interrupt

Fig. 2.4.6 Timing for Setting ORE and RDRF (Mode 2)

d) Transmit in mode 0, mode 1, and mode 2

TDRE is cleared when data is written to the SODR register, and is set when that data is transferred

to the internal shift register (so that the SODR register is ready for the next data to be written); an

interrupt request is then sent to the CPU. If a "0" is written to TXE (and RXE also, in mode 2) in the

SCR register during a transmit operation, TDRE in the SSR register changes to "1" and once the

transmission shifter halts operation, the UART transmit operation is disabled. If a "0" has been

written to TXE (and RXE also, in mode 2) in the SCR register during a transmit operation, the data

that was written to the SODR register is sent before transmission is stopped.

SODR write

TDRE

Interrupt request is sent to CPU

SOT0 interrupt

SOT0 output

ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3

A/D

ST: Start bit DO to D7: Data bits SP: Stop bit A/D: Address/data multiplexer

Fig. 2.4.7 Timing for Setting TDRE (Mode 0, 1)

79

2.4 UART

SODR write

TDRE

Interrupt request is sent to CPU

SOT0 interrupt

SOT0 output

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

DO to D7: Data bits

Fig. 2.4.8 Timing for Setting TDRE (Mode 2)

(6) I²OS (Intelligent I/O Service)

Refer to the section on the I²OS for details on the I²OS.

2.4.5 Notes on Use

Set the transmit mode while operation is stopped. Data that is transmitted or received when the mode is

being set is not guaranteed.

2.4.6 Application Example

Mode 1 is used when multiple slave CPUs are connected to a single host CPU (see Fig. 2.4.9). With these

resources, only the communications interface on the host side is supported.

SO

SI

Host CPU

SO

SI

SO

SI

Slave CPU #0

Slave CPU #1

Fig. 2.4.9 Sample System Configuration When Using Mode 1

Communications are started when the CPU sends the address data. "Address data" is data sent when A/D

in the SCR register is set to "1". After the address data is used to select the destination slave CPU,

communications with the host CPU are now possible. For normal data, A/D in the SCR register is set to

"0". Fig. 2.4.10 shows a flow chart for this operation.

Because the parity checking function cannot be used in this mode, set the PEN bit in the SCR register to

"0".

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Chapter 2: HARDWARE

2.4 UART

(Host CPU)

START

Set transfer mode to "1"

Set the data selecting the slave CPU in

D0 to D7, and set A/D to "1", and

transfer one byte

Set A/D to "0"

Enable the receive operation

Communications with the slave CPU

No

Are communications

completed?

Yes

No

Communicate with

another slave CPU?

Yes

Disable receive operation

END

Fig. 2.4.10 Communications Flow Chart When Using Mode 1

81

2.5 I/O Extended Serial Interface

This block is an 8-bit × 1-channel serial I/O interface that permits clock-synchronized data transfer. It is

possible to select either LSB first or MSB first for data transfers. It is also possible to switch the serial I/O

ports.

There are two serial I/O operation modes:

•

Internal shift clock mode:

External shift clock mode:

Data transfers are performed in sync with the internal clock.

Data transfers are made in sync with a clock input from the external

pin (SCK1). In this mode it is also possible to perform transfer

operations in accordance with instructions from the CPU by using

the general-purpose port that shares the external pin (SCK1).

2.5.1 Block Diagram

Internal data bus

(MSB first) D0 to D7

SIN1

D7 to D0 (LSB first)

Transfer direction selection

Read

Write

SDR (serial data register)

SOT1

SCK1

Control circuit

Shift clock counter

Internal clock

0

1

2

SMD2 SMD1 SMD0 SIE

SIR BUSY STOP STRT MODE BDS SOE SCOE

Interrupt

request

Internal data bus

Fig. 2.5.1 I/O Extended Serial Interface Block Diagram

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2.5 I/O Extended Serial Interface

2.5.2 Register List

15

14

13

12

11

10

9

8

SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT

Address : 000025H

Serial mode control status register

(SMCS)

7

–

6

–

5

–

4

–

3

2

1

0

MODE BDS SOE SCOE

Address : 000024H

Address : 000026H

7

6

5

4

3

2

1

0

Serial data register

(SDR)

D7

D6

D5

D4

D3

D2

D1

D0

2.5.3 Explanation of Register Details

(1) Serial mode control status register (SMCS)

15

14

13

12

11

10

9

8

SMCS

Address : 000025H

Initial value

000010B

SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT

R/W R/W R/W R/W R/W

R

R/W R/W

•

Note 1

Note 2

7

6

5

4

3

2

1

0

SMCS

Address : 000024H

Initial value

---00000B

–

MODE BDS SOE SCOE

R/W R/W

R/W

Note1: Note 1: Write operation is enabled for "0" only.

Note2: Note 2: Write operation is enabled for "1" only; read operation is enabled for "0" only.

This register is used to control the serial I/O transfer operation mode. The function of each bit is explained

below.

[Bits 15, 14, 13] Shift clock selection bits

(SMD2, SMD1, SMD0: Serial shift clock mode)

The serial shift clock mode can be selected as follows:

Table 2.5.1 Serial Shift Clock Mode Settings

SMD2 SMD1

SMD0

Shift clock mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f ÷ div ÷ 2

f ÷ div ÷ 4

f ÷ div ÷ 16

f ÷ div ÷ 32

f ÷ div ÷ 64

Internal shift clock mode

* Set the communications prescaler. The communications

prescaler is shared with UART.

f : machine clock div: Number of divisions

External shift clock mode

Reserved

83

2.5 I/O Extended Serial Interface

These bits are set to "000" by a reset. These bits can be read and written. Overwriting these bits is

prohibited while a transfer is in progress.

There are five internal shift clock modes and one external shift clock mode. SMD2, 1, 0 = "110" or

"111" are reserved settings; do not set these values.

Assuming SCOE = 0 by selecting the external shift clock, it is possible to perform a shift operation

for each instruction by using the port that shares the SCK1 pin.

Because this module has a separate prescaler, it is possible to change the clock frequency according

to the prescaler setting. Refer to the following table when setting the prescaler.

Communications prescaler (CDCR) settings

Communications prescaler register value

Recommended

machine cycles

div

MD

1

DIV3

DIV2

DIV1

DIV0

3

4

5

6

7

8

1

0

1

0

1

0

1

0

1

0

6 MHz

8 MHz

1

10 MHz

12 MHz

14 MHz

16 MHz

1

div: Number of divisions

Note that this prescaler is shared with UART.

Sample settings

•

f = 16 MHz

f = 8 MHz

div = 4

f = 4 MHz

div = 4

Register value

div = 8

SMD2 SMD1

SMD0

Internal shift clock

1 MHz

0

1

0

1

0

1

0

1

0

1 MHz

500 kHz

125 kHz

62.5 kHz

31.25 kHz

500 kHz

250 kHz

500 kHz

125 kHz

62.5 kHz

31.25 kHz

15.63 kHz

62.5 kHz

31.25 kHz

div: Set by the communications prescaler f : Machine cycles

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2.5 I/O Extended Serial Interface

[Bit 12] Serial I/O interrupt enable bit (SIE: Serial I/O Interrupt Enable)

This bit controls serial I/O interrupt requests as shown in the following table.

Table 2.5.2 Interrupt Request Enable Bit Settings

0

1

Serial I/O interrupts disabled [Initial value]

Serial I/O interrupts enabled

This bit is set to "0" by a reset. This bit can be read and written.

[Bit 11] Serial I/O interrupt request bit (SIR: Serial I/O Interrupt Request)

This bit is set to "1" when the serial data transfer is completed; if this bit is set to "1" while interrupts

are enabled (SIE = 1), an interrupt request is sent to the CPU. The conditions for clearing this bit

differ according to the MODE bit. When the MODE bit is "0", the SIR bit is cleared by writing "0"

to it. If the MODE bit is "1", this bit is cleared when the SDR is read or written. Regardless of the

value of the MODE bit, this bit is also cleared by a reset or by writing a "1" to the STOP bit.

Writing a "1" to this bit has no meaning. If read by a read-modify-write instruction, this bit is

always read as "1".

[Bit 10] Transfer status bit (BUSY)

This bit indicates whether a serial transfer is in progress or not.

Table 2.5.3 Transfer Status Bit Settings

BUSY

Operation

Stopped or serial data register R/W standby state [initial value]

Serial transfer status

0

1

This bit is set to "0" by a reset. This bit can only be read.

[Bit 9] Stop bit (STOP)

This bit forcibly interrupts a serial transfer. If this bit is set to "1", the device enters the "stopped by

STOP = 1" state.

Table 2.5.4 Stop Bit Settings

STOP

Operation

0

1

Normal operation

Transfer stopped by STOP = 1

[initial value]

[Bit 8] Start bit (STRT: Start)

This bit is used to start up serial transfers. A transfer is started by writing "1" to this bit while in the

stopped state. Writing "1" to this bit is ignored when a serial transfer operation is in progress and

when in the serial shift register R/W standby state. Writing "0" is always meaningless.

When this bit is read, it always returns a "0".

85

2.5 I/O Extended Serial Interface

[Bit 3] Serial mode selection bit (MODE)

This bit selects the conditions for starting up from the stopped state. This bit must not be

overwritten while a transfer is in progress.

Table 2.5.5 Serial Mode Selection Bit Settings

MODE

Operation

Start up when STRT is set to "1"

Start up when the serial data register is read/written

0

1

[initial value]

This bit is set to "0" by a reset. This bit can be read and written. When starting up the intelligent I/

O service, set this bit to "1".

[Bit 2] Transfer direction selection bit (BDS: Bit Direction Select)

This bit selects whether serial data I/O is to be executed starting from the lower bit first (LSB first)

or form the upper bit first (MSB first).

Table 2.5.6 Transfer Direction Selection Bit Settings

0

1

LSB first

MSB first

[initial value]

Note: Set the transfer direction before writing the data to the SDR register.

This bit is set to "0" by a reset. This bit can be read and written.

[Bit 1] Serial output enable bit (SOE: Serial Out Enable)

This bit controls output on the serial I/O output external pin (SOT1) as follows:

Table 2.5.7 Serial Output Enable Bit Settings

0

1

General-purpose port pin

Serial data output

[initial value]

This bit is set to "0" by a reset. This bit can be read and written.

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2.5 I/O Extended Serial Interface

[Bit 0] Shift clock (SCK1) output enable bit (SCOE)

This bit controls output from the shift clock I/O external pin (SCK1) as follows:

Table 2.5.8 Shift Clock Output Enable Bit Settings

0

1

General-purpose port pin; set at every data transfer for each instruction

Shift clock output pin

[initial value]

Set this bit to "0" when transferring data for each instruction in external shift clock mode. This bit is

set to "0" by a reset. This bit can be read and written.

(2) Serial shift data register (SDR)

7

6

5

4

3

2

1

0

Initial value

XXH

(indeterminate)

SDR

Address : 000026H

D7

D6

D5

D4

D3

D2

D1

D0

R/W R/W R/W R/W R/W R/W R/W R/W

This serial data register is used to store serial I/O transfer data. Writing to and reading from SDR

while a transfer is in progress is prohibited.

2.5.4 Operational Description

(1) Overview of operation

This block consists of a serial mode control status register (SMCS) and a shift register (SDR), and is

used for 8-bit serial data input and output. In serial data I/O, the contents of the shift register are output

to the serial output pin (SOT1) as a series of bits in synchronization with the falling edge of the serial

shift clock (external clock or internal clock), and a series of bits is input to the SDR (shift register) from

the serial input pin (SIN1) in synchronization with the rising edge of the serial shift clock. The shift

direction (transfer starting from the MSB or from the LSB) can be specified by the bit direction select

bit (BDS) in the SMCS (serial mode control status register).

After transfer is completed, the block either enters the paused state or the data register R/W standby

state, depending on the MODE bit setting in the serial mode control status register (SMCS). To shift

from one of these states to the transfer state, perform the corresponding step described below:

(1) To recover from the paused state, write a "0" to the STOP bit and a "1" to the STRT bit. (STOP

and STRT can be set simultaneously.)

(2) To recover from the serial shift data register R/W standby state, either read from or write to the

data register.

87

2.5 I/O Extended Serial Interface

(2) Shift clock

There are two shift clock modes: internal shift clock mode and external shift clock mode. The mode is

specified by the setting of SMCS. Switch modes when serial I/O is paused. To confirm that serial I/O

is in the paused state, read the BUSY bit.

(2.1) Internal shift clock mode

In this mode, operations are performed in synchronization with the internal clock; a shift clock can be

output as the sync timing output from the SCK1 pin with a duty factor of 50%. One data bit is

transferred with each clock pulse. The transfer speed is obtained from:

A

Transfer speed (s) =

Internal clock machine cycle(Hz)

, where

A is determined by the value indicated by the SMD bit in the SMCS register and the value set by the

communication prescaler.

(2.2) External shift clock mode

In this mode, one data bit is transferred with each clock pulse in synchronization with an external shift

clock input from the SCK1 pin.

The transfer speed can range from DC to 1/(5 machine cycles). For example, when one machine cycle

is 0.1 µs, the transfer speed can range up to 2 MHz.

It is also possible to perform one transfer per instruction; the following settings are needed:

Select external shift clock mode, and set the SCOE bit of the SMCS register to "0". Then, write a "1" to

the data direction register for the port that is also used for the SCK1 pin, setting the port to output mode.

After the above settings have been made, whenever a "1" or a "0" is written to the port data register

(PDR), the port value output to the SCK2 pin is fetched as the external clock signal, and the transfer

operation is performed. Start the shift clock at high level.

Note: Writing to the SMCS or SDR register during serial I/O operations is prohibited.

(3) Serial I/O operation states

There are four serial I/O operation states: STOP state, paused state, SDR R/W standby state, and

transfer state.

(3.1) STOP state

The mode is in the STOP state when a RESET is executed or a "1" is written to the SMCS STOP bit;

the shift counter is initialized and the SIR bit is set to "0."

Recovery from the STOP state is accomplished by setting the STOP bit to "0" and the STRT bit to "1"

(both can be set simultaneously). Because the STOP bit has priority over the STRT bit, then whenever

the STOP bit is "1," the transfer operation is not performed, even if STRT = 1.

(3.2) Paused state

When the MODE bit is "0", and BUSY = 0 and SIR = 1 as the result of the completion of a transfer, the

counter is initialized and the device enters the paused state. To recover from the paused state, set STRT

= 1 to resume the transfer operation.

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2.5 I/O Extended Serial Interface

(3.3) Serial data register R/W standby state

When the SMCS MODE bit is "1" and BUSY = 0 and SIR = 1 as the result of the completion of a

transfer, the device enters the serial data register R/W standby state. If the interrupt enable register is in

the enabled state, an interrupt signal is output by this block.

To recover from this R/W standby state, reading from or writing to the serial data register causes BUSY

= 1 to be set, and the transfer operation is resumed.

(3.4) Transfer state

This is the state when BUSY = 1, a serial transfer is in progress. The MODE bit can be used to shift to

the paused state and the R/W standby state.

An operation transition diagram for each state is shown below.

Reset

STOP = 0 & STRT =0

Transfer completed

STOP

STRT = 0, BUSY = 0

MODE =0

STRT = 0, BUSY = 0

STOP = 1

MODE = 0

STOP = 0

&

STOP =0

&

STOP = 1

&

STOP = 0

&

STRT =1

End

Transfer operation

Serial data register R/W standby

MODE = 1 & End & STOP =0

SDR R/W & MODE = 1

STRT = 1, BUSY = 0

MODE =1

STRT = 1, BUSY = 1

Fig. 2.5.2 I/O Extended Serial Interface Operation Transition Diagram

Serial data

SOT1

SIN1

Data bus

Read

CPU

Read

Write

Interrupt output

➁

I/O extended

serial interface

Interrupt input

Data bus

Interrupt controller

➀

Fig. 2.5.3 Conceptual Diagram of Reading from/Writing to Serial Data Register

(1) When the MODE bit is "1," and transfer is completed by the shift clock counter, the SIR bit

becomes "1", and the device enters the read/write standby state. If the SIE bit is set to "1", an

interrupt signal is generated. An interrupt signal is not generated if the SIE bit is inactive or if

the transfer was interrupted by writing a "1" to the STOP bit.

(2) If the serial data register is read or written, the interrupt request is cleared and then serial transfer

is resumed.

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2.5 I/O Extended Serial Interface

(4) Shift operation start/stop timing and I/O timing

Start: The SMCS STOP bit is set to "0" and the STRT bit is set to "1".

Stop: Operation may be paused either because the transfer was completed, or transfer is sometimes

because STOP = "1."

When paused because STOP = 1, transfer is paused with SIR = 0, regardless of the MODE bit.

When paused because the transfer was completed, transfer pauses with SIR = 1, regardless of the

MODE bit.

Regardless of the MODE bit, the BUSY bit is "1" in the serial transfer state, and "0" in the paused state

and the R/W standby state. Read this bit to check whether the device is in the transfer state.

(a) Internal shift clock mode (LSB first)

"1" output

(Transfer end)

SCK1

(Transfer start)

STRT

BUSY

When MODE = 0

SOT1

· · ·

DO0

DO7 (Data retained)

Fig. 2.5.4 Shift Operation Start/Stop Timing (with Internal Clock)

(b)-1 External shift clock mode (LSB first)

SCK1

(Transfer start)

(Transfer end)

STRT

BUSY

When MODE = 0

SOT1

· · ·

DO0

DO7 (Data retained)

Fig. 2.5.5 Shift Operation Start/Stop Timing (with External Clock)

(b)-2 External shift clock mode when an instruction shift is executed (LSB first)

PDR SCK1 bit = "0"

When MODE = 0

PDR SCK1 bit = "0"

SCK1

PDR SCK1 bit = "1"

(transfer end)

STRT

BUSY

SOT1

· · ·

DO6

DO7 (Data retained)

* In an instruction shift, a high signal is output when a "1" is written to the bit corresponding to

PDR SCK1, and a low signal is output when a "0" is written. (However, this only applies

when external shift clock mode is selected and SCOE = "0.")

Fig. 2.5.6 Shift Operation Start/Stop Timing

(in External Shift Clock Mode, with a Shift Executed for Each Instruction)

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(c) Paused by STOP = 1 (LSB first, internal clock)

"1" output

(Transfer end)

SCK1

(Transfer start)

STRT

BUSY

When MODE = 0

STOP

SOT1

· · ·

DO3

DO5 (Data retained)

DO4

Fig. 2.5.7 Stop Timing When STOP Bit Is Set to "1"

Note: DO7 to DO0 indicate the output data.

During a serial data transfer, data is output from the serial output pin (SOTx) at the falling edge of the

shift clock, and the data on the serial input pin (SIN1) is input at the rising edge.

LSB first (when the BDS bit is "0")

SCK1

SIN1 input

SIN1

DI0

DI1

DI2

SOT1 output

DO2 DO3

DI3

DI4

DI5

DI6

DI7

SOT1

DO0

DO1

DO4

DO5

DO6

DO7

MSB first (when the BDS bit is "1")

SCK1

SIN1 input

SIN1

DI7

DI6

DI5

SOT1 output

DO5 DO4

DI4

DI3

DI2

DI1

DI0

SOT1

DO7

DO6

DO3

DO2

DO1

DO0

Fig. 2.5.8 Input/Output Shift Timing

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2.5 I/O Extended Serial Interface

(5) Interrupt function

This block can generate interrupt requests for the CPU. When data transfer is completed, the interrupt

flag SIR is set; if the interrupt enable bit SIE in the SMCS is "1", an interrupt request is output to the

CPU.

SCK1

(Transfer end) * When MODE = 1

BUSY

SIE = 1

SIR

SDR read/write

SOT1

DO6

DO7 (Data retained)

Fig. 2.5.9 Interrupt Signal Output Timing

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2.6 A/D Converter

The A/D converter converts an analog input voltage to a digital value. The features of this converter are

indicated below.

•

Conversion time: Minimum of 7 µs per channel (when the machine clock is 12 MHz)

Uses RC-type sequential conversion system with sample-and-hold circuit

8-bit/10-bit resolution

The analog input can be selected from among four channels by software

One of the following three A/D conversion modes can be selected:

•

One-time conversion mode: Converts the specified channel once and then terminates.

Continuous conversion mode: Repeatedly and continuously converts the specified channel.

Pause conversion mode:

Pauses after converting one channel and waits until the next

startup. (Permits synchronization of conversion start.)

Single conversion operation - Converts one channel (when the starting channel and ending

channel are the same).

Scan conversion operation - Consecutively converts multiple channels (when the starting

channel and ending channel are different).

•

It is possible to generate an "A/D conversion completed" interrupt request to the CPU when A/D

conversion is completed. It is possible to start up I²OS when this interrupt is generated and then to

transfer the data on the A/D conversion results to memory, making this A/D converter suitable for

continuous processing.

The startup sources can be selected from among software, an external trigger (falling edge), and a

timer (rising edge).

2.6.1 Register List

15 14 13 12 11 10

ADCS1

9

8

7

6

5

4

3

2

1

0

BIT

00002D,2C ^H

00002F,2E H

ADCS0

ADCR1

ADER

ADCR0

00001D H

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2.6 A/D Converter

2.6.2 Block Diagram

AVCC

AVRH,L

AVSS

D/A converter

MPX

AN0

AN1

AN2

AN3

Successive

approximation register

Comparator

Sample-and-hold circuit

Data register

ADCR1,0

A/D control register0

A/D control register1

Trigger activation

ATGX

Reload timer 0

ADCS1,0

Operation clock

f

Prescaler

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2.6.3 Detailed Register Description

(1) ADCS1, ADCS0 (Control Status Registers)

■ Register configuration

Ü Bit no.

High-order control status register

Address : 00002DH

15

14

13

12

11

10

9

8

ADCS1

BUSY

INT

INTE

PAUS

Reserved

STS1

STS0

STRT

R/W R/W R/W R/W R/W R/W

W

0

–

0

Read/write Þ

Initial valueÞ

0

Ü Bit no.

Low-order control status register

Address : 00002CH

7

6

5

4

3

2

1

0

ADCS0

MD1 MD0 Reserved ANS1 ANS0 Reserved ANE1 ANE0

R/W R/W R/W R/W R/W R/W R/W R/W

Read/write Þ

Initial valueÞ

0

■ Register contents

This register is used for A/D converter control and status display. Do not update the ADCS during the

A/D conversion operation.

■ Bit contents

[Bit 15] BUSY (busy flag and stop)

During reads: This bit is used for A/D converter operation display. This bit is set at the start of the

A/D conversion operation, and is cleared at the end.

During writes: If a "0" is written to this bit during an A/D conversion operation, operation is

forcibly paused. This function is used for forced pauses in continuous and pause

conversion modes.

Writing a "1" to this bit has no effect on operation. A "1" is returned when this bit is read using an

RMW-type instruction. In one-time conversion mode, this bit is cleared when A/D conversion is

completed. In continuous and pause conversion modes, this bit is not cleared until a "0" is written to

it and operation is paused. This bit is initialized to "0" by a reset.

Note: Do not perform a forced pause and a software startup (BUSY = 0, STRT = 1) simultaneously.

[Bit 14] INT (interrupt)

This is the data display bit. This bit is set when the converted data is stored in the ADCR register. If

2

bit 5 (INTE) is "1" when this bit is set, an interrupt request is generated. In addition, if I OS startup

is enabled, I²OS is started up. Writing a "1" to this bit has no meaning. This bit is cleared by the

CPU writing a "0" and by an I²OS transfer. This bit is initialized to "0" by a reset.

Note: Clear this bit by having the CPU write a "0" to this bit while A/D conversion is paused.

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2.6 A/D Converter

[Bit 13] INTE (interrupt enable)

This bit enables/disables the interrupt upon the completion of conversion.

0: Interrupt disabled

1: Interrupt enabled

Be certain to set this bit when using I²OS. I²OS is designed to be started up by the generation of an

interrupt request.

This bit is set to "0" by a reset.

[Bit 12] PAUS (A/D converter pause)

This bit is set when the A/D conversion operation is paused.

Because this A/D converter has one register for storing conversion results, if continuous conversion

mode is used and the CPU has not finished reading old conversion results, the old data is lost.

Therefore, when using continuous conversion mode, it is basically necessary to use the I²OS and set

it so that each time a conversion is completed, the conversion results are automatically transferred to

memory. However, it is conceivable that a large number of interrupts or other situation could

prevent the transfer of conversion data from occurring before the next conversion is performed.

This bit is provided as a solution for such occurrences. After conversion is completed, this bit is set

until the contents of the data register are transferred by the I²OS; during this period, the A/D

conversion operation is paused, and the next conversion data is not stored. This register is valid

only when the I²OS is used. This bit is initialized to "0" by a reset.

[Bits 11, 10] STS1, STS0 (start source select)

The setting of this bit selects the A/D start source. These bits are initialized to "00" by a reset.

STS1 STS0

Function

0

1

0

1

0

1

Software start

External pin trigger start and software start

Timer start and software start

External pin trigger/timer start and software start

In modes with multiple startup sources, A/D conversion is started by whichever source is detected

first. The start sources change immediately when these bits are overwritten, so if overwriting these

bits while an A/D operation is in progress, do so while the conversion start source to be subject to

change is not present.

A/D conversion may start if this bit is set to "external pin trigger" while the external trigger input

level is low.

[Bit 9] STRT (start)

A/D conversion is started by writing a "1" to this bit. To restart conversion, write a "1" to this bit

again. Note that in pause mode, restarting has no effect. This bit is set to "0" by a reset.

Note: Do not perform a forced pause and a software startup (BUSY = 0, STRT = 1) simultaneously.

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2.6 A/D Converter

[Bit 8] Test bit

This is a test bit. When writing to this bit, always write a "0".

[Bits 7, 6] MD1, MD0 (A/D converter MoDe set)

These bits set the operating mode. The following modes can be set:

MD1

MD0

Operating mode

One-time conversion mode; all restarts are permitted while an operation is in progress

[initial value]

0

1

0

1

One-time conversion mode; restarts are not permitted while an operation is in progress

Continuous conversion mode; restarts are not permitted while an operation is in progress

Pause conversion mode; restarts are not permitted while an operation is in progress

One-time conversion mode: Performs A/D conversion once on each channel consecutively from the

channel set by ANS2 to ANS0 to the channel set by ANE2 to ANE0.

Continuous conversion mode: Performs A/D conversion repeatedly and continuously on each

channel from the channel set by ANS2 to ANS0 to the channel set by ANE2 to ANE0.

Pause conversion mode: Performs A/D conversion once and then pauses for each channel from the

channel set by ANS2 to ANS0 to the channel set by ANE2 to ANE0. Conversion is resumed by

start source generation.

•

If A/D conversion is started in continuous mode or pause mode, the conversion

operation continues until paused by the BUSY bit.

•

Pause is accomplished by writing a "0" to the BUSY bit.

Restarting is not possible in one-time, continuous, or pause conversion mode when

conversion was started by a timer, external trigger, or software.

[Bit 5] This is a reserved bit.

Always write "0" when writing this bit.

[Bits 4, 3] ANS1, ANS0 (analog start channel set)

These bits set the starting channel for A/D conversion. When the A/D converter is started up, A/D

conversion starts with the channel selected by these bits.

ANS1 ANS0

Starting channel

0

1

0

1

0

1

AN0

AN1

AN2

AN3

These bits can be used to read the channel number for currently undergoing conversion during the

A/D conversion operation. When paused in pause mode, the channel that was just converted can be

read. These bits are initialized to "000" by a reset.

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2.6 A/D Converter

[Bit 2] This is a reserved bit.

Always write "0" when writing to this bit.

[Bits 1, 0] ANE1, ANE0 (analog end channel set)

These bits set the ending channel for A/D conversion. When the A/D converter is started up, A/D

conversion proceeds until the channel selected by these bits is reached.

ANE1 ANE0

Ending channel

0

1

0

1

0

1

AN0

AN1

AN2

AN3

If these bits are set to the same channel that is set by ANS1 and ANS0, then just that channel is

converted. In addition, if continuous mode or pause mode is set, then when conversion is performed

for the channel set by these bits, processing returns to the starting channel set by ANS1 and ANS0.

Note: Set the channels so that the channel specified by ANS1 to ANS0 (starting channel) < the

channel specified by ANE1 to ANE0 (ending channel)

These bits are initialized to "00" by a reset.

(2) ADCR1 and ADCR0 (Data registers)

This register is used to store the digital value that is the result of the conversion process.

The storage format differs, depending on the value of the CREG bit of the ADCR1. (The format can be

switched without regard to the A/D conversion operation.)

The value in this register is updated each time a conversion is completed. Normally, this register

contains the most recent conversion value. The value in this register is undefined when a reset is

executed.

bit

15

14

0

13

0

12

0

11

0

10

0

9

8

Conversion data

ADCR1

Address : 00002FH

CREG

Ü Initial value

Ü Bit attribute

0

W

0

–

0

–

0

–

0

–

0

–

X

R

X

R

bit

7

6

5

4

3

2

1

0

Conversion data

ADCR0

Address : 00002EH

Ü Initial value

Ü Bit attribute

X

R

X

R

X

R

X

R

X

R

X

R

X

R

X

R

A "0" is always returned when CREG is read.

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(a)When a "0" is written to the CREG bit (10-bit mode)

bit

15

0

14

0

13

0

12

0

11

0

10

0

9

8

ADCR1

ADCR0

Address : 00002FH

D8

D9

bit

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Address : 00002EH

ADCR1 corresponds to the two most significant bits of the conversion value, and ADCR0

corresponds to the eight least significant bits. "0" is returned when bits 15 to 10 of ADCR1 are read.

(b)When a "1" is written to the CREG bit (8-bit mode)

bit

15

X

14

X

13

X

12

X

11

X

10

X

9

8

ADCR1

ADCR0

X

Address : 00002FH

bit

7

6

5

4

3

2

1

0

Address : 00002EH

D7

D6

D5

D4

D3

D2

D1

D0

ADCR0 corresponds to the eight most significant bits of the conversion value. "00^H" is returned

when ADCR1 is read.

■ Register contents

These registers are the A/D conversion storage registers, and are used to store the digital value that is

the result of the conversion. When the CREG bit is "0", the conversion result consists of 10 bits; when

the CREG bit is "1", the conversion result consists of 8 bits. The two least significant bits of converted

value are stored in ADCR1 and the eight most significant bits are in ADCR0. The value stored in these

registers are updated each time a conversion operation is completed. Normally, these registers contain

the most recent conversion value. Aside from the CREG bit, the value in this register is indeterminate

when a reset is executed.

In 10-bit mode, when bits 15 to 10 of ADCR1 are read, "0" is returned. In 8-bit mode, the entire

contents of ADCR1 are indeterminate; conversion results are stored in ADCR0.

Be certain to overwrite the CREG bit only when A/D operation is paused before the conversion

operation. If the CREG bit is overwritten after a conversion operation, the contents of ADCR are

undefined.

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2.6 A/D Converter

2.6.4 Operational Description

This A/D converter uses the sequential comparison system and offers resolution of either 8 bits or 10

bits. Because the register used for storing conversion results totals 16 bits and supports only one

channel, each time a conversion is completed the previous conversion data is lost. Therefore, in

continuous conversion mode, it is necessary to use the I²OS to transfer the conversion data to sequential

memory.

The operation modes are described below.

■ One-time mode

In this mode, the analog inputs, set by the ANS bits and the ANE bits, are converted in sequence until

conversion of the ending channel set by the ANE bits is completed, at which point the A/D operation is

paused. When the starting channel and the ending channel are the same (ANS = ANE), then only the

channel specified by ANS is converted.

Examples:

ANS = 00, ANE = 11

Start ® AN0 ® AN1 ® AN2 ® AN3 ® End

ANS = 10, ANE = 10

Start ® AN2 ® End

■ Continuous mode

In this mode, the analog inputs, set by the ANS bits and the ANE bits, are converted in sequence until

conversion of the ending channel set by the ANE bits is completed, at which point processing returns to

the ANS analog input and the A/D conversion operation continues. When the starting channel and the

ending channel are the same (ANS = ANE), then only the channel specified by ANS is converted.

Examples:

ANS = 00, ANE = 11

Start ® AN0 ® AN1 ® AN2 ® AN3 ® AN0 .... ® Repeat

ANS = 10, ANE = 10

Start ® AN2 ® AN2 ® AN2 .... ® Repeat

If conversion is performed in continuous mode, the conversion operation is repeated until a "0" is

written to the BUSY bit. Writing a "0" to the BUSY bit forcibly pauses operation.

Because executing a forced operation pause causes the A/D converter operation to stop in the middle of

a conversion, the value being converted is not received. The result in the ADCR is the value that was

converted last immediately before the stop.

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■ Pause mode

In this mode, the analog inputs, set by the ANS bits and the ANE bits, are converted in sequence, except

that the conversion operation pauses after the conversion of each channel. The pause is exited by

restarting the conversion operation. When conversion of the ending channel set by the ANE bits is

completed, processing returns to the ANS analog input and the A/D conversion operation continues.

When the starting channel and the ending channel are the same (ANS = ANE), then only the channel

specified by ANS is converted.

Examples:

ANS = 00, ANE = 11

Start ® AN0 ® Pause ® Start ® AN1 ® Pause ® Start ® AN2 ® Pause ® Start ® AN3 ®

Pause ® Start ® AN0 .... ® Repeat

ANS = 10, ANE = 10

Start ® AN2 ® Pause ® Start ® AN2 ® Pause ® Start ® AN2 .... ® Repeat

In this mode, only the start source set by STS1 and STS0 is valid. This mode can be used to

synchronize conversion start.

■ Conversion operation using I²OS

An example of the flow of the conversion operation in continuous mode from the start of A/D

conversion to conversion data transfer is shown below.

A/D conversion start

I²OS start

Sample and hold

Data transfer

Conversion

Interrupt processing

❶

Conversion end

Interrupt cleared

Interrupt generation

The decision indicated by the ❶depends on the I2OS settings.

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2.6 A/D Converter

V Conversion Data Preservation Function

One of the features of this A/D converter is that it has a conversion data preservation function,

making continuous conversion possible and making it possible to secure multiple conversion data.

Because there is only one conversion data register, each time a conversion is completed in

continuous A/D conversion the data is stored in the conversion data register, and the previous data is

lost. To preserve this data, the A/D converter has a function that, if the previous data has not been

transferred to memory by the I²OS, temporarily pauses the A/D converter, even if conversion has

been completed.

The paused state is released when the data is transferred to memory by the I²OS.

If the previous data has been transferred, A/D conversion continues without pausing.

Note:

This function is associated with the INT and INTE bits in ADCS1.

The data preservation function only operates when interrupts are enabled (INTE = 1).

If interrupts are disabled (INTE = 0), this function does not operate; if A/D conversion is performed

in continuous mode, new data is continually stored in the register, destroying the old data.

In addition, if interrupts are enabled (INTE = 1) but the I²OS is not being used, the INT bit is not

cleared, so the data preservation function works and pauses A/D conversion. In this case, the paused

state is released once the INT bit is cleared during the interrupt sequence.

When the A/D converter is paused while the I²OS is in operation and interrupts are then disabled,

the A/D converter operates and the contents of the conversion data register may be changed before

the data is transferred.

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In addition, the standby (waiting) data is lost if conversion is restarted while it is paused.

Flow of the data preservation function (when using I²OS)

Set I²OS

The flow of operations while A/D converter

operations are paused is omitted.

Note: If conversion is restarted while paused,

conversion data that is standing by is lost.

Start continuous A/D conversion

Complete first conversion

Store result in data register

End second conversion

Start I²OS

NO

Note

Terminate I²OS?

Pause A/D converter

YES

NO

Terminate I²OS?

Start I²OS

Store result in data register

End third conversion

Continue

End all conversions

Start I²OS

Interrupt routine

Pause A/D converter

End

103

2.6 A/D Converter

● Example of starting I²OS in one-time mode

•

Converts analog inputs AN1 to AN3 and then ends.

Transfers the conversion data in sequence to addresses 200^Hto 205H.

Start triggered by software.

Interrupt level is at the highest level.

❑ I²OS settings

ICR settings in the interrupt controller

MOV ICR14, #08H............................................................................................... (1)

2

I OS descriptor settings

MOV BAPL, #00H ............................................................................................... (2)

MOV BAPM, #02H.............................................................................................. (3)

MOV BAPH, #00H............................................................................................... (4)

MOV ISCS, #00H................................................................................................. (5)

MOV IOAL, #38H................................................................................................ (6)

MOV IOAH, #00H ............................................................................................... (6)

MOV DCTL, #03H............................................................................................... (7)

MOV DCTH, #00H .............................................................................................. (7)

❑ A/D converter settings

MOV ADCS0, #0BH............................................................................................ (8)

MOV ADCS1, #A2H............................................................................................ (9)

❑ Other processing

❑ I²OS termination interrupt sequence

MOV ADCS1, #00H

RETI..................................................................................................................... (10)

(1) Highest interrupt setting, I²OS start upon interrupt, descriptor address setting.

(2)(3)(4) Conversion data transfer destination address.

(5) Word data transfer, and increment transfer destination address after transfer. Transfer

from I/O to memory.

(6) A/D converter results register setting

(7) Perform I²OS transfer three times. Perform transfer as many times as conversion.

(8) One-time mode, starting channel AN1, ending channel AN3

(9) Software start, A/D conversion start

(10) Recovery from interrupt

ICR14: Interrupt control register

BAPL: Low-order buffer address pointer

BAPM: Mid-order buffer address pointer

BAPH: High-order buffer address pointer

ISCS:

I²OS status register

I/OAL: Low-order I/O address register

I/OAH: High-order I/O address register

DCTL: Low-order data counter

DCTH: High-order data counter

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Start Þ AN1® Interrupt ® I²OS transfer

ß

AN2® Interrupt ® I²OS transfer

ß

AN3® Interrupt ® I²OS transfer

ß

End

Interrupt sequence

Parallel processing

105

2.6 A/D Converter

● Example of starting I²OS in continuous mode

•

Converts analog inputs AN0 to AN2 and fetches conversion data from each channel twice.

Transfers the conversion data in sequence to addresses 600H to 60BH.

Start triggered by external edge input.

Interrupt level is at the highest level.

❑ I²OS settings

ICR settings in the interrupt controller

MOV ICR14, #08H............................................................................................... (1)

I²OS descriptor settings

MOV BAPL, #00H ............................................................................................... (2)

MOV BAPM, #06H.............................................................................................. (3)

MOV BAPH, #00H............................................................................................... (4)

MOV ISCS, #00H................................................................................................. (5)

MOV IOAL, #38H................................................................................................ (6)

MOV IOAH, #00H ............................................................................................... (6)

MOV DCTL, #06H............................................................................................... (7)

MOV DCTH, #00H .............................................................................................. (7)

❑ A/D converter settings

MOV ADCS0, #82H............................................................................................ (8)

MOV ADCS1, #A4H (edge-triggered start)........................................................ (9)

❑ Other processing

❑ I²OS termination interrupt sequence

MOV ADCS1, #00H............................................................................................ (10)

RETI

(1) Highest interrupt setting, I²OS start upon interrupt, descriptor address setting.

(2)(3)(4) Conversion data transfer destination address.

(5) Transfer word data, and increment transfer destination address after transfer. Transfer

from I/O to memory. Termination by request from resource.

(6) Transfer origin address.

(7) Perform I²OS transfer six times. Transfer two data values for each of three channels.

(8) Continuous mode, starting channel AN0, ending channel AN2

(9) External edge-triggered start, A/D conversion start

(10) Recovery from interrupt

Start Þ AN0® Interrupt ® I²OS transfer

ß

AN1® Interrupt ® I²OS transfer

After all six transfers

ß

AN2® Interrupt ® I²OS transfer

Interrupt sequence

ß

End

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Chapter 2: HARDWARE

2.6 A/D Converter

● Example of starting I²OS in pause mode

•

Converts analog input AN3 12 times at fixed intervals.

Transfers the conversion data to addresses 600H to 617H.

Start triggered by external edge input.

Interrupt level is at the highest level.

❑ I²OS settings

ICR settings in the interrupt controller

MOV ICR14, #08H............................................................................................... (1)

2

I OS descriptor settings

MOV BAPL, #00H ............................................................................................... (2)

MOV BAPM, #06H.............................................................................................. (3)

MOV BAPH, #00H............................................................................................... (4)

MOV ISCS, #00H................................................................................................. (5)

MOV IOAL, #38H................................................................................................ (6)

MOV IOAH, #00H ............................................................................................... (6)

MOV DCTL, #0CH .............................................................................................. (7)

MOV DCTH, #00H .............................................................................................. (7)

❑ A/D converter settings

MOV ADCS0, #DBH ........................................................................................... (8)

MOV ADCS1, #A4H (edge-triggered start)........................................................ (9)

❑ Other processing

❑ I²OS termination interrupt sequence

MOV ADCS1, #80H............................................................................................ (10)

RETI

(1) Highest interrupt setting, I²OS start upon interrupt, descriptor address setting.

(2)(3)(4) Conversion data transfer destination address.

(5) Transfer word data, and increment transfer destination address after transfer. Transfer

from I/O to memory. Termination by request from resource.

(6) Transfer origin address.

(7) Perform I²OS transfer 12 times.

(8) Continuous mode, starting channel AN3, ending channel AN3 (conversion of one

channel).

(9) External edge-triggered start, A/D conversion start

(10) Recovery from interrupt

Start Þ AN3® Interrupt ® I²OS transfer

After 12 transfers

ß

Pause

ß

Interrupt sequence

External edge-triggered start

ß

End

107

2.6 A/D Converter

■ Notes on Usage

When using either an external trigger or the internal timer to start the A/D converter, select the source

by setting the A/D start source bits STS1 and STS0 in the ADCS1 register. When doing so, set the

external trigger and internal timer input values to the inactive side. If these values are on the active

side, the A/D converter may begin operations.

When setting STS1 and STS0, input "1" to ATGX and set the internal timer (reload timer 0) so that it

outputs "0".

2.6.5 Other Notes

Always be sure to set the bits in ADER corresponding to the pins used for analog input to "1".

ADER

15

14

13

12

11

10

9

8

Bit

Initial value

----1111B

ADE3 ADE2 ADE1 ADE0

Address : 00001DH

–

R/W R/W R/W R/W

–

Control each of the port 5 pins as shown below.

0: Port input mode

1: Analog input mode

These pins are set to "1" by a reset.

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Chapter 2: HARDWARE

2.7 16-bit Timer (with Event Counter Function)

The 16-bit timer consists of a 16-bit down counter, a 16-bit reload register, one input/output pin (TINx,

TOTx), and a control register. Three internal clocks and an external clock can be selected for an input

clock. When in reload mode, a toggled output waveform is output to the output pin (TOTx), while in one-

shot mode a square wave indicating that the count is in progress is output. The input pin (TINx) serves as

an event input in event count mode, and can be used for trigger input or gate input in internal clock mode.

2.7.1 Block Diagram

16

/

16-bit reload timer

/

8

Reload

/

RELD

OUTE

OUTL

INTE

UF

16-bit down counter

UF

16

2

/

OUT

CTL.

GATE

CSL1

/

2

IRQ

Clear

I²OSCLR

Clock selector

CSL0

CNTE

TRG

Retrigger

/

2

Port(Tin)

(Tout)

IN CTL.

3

EXCK

f

Prescaler

Clear

1

2³2⁵

MOD2

2

MOD1

MOD0

Internal clock

/

3

Fig. 2.7.1 Block Diagram

109

2.7 16-bit Timer (with Event Counter Function)

2.7.2 Register List

7

6

5

4

3

2

1

0

Address:000040H

000046H

MOD0 OUTE OUTL RELD INTE

UF

CNTE

TRG

000050H

15

14

13

12

11

10

9

8

Address:000041H

000047H

Control status register

TMCSR✕

–

CSL1 CSL0 MOD2 MOD1

000051H

15

0

Address:000042H

000048H

16-bit timer register

TMRx

000052H

0

Address:000044H

00004AH

16-bit reload register

TMRLRx

000054H

2.7.3 Detailed Register Description

(1) Control status register (TMCSR)

11

CSL1 CSL0 MOD2MOD1MOD0 OUTE OUTL RELD INTE UF CNTE TRG

R/W R/W R/W R/W R/W R/W R/W R/W R/W

10

9

8

7

6

5

4

3

2

1

0

TMCSR

Initial value

-000H

Address : 000040H

000046H

R/W R/W R/W

000050H

This register controls the 16-bit timer operation mode and interrupts.

Except for the UF, CNTE, and TRG bits, overwrite the bits in this register when CNTE = 0.

[Bits 11, 10] CSL1, CSL0:

These are the count clock select bits.

The clock sources that are selected are shown in Table 2.7.1. The edge that is valid for counting

purposes when external event count mode is selected is set by the MOD1 and MOD0 bits.

Table 2.7.1 CSL Bit Setting Clock Source

CSL1

CSL0

Clock source

f = 12 MHz

61.2 µs

0.66 µs

2.66 µs

–

f = 8 MHz

61.2 µs

1 µs

f = 4 MHz

61.2 µs

2 µs

0

1

0

1

0

1

Subclock/2

f /2³

f /2⁵

4 µs

8 µs

External event count mode

–

Subclock = 32.1 kHz

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Chapter 2: HARDWARE

2.7 16-bit Timer (with Event Counter Function)

[Bits 9, 8, 7] MOD2, MOD1, MOD0:

These bits set the operation mode and the input/output pin functions.

The MOD2 bit is the bit that selects the function of the input pin. When "0", the input pin is a

retrigger input pin; when the valid edge is input, the contents of the reload register are loaded into

the counter, and the count operation continues. When "1", gate count mode is in effect; the input pin

becomes a gate input, and counting is on only while the valid level is being input.

The MOD1 and MOD0 bits set the function of the pin in each mode. The settings for the MOD2,

MOD1, and MOD0 bits are shown in Table 2.7.2 and Table 2.7.3.

Table 2.7.2 MOD2, MOD1, and MOD0 Bit Setting Method (1)

In internal clock mode (CSL0, CSL1 = 00, 01, 10)

MOD2 MOD1 MOD0

Input pin function

Valid edge/level

–

0

1

0

1

×

0

1

0

1

0

1

Trigger prohibited

Trigger input

Rising edge

Falling edge

Both edges

'L' level

•

Gate input

•

'H' level

Table 2.7.3 MOD2, MOD1, and MOD0 Bit Setting Method (2)

In event count mode (CSL0, CSL1 = 11)

MOD2 MOD1

MOD0

Input pin function

Valid edge/level

–

0

1

0

1

–

0

Event input

Trigger prohibited

Trigger input

Both edges

×

1

•

1

Note: The "✕" symbol in the table means "Don't care."

[Bit 6] OUTE:

This is the output enable bit. When "0", the Tout pin is a general-purpose port; when "1", the Tout

pin is a timer output pin. The output waveform is toggle output in reload mode and is a square wave

output indicating that counting is in progress in one-shot mode.

111

2.7 16-bit Timer (with Event Counter Function)

[Bit 5] OUTL:

This bit sets the Tout pin output level. The pin level is reversed, depending on whether this bit is "0"

or "1".

Table 2.7.4 OUTE, RELD, and OUTL Setting Method

OUTE RELD

OUTL

Output waveform

General-purpose port

0

1

×

0

1

×

0

1

0

1

Square wave, high when counting

Square wave, low when counting

Low toggle output at count start

High toggle output at count start

[Bit 4] RELD:

This bit is the reload enable bit. When this bit is "1", reload mode is in effect; in reload mode, the

contents of the reload register are loaded in the counter simultaneously with an underflow in the

counter value from 0000^Hto FFFFH so that the counting operation can continue. When this bit is set

to "0", the count operation is paused by an underflow in the counter value from 0000^Hto FFFFH.

[Bit 3] INTE:

This bit is the interrupt request enable bit. If this bit is "1" when the UF bit is set to "1", an interrupt

request is generated. If this bit is "0", no interrupt request is generated.

[Bit 2] UF:

This bit is the timer interrupt request flag. This bit is set to "1" by an underflow in the counter value

from 0000^Hto FFFFH. This bit is either cleared by the Intelligent I/O Service, or by writing a "0" to

this bit. Writing a "1" to this bit has no meaning.

When this bit is read by a read-modify-write instruction, a "1" is read.

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Chapter 2: HARDWARE

2.7 16-bit Timer (with Event Counter Function)

[Bit 1] CNTE:

This bit is the timer count enable bit. If a "1" is written to this bit, the device waits for the start

trigger. Writing a "0" to this bit pauses the counting operation.

[Bit 0] TRG:

This bit is the software trigger bit. Writing a "1" to this bit activates the software trigger, causing the

contents of the reload register to be loaded into the counter, after which the counting operation

begins. Writing a "0" to this bit has no meaning. The value that is read from this bit is always "0".

Trigger input by this register is valid only when CNTE = "1". When CNTE = "0", nothing happens.

(2) 16-bit timer register (TMR)

TMR

Address : 000042^H

15

0

Initial value

----1111B

000048^H

000052H

R

· · ·

Initial value

×

The 16-bit timer count value can be read from this register. The initial value of this register is

undefined. Always use a word transfer instruction to read this register.

(3) 16-bit reload register (TMRLR)

TMRLR

Address : 000044^H

15

0

Initial value

----1111B

00004A^H

000054H

R/W R/W R/W R/W

R/W R/W R/W R/W R/W

· · ·

Initial value

×

The 16-bit reload register is used to store the initial value for counting. The initial value of this

register is undefined. Always use a word transfer instruction to read this register.

113

2.7 16-bit Timer (with Event Counter Function)

2.7.4 Detailed Register Description

(1) Internal clock operation

When the timer operates according to a divide clock derived from the internal clock, it is possible to

select as a source clock, a clock that is either 2³or 2⁵divisions of the source oscillation. Depending on

the register setting, the external input pin is possible to be used either for trigger input or gate input.

To start the count operation simultaneously with the enabling of the count, write a "1" to both the

CNTE bit and the TRG bit in the control register. Trigger input generated by the TRG bit is always

valid when the timer is in the start state (CNTE = "1"), regardless of the operation mode.

Fig. 2.7.2 illustrates counter startup and counter operation.

"T" (T: machine cycle) is the period of time from when the counter start trigger is input to when the

reload register data is loaded in the counter.

Count clock

Counter

Data load

-1

Reload data

-1

CNTE (register)

TRG (register)

T

Fig. 2.7.2 Counter Startup and Operation

(2) Underflow operation

An underflow occurs when the counter value goes from 0000^Hto FFFFH. Therefore, an underflow

occurs at the count [value set in the reload register + 1].

If the RELD bit in the control register is "1" when an underflow occurs, the contents of the reload

register are loaded into the counter and the count operation continues. When the RELD bit is "0", the

counter stops at FFFF^H.

When an underflow occurs, the UF bit is set, and an interrupt request is generated if the INTE bit is "1".

Fig. 2.7.3 illustrates the underflow operation.

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Chapter 2: HARDWARE

2.7 16-bit Timer (with Event Counter Function)

Count clock

Counter

Reload data

-1

0000H

-1

Data load

Underflow set

[RELD=1]

Count clock

Data load

0000^H

FFFFH

Underflow set

[RELD=0]

Fig. 2.7.3 Underflow Operation

(3) Input pin functions (in internal clock mode)

When the internal clock is selected as the clock source, the Tin pin can be used either as a trigger input

or a gate input. When used as a trigger input, the contents of the reload register are loaded into the

counter when the valid edge is input, and after the internal prescaler is cleared, the count operation

begins. Input a pulse of 2✕T (T: machine cycle) or more to Tin. Fig. 2.7.4 illustrates the trigger input

operation.

Count clock

When rising edge is detected

Tin

Prescaler clear

Counter

-1

Reload data

-1

Load

2T to 2.5T

Fig. 2.7.4 Trigger Input Operation

115

2.7 16-bit Timer (with Event Counter Function)

When used as a gate input, the counting operation occurs only while the valid level (set by the MOD0

bit in the control register) is being input from the Tin pin. In this case, the count clock continues to

operate without stopping. A software trigger can be used in gate mode regardless of the gate level. The

Tin pin pulse width should be 2.T (T: machine cycle) or more. Fig. 2.7.5 illustrates the gate input

operation.

Count clock

Tin

When MOD0 = "1" (count while input is high)

Counter

-1

Fig. 2.7.5 Gate Input Operation

(4) External event count

If an external clock is selected, the Tin pin serves as the external event input pin, and the valid edge set

by the register is counted. The Tin pin pulse width should be 4.T (T: source oscillation cycle) or more.

(5) Output pin functions

The Tout pin functions as a toggle output that is inverted by an underflow in reload mode, and as a

pulse output that indicates that counting is in progress in one-shot mode. The output polarity can be set

by the register OUTL bit. When OUTL = "0", the initial value for the toggle output is "0", and a "1" is

output while counting is in progress for the one-shot pulse output. When OUTL = "1", the output

waveform is inverted.

Count start

Underflow

Tout

Inverted when OUTL = 1

General-purpose port

CNTE

Start trigger

[RELD=1, OUTL=0]

Fig. 2.7.6 Output Pin Functions (1)

116

Chapter 2: HARDWARE

2.7 16-bit Timer (with Event Counter Function)

Underflow

Tout

Inverted

when OUTL = 1

General-purpose port

CNTE

Start trigger

Waiting for start trigger

[RELD=0, OUTL=0]

Fig. 2.7.7 Output Pin Functions (2)

(6) Clearing of interrupt flags by the intelligent I/O service

The UF bit in the control register is cleared by the Intelligent I/O Service (I²OS) once the interrupt

processing initiated by the I²OS is completed.

117

2.7 16-bit Timer (with Event Counter Function)

(7) Counter operation state

The counter state is determined by the CNTE bit in the control register and the internal WAIT signal.

The states that can be set are: the STOP state (CNTE = "0", WAIT = "1"), the WAIT state (waiting for

the start trigger; CNTE = "1", WAIT = "1"), and the RUN state (CNTE = "1", WAIT = "0"). Fig. 2.7.8

shows the transitions between the various states.

State transition caused by hardware

Reset

State transition caused by register access

STOP

CNTE=0,WAIT=1

Tin: Input prohibited

Tout: General-purpose port

Counter: Retains value that was

held when stopped;undefined

immediately after reset

CNTE=‘0’

CNTE=‘1’

TRG=‘0’

CNTE=‘1’

TRG=‘1’

WAIT

CNTE=1,WAIT=1

RUN

CNTE=1,WAIT=0

Tin: Only trigger input is valid

Tout: Initial value output

Tin: Functions as Tin

Tout: Functions as Tout

Counter: Operates

Counter: Retains value that was

held when stopped;undefined

immediately after reset until value

is loaded

RELD·UF

TRG=‘1’

RELD·UF

LOAD

CNTE=1,WAIT=0

Trigger from Tin

Loads contents of reload register

into counter

Load end

Fig. 2.7.8 Counter State Transitions

118

Chapter 2: HARDWARE

2.8 16-bit Free-running Timer

The 16-bit free-running timer consists of a 16-bit up counter, a control status register, and a compare

register.

•

One of four types of count clocks can be selected.

An interrupt can be generated for a counter overflow.

An interrupt can be generated for a match between the compare registers.

It is possible, through the mode setting, to initialize the counter when it matches the value of compare

register 0.

2.8.1 Register List

15

0

000056^H

000060^H

Timer data register

Control status register

Compare register 0

Compare register 1

TCDTx

000059,58H

000063,62H

CCSx

TCSx

00005AH

000064H

TCRLx

TCRHx

00005CH

000066H

2.8.2 Block Diagram

f

Interrupt request

IVF

IVFE STOP MODE CLR CLK1 CLK0

Divider

Comparator 0

Clock

16-bit up counter

T00 to 15

Compare match interrupt

Comparator ✕ 0

T00 to 15

Comparator ✕ 1

119

2.8 16-bit Free-running Timer

2.8.3 Detailed Register Description

(1) Timer data register (TCDT)

15

14

13

12

11

10

9

8

bit

000056,60H

T15 T14 T13 T12 T11 T10 T09 T08

R/W R/W R/W R/W R/W R/W R/W R/W

Ü Attributes

0

Ü Initial value

bit

7

6

5

4

3

2

1

0

T07 T06 T05 T04 T03 T02 T01 T00

R/W R/W R/W R/W R/W R/W R/W R/W

Ü Attributes

0

Ü Initial value

This register can be used to read the count value of the 16-bit free-running timer. The counter value is

cleared to "0000" when reset.

Although the timer value can be set by writing the value to this register, do so while the timer is stopped

(STOP = 1).

Use word access to access this register.

The 16-bit free-running timer is initialized through the following causes:

•

Initialization by reset

Initialization through the clear bit (CLR) in the control status register

Initialization by matching of compare register 0 and the timer counter value (mode setting is

required)

(2) Control status register (TCS)

7

6

5

4

3

2

1

0

bit

Reserved

IVF IVFE STOPMODE CLR CLK1 CLK0

000058,62H

R/W R/W R/W R/W R/W R/W R/W R/W

Ü Attributes

0

Ü Initial value

[Bit 7] Reserved bit

Be certain to write "0" to this bit.

[Bit 6] IVF

This bit is the 16-bit free-running timer interrupt request flag.

This bit is set to "1" when the 16-bit free-running timer overflows, or when the counter was cleared

because it matched compare register 0.

If the interrupt request enable bit (Bit 5: IVFE) is set, an interrupt is generated.

This bit is cleared by writing a "0" to this bit. Writing a "1" to this bit has no meaning. When read

by a read-modify-write instruction, this bit returns a "1".

0

1

No interrupt request

Interrupt request

(initial value)

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Chapter 2: HARDWARE

2.8 16-bit Free-running Timer

[Bit 5] IVFE

This bit is the 16-bit free-running timer interrupt enable bit.

When this bit is "1" and the interrupt flag (Bit 5: IVF) is set to "1", an interrupt is generated.

0

1

Interrupt disabled

Interrupt enabled

(initial value)

[Bit 4] STOP

This bit is used to stop the 16-bit free-running timer count.

Writing a "1" to this bit stops the timer counting.

Writing a "0" to this bit starts the timer counting.

0

1

Counting enabled (running)

Counting disabled (stopped)

(initial value)

If the 16-bit free-running timer counting is stopped, the output compare operation is also stopped.

[Bit 3] MODE

This bit sets the initialization conditions for the 16-bit free-running timer.

When this bit is "0", the counter value can be initialized by a reset and by the clear bit (Bit 2: CLR).

When this bit is "1", the counter value can be initialized not only by a reset and by the clear bit (Bit

2: CLR), but also by a match between the output compare and compare register 0.

0

1

Initialize by reset and clear bit

(initial value)

Initialize by reset, clear bit, and compare register 0

The counter value is initialized at the point when the count value changes.

[Bit 2] CLR

This bit initializes the 16-bit free-running timer to "0000" while it is running.

If a "1" is written to this bit, the counter value is initialized to "0000".

Writing a "0" to this bit has no meaning. The value read from this bit is always "0".

0

1

No meaning

(initial value)

Initializes the counter value to "0000"

The counter value is initialized at the point when the count value changes.

To initialize while the timer is stopped, write "0000" to the data register.

121

2.8 16-bit Free-running Timer

[Bits 1, 0] CLK1, CLK0

These bits select the 16-bit free-running timer count clock.

Because the clock is changed soon after these bits are written, change the clock while the

compare operation is stopped.

CLK1 CLK0 Couter clock f = 12 MHz

f = 8 MHz

0.5 µs

2 µs

f = 4 MHz

1 µs

0

1

0

1

0

1

f /4

f /16

f /64

f /256

0.33 µs

1.33 µs

5.33 µs

21.33 µs

4 µs

8 µs

16 µs

32 µs

64 µs

f = machine clock

(3) Compare register (TCRL/TCRH)

15

14

13

12

11

10

9

8

bit

C15 C14 C13 C12 C11 C10 C09 C08

00005A, 5CH

000064, 66H

R/W R/W R/W R/W R/W R/W R/W R/W

Ü Attributes

X

Ü Initial value

bit

7

6

5

4

3

2

1

0

C07 C06 C05 C04 C03 C02 C01 C00

R/W R/W R/W R/W R/W R/W R/W R/W

Ü Attributes

X

Ü Initial value

This is the 16-bit compare register that compares with the 16-bit free-running timer. The initial value

of the register is indeterminate, so set the value before enabling startup.

Use word access to access this register.

When the value in this register matches the 16-bit free-running timer value, the compare signal is

generated, and the compare interrupt flag is set.

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Chapter 2: HARDWARE

2.8 16-bit Free-running Timer

(4) Control status register (CCS)

15

14

13

12

11

–

10

–

9

8

bit

000059H

000063H

ICP1 ICP0 ICE1 ICE0

CST1 CST0

R/W R/W R/W R/W

0

–

R/W R/W

0

Ü Attributes

Ü Initial value

0

[Bits 15, 14] ICP1, ICP0

These bits are the output compare interrupt flags.

These bits are set to "1" when the compare register and the 16-bit free-running timer value match. If

the interrupt request bits (ICE1, ICE0) are enabled and these bits are set, a compare match interrupt

is generated.

These bits are cleared by writing a "0" to them. Writing a "1" to these bits has no meaning. When

read by a read-modify-write instruction, these bits return a "1".

0

1

No compare match

Compare match

(initial value)

(ICP1: Corresponds to compare register 1; ICP0: Corresponds to compare register 0)

[Bits 13, 12] ICE1, ICE0

These are the output compare interrupt enable bits.

If the interrupt flags (ICP0, ICP1) are set while these bits are set to "1", an output compare interrupt

is generated.

0

1

Compare match interrupt disabled (initial value)

Compare match interrupt enabled

(ICE1: Corresponds to compare register 1ICE0: Corresponds to compare register 0)

[Bits 11, 10] Unused

[Bts 9, 8] CST1, CST0

These bits enable the matching operation with the 16-bit free-running timer.

0

1

Compare operation disabled

Compare operation enabled

(initial value)

Set the compare register value before enabling or disabling the compare operation.

(CST1: Corresponds to compare register 1 CST0: Corresponds to compare register 0)

Note: Because the compare operation is synchronized with the clock derived from the 16-bit free-

running timer, stopping the 16-bit free-running timer stops the compare operation.

123

2.9 PPG (Programmable Pulse Generator) Timer

This module can output a pulse synchronized with an external source or a software trigger. In addition, the

pulse that is output can be used to change the cycle and duty factor as desired by overwriting the two 16-bit

registers.

•

PWM function:

It is possible to program the output of a pulse that is synchronized with the

trigger while overwriting the value in the above register.

This function can also be used as a D/A converter when the appropriate

external circuit is provided.

•

One-shot function: This function detects the trigger input edge and outputs a single pulse.

Module configuration

This module consists of a 16-bit down counter, a prescaler, a 16-bit cycle setting register, a 16-bit duty

factor setting register, a 16-bit control register, an external trigger input pin, and a PPG output pin.

2.9.1 Register List

15

8 7

0

PPG down counter

PPGC

Cycle setting register

Duty factor setting register

Control/status register

PCSR

PDUT

PCNH

PCNL

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2.9 PPG (Programmable Pulse Generator) Timer

2.9.2 Block Diagram

PCSR

PDUT

Prescaler

f /2

cmp

ck

16-bit down counter

Start Borrow

Load

f /8

f /32

f /128

PPG mask

PPG output

S

R

Q

Inverter bit

Enable

IRQ

TRG input

Edge detector

Software trigger

125

2.9 PPG (Programmable Pulse Generator) Timer

2.9.3 Detailed Register Description

(1) Control/status register (PCNL/H)

15

14

13

12

11

10

9

8

–

Bit No. Þ

PCNH 00035, 3DH

CNTE STGR MDSE RTRG CKS1 CKS0 PGMS

Read/write Þ

Initial value Þ

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(0)

×

(0)

×

(0)

×

(0)

×

(0)

Overwritable while

in operation Þ

7

6

5

4

3

2

1

0

Bit No. Þ

EGS1 EGS0 IREN IRQF IRS1 IRS0 POEN OSEL

PCNL 00034/3CH

Read/write Þ

Initial value Þ

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(0)

×

(0)

×

(0)

×

(0)

×

(0)

×

(0)

×

Overwritable while

in operation Þ

[Bit 15] CNTE: Timer enable bit

0

1

Disabled

Enabled

[Bit 14] STGR: Software trigger bit

Writing a "1" to this bit initiates the software trigger.

The value that is read from the STGR bit is always "0".

[Bit 13] MDSE: Mode selection bit

0

1

PWM operation

One-shot operation

[Bit 12] RTRG: Retriggering selection bit

0

1

Retriggering disabled

Retriggering enabled

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2.9 PPG (Programmable Pulse Generator) Timer

[Bits 11, 10] CKS1,CKS0: Counter clock selection bit

CKS1 CKS0

Cycle

f /2

f = 12 MHz

166.66 ns

666.66 ns

2.66 µs

f = 8 MHz

250 ns

1 µs

f = 4 MHz

500 ns

2 µs

0

1

0

1

0

1

f /8

f /32

f /128

4 µs

8 µs

10.66 µs

16 µs

32 µs

[f ]: Machine clock

[Bit 9] PGMS: PPG output mask selection bit

By writing a "1" to this bit, it is possible to mask PPG output with either a "0" or a "1", regardless of

the mode setting, period setting value, or duty factor setting value.

PPG output when "1" is written to PGMS

Polarity

PPG output

Normal polarity

Polarity inversion

L

H

To output "all high" for normal polarity or "all low" for inverse polarity, writing the same value both

in the period setting register and the duty ratio setting register makes it possible to output the inverse

of the mask values shown at left.

[Bits 7, 6] EGS1, EGS0: External trigger input edge selection bit

EGS1 EGS0

Edge selection

Invalid

0

1

0

1

0

1

Rising edge

Falling edge

Both edges

No matter which mode is selected, writing a "1" to the software trigger bit makes the software

trigger valid.

[Bit 5] IREN: PPG interrupt request enable bit

0

1

Disabled

Enabled

[Bit 4] IRQF: PPG interrupt request flag

If IREN (Bit 5) is enabled and an interrupt is generated by the interrupt source selected by bits 3 and

2 (IRS1 and IRS0), this bit is set and an interrupt is generated into the CPU.

This bit can be read and written. However, only "0" can be written to this bit; even if "1" is written

to this bit, it does not change. In a read-write-modify instruction, the value that is read is "1",

regardless of the bit value.

127

2.9 PPG (Programmable Pulse Generator) Timer

[Bits 3, 2] IRS1, IRS0: Interrupt source selection bits

IRS1

IRS0

Interrupt source

0

1

Valid trigger

Counter borrow

Rising edge of normal polarity PPG, or falling edge of inverse

polarity PPG

1

0

1

Counter borrow, rising edge of normal polarity PPG, or falling

edge of inverse polarity PPG

[Bit 1] POEN: PPG pin function enable bit

0

1

General-purpose I/O pin

PPG output pin

[Bit 0] OSEL: PPG output inversion bit

0

1

Normal polarity

Inverted polarity

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Chapter 2: HARDWARE

2.9 PPG (Programmable Pulse Generator) Timer

(2) Period setting register (PCSR)

15

14

13

12

11

10

9

8

Bit No. Þ

00031, 39H

Address

7

6

5

4

3

2

1

0

Bit No. Þ

Address

00030, 38H

Read/write Þ Write only

Initial value Þ Indeerminate

(3) Duty factor setting register (PDUT)

15

14

13

12

11

10

9

8

Bit No. Þ

00033, 3BH

Address

7

6

5

4

3

2

1

0

Bit No. Þ

Address

00032, 3AH

Read/write Þ Write only

Initial value Þ Indeerminate

When setting or overwriting the period setting register, always write the period setting register first,

followed by the duty factor setting register.

The timing for overwriting both the period setting register and the duty factor setting register is the

same as the counter borrow timing.

If the same value is set in both the cycle setting register and the duty factor setting register, "all high" is

output in normal polarity, and "all low" is output when the polarity is inverted.

If PCSR is set so that it is less than PDUT, the PPG output is undefined.

129

2.9 PPG (Programmable Pulse Generator) Timer

2.9.4 Explanation of PWM Operation

PWM operation timing charts

(1) When retriggering is disabled

Rising edge detected

The trigger is ignored

Trigger

m

n

0

PPG

(1)

(2)

(1) = T(n+1) µs T: Count clock cycle

m: PCSR value

n: PDUT value

(2) = T(m+1) µs

(2) When retriggering is enabled

Rising edge detected

Restarted by trigger

Trigger

m

n

0

PPG

(1)

(2)

PWM operation

During PWM operation, it is possible to output pulses continuously once the trigger is detected. The

output pulse cycle can be controlled by changing the value of PCSR. In addition, the duty ratio can

be controlled by changing the PDUT value.

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2.9 PPG (Programmable Pulse Generator) Timer

Explanation of one-shot operation

One-shot operation timing charts

(1) When retriggering is disabled

Rising edge detected The trigger is ignored

Trigger

m

n

0

PPG

(1)

(2)

(2) When retriggering is enabled

Rising edge detected

Restarted by trigger

Trigger

m

n

0

PPG

(1)

(2)

One-shot operation

In one-shot operation, it is possible to output a single pulse of any width in response to the trigger.

If retriggering is enabled, the counter is reloaded if an edge is detected during operation.

131

2.9 PPG (Programmable Pulse Generator) Timer

Interrupt source and timing diagram (PPG output is normal polarity)

Trigger

Load

Clock

Count value

X

0003

0002

0001

0000

0003

PPG

Interrupt

Valid edge

Compare match

Borrow

Output examples of all low or all high PPG output

PPG

Reduce

the duty

factor Þ

•

A "1" is written to PGMS (mask bit) by an interrupt

generated by a borrow. In addition, it is also possible

to output a PWM waveform without outputting any

spikes if a "0" is written to PGMS (mask bit) by an

interrupt generated by a borrow.

Þ

PPG

Increase

the duty

factor Þ

•

The same value as is in the period setting register is

written to the duty factor setting register by an interrupt

generated by a compare match.

Þ

132

Chapter 2: HARDWARE

2.10 LCD Controller/Driver

The LCD controller/driver consists of a display controller that generates segment signals and common

signals in accordance with the display data and memory data, and also a segment driver and common

driver that are capable of directly driving an LCD panel.

The main functions are listed below.

(1) LCD direct drive

(2) Four common outputs (COM0 to COM3),and 32 segment outputs (SEG0 to SEG31)

(3) 16 bytes of display memory built in

(4) The duty factor can be selected as 1/2, 1/3, or 1/4

(5) The main clock (4 MHz) and the subclock (32kHz) can be selected as a drive clock source

(6) SEG16 to SEG31 can be used as open-drain ports

(1) Register list

Address:

15

8 7

0

000080H

000081^H

LCR1

LCR0

LCDC control register 1/0 (LCR0/LCR1)

4MHz

32KHz

LCDC control register

LCR

Power supply input (V0 to V3)

4

/

COM0

COM1

COM2

COM3

Timing controller

SEG00

SEG01

SEG02

32

/

SEG03

SEG04

Display RAM (16 bytes)

SEG27

SEG28

SEG29

SEG30

SEG31

Controller

Drivers

Fig. 2.10.1 LCDC Block Diagram

133

2.10 LCD Controller/Driver

(2) Detailed register description

(a)LCDC control register 0 (LCR0)

7

6

5

4

3

2

1

0

Initial value

001 0000B

FP0

000080H

CSS LCEN VSEL BK MS1 MS0 FP1

(R/W) (R/W) (R/W)

(R/W) (R/W) (R/W) (R/W)

(R/W)

[Bit 7] CSS (clock source select)

This bit is the frame period generation clock selection bit.

0

1

Main clock

Subclock

[Bit 6] LCEN

This bit is the clock mode operation enable bit.

0

1

Stop in clock mode

Run in clock mode

[Bit 5] VSEL

This bit is the LCD drive power supply control bit.

0

1

Connection with the built-in separation resistor is interrupted.

Connection with the built-in separation resistor is made.

[Bit 4] BK (blanking)

This bit is the display/display blanking selection bit. With display blanking, the segment output is

the non-selected waveform.

0

1

Display

Display blanking

[Bit 3] MS1

[Bit 2] MS0 (mode select 1, 0)

These bits are the display mode selection bits. These bits are set as shown in the following table.

MS1

MS0

Display mode

Number of time divisions: N

0

1

0

1

0

1

LCD operation stop

–

2

3

4

1/2 duty factor output mode

1/3 duty factor output mode

1/4 duty factor output mode

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Chapter 2: HARDWARE

2.10 LCD Controller/Driver

[Bit 1] FP1

[Bit 0] FP0 (frame period 1, 0)

These bits are the LCD clock period selection bits. The frame frequency is as shown in the

following table. Calculate the optimum frame frequency for the LCD module being used and set the

register accordingly.

Frame frequency

FP1

FP0

CCS=1

256 Hz (N=4)

CCS=0

244 Hz (N=4)

0

1

0

1

0

1

fch/(2¹²× N)

fch/(2¹³× N)

fch/(2¹⁴× N)

fch/(2¹⁵× N)

fcl/(2⁵× N)

fcl/(2⁶× N)

fcl/(2⁷× N)

fcl/(2⁸× N)

122 Hz (N=4)

61 Hz (N=4)

30.5 Hz (N=4)

128 Hz (N=4)

64 Hz (N=4)

32 Hz (N=4)

N: Number of time divisions

fch Main clock oscillating frequency (4 MHz)

fcl: Subclock oscillating frequency (32 KHz)

(b)Mister 1 (LCR1)

15

14

–

13

–

12

11

10

9

8

Initial value

0--0 0000B

Reserved

000081H

SEG3 SEG2 SEG1 SEG0

(R/W) (R/W) (R/W) (R/W)

–

[Bits 14, 13] Unused bits.

[Bits 15, 12] Reserved bits. Always write "0" to these bits.

[Bit 11] SEG3

This is a segment/port switching bit. This bit is used to select the function for P77/SEG31 to P74/

SEG28.

0

1

General-purpose input/output port

Segment output

[Bit 10] SEG2

This is a segment/port switching bit. This bit is used to select the function for P73/SEG27 to P70/

SEG24.

0

1

General-purpose input/output port

Segment output

[Bit 9] SEG1

This is a segment/port switching bit. This bit is used to select the function for P67/SEG23 to P64/

SEG20.

0

1

General-purpose input/output port

Segment output

135

2.10 LCD Controller/Driver

[Bit 8] SEG0

This is a segment/port switching bit. This bit is used to select the function for P63/SEG19 to P60/

SEG16.

0

1

General-purpose input/output port

Segment output

136

Chapter 2: HARDWARE

2.10 LCD Controller/Driver

(3) Display RAM

The LCD controller/driver has built-in 16 ´ 8-bit RAM for segment output signal generation. The

contents of this RAM are output from the segment output pins automatically read out in

synchronization with the common signal selection timing.

There are 32 segment signals, corresponding to 16 locations in display RAM. Bit 0 and bit 4 of each

location are in sync with the selection timing for COM0, bit 1 and bit 5 are in sync with selection timing

for COM1, bit 2 and bit 6 are in sync with selection timing for COM2, and bit 3 and bit 7 are in sync

with selection timing for COM3. If a bit is "1", it is converted to the selected voltage for output; if "0",

it is converted to the non-selected voltage for output. However, during a reset, the common pins

become common outputs, and the segment 17 to 31 outputs become general-purpose input/output ports.

In addition, COM0 and 1 and SEG0 to 15 go low during a reset, so the LCD display is blanked.

Note that, because this operation is performed without any connection to the operation of the CPU, the

display RAM can be read/written with any timing.

When SEG16 to SEG31 are used as general-purpose ports, the most significant 8 bytes can be used as

normal RAM.

Address

SEG00

SEG01

SEG02

SEG03

SEG04

SEG05

b3

b7

b3

b7

b3

b7

b2

b6

b2

b6

b2

b6

b1

b5

b1

b5

b1

b5

b0

b4

b0

b4

b0

b4

070^H

071^H

072^H

SEG16

SEG17

SEG18

SEG19

b3

b7

b3

b7

b2

b6

b2

b6

b1

b5

b1

b5

b0

b4

b0

b4

078^H

079^H

î

ï

í

ï

ì

SEG28

SEG29

SEG30

SEG31

b3

b7

b3

b2

b6

b2

b1

b5

b1

b0

b4

b0

07E^H

07F^H

Multiplexed with ports 6 and 7

b7

b6

b5

b4

COM2

COM1

COM0

COM3

137

2.10 LCD Controller/Driver

(4) Explanation of operation

First, the data to be displayed is written into display RAM. Next, the value corresponding to the LCD

panel to be used is set into the LCR (LCD control register). Next, if a clock signal is being supplied, the

LCD panel drive waveform is output according to the data in the display RAM. Either a high-speed

clock or a watch clock can be selected as the clock source, and the clock source can be switched during

the LCD display operation. However, switching can cause flickering on the screen, so it is better to

first stop the display operation via blanking, etc., and then switch the clock.

A two-frame AC-converted waveform is used for the display drive output. The following table show

the possible combinations of bias and duty factor. Note that 1/2 bias should not be used. Examples of

display waveforms are shown below and on the pages that follow.

1/2 duty factor 1/3 duty factor 1/4 duty factor

1/3 bias

: Recommended mode

When using 1/2 duty mode, the COM2 and COM3 output waveforms are the non-selected level

waveforms. The same applies to COM3 in 1/3 duty factor mode. However, when the port was selected

using the COM0 and COM1 bits, the ports are used as general-purpose I/O ports.

If the LCD operation has been halted, a low level waveform is output for both commons and segments.

However, if SEG16 to SEG31 have been specified as general-purpose ports by their SEG bits, the

segment data is not output.

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2.10 LCD Controller/Driver

(5) LCD drive output waveform example

(1) 1/3 bias, 1/2 duty factor waveform

COM2 COM1 COM0

COM3

SGn

–

0

1

SGn+1

Example of display RAM

V^L3

VL2

VL1

VL0 = VSS

COM0

COM1

VL3

VL2

VL1

VL0 = VSS

VL3

COM2

COM3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

SG ⁿ

VL0 = VSS

VL3

VL2

VL1

SG n+1

VL0 = VSS

1 frame

139

2.10 LCD Controller/Driver

(2) 1/3 bias, 1/3 duty factor waveform

COM2 COM1 COM0

COM3

SGⁿ

–

1

0

1

SGn+1

Example of display RAM

VL3

VL2

VL1

VL0 = VSS

COM0

COM1

COM2

COM3

SG ⁿ

VL3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

SG n+1

VL0 = VSS

1 frame

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Chapter 2: HARDWARE

2.10 LCD Controller/Driver

(3) 1/3 bias, 1/4 duty factor waveform

COM2 COM1 COM0

COM3

SGⁿ

0

1

0

1

SGn+1

Example of display RAM

VL3

VL2

VL1

VL0 = VSS

COM0

COM1

COM2

COM3

SG ⁿ

VL3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

VL0 = VSS

VL3

VL2

VL1

SG n+1

VL0 = VSS

1 frame

141

2.10 LCD Controller/Driver

(6) Voltage settings for LCD drive power supply pins (V3, V2, V1, V0)

Set the voltage for the LCD drive power supply pins (V3, V2, V1, V0) as shown in the following table.

V3

V2

V1

V0

1/3 bias

V^LCD

2/3VLCD

1/3VLCD

GND

V^LCD: LCD operating voltage

An example of LCD drive power supply connections are shown below.

Vcc

V3

V2

VLCD

V1

V0

1/3 bias

Built-in separation resistor

Vcc

V3

The built-in separation resistance is connected as shown

in the figure at right. Setting the VSEL bit to "1" puts the

built-in separation resistor in the conductive state.

Therefore, set VSEL to "1" when no external separation

resistor is connected, and set VSEL to "0" when not

connected.

2R

R

In addition, because the V0 pin is connected on chip to

Vss via a transistor, when using an external resistor

separation circuit, it is possible to shutoff the current

flowing to the resistor with the LCDC stopped by

connecting the Vss side to the V0 pin only.

V2

R

V1

V0

R

In the right diagram, LCDC enable is inactive when LCD

operation is stopped and in watch mode (LCEN = 0).

Note: When pins that also serve as ports are used as

SEG/COM outputs, use the port in the input state

(DDR = 0).

VSEL

LCDC enabled

Internal equivalent circuit

142

Chapter 2: HARDWARE

2.11 DTP/External Interrupts

DTP (Data Transfer Peripheral) is positioned between peripherals external to the device and the F²MC-

16L CPU. The DTP is a peripheral circuit that accepts DMA requests or interrupt requests generated by

the external peripheral, passes the request to the F²MC-16L CPU, and then starts up the extended

intelligent I/O service or interrupt processing. In the case of the extended intelligent I/O service, the

request level can be either high or low; in the case of an external interrupt request, the request level can be

either high, low, rising edge, or falling edge.

2.11.1 Register List

15 14 13 12 11 10

EIRR

9

8

7

6

5

4

3

2

1

0

EIRR:ENIR

ENIR

000029^H,28H

ELVR

00002B^H,2AH

2.11.2 Block Diagram

F²MC-16 bus

4

Interrupt/DTP enable register

Source of

interrupt F/F

4

8

3

Request input

Gate

Edge detection circuit

Interrupt/DTP source register

Request level setting register

Fig. 2.11.1 Block Diagram

143

2.11 DTP/External Interrupts

2.11.3 Detailed Register Description

(1) Interrupt/DTP enable register (ENIR)

■ Register configuration

Ü Bit no.

Interrupt/DTP enable register

Address : 000028H

7

6

5

4

3

2

1

0

ENIR

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(0)

■ Register contents

The ENIR register decides which of the device pins to use as external interrupt/DTP request inputs, and

executes the function that generates requests to the interrupt controller. The pins corresponding to the

bits set to "1" in this register are used as external interrupt/DTP request inputs, and the function that

generates requests to the interrupt controller is executed. The pins corresponding to the bits set to "0" in

this register are retained as external interrupt/DTP request sources, but no requests to the interrupt

controller are generated.

(2) Interrupt/DTP source register (EIRR)

■ Register configuration

Ü Bit no.

Interrupt/DTP register

Address : 000029H

15

14

13

12

11

10

9

8

EIRR

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(0)

■ Register contents

Reading from the EIRR register indicates that there is a corresponding external interrupt/DTP request,

and writing to the register clears the contents of the flip-flop contents indicating this request. If this

register is read, a "1" indicates that there is an external interrupt/DTP request on the pin corresponding

to that bit. If a "0" is written to this register, the request flip-flop for the corresponding bit is cleared.

Writing a "1" has no effect. A "1" is returned when read using a read-modify-write instruction.

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Chapter 2: HARDWARE

2.11 DTP/External Interrupts

(3) Request level setting register (ELVR)

■ Register configuration

Ü Bit no.

Request level register

7

6

5

4

3

2

1

0

LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4

Address : 00002BH

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(0)

7

(0)

6

(0)

5

(0)

4

(0)

3

(0)

2

(0)

1

(0)

0

Ü Bit no.

ELVR

LB3 LA3 LB2 LA2 LB1 LA1

LB0 LA0

00002AH

(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (0) (0) (0) (0)

Read/write Þ

Initial valueÞ

■ Register contents

The ELVR register selects request detection. Two bits are assigned to one pin, and their meanings are

shown in the table below. When the request input is at level, if an input is active even after being

cleared, the input is set again.

Table 2.11.1 ELVR Assignment Table

LBx

LAx

Operation

0

1

0

1

0

1

Request detected at low level

Request detected at high level

Request detected at rising edge

Request detected at falling edge

2.11.4 Explanation of Operation

(1) External interrupt operation

If, after an external interrupt request is set, the request set by the ELVR register is input to the

corresponding pin, this resource generates an interrupt request signal to the interrupt controller. When

the result of recognition, within the interrupt controller, of priority levels for interrupts that were

generated simultaneously indicates that the interrupt from this resource has the highest priority, the

interrupt controller generates an interrupt request to the F²MC-16 CPU. The F²MC-16 CPU compares

the interrupt request with the ILM bits in its own internal CCR register, and if the requested level is

higher than the ILM bits, then immediately after execution of the current instruction is completed, the

hardware interrupt processing microprogram is started.

F²MC-16 CPU

External interrupt/DTP

Interrupt controller

Other requests

ELVR

EIRR

ENIR

ICR yy

IL

CMP

ICR xx

ILM

INTA

source

Fig. 2.11.2 External Interrupt Operation

145

2.11 DTP/External Interrupts

In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the

interrupt controller, recognizes on the basis of that information that the request in question is for

interrupt processing, and branches to the interrupt processing microprogram. The interrupt processing

microprogram reads the interrupt vector area and generates an interrupt acknowledge to the interrupt

controller. After the microprogram transfers the jump destination address for the macro instruction

(generated from the vector) to the program counter, the user interrupt processing program is executed.

(2) DTP operation

For the initialization process in the user program, when the extended intelligent I/O service is started,

register addresses distributed between the addresses from 000000^Hto 00FFFFH are set in the I/O

address pointers within the extended intelligent I/O service descriptors, and the memory buffer starting

address is set in the buffer address pointer.

The DTP operation sequence is roughly the same as that for external interrupts, and is exactly the same

up to the point when the CPU starts the hardware interrupt processing microprogram. In the case of the

DTP, because the ISE bit read by the CPU through the hardware interrupt processing microprogram

indicates the DTP, control is passed to the extended intelligent I/O service processing microprogram.

Once the extended intelligent I/O service is started up, a read or write signal is sent to the external

peripheral being addressed, and the transfer operation between that peripheral and this chip is

performed. The external peripheral should withdraw its interrupt request to this chip within three

machine cycles after the transfer is started. When the transfer is completed, the descriptors are updated,

etc., and then the signal that clears the transfer source is sent to the interrupt controller. After receiving

the signal clearing the transfer source, this resource clears the flip-flop that is holding the source, and

prepares for the next request from the pins. For details on extended intelligent I/O service processing,

refer to the programming manual.

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2.11 DTP/External Interrupts

• edge request or 'H' level request

Source of interrupt

Internal operation

Address bus pins

Data bus pins

Read signal

* When the extended intelligent I/O service is

transferring data from an I/O register to memory

Descriptor

selection, read

Read address Write address

Read data

Write data

(1)

(2)

Write signal

Withdraw within three machine cycles

Fig. 2.11.3 External Interrupt Withdrawal Timing at End of DTP Operation

Because there is no external bus, subsequent processing does not apply.

Internal bus

Data, address bus

(1)

(2)

INT

IRQ

DTP

CORE

MEMORY

Cancel within three machine

cycles after completion of transfer

MB90620 Series

Fig. 2.11.4 Simplified Example of Interface with External Peripherals

147

2.11 DTP/External Interrupts

(3) Switching between external interrupt requests and DTP requests

Switching between external interrupt requests and DTP requests is accomplished through the setting of

the ISE bits in the ICR register corresponding to this resource within the interrupt controller. Because

an ICR is assigned to each pin, a pin for which a "1" is written in the ISE bit in the corresponding ICR

is used as a DTP request; if a "0" is written, operation proceeds for an external interrupt request.

Interrupt controller

ICR xx

ICR yy

0

1

F²MC-16

CPU

External interrupt/DTP

DTP

External interrupt

Fig. 2.11.5 Switching between External Interrupt Requests and DTP Requests

2.11.5 Notes on Usage

(1) Requirements for externally connected peripherals when DTP is used

External peripherals to be supported by the DTP must be able to automatically clear the request by

performing a transfer. In addition, once the transfer operation is started, if the transfer request is not

withdrawn within three machine cycles (tentative value), this resource will handle that transfer request

as if it were the next transfer request.

(2) Recovery from standby

With edge requests, recovery is not made from the clock stop mode standby state, so set level requests.

(3) External interrupt/DTP operating procedure

Use the following procedure when setting a register that exists within the external interrupt/DTP:

1. Disable the bits that are the object of the enable register.

2. Set the bits that are the object of the request level setting register.

3. Clear the bits that are the object of the source register.

4. Enable the bits that are the object of the enable register.

(Steps 3 and 4 can be performed simultaneously by word specification.)

When setting a register within this resource, the enable register must be set to the disabled state. In

addition, the source register must always be cleared before restoring the enable register to the enabled

state. This is necessary in order to avoid the inadvertent generation of an interrupt source when setting

a register or while interrupts are enabled.

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2.11 DTP/External Interrupts

(4) External interrupt request level

(1) When the request level is set to edge requests, a pulse width of at least three machine cycles is

necessary in order for an edge to be detected.

(2) When a level is set for the request input level, even if a request is input from an external source

and then subsequently withdrawn, the request to the interrupt controller remains active due to the

existence of the internal source retention circuit. To withdraw a request to the interrupt

controller, it is necessary to clear the source retention circuit.

Interrupt

source

Source F/F

(source retention circuit)

To interrupt

controller

Level detection

Enable gate

Source is retained unless cleared

Fig. 2.11.6 Clearing the Source Retention Circuit When Level Is Set

High level

Interrupt source

Interrupt request to interrupt controller

Inactive since source flip-flop was cleared

Fig. 2.11.7 Interrupt Source and Interrupt Request to Interrupt Controller When Interrupts Were Enabled

149

2.12 Clock Output Module

■ Clock output enable register (CKOT)

This clock output is a divided clock derived from the machine clock.

Initial value

----0000

Bit

7

6

5

4

3

2

1

0

Address : 0001EH

–

CKEN FRQ2 FRQ1 FRQ0

R/W R/W R/W R/W

[Bit 3] CKEN

CKOT output enable bit

0

Normal port

CKOT output

1

[Bits 2-1] FRQ2, FRQ1, FRQ0

These bits select the clock output frequency.

FRQ2 FRQ1 FRQ0 Output clock f = 16 MHz

f = 8 MHz

250 ns

500 ns

1 µs

f = 4 MHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f ÷ 2

125 ns

250 ns

500 ns

1 µs

500 ns

1 µs

f ÷ 4

f ÷ 8

2 µs

f ÷ 16

f ÷ 32

f ÷ 64

f ÷ 128

f ÷ 256

2 µs

4 µs

2 µs

4 µs

8 µs

4µs

8 µs

16 µs

32 µs

64 µs

8 µs

16 µs

32 µs

16 µs

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Chapter 2: HARDWARE

2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

The watchdog timer consists of a 2-bit watchdog counter that uses as its clock source the carry signal from

the 18-bit timebase timer or the 15-bit watch timer, a control register, and a watchdog reset control block.

The timebase timer consists of an 18-bit timer and a circuit that controls interval interrupts. Note that the

timebase timer uses the main clock, regardless of the MCS bit and the SCS bit in the CKSCR.

The timekeeping timer consists of a 15-bit timer and a circuit that controls interval interrupts. Note that the

watch timer uses the subclock, regardless of the MCS bit and the SCS bit in the CKSCR.

Fig. 2.13.1 shows the configuration of the watchdog timer, timebase timer, and the watch timer blocks.

2.13.1 Register List

Ü Bit no.

Watchdog timer control register

Address : 0000A8H

7

6

5

4

3

2

1

0

WDTC

PONR STBR WRSTERST SRST WTE WT1 WT0

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R) (W)

(W) (W)

Read/write Þ

Initial valueÞ

(X)

Ü Bit no.

Timebase timer control register

Address : 0000A9H

15

14

13

12

11

10

9

8

TBTC

Reserved

–

TBIE TBOF TBR TBC1 TBC0

(–)

(1)

(–)

(–) (R/W) (R/W) (R) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(–)

(0)

Ü Bit no.

Watch timer control register

0000AAH

7

6

5

4

3

2

1

0

WTC

WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0

(R/W) (R) (R/W) (R/W) (R) (R/W) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(1)

(X)

(0)

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2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

2.13.2 Block Diagram

Main clock

TBTC

2¹²

2¹⁴

Clock input

Timebase timer

TBC1

2¹⁶

Selector

S

2¹⁸

TBC0

TBR

TBTRES

2¹⁴2¹⁶2¹⁷2¹⁸

TBIE

AND

Q

R

TBOF

Timebase

interrupt

WDTC

WT1

Watchdog reset

generation circuit

2-bit counter

Selector

To WDGRST

internal reset

generation circuit

OF

WT0

WTE

CLR

WTC

AND

WDCS

SCM

Power-on reset

/subclock stop

S

R

SCE

Q

2¹⁰

2¹⁰2¹³2¹⁴2¹⁵

2¹³

WTC1

2¹⁴

Selector

S

2¹⁵

Watch timer

WTC0

WTR

WTRES

Clock input

WTIE

AND

Subclock

Q

R

WTOF

Clock

interrupt

WDTC

PONR

STBR

WRST

ERST

SRST

From power-on

generation

From hardware

standby control

circuit

RSTX pin

From RST bit of

STBYC register

Fig. 2.13.1 Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram

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Chapter 2: HARDWARE

2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

2.13.3 Detailed Register Description

(1) Watchdog timer control register (WDTC)

■ Register configuration

Ü Bit no.

Watchdog timer control register

Address : 0000A8H

7

6

5

4

3

2

1

0

WDTC

PONR STBR WRST ERST SRST WTE WT1 WT0

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R) (W)

(X) (X)

(W) (W)

(X) (X)

Read/write Þ

Initial valueÞ

■ Register contents

This register consists of bits governing various types of control over the watchdog timer and bits used

to identify reset sources.

■ Bit contents

[Bits 7 to 3] PONR, STBR, WRST, ERST, SRST

These are the reset source flags. When a reset source is generated, these bits are set as shown in

Table 2.13.1. These bits are all cleared to "0" after the WDTC is read. This is a read-only register.

Note that during power-on only, the contents of the bits that indicate sources other than power-on

are not guaranteed. Therefore, software should be designed to ignore the other bits when the PONR

bit is "1".

Table 2.13.1 Correspondence between the Contents of the Reset Source Bits and Reset Sources

Reset source

PONR

STBR

WRST

ERST

SRST

Power on

1

–

Hardware

standby

*

1

*

Watchdog timer

External pin

RST bit

*

1

*

1

*

1

("*": Indicates that the previous value is retained.)

[Bit 2] WTE

Writing a "0" to this bit while the watchdog timer is stopped puts the watchdog timer in the

operating state. Writing a second or subsequent "0" to this bit clears the watchdog timer counter.

Writing a "1" has no effect.

The watchdog timer is stopped by power-on, hardware standby, and a watchdog timer reset. When

read, a "1" is returned.

153

2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

[Bits 1, 0] WT1, WT0

These bits select the watchdog interval time. Only the data written when the watchdog timer is

started up is valid. Data written to these bits at any time other than watchdog startup is ignored.

Note that the clock that is input to the watchdog timer is selected according to the result of ANDing

the WDCS bit of the WTC and the SCM bit of the LPMCR. In other words, if WDCS is set to "1",

then the timebase timer output can be selected if the main clock and the PLL clock are selected, and

the watch timer output can be selected if the subclock is selected.

The interval time settings are shown in Table 2.13.2.

These bits are write-only bits.

Table 2.13.2 Watchdog Timer Interval Selection Bits

Interval Time

(Source oscillation: 4 MHz)

Minimum

WDCS/

SCM

WT1

WT0

Maximum

1

0

1

0

1

0

1

0

1

0

1

0

1

Approx. 3.58 ms

Approx. 4.61 ms

Approx. 18.43 ms

Approx. 73.73 ms

Approx. 14.33 ms

Approx. 57.23 ms

Approx. 458.75 ms Approx. 589.82 ms

Approx. 0.109 s

Approx. 0.875 s

Approx. 1.75 s

Approx. 3.5 s

Approx. 0.141 s

Approx. 1.125 s

Approx. 2.25 s

Approx. 4.5 s

Note: The maximum interval value is the value when the time base counter or the clock counter are

not reset during watchdog operation.

(2) Timebase timer control register (TBTC)

■ Register configuration

Ü Bit no.

Timebase timer

Address : 0000A9H

15

14

–

13

–

12

11

10

9

8

TBTC

Reserved

TBIE TBOF TBR TBC1 TBC0

(–)

(1)

(–)

(–) (R/W) (R/W) (R/W) (R/W) (R/W)

(–) (0) (0) (0) (0) (0)

Read/write Þ

Initial valueÞ

■ Register contents

This register controls the timebase timer operation and the interval interrupt time.

■ Bit contents

[Bit 15] Test bit

This bit is a test bit. Always write "1" when writing this bit.

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2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

[Bits 14, 13] Open

[Bit 12] TBIE

This bit enables interval interrupts by the timebase timer. When this bit is "1", interrupts are

enabled; when this bit is "0", interrupts are disabled. This bit is initialized to "0" by a reset. This bit

can be read and written.

[Bit 11] TBOF

This bit is the timebase timer interrupt request flag. If the TBIE bit is "1" and the TBOF bit is "1",

an interrupt request is generated. This bit is set to "1" at the intervals set by the TBC1 and TBC0

bits. This bit is cleared by writing a "0", by switching to stop mode or hardware standby mode, and

by a reset. Writing "1" to this bit has no meaning.

When this bit is read by a read-modify-write instruction, a "1" is read.

[Bit 10] TBR

This bit clears all of the timebase timer counter bits to "0". The time base counter is cleared by

writing a "0" to these bits. Writing "1" to these bits has no meaning. Reading this bit returns a "1".

[Bits 9, 8] TBC1, 0

These bits set the timebase timer interval. The interval settings are shown in Table 2.13.3. These

bits are initialized to "00" by a reset. These bits can be read and written.

Table 2.13.3 Timebase Timer Interval Selection

Interval time when source

TBC1

TBC0

oscillation is 4 MHz

0

1

0

1

0

1

1.024 ms

4.096 ms

16.384 ms

131.072 ms

(3) Watch timer control register (WTC)

■ Register configuration

Ü Bit no.

Watchdog timer control register

Address : 0000AAH

7

6

5

4

3

2

1

0

WTC

WDCS SCE WTIE WTOF WTR WTC2 WCT1WCT0

(R/W) (R) (R/W) (R/W) (R/W) (R) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(1)

(X)

(0)

155

2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

■ Register contents

This register controls the watch timer and the interval interrupt time.

■ Bit contents

[Bit 7] WDCS

This bit selects whether to use the clock signal from the watch timer or from the timebase timer for

the watchdog timer input clock when the main clock and PLL clock are selected. When this bit is

"0", the clock signal from the watch timer is selected; when this bit is "1", the clock signal from the

timebase timer is selected. In short, if WDCS is set to "1", then the timebase timer output can be

selected if the main clock and the PLL clock are selected, and the watch timer output can be selected

if the subclock is selected.

This bit is initialized to "1" by a power-on reset.

Note: When WDCS is set to "1", because the timebase timer output and the watch timer output are

asynchronous, there is a possibility that the watchdog timer count may advance. Therefor,

when WDCS is set to "1", it is necessary to clear the watchdog timer before and after

changing the clock mode.

[Bit 6] SCE

This bit indicates that the subclock oscillation stabilization waiting period has elapsed. When this

bit is "0", it indicates that the oscillation stabilization period is currently in progress. The oscillation

stabilization period is fixed at 2¹⁴cycles (subclock). This bit is initialized to "0" by a power-on reset

and by stopping.

[Bit 5] WTIE

This bit enables interval interrupts by the watch timer. When this bit is set to "1", interrupts are

enabled; when set to "0", interrupts are disabled. This bit is initialized to "0" by a reset. This bit can

be read and written.

[Bit 4] WTOF

This bit is the watch timer interrupt request flag. When the WTIE bit is "1", an interrupt request is

generated if WTOF is set to "1". This bit is set to "1" at the intervals set by the WTC1 and WTC0

bits. This bit is cleared by writing a "0", by switching to stop mode or hardware standby mode, and

by a reset. Writing "1" to this bit has no meaning.

When this bit is read by a read-modify-write instruction, a "1" is read.

[Bit 3] WTR

This bit clears all of the watch timer counter bits to "0". The clock counter is cleared by writing a

"0" to this bit. Writing "1" to this bit has no meaning. Reading this bit returns a "1".

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Chapter 2: HARDWARE

2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

[Bits 2, 1, 0] WTC2, WTC1, WTC0

These bits set the watch timer interval. The interval settings are shown in Table 2.13.4. These bits

are initialized to "00" by a reset. These bits can be read and written.

When writing these bits, clear bit 4 (WTOF) at the same time.

Table 2.13.4 Watch Timer Interval Selection

Interval time when

WTC2 WTC1

WTC0

subclock is 32 kHz

15.625 ms

31.25 ms

62.5 ms

0.125 s

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.250 s

0.500 s

1.000 s

–

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2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

2.13.4 Explanation of Operation

(1) Watchdog timer

The watchdog timer function makes it possible to detect when a program is running out of control.

When a "0" is not written to the WTE bit in the watchdog timer within the specified time because the

program is running out of control, etc., a watchdog reset request is generated by the watchdog timer.

■ Startup method

The watchdog timer is started up by writing a "0" to the WTE bit in the WDTC register while the

watchdog timer is stopped. In this case, the watchdog timer reset generation interval is set by the WT1

and WT0 bits at the same time. Only the data set at startup is valid for the interval setting.

■ Hindrances to the watchdog timer reset

Once the watchdog timer is started, it is necessary for the software to clear the two-bit watchdog timer

regularly. Specifically, it is necessary to regularly write a "0" to the WTE bit in the WDTC register.

The watchdog counter is a two-bit counter that uses the time base counter carry signal as its clock

source. Therefore, if the timebase timer is cleared, the actual watchdog reset generation time may be

longer than the set time.

Fig. 2.13.2 illustrates the operation of the watchdog timer.

Timebase timer

Watchdog timer

WTE write

00

01

10

00

01

10

11

00

Watchdog start

Watchdog clear

Watchdog reset generation

Fig. 2.13.2 Watchdog Timer Operation

■ Watchdog stop

Once the watchdog timer is started, it is initialized and stopped only by a reset caused by power-on,

hardware standby, and the watchdog. Although resets by external pins or software clear the watchdog

counter, the watchdog function does not stop operating.

■ Miscellaneous

In addition to being cleared by writing to the WTE bit, the watchdog timer is also cleared by the

generation of a reset, by transitioning to sleep mode or stop mode, and by the hold acknowledge signal.

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2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

(2) Timebase timer

The timebase timer functions as the clock source for the watchdog counter, as the timer for the main

clock and PLL clock oscillation stabilization wait, and as an interval timer that generates interrupts at a

given period.

■ Timebase timer

The timebase timer is an 18-bit counter that counts the source oscillation input which is used to

generate the machine clock. The timebase timer always continues its counting operation as long as the

source oscillation is being input. The timebase timer is cleared by: power-on reset, shifting to stop

mode or hardware standby mode, shifting from the main clock to the PLL clock through the setting of

the MCS bit in the CKSCR register, shifting from the main clock to the subclock through the setting of

the SCS bit in the CKSCR register, and writing "0" to the TBR bit in the TBTC register.

The watchdog counter and the interval interrupts, both of which utilize the timebase timer output, are

affected by the timebase timer being cleared.

■ Interval interrupt function

This function generates interrupts at a given period based on the timebase timer counter carry signal.

This function sets the TBOF flag at a regular interval, which is set by the TBC1 and TBC0 bits in the

TBTC register. The timing for the setting of this flag is based on the time when the timebase timer was

last cleared.

If a shift is made from the main clock mode to the PLL clock mode, the timebase timer is cleared, since

it is used as the timer for the PLL clock oscillation stabilization waiting period.

In addition, if a shift is made from the main clock mode to the subclock mode, the timebase timer is

cleared, since it is used as the timer for the main clock oscillation stabilization waiting period.

If a shift is made to stop mode or hardware standby mode, the TBOF flag is cleared at the same time as

the mode shift, since the timebase timer is used for the oscillation stabilization waiting period during

recovery.

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2.13 Watchdog Timer, Timebase Timer, and Watch Timer Functions

(3) Watch timer

The watch timer functions as the clock source for the watchdog counter, as the timer for the subclock

stabilization wait, and as an interval timer that generates interrupts at a given period.

■ Watch timer

The watch timer is a 15-bit counter that counts the source oscillation input which is used to generate the

machine clock. The watch timer always continues its counting operation as long as the source

oscillation is being input. The watch timer is cleared by: power-on reset, shifting to stop mode or

hardware standby mode, and writing "0" to the WTR bit in the WTC register.

The watchdog counter and the interval interrupts, both of which utilize the watch timer output, are

affected by the watch timer being cleared.

■ Interval interrupt function

This function generates interrupts at a given period based on the clock counter carry signal. This

function sets the WTOF flag at a regular interval, which is set by the WTC1 and WTC0 bits in the

WDTC register. The timing for the setting of this flag is based on the time when the watch timer was

last cleared.

If a shift is made to stop mode or hardware standby mode, the WTOF flag is cleared at the same time as

the mode shift, since the watch timer is used for the oscillation stabilization waiting period during

recovery.

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Chapter 2: HARDWARE

2.14 Delay Interrupt Generation Module

The delay interrupt generation module generates interrupts used for task switching. By using this module,

it is possible to generate and withdraw interrupt requests to the F²MC-16L.CPU via software.

2.14.1 Register List

Ü Bit no.

Address :

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

DIRR

00009FH

R0

(–)

(–) (R/W)

(–) (0)

Read/write Þ

Initial valueÞ

2.14.2 Block Diagram

2

F MC-16 bus

Delay interrupt source generation/cancellation decoder

Source latch

Fig. 2.14.1 Block Diagram

2.14.3 Detailed Register Description

(1) Delay interrupt source generation/cancellation decoder (DIRR)

■ Register configuration

Ü Bit no.

Address :

15

–

14

–

13

–

12

–

11

–

10

–

9

–

8

DIRR

00009FH

R0

(–)

(–) (R/W)

(–) (0)

Read/write Þ

Initial valueÞ

■ Register contents

The DIRR register controls the generation/cancellation of delay interrupt requests. If a "1" is written to

this register, a delay interrupt request is generated; if a "0" is written to this register, the delay interrupt

request is cancelled. During a reset, the source cancelled state is set. Although it currently does not

matter if a "1" or a "0" is written to the reserved bits, we recommend that "set bit" and "clear bit"

instructions be used when accessing this register due to the possibility that the reserved bits will be used

in the future.

161

2.14 Delay Interrupt Generation Module

2.14.4 Explanation of Operation

(1) Delay interrupt generation

If the CPU is directed by software to write a "1" to the appropriate bit in the DIRR, the request latch in

the delay interrupt generation module is set, and an interrupt request is generated to the interrupt

controller. If all other interrupt requests have a lower priority than this interrupt, or if there are no other

interrupt requests, the interrupt controller generates an interrupt request to the F²MC-16L.CPU. The

2

F MC-16L CPU compares the interrupt request with the ILM bits in its own internal CCR register, and

if the interrupt level is higher than the ILM bits, then after execution of the current instruction is

completed, the hardware interrupt processing microprogram is started. As a result, the interrupt

processing routine for this interrupt is executed.

2

Delay interrupt generation module

Interrupt controller

WRITE

F MC-16F CPU

Other requests

ICR yy

IL

CMP

ICR xx

ILM

ENIR

INTA

Fig. 2.14.2 Explanation of Delay Interrupt Generation Operation

This interrupt source is cleared by writing a "0" to the appropriate bit in the DDIR within the interrupt

processing routine; the task is then switched accordingly.

2.14.5 Notes on Use

(1) Delay interrupt request latch

This latch is set by writing a "1" to the appropriate bit in the DDIR, and is cleared by writing a "0" to the

same bit. Therefore, if the software is not written so that the source is cleared within the interrupt

processing routine, as soon as interrupt processing is exited, the interrupt processing will be started

again. Therefore, it is necessary to write the software so that this situation is avoided.

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Chapter 2: HARDWARE

2.15 Low Power Consumption Control Circuit

(CPU Intermittent Operation Function, Oscillation Stabilization

Waiting Period, Clock Multiplier Function)

The following are the operating modes: PLL clock mode, PLL watch mode, PLL watch mode, pseudo-

watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, subclock mode, sub

sleep mode, sub watch mode, sub stop mode, and hardware standby mode. Aside from the PLL clock

mode, all of the other operating modes are low power consumption modes.

In main clock mode and main sleep mode, only the main clock (main OSC oscillation clock) and the

subclock (sub OSC oscillation clock) operate. In these modes, the main clock divided by two is used as the

operation clock, the subclock (sub OSC oscillation clock) is used as the watch clock, and the PLL clock

(VCO oscillation clock) is stopped.

In subclock mode and sub sleep mode, only the subclock (sub OSC oscillation clock) operates. The

subclock is used as the operation clock, and the main clock and the PLL clock are stopped.

In PLL sleep mode and main sleep mode, only the CPU's operation clock is stopped, all clocks other than

the CPU clock operate.

In pseudo-watch mode, only the watch timer and the timebase timer operate.

In PLL watch mode, main watch mode, and sub-watch mode, only the watch timer operates. Only the

subclock is in operation in this mode; the main clock and the PLL clock are stopped. (The difference

among PLL watch mode, main watch mode, and sub-watch mode is that the operating mode upon recovery

from an interrupt is PLL clock mode, main clock mode, or subclock mode, respectively. There are no

differences in the watch mode operations.)

The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to

retain data while consuming the least amount of power possible. (The difference between main stop mode

and sub stop mode is that the operating mode upon recovery from an interrupt is main clock mode or

subclock mode, respectively. There are no differences in the stop mode operations.)

The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing

registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower

power consumption by reducing the execution speed of the CPU while supplying a high-speed clock to the

on-chip resources.

The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. The

selected clock divided by two is used as the machine clock.

The WS1 and WS0 bits can be used to set the main clock oscillation stabilization waiting period for when

stop mode and hardware standby mode are released.

163

2.15 Low Power Consumption Control Circuit

2.15.1 Register List

Low power consumption mode

control register

Ü Bit no.

7

6

5

4

3

2

1

0

Address : 0000A0H

LPMCR

STP SLP SPL RST TMD CG1 CG0 SSR

(W) (W) (R/W) (W) (W) (R/W) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(0)

15

(0)

14

(0)

13

(1)

12

(1)

11

(0)

10

(0)

9

(0)

8

Ü Bit no.

Clock selection register

CKSCR

SCM MCM WS1 WS0 SCS MCS CS1 CS0

Address : 0000A1H

(R)

(1)

(R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(1) (1) (1) (1) (1) (0) (0)

Read/write Þ

Initial valueÞ

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Chapter 2: HARDWARE

2.15 Low Power Consumption Control Circuit

2.15.2 Block Diagram

CKSCR

SCM

Subclock

(OSC oscillation)

Subclock switching

controller

SCS

CKSCR

Main clock

(OSC oscillation)

MCM

MCS

PLL multiplier circuit

CPU system

clock

1

2

3

4

generation

CPU clock

CKSCR

CS1

0/9/17/33 intermittent

cycle selection

1/2 S

CPU clock selector

CS0

LPMCR

CG1

CPU intermittent

operation function

cycle number

CG0

selection circuit

Peripheral

system clock

generation

Peripheral clock

LPMCR

SLP

SCM

SLEEP

Main OSC stop

Sub OSC stop

Standby

Control circuit

MSTP

STOP

STP

TMD

RST Cancel HST start

HSTX pin

Interrupt request

or RST

CKSCR

WS1

2⁴

Clock input

2¹³

2¹⁵

2¹⁸

Oscillation

stabilization

wait time

selector

Timebase timer

WS0

2¹²2¹⁴2¹⁶2¹⁹

LPMCR

SPL

Pin high-impedance

control circuit

Pin HI-Z

Self-refresh

SSR

Self-refresh control circuit

RSTX pin

Internal reset

generation circuit

LPMCR

RST

Internal RST

To watchdog timer

WDGRST

Fig. 2.15.1 Low Power Consumption Control Circuit and Clock Generation Block

165

2.15 Low Power Consumption Control Circuit

2.15.3 Detailed Register Description

(1) Low power consumption mode control register (LPMCR)

■ Register configuration

Ü Bit no.

Address :

0000A0H

7

6

5

4

3

2

1

0

LPMCR

STP SLP SPL RST TMD CG1 CG0 SSR

(W) (W) (R/W) (W) (W) (R/W) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(0)

(1)

(0)

■ Register contents

[Bit 7] STP

Writing a "1" to this bit changes the mode to pseudo-watch mode (CKSCR. MCS = 0 and SCS = 1)

or stop mode (CKSCR. MCS = 1 or SCS = 0). Writing a "0" to this bit has no effect. This bit is

cleared to "0" by a reset, wake-up from watch or stop mode. This bit is a write-only bit. When this

bit is read, "0" is always returned.

[Bit 6] SLP

Writing a "1' to this bit changes the mode to sleep mode. Writing a "0" to this bit has no effect. This

bit is cleared to "0" by a reset, wake-up from sleep or stop mode.

If a "1' is written to both the STP bit and the SLP bit simultaneously, the mode changes to either

pseudo-watch mode or to stop mode. This bit is a write-only bit. When this bit is read, "0" is always

returned.

[Bit 5] SPL

When this bit is "0", the level of external pins in watch mode or stop mode is retained. When this bit

is "1", the external pins in watch mode or stop mode go to high-impedance. This bit is cleared to "0"

by a reset. This bit can be read and written.

[Bit 4] RST

Writing a "0" to this bit generates an internal reset signal in three machine cycles. Writing a "1' to

this bit has no effect. When this bit is read, a "1" is returned.

166

Chapter 2: HARDWARE

2.15 Low Power Consumption Control Circuit

[Bit 3] TMD

Writing a "0" to this bit changes the mode to watch mode. Writing a "0" to this bit has no effect.

This bit is cleared to "1" by a reset, wake-up from watch or stop mode. This bit is a write-only bit.

When this bit is read, "1" is always returned.

[Bits 2, 1] CG1, CG0

These bits set the number of clock pause cycles for the CPU intermittent operation function.

These bits are initialized to "00" by a reset due to power-on, hardware standby, or a reset by the

watchdog timer. These bits are not initialized by resets due to other sources. These bits can be read

or written.

Table 2.15.1 CG Bit Setting

CG1

CG0

Number of CPU clock pause cycles

0 cycles (CPU clock = resource clock)

0

1

0

1

0

1

9 cycles (CPU clock: resource clock = 1: approximately 3 to 4)

17 cycles (CPU clock: resource clock = 1: approximately 5 to 6)

33 cycles (CPU clock: resource clock = 1: approximately 9 to 10)

[Bit 0] SSR

When this bit is set to "1", DRAMC self-refresh control is performed in sleep (main/PLL) mode,

watch mode, and stop mode. This bit is cleared to "0" by a refresh. This bit can be read and written.

Note: SSR has no function if there is no DRAMC on chip.

(2) Clock selection register (CKSCR)

■ Register configuration

Ü Bit no.

Address :

15

14

13

12

11

10

9

8

CKSCR

SCM MCM WS1 WS0 SCS MCS CS1 CS0

0000A1H

(R)

(1)

(R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(1) (1) (1) (1) (1) (0) (0)

Read/write Þ

Initial valueÞ

■ Register contents

[Bit 15] SCM

This bit indicates whether the main clock or the subclock is selected as the machine clock. When

this bit is "0", it indicates that the subclock is selected; when this bit is "1", it indicates that the main

clock is selected. If SCS = 0 and SCM = 1, it indicates that the main clock oscillation stabilization

waiting period is in progress.

167

2.15 Low Power Consumption Control Circuit

[Bit 14] MCM

This bit indicates whether the main clock or the PLL clock is selected as the machine clock. When

this bit is "0", it indicates that the PLL clock is selected; when this bit is "1", it indicates that the

main clock is selected. If MCS = 0 and MCM = 1, it indicates that the PLL clock oscillation

stabilization waiting period is in progress. Note that the PLL clock oscillation stabilization waiting

12

period is fixed at 2 main clock cycles.

[Bits 13, 12] WS1, WS0

These bits set the main clock oscillation stabilization waiting period upon wake-up from stop mode

or hardware standby mode is released.

These bits are initialized to "11" by a power-on reset; these bits are not initialized by a reset due to

other sources. These bits can be read and written.

Table 2.15.2 WS Bit Settings

Oscillation stabilization waiting period

WS1

WS0

(source oscillation at 4 MHz)

0

1

0

1

0

1

No oscillation stabilization waiting period

Approx. 1.02 ms (count of 2¹³of the source oscillation)

Approx. 8.19 ms (count of 2¹⁵of the source oscillation)

Approx. 65.54 ms (count of 2¹⁸of the source oscillation)

[Bit 11] SCS

This bit selects either the main clock or the subclock as the machine clock. When a "0" is written to

this bit, the subclock is selected; when a "1" is written to this bit, the main clock is selected. If a "1"

is written to this bit while it is "0", the oscillation stabilization waiting period for the main clock is

generated; therefore, the timebase timer is automatically cleared. In addition, the subclock (as is) is

used for the operation clock when the subclock is selected. (When the source oscillation is 32 kHz,

the operation clock is 32 KHz.) When SCS and MCS are both set to "0", SCS takes priority and the

subclock is selected.

This bit is initialized to "1" by a reset due to power-on, hardware standby, the watchdog timer, an

external source, or software.

[Bit 10] MCS

This bit selects either the main clock or the PLL clock as the machine clock. When a "0" is written

to this bit, the PLL clock is selected; when a "1" is written to this bit, the main clock is selected. If

a "0" is written to this bit while it is "1", the oscillation stabilization waiting period for the PLL

clock is generated; therefore, the timebase timer is automatically cleared. Note that the PLL clock

oscillation stabilization waiting period is fixed at 2¹²main clock cycles. In addition, the main clock

divided by two is used for the operation clock when the main clock is selected. (When the source

oscillation is 4 MHz, the operation clock is 2 MHz.)

This bit is initialized to "1" by a reset due to power-on, hardware standby, or the watchdog timer.

168

Chapter 2: HARDWARE

2.15 Low Power Consumption Control Circuit

[Bits 9, 8] CS1, CS0

These bits select the PLL clock multiplier. These bits are not initialized by a reset initiated by an

external pin or the RST bit. These bits are initialized to "00" by a reset due to power-on, hardware

standby, and the watchdog timer.

Writing to these bits is suppressed when the MCS bit is "0". Set the MCS bit to "1" (main clock

mode) first and then overwrite the CS bits.

These bits can be read and written.

Table 2.15.3 CS Bit Settings

CS1

CS0

Machine clock (source oscillation at 4 MHz)

4 MHz (operation frequency = OSC oscillation frequency)

8 MHz (operation frequency = OSC oscillation frequency × 2)

12 MHz (operation frequency = OSC oscillation frequency × 3)

12 MHz (operation frequency = OSC (3 MHz) × 4)

0

1

0

1

0

1

2.15.4 Explanation of Operation

See section 3.5, "Low Power Consumption Modes" for an explanation of operation in the low power

consumption modes.

(1) Clock selection state transitions

Figs. 2.15.2 and 2.15.3 show the clock selection state transitions.

169

2.15 Low Power Consumption Control Circuit

Power on

(1)

(2)

Main

Main Þ PLLx

SCS=1, MSC=0

SCM=1,MCM=1

CS1/0=xx

SCS=1, MSC=1

SCM=1,MCM=1

CS1/0=xx

(3)

(7)

PLL1 Þ Main

SCS=0orMSC=1

SCM=1,MCM=0

CS1/0=00

PLL1 multiplier

SCS=1, MSC=0

SCM=1,MCM=0

CS1/0=00

(6)

(4)

(7)

(9)

Sub Þ PLLx

SCS=1, MSC=0

SCM=0,MCM=1

CS1/0=xx

PLL2 Þ Main

SCS=0orMSC=1

SCM=1,MCM=0

CS1/0=01

PLL2 multiplier

SCS=1, MSC=0

SCM=1,MCM=0

CS1/0=01

(5)

PLL3 Þ Main

SCS=0orMSC=1

SCM=1,MCM=0

CS1/0=10

PLL3 multiplier

SCS=1, MSC=0

SCM=1,MCM=0

CS1/0=10

(8)

(6)

(7)

(8)

Main Þ Sub

SCS=1, MSC=x

MCM=1

PLL4 Þ Main

SCS=0orMSC=1

SCM=1,MCM=0

CS1/0=11

PLL4 multiplier

SCS=1, MSC=0

SCM=1,MCM=0

CS1/0=11

(6)

(8)

SCM=1

(1) MCS bit clear and SCS bit set

(2) Completion of PLL clock oscillation stabilization wait and CS1/0 = 00

(3) Completion of PLL clock oscillation stabilization wait and CS1/0 = 01

(4) Completion of PLL clock oscillation stabilization wait and CS1/0 = 10

(5) Completion of PLL clock oscillation stabilization wait and CS1/0 = 11

(6) MCS bit set and SCS bit clear

(7) PLL clock and main clock synchronization timing and SCS = 1

(8) PLL clock and main clock synchronization timing and SCS = 0

(9) Completion of main clock oscillation stabilization wait MCS = 0

Fig. 2.15.2 Clock Selection State Transition Diagram (1)

170

Chapter 2: HARDWARE

2.15 Low Power Consumption Control Circuit

Power on

(2)

(1)

Main

SCS=1, MSC=1

SCM=1

Main Þ Sub

SCS=0

SCM=1

MCM=1

(4)

PLLx Þ Sub

SCS=0, MSC=x

SCM=1,MCM=0

CS1/0=xx

Sub Þ Main

SCS=1

SCM=0

Sub

SCS=0

SCM=0

MCM=1

(5)

(3)

MCM=1

Main Þ PLLx

SCS=1, MSC=0

SCM=1, MCM=1

CS1/0=xx

(6)

(1) SCS bit clear

(2) Subclock edge detection timing

(3) SCS bit set

(4) Completion of main clock oscillation stabilization wait and MCS = 1

(5) PLL clock and main clock synchronization timing and SCS = 0

(6) Completion of main clock oscillation stabilization wait and MCS = 0

Fig. 2.15.3 Clock Selection State Transition Diagram (2)

171

2.16 Interrupt Controller

The interrupt control registers are located within the interrupt controller; there is an interrupt control

register for all I/Os that has an interrupt function. These registers have three functions:

•

Setting the interrupt level of the corresponding peripheral

Selecting whether interrupts of the corresponding peripheral are to be treated as normal interrupts or

are to be handled via the extended intelligent I/O service

•

Selecting the extended intelligent I/O service channel

2.16.1 Register List

Interrupt control register

î

ï

Address : ICR01 0000B1H

ICR03 0000B3H

ICR05 0000B5H

ICR07 0000B7H

ICR09 0000B9H

ICR0B 0000BBH

ICR0D 0000BDH

ICR0F 0000BFH

ï

Ü Bit no.

15

14

13

12

or

11

10

9

8

ï

í

ï

ì

ICS1 ICS0

or

S1

or

ICS3 ICS2

ISE

IL2

IL1

or

S1

ISE

S0

IL2

IL0

S0

(w)

(0)

(w) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (1) (1) (1)

Read/write Þ

Initial valueÞ

Interrupt control register

î

Address : ICR00 0000B0H

ICR02 0000B2H

ICR04 0000B4H

ICR06 0000B6H

ICR08 0000B8H

ICR0A 0000BAH

ICR0C 0000BCH

ICR0E 0000BEH

ï

7

6

5

4

3

2

1

0

Ü Bit no.

ï

í

ï

ì

ICS1 ICS0

or

ICS3 ICS2

ISE

IL2

IL1

IL0

or

ICS3 ICS2

ISE

S1

S0

S1

S0

(W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (0) (1) (1) (1)

Read/write Þ

Initial valueÞ

Note: Because accessing these registers via read-modify-write instructions can lead to misoperation,

do not use those instructions to access these registers.

172

Chapter 2: HARDWARE

2.16 Interrupt Controller

2.16.2 Block Diagram

4

/

32

/

4

/

Interrupt/I²OS priority

determination

ISE

IL2

IL1

IL0

Interrupt request/

I²OS request

(peripheral resource)

3

/

I²OS selection

4

(CPU)

Interrupt level

4

/

4

/

I²OS vector

(CPU)

I²OS vector selection

/

ICS3 ICS2 ICS1

ICS0

2

/

2

/

2

/

I²OS end

condition

I²OS end condition

detection

S1

S0

Fig. 2.16.1 Interrupt Controller Block Diagram

173

2.16 Interrupt Controller

2.16.3 Detailed Register Description

(1) Interrupt control register (ICR)

■ Register configuration

Interrupt control register

î

Address : ICR01 0000B1H

ï

ICR03 0000B3H

ICR05 0000B5H

ICR07 0000B7H

ICR09 0000B9H

ICR0B 0000BBH

ICR0D 0000BDH

ICR0F 0000BFH

ï

Ü Bit no.

15

14

13

or

12

or

11

10

9

8

ï

í

ICS1 ICS0

or

S1

ICS3 ICS2

ISE

IL2

IL1

ï

ì

or

S1

ISE

S0

IL2

IL0

S0

(w)

(0)

(w) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (1) (1) (1)

Read/write Þ

Initial valueÞ

Interrupt control register

î

Address : ICR00 0000B0H

ICR02 0000B2H

ICR04 0000B4H

ICR06 0000B6H

ICR08 0000B8H

ICR0A 0000BAH

ICR0C 0000BCH

ICR0E 0000BEH

ï

7

6

5

4

3

2

1

0

Ü Bit no.

ï

í

ï

ì

ICS1 ICS0

or

ICS3 ICS2

ISE

IL2

IL1

IL0

or

ICS3 ICS2

ISE

S1

S0

S1

S0

(W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(0) (0) (0) (0) (0) (1) (1) (1)

Read/write Þ

Initial valueÞ

Note: ICSS to ICS0 is valid only when the EI²OS is to be initiated. When the EI²OS is to be initiated,

2

set ISE to "1"; when the EI OS is not to be initiated, set ISE to "0". If the EI²OS is not to be

initiated, it does not matter what is set in ICS3 to ICS0.

*: When read, a "1" is returned.

Note: ICS1 and ICS0 are write-only, and S1 and S0 are read-only.

Note: Because accessing these registers via read-modify-write instructions can lead to misoperation,

do not use those instructions to access these registers.

■ Register contents

(1) Interrupt level setting bits: IL0, IL1, IL2

These writable bits specify the interrupt level for the corresponding on-chip resource. The interrupt

level is initialized to level 7 (no interrupts) by a reset. Table 2.16.1 shows the relationship between the

interrupt level setting bits and each interrupt level.

174

Chapter 2: HARDWARE

2.16 Interrupt Controller

Table 2.16.1 Correspondence between Interrupt Level Setting Bits and the Interrupt Levels

IL2

0

IL1

0

IL0

0

Level value

0 (highest interrupt level)

0

1

0

1

0

2

0

1

3

1

0

4

1

0

1

5

1

0

6 (lowest interrupt level)

7 (no interrupts)

1

(2) Extended intelligent I/O service enable bit: ISE

2

This bit can be read and written. If this bit is "1" when an interrupt request is generated, the EI OS is

2

started up; if this bit is "0", the interrupt sequence is started up. In addition, when the EI OS is

terminated, the ISE bit is cleared to "0". If the corresponding peripheral does not support the EI OS,

2

the ISE bit must be set to "0" by software.

This bit is initialized to "0" by a reset.

(3) Extended intelligent I/O service channel select bits: ICS3 to ICS0

These bits are write-only bits that specify the EI²OS channel. The value set in these bits determines the

address of the extended intelligent I/O service descriptor in memory (described later). The ICS bits are

initialized by a reset.

Table 2.16.2 indicates the correspondence between the ICS bits, the channel number, and the descriptor

address.

175

2.16 Interrupt Controller

Table 2.16.2 Correspondence between the ICS Bits, the Channel Number, and the Descriptor Address

ICS3

ICS2

ICS1

ICS0

Selected channel

Descriptor address

000100^H

000108H

000110H

000118H

000120H

000128H

000130H

000138H

000140H

000148H

000150H

000158H

000160H

000168H

000170H

000178H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

(4) Extended intelligent I/O service termination status: S0, S1

These read-only bits can be used to determine the termination condition of the EI²OS by checking the

value of these bits.

Table 2.16.3 shows the relationship between the S bits and the termination conditions.

Table 2.16.3 S Bits and Termination Conditions

S1

0

S0

0

Termination condition

Reserved

0

1

Termination due to count termination

Reserved

1

0

1

Termination due to request from resource

2.16.4 Explanation of Operation

See section 3.3, "Interrupts," for details on interrupts and EI²OS operation.

176

Chapter 2: HARDWARE

3.1 Clock Generation Block

Chapter 3:

OPERATION

3.1 Clock Generation Block

The clock generation block controls the operation of the internal clock, such as the sleep, watch, stop, and

PLL clock multiplier function. This internal clock is called the "machine clock," and one cycle of this

clock is called the "machine cycle." In addition, the clock produced by the source oscillator is the main

clock, and the clock derived from the internal VCO oscillation is used as the PLL clock.

Fig. 3.1.1 shows a block diagram of the clock generation circuit.

S

Q

Reset

Internal clock

S

R

Q

Watch mode/

sleep mode

transition

Interrupt HSTX

R

S

Machine clock selection

Stop mode

transition

Q

1

2

3

4

R

PLL multiplier

Selection during

oscillation stabilization

waiting period

Timebase timer

1/4096

1/2

1/4

Watchdog interval selection

Monitor timer

X0

X1

Watchdog reset

Fig. 3.1.1 Clock Generation Circuit Block Diagram

177

3.2 Resets

3.2.1 Reset Source Generation

If a reset source is generated, this device immediately interrupts the processing currently being executed,

and begins waiting for reset release. Resets are generated by a number of different sources, as shown

below:

•

Generation of power-on reset

Hardware standby release

Watchdog timer overflow

Generation of external reset request through the RSTX pin

Generation of reset request through software

When the external bus is being used, if a reset source is generated, the address generated by the device

while it is being reset is undefined. All external bus access signals, such as RDX and WRX, become

inactive.

3.2.2 Using the RSTX Pin to Send All Pins to High Impedance

If a low signal is input to the RSTX pin, all I/O pins go to high impedance. Because this function does not

include a circuit for synchronization with the clock, the pins go to high impedance at the moment that the

low signal is input to the RSTX pin.

When the mode pin is set to the external vector mode, addresses, etc., are output after a high signal is input

to the RSTX pin.

3.2.3 Operation after Reset Release

If the reset source is withdrawn, this device immediately outputs the address where the reset vector is

stored and fetches the reset vector and mode data. The reset vector and mode data are assigned to the four

bytes FFFFDC^Hthrough FFFFDFH, and are transferred by the hardware to the registers shown in Fig. 3.2.1

after the reset is released.

·F²MC-16F CPU·

Mode

· Memory space ·

Register

î

í

ì

î

í

ì

î

í

ì

Micro ROM

Mode data

FFFFDFH

FFFFDEH

FFFFDDH

FFFFDCH

Reset vector bits 23 to 16

Reset vector bits 15 to 8

Reset vector bits 7 to 0

Reset sequence

PCB

PC

Fig. 3.2.1 Reset Vector and Mode Data Storage Location and Storage Destination

178

Chapter 3: OPERATION

3.2 Resets

3.2.4 Reset Sources

There are five reset sources, as shown in Table 3.2.1. Depending on the reset source, the initialized state of

the machine clock and watchdog function vary.

The reset source register can be used to determine the reset source.

Table 3.2.1 Reset Sources

Oscillation

Reset

Generating source

Machine clock Watchdog timer

stabilization

wait?

Power on

When power is applied

Main clock

Stopped

Yes

No

Hardware

standby

Low level input to HSTX pin

Watchdog timer Watchdog timer overflow

Previous state

retained

Previous state

retained

External pin

Software

Low level input to RSTX pin

No

Writing "0" to RST bit in

STBYC

Previous state

retained

Previous state

retained

No

* A reset input in stop or hardware standby mode allows for an oscillation stabilization waiting period,

regardless of the reset source.

As shown in Fig. 3.2.2, there is a flip-flop corresponding to each reset source. Because the contents of

these flip-flops can be obtained by reading the watchdog timer control register, whenever it is necessary to

identify the reset generation source after the reset was released, process the value read from the watchdog

timer control register and branch to an appropriate program. For reference purposes, the watchdog timer

control register is shown again in Fig. 3.2.3.

HSTX pin

RSTX pin

No regular clearing

RST bit set

HSTX=® H

Power supply on

RSTX=L

Power-on generation

detection circuit

External reset request

detection circuit

Watchdog timer reset

STBYC.RST bit write

detection circuit

Hardware standby

generation detection circuit

wake-up detection circuit

S

F / F

R

S

F / F

R

S

F / F

R

S

F / F

R

S

F / F

R

WTC register

Delay circuit

WTC register read

F²MC-16 internal bus

Fig. 3.2.2 Reset Source Bit Block Diagram

179

3.2 Resets

Ü Bit no.

7

6

5

4

3

2

1

0

WTC

PONR STBR WRST ERST SRST WTE WT1 WT0

Address : 0000A8H

(R)

(X)

(R)

(X)

(R)

(X)

(R)

(X)

(R) (W)

(X) (X)

(W) (W)

(X) (X)

Read/write Þ

Initial valueÞ

Fig. 3.2.3 WTC (Watchdog Timer Control Register)

Even if multiple reset sources are generated, the corresponding reset source bits in the watchdog timer

control register are set. Therefore, even if an external reset request and a watchdog reset are generated

simultaneously, both the ERST bit and the WRST bit are set to "1".

The only exception, however, is the power-on reset. When the PONR bit is "1", the contents of the other

bits do not indicate normal reset sources. Therefore, software should be written so that when the PONR bit

is "1', the contents of the other reset source bits are ignored.

Table 3.2.2 Correspondence between the Contents of the Reset Source Bits and Reset Sources

Reset source

Power on

PONR

STBR

WRST

ERST

SRST

1

*

–

1

*

–

*

1

*

–

*

1

*

–

*

1

Hardware standby

Watchdog timer

External pin

RST bit

(Asterisks ( ) in the table indicate that the previous value is retained.)

"*"

The reset source bits are cleared only by reading the watchdog timer control register. Once a reset source

bit corresponding to a reset source that was generated is set, it remains "1" even if other reset sources are

generated.

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3.3 Interrupts

The F²MC-16L has an interrupt function that interrupts the current processing when a predefined event,

etc., occurs, and shifts control to a separately defined program. Interrupt functions can be divided into the

following four types:

•

Hardware interrupts: ...................................... Interrupt processing caused by the occurrence of an

event in an on-chip resource

Software interrupts: ........................................ Interrupt processing caused by an instruction

generating a software event

Extended Intelligent I/O Service (EI²OS): ..... Transfer processing caused by the occurrence of an

event in an on-chip resource

Exceptions: ..................................................... An interruption of processing caused by the

occurrence of an operating exception

This section explains these four interrupt functions.

3.3.1 Hardware Interrupts

(1) Overview

The hardware interrupt function temporarily interrupts program execution by the CPU in response to an

interrupt request signal from an on-chip peripheral resource and shifts control to a user-defined

interrupt processing program. The hardware interrupt is started up by comparing the interrupt level of

the interrupt request with the interrupt level mask register in the CPU's PS register and then referencing

via the hardware the contents of the I flag in the PS; then, if the conditions for generating the interrupt

are met, the interrupt is generated. The processing performed by the CPU when a hardware interrupt is

generated includes the following:

Saving the contents of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers within the CPU

into the system stack

Setting the ILM bits in the PS register automatically to the same level as that of the interrupt

currently being requested

Fetching the contents of the corresponding interrupt vector and then branching there

(2) Structure

The facilities related to hardware interrupts can be grouped into three parts:

On-chip resources: ......Interrupt enable bit and interrupt request bit (Control of interrupt

requests from resources)

Interrupt controller: .....ICR (Interrupt level assignment and determination of priority of

simultaneously requested interrupts)

CPU: ............................I, ILM (Comparison of level of requested interrupt with current level,

identification of interrupt enable state)

Microcode (Interrupt processing steps)

The on-chip resources are represented through the contents of the resource control register. The

interrupt controller is represented through the contents of the ICR. The CPU is represented through the

contents of the CCR, etc. When using hardware interrupts, these three settings must be made

beforehand through software.

The interrupt vector table referenced during interrupt processing is assigned to the memory area from

FFFC00^Hto FFFFFFH; this table is also used by software interrupts. The assignments in this device are

shown in Table 3.3.1.

181

3.3 Interrupts

Table 3.3.1 MB90620/625 Interrupt Assignment Table (1)

Software

interrupt

instruction

Vector

address L

Vector

address M

Vector

address H

Mode

register

Interrupt No.

Hardware interrupt

INT 0

FFFFFCH FFFFFDH FFFFFEH

Unused

#0

None

INT 7

INT 8

FFFFE0^HFFFFE1H FFFFE2H

Unused

#7

FFFFDC^HFFFFDDH FFFFDEH FFFFDF

#8

(RESET vector)

None

INT 9

FFFFD8^HFFFFD9H FFFFDAH

FFFFD4^HFFFFD5H FFFFD6H

FFFFD0^HFFFFD1H FFFFD2H

FFFFCC^HFFFFCDH FFFFCEH

FFFFC8^HFFFFC9H FFFFCAH

FFFFC4^HFFFFC5H FFFFC6H

FFFFC0^HFFFFC1H FFFFC2H

FFFFBC^HFFFFBDH FFFFBEH

FFFFB8^HFFFFB9H FFFFBAH

FFFFB4^HFFFFB5H FFFFB6H

FFFFB0^HFFFFB1H FFFFB2H

FFFFAC^HFFFFADH FFFFAEH

FFFFA8^HFFFFA9H FFFFAAH

FFFFA4^HFFFFA5H FFFFA6H

FFFFA0^HFFFFA1H FFFFA2H

FFFF9C^HFFFF9DH FFFF9EH

Unused

#9

INT 10

INT 11

INT 12

INT 13

INT 14

INT 15

INT 16

INT 17

INT 18

INT 19

INT 20

INT 21

INT 22

INT 23

INT 24

INT 25

INT 26

INT 27

INT 28

INT 29

INT 30

INT 31

INT 32

INT 33

INT 34

INT 35

INT 36

INT 37

INT 38

INT 39

INT 40

INT 41

#10

#11

#12

#13

#14

#15

#16

#17

#18

#19

#20

#21

#22

#23

#24

#25

#26

#27

#28

#29

#30

#31

#32

#33

#34

#35

#36

#37

#38

#39

#40

#41

External interrupt #0

External interrupt #1

External interrupt #2

External interrupt #3

External interrupt #4

External interrupt #5

External interrupt #6

External interrupt #7

Extended serial

Unused

Free-running timer 0 overflow

Free-running timer 1 overflow

Free-running timer 0 compare 0

Free-running timer 0 compare 1

Free-running timer 1 compare 0

Free-running timer 1 compare 1

PPG #0

FFFF98^H

FFFF94^H

FFFF90^H

FFFF99H FFFF9AH

FFFF95H

FFFF91H

FFFF96H

FFFF92H

FFFF8C^HFFFF8DH FFFF8EH

PPG #1

FFFF88^H

FFFF84^H

FFFF80^H

FFFF89H FFFF8AH

Timer #0

FFFF85H

FFFF81H

FFFF86H

FFFF82H

Timer #1

Timer #2

FFFF7C^HFFFF7DH FFFF7EH

Unused

FFFF78^H

FFFF74^H

FFFF70^H

FFFF79H FFFF7AH

A/D end

FFFF75H

FFFF71H

FFFF76H

FFFF72H

Unused

Watch prescaler

Timebase timer overflow

UART transmission end

Unused

FFFF6C^HFFFF6DH FFFF6EH

FFFF68^H

FFFF64^H

FFFF60^H

FFFF69H FFFF6AH

FFFF65H

FFFF61H

FFFF66H

FFFF62H

UART reception end

Unused

FFFF5C^HFFFF5DH FFFF5EH

FFFF58^HFFFF59H FFFF5AH

(Reserved)

182

Chapter 3: OPERATION

3.3 Interrupts

Table 3.3.1 MB90620/625 Interrupt Assignment Table (2)

Software

interrupt

instruction

Vector

address L

Vector

address M

Vector

address H

Mode

register

Interrupt No.

Hardware interrupt

INT 42

INT 43

FFFF54^H

FFFF50^H

FFFF55H

FFFF51H

FFFF56H

FFFF52H

Unused

#42

#43

Delay interrupt

None

INT 254

INT 255

FFFC04^HFFFC05H FFFC06H

FFFC00^HFFFC01H FFFC02H

Unused

#254

#255

None

(3) Operation

On-chip resources with a hardware interrupt request function have an 'interrupt request flag,' which

indicates the existence of an interrupt request, and an 'interrupt enable flag,' which the resource uses to

select whether or not to issue its own interrupt requests to the CPU. The interrupt request flag is set by

the occurrence of an event unique to that resource; if the interrupt enable flag is set to "enabled," the

resource uses an interrupt request to the interrupt controller.

The interrupt controller compares the level of individual interrupt requests that are received

simultaneously with the interrupt level (IL) in the ICR, selects the request with the highest level (the

smallest IL value) and notifies the CPU. If there are multiple requests with the same interrupt level, the

interrupt with the smaller interrupt level number is given priority. The relationship between each

interrupt request and each ICR is determined by the hardware.

The CPU compares the interrupt level that it received with the ILM bits in the PS register, and if the

interrupt level is less than the ILM and the I bit in the PS register is set to "1", then once the instruction

that is currently being executed is terminated, the CPU begins executing the interrupt processing

microcode. At the top of the interrupt processing microcode, the ISE bit in the ICR in the interrupt

controller is referenced; after confirming that it is "0" (i.e., an interrupt), the main body of interrupt

processing is initiated.

In the main body of interrupt processing, after the 12 bytes of the PS and PC, PCB, DTB, ADB, DPR,

and A are saved to the memory locations indicated by the SSB and SSP, a three-byte fetch is performed

to get the interrupt vector, which is loaded into the PC and PCB. After updating the ILM bits in the PS

to the level of the interrupt request that was accepted, the S flag is set and branch processing is

performed. As a result, the next instruction that is executed is the user-defined interrupt processing

program.

Fig. 3.3.1 shows the flow of processing from the occurrence of the hardware interrupt until the point

when there are no more interrupt requests in the interrupt processing program. Fig. 3.3.2 shows the

operational flow of hardware interrupts.

183

3.3 Interrupts

PS: Processor status

I: Interrupt enable flag

ILM: Interrupt level mask register

IR: Instruction register

Register file

Microcode

PS

I

ILM

Comparator

IR

Check

(5)

(6)

(4)

(3)

F²MC-16L · CPU

Peripheral

Enable FF

AND

Source FF

(1)

Peripheral

(7)

(2)

Interrupt

controller

Fig. 3.3.1 Hardware Interrupt Generation and Cancellation

(1) An interrupt source is generated within the peripheral.

(2) The interrupt enable bit within the peripheral is referenced, and if interrupts are enabled, an

interrupt request is sent from the peripheral to the interrupt controller.

(3) After receiving the interrupt request, the interrupt controller determines the priority ranking of

the interrupts that are requested simultaneously, and the interrupt level of the appropriate

interrupt is transferred to the CPU.

(4) The CPU compares the interrupt level of the request from the controller with the IL bits in the

processor status register.

(5) Only if the comparison in step 4 indicates that the requested interrupt has a higher priority level

than that of the current interrupt processing, the I flag in the same processor status register is

checked.

(6) Only if the check in step 5 indicates that the I flag is set to the interrupt enable state, the IL bits

are set to the level of the new request. Once the execution of the current instruction is completed,

interrupt processing immediately is performed and control is immediately passed to the interrupt

processing routine.

(7) When the software in the user's interrupt processing routine clears the interrupt source that was

generated in step 1, the interrupt request is completed.

184

Chapter 3: OPERATION

3.3 Interrupts

I:

Flag in CCR

ILM: CPU level register

IF:

IE:

On-chip resource interrupt request

On-chip resource interrupt enable flag

ISE: EI²OS enable flag

IL:

S:

On-chip resource interrupt request level

Flag in CCR

I & IF & IE = 1

AND

YES

ILM > IL

NO

YES

ISE = 1

Fetch and decode next instruction

Save PS, PC, PCB, DTB, ADB,

DPR, and A into SSP stack and

then set ILM = IL

Extended Intelligent I/

O Service Processing

YES

INT instruction?

Save PS, PC, PCB, DTB, ADB,

DPR, and A into SSP stack and

then set I = 0 and ILM = IL

NO

Execute instruction normally

Repetition of

string instruction

completed?

NO

S ¬ 1

Fetch interrupt vector

YES

Update PC

Fig. 3.3.2 Hardware Interrupt Operation Flow

185

3.3 Interrupts

(4) Miscellaneous

As a special case, hardware interrupt requests are not accepted while writing to the I/O area. This is

done in order to prevent the CPU from operating incorrectly as a result of an interrupt request occurring

while a resource interrupt control register is being overwritten.

The F²MC-16L CPU supports multiple interrupts. Therefore, while interrupt processing is being

executed, if an interrupt is generated that has a stronger interrupt level than the level of the interrupt that

is being executed, then once the current instruction being executed is completed, control shifts to the

interrupt with the higher interrupt level. Once that interrupt is completed, processing of the original

interrupt is resumed. If, while an interrupt is being processed, an interrupt is generated with the same or

a lower interrupt level, the new interrupt is put on hold and processing of the current interrupt

continues, as long as the contents of the ILM bits or the I flag are not changed by an instruction. Note

that the extended intelligent I/O service can not be started up more than once at one time; as long as one

extended intelligent I/O service process is in progress, all other interrupt requests and extended

intelligent I/O service requests are made pending.

The order of the registers saved into the stack is shown in Fig. 3.3.3.

Saving of registers during an interrupt

Word (16 bits)

MSB

LSB

H

¬ SSP (value of SSP before generation of interrupt)

•

AH

AL

DPR

DPB

ADB

PCB

PC

PS

¯

¬ SSP (value of SSP after generation of interrupt)

L

Fig. 3.3.3 Registers Saved into the Stack

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3.3 Interrupts

3.3.2 Software Interrupts

(1) Overview

The software interrupt function shifts control from the program that the CPU was in the process of

executing to a user-defined interrupt processing program in response to the execution of a dedicated

instruction. The processing performed by the CPU when a software interrupt is generated includes the

following:

Saving the contents of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers within the CPU

into the system stack

Setting the I flag in the PS register, thus automatically disabling interrupts

Fetching the contents of the corresponding interrupt vector and then branching there

There is no interrupt request flag and enable flag for interrupt requests generated by executing the INT

instruction (the software interrupt instruction); an interrupt request is always generated when the INT

instruction is executed.

There is no interrupt level for the INT instruction. Therefore, when the INT instruction is executed, the

ILM bits are not updated, the I flag is cleared, and continuing interrupt requests are put on hold.

(2) Structure

The facilities related to software interrupts all reside in the CPU:

CPU:....................... Microcode: Interrupt processing steps

To use a software interrupt, it is necessary to execute the corresponding instruction.

As shown in Table 3.3.1, the same areas are used by the hardware interrupts and software interrupts for

the interrupt vectors. For example, interrupt request number INT 11is used by the hardware interrupt

external interrupt #0 as well as by the software interrupt INT #11. Therefore, external interrupt #0 and

INT #11 both call up the same interrupt processing routine.

(3) Operation

Once the CPU fetches and begins executing a software interrupt instruction, it begins executing the

software interrupt processing microcode. In the software interrupt processing microcode, after the 12

bytes of the PS and PC, PCB, DTB, ADB, DPR, and A are saved to the memory locations indicated by

the SSB and SSP, a three-byte fetch is performed to get the interrupt vector, which is loaded into the PC

and PCB. After resetting the I flag and setting the S flag, branch processing is performed. As a result,

the next instruction that is executed is the user-defined interrupt processing program.

Fig. 3.3.4 shows the flow of processing from the occurrence of the software interrupt until the point

when there are no more interrupt requests in the interrupt processing program.

187

3.3 Interrupts

PS: Processor status

I: Interrupt enable flag

(1)

PS

I

S

Register file

(2)

ILM: Interrupt level mask register

IR: Instruction register

B unit: Bus interface unit

B unit

Fetch

IR

Microcode

Queue

F²MC-16L · CPU

Save

Instruction bus

RAM

Fig. 3.3.4 Software Interrupt Generation and Release

(1) The software interrupt instruction is generated.

(2) The dedicated registers in the register file within the CPU are saved according to the microcode

corresponding to the software interrupt instruction.

(3) Interrupt processing is terminated by the RETI instruction in the user interrupt processing

routine.

(4) Miscellaneous

When the program bank register (PCB) is FF^H, the CALLV instruction vector area overlaps the INT

#vct8 instruction table. When creating software, be careful not to use a CALLV instruction and INT

#vct8 instruction that use the same address.

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Chapter 3: OPERATION

3.3 Interrupts

3.3.3 Extended Intelligent I/O Service (EI²OS)

(1) Overview

The EI²OS is one type of hardware interrupt operation that transfers data automatically between I/O and

memory. This function makes it possible to use DMA transfer to exchange data with I/O. This

exchange has been done by the conventional interrupt processing program. Compared with methods

used in conventional interrupt processing, the EI²OS offers the following benefits.

Because there is no need to describe a transfer program, the program size can be reduced.

Because the internal registers are not used during the transfer, there is no need to save data into

the registers, resulting in a faster transfer speed

Because I/O can stop the transfer when necessary, unneeded data is not transferred.

It is possible to select whether to increment/decrement or not to update the buffer address.

It is possible to select whether to increment/decrement or not to update the I/O register address

(when there is a buffer address update).

When the EI²OS is terminated, program control automatically branches to the interrupt processing

routine after the termination condition is set, making it possible for the user to determine the

termination condition type.

An overview of the EI²OS is shown in Fig. 3.3.5.

Memory space

by IOA

I/O register

eral

riph

Pe

(1)

Interrupt request

CPU

(3)

by ICS

(2)

ISD

Interrupt control register

Interrupt controller

(1) I/O requests transfer.

(2) The interrupt controller selects the

descriptor.

by BAP

(3) The transfer source and destination

are read from the descriptor.

by DCT

(4)

Buffer

(4) The transfer between I/O and memory

is performed.

Fig. 3.3.5 Overview of Extended Intelligent I/O Service

189

3.3 Interrupts

(2) Structure

The facilities related to the EI²OS can be grouped into four parts:

On-chip resources: ........ Interrupt enable bit and interrupt request bit: Control of interrupt

requests from resources

Interrupt controller: ....... ICR: Interrupt level assignment, determination of priority of

simultaneously requested interrupts, and selection of EI²OS operation

CPU: .............................. I, ILM: Comparison of level of requested interrupt with current level,

identification of interrupt enable state

Microcode: EI²OS processing steps

RAM: ............................. Descriptor: Description of EI²OS transfer information

Each of the registers are described below.

■ Interrupt control registers (ICR)

The interrupt control registers are located within the interrupt controller; one exists for each I/O that has

an interrupt function. These registers have the following three functions:

Setting of the interrupt level for the corresponding peripheral

Selection of whether to handle interrupts from the corresponding peripheral as normal interrupts

or as extended intelligent I/O service interrupt

Selection of the extended intelligent I/O service channel

Note that accessing this register through a read-modify-write instruction can cause misoperation. Fig.

3.3.6 shows the bit configuration for an interrupt control register.

15/7 14/6 13/5 12/4 11/3 10/2 9/1

ICS1 ICS0

8/0

IL0

Interrupt control register

When reset: 00000111B

or

ICS3 ICS2

ISE

IL2

IL1

S1

S0

W

R/W R/W R/W R/W

*

Note: ICS3 to ICS0 are valid only when EI²OS is started up. When starting up EI²OS, set ISE to "1";

when not starting it up, set ISE to "0". If EI²OS is not to be started up, it does not matter what

ICS3 to ICS0 are set to.

* When these bits are read, a "1" is returned.

ICS1 and 0 are write-only, S1 and S0 are read-only.

Fig. 3.3.6 Interrupt Control Register (ICR)

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Chapter 3: OPERATION

3.3 Interrupts

[Bits 10 to 8] or [Bits 2 to 0] IL0, IL1, IL2

These are the interrupt level setting bits. These bits specify the interrupt level of the corresponding

on-chip resource. These bits can be read and written. The level is initialized to level 7 by a reset.

The relationship between the interrupt level setting bits and each interrupt level is indicated in Table

3.3.2.

Table 3.3.2 Correspondence between the Interrupt Level Setting Bits and the Interrupt Level

IL2

0

IL1

0

IL0

0

Level value

0 (highest interrupt level)

0

1

0

1

0

2

0

1

3

1

0

4

1

0

1

5

1

0

6 (lowest interrupt level)

7 (no interrupts)

1

[Bit 11] or [Bit 3] ISE

This bit is the EI²OS enable bit. This bit can be read and written. If this bit is "1" when an interrupt

request is generated, the EI²OS is started up; if this bit is "0", the interrupt sequence is started up. In

addition, if the EI²OS is terminated abnormally (the S1 and S0 bits are other than "00"), the ISE bit

is cleared to "0". If the corresponding peripheral does not have the EI²OS function, the ISE bit must

be set to "0" by software.

This bit is initialized to "0" by a reset.

191

3.3 Interrupts

[bits 15 to 12] or [bits 7 to 4] ICS3 to ICS0

These bits are the EI²OS channel selection bits. These bits are write-only bits that specify the EI²OS

channel. The value set in these bits determines the address of the extended intelligent I/O service

descriptor in memory (described later). The ICS bits are initialized by a reset.

Table3.3.3 indicates the correspondence between the ICS bits, the channel number, and the

descriptor address.

Table 3.3.3 Correspondence between the ICS Bits, the Channel Number, and the Descriptor Address

ICS3

ICS2

ICS1

ICS0

Selected channel

Descriptor address

000100^H

000108H

000110H

000118H

000120H

000128H

000130H

000138H

000140H

000148H

000150H

000158H

000160H

000168H

000170H

000178H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

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Chapter 3: OPERATION

3.3 Interrupts

[bits 13, 12] or [bits 5, 4] S0, S1

These bits are the EI²OS termination status bits. These read-only bits can be used to determine the

termination condition of the EI²OS by checking the value of these bits. These bits are initialized to

"00" by a reset.

Table 3.3.4 shows the relationship between the S bits and the termination conditions.

Table 3.3.4 S Bits and Termination Conditions

S1

0

S0

0

Termination condition

Reserved

0

1

Termination due to count termination

Reserved

1

0

1

Termination due to request from resource

193

3.3 Interrupts

● Extended Intelligent I/O Service Descriptor (ISD)

The extended intelligent I/O service Descriptor (ISD) resides in internal RAM between 000100^Hand

00017F^H, and consists of the following information:

Control data for the data transfer

Status data

Buffer address pointer

Fig. 3.3.7 shows the Extended Intelligent I/O Service Descriptor configuration.

L

ISD start address

Buffer address pointer low-order 8 bits (BAPL)

Buffer address pointer mid-order 8 bits (BAPM)

Buffer address pointer high-order 8 bits (BAPH)

EI²OS status (ISCS)

I/O address pointer low-order 8 bits (IOAL)

I/O address pointer high-order 8 bits (IOAH)

Data counter low-order 8 bits (DCTL)

Data counter high-order 8 bits (DCTH)

H

Fig. 3.3.7 Extended Intelligent I/O Service Descriptor Configuration

■ Data counter (DCT)

This 16-bit register is a counter that handles the transfer data count. Before a data transfer, the counter

is decremented by 1. Once the counter reaches zero, EI²OS terminates. Fig. 3.3.8 shows the data

counter configuration.

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

: DCT

B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

(Indeterminate at reset)

Fig. 3.3.8 Data Counter Configuration

■ I/O Register Address Pointer (IOA)

This 16-bit register indicates the low-order addresses (A15 to A0) of the I/O register used for buffering

and data transfer. The high-order addresses are all zeroes; I/O can be specified for any address from

000000^Hto 00FFFFH. Fig. 3.3.9 shows the configuration of the IOA register.

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

: IOA

A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00

(Indeterminate at reset)

Fig. 3.3.9 I/O Register Address Pointer Configuration

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Chapter 3: OPERATION

3.3 Interrupts

■ EI²OS status register (ISCS)

This 8-bit register indicates the update direction (increment/decrement) of the buffer address pointer

and the I/O register address pointer, the transfer data format (byte/word), the transfer direction, and

whether the buffer address pointer and the I/O register address pointer are updated or fixed. Fig. 3.3.10

shows the configuration of the ISCS register.

7

6

5

4

3

2

1

0

Reserved

IF

BW

BF

DIR SE

:ISCS (Indeterminate at reset)

* Be sure to write "0" to the empty bits in the ISCS register.

Fig. 3.3.10 ISCS Configuration

The contents of each bit are as follows:

[Bit 4] IF: This bit specifies whether the I/O register address pointer is updated or fixed.

0: The I/O register address pointer is updated after a data transfer.

1: The I/O register address pointer is not updated after a data transfer.

Note: Only incrementing is possible.

[Bit 3] BW: This bit specifies the transfer data length.

0: Byte

1: Word

[Bit 2] BF: This bit specifies whether the buffer address pointer is updated or fixed.

0: The buffer address pointer is updated after a data transfer.

1: The buffer address pointer is not updated after a data transfer.

Note: When updated, only the low-order 16 bits of the buffer address pointer are updated. Only

incrementing is possible.

[Bit 1] DIR:This bit specifies the data transfer length.

0: I/O -> buffer

1: Buffer -> I/O

[Bit 0] SE: This bit controls the termination of the extended intelligent I/O service upon a request

from a resource.

0: The EI²OS does not terminate upon a request from a resource.

1: The EI²OS does terminate upon a request from a resource.

■ Buffer address pointer (BAP)

This 24-bit register holds the address to be used next by the EI²OS for transfers. Because there is an

independent BAP for each EI²OS channel, each EI²OS channel can transfer data to an 16MB area. If

updating is specified by the BF bit in the ISCS, only the low-order 16 bits of the buffer address pointer

are updated. BAPH does not change.

Fig. 3.3.11 shows the operational flow of the EI²OS, while Fig. 3.3.12 shows the procedural flow for

using the EI²OS.

195

3.3 Interrupts

Interrupt request generated

by internal resource

BAP: Buffer address pointer

I/OA: I/O address pointer

ISD: EI²OS descriptor

NO

ISCS: EI²OS status

ISE=1

DCT: Data counter

ISE: EI²OS enable bit

YES

S1,S0: EI²OS termination status

Read ISD/ISCS

Interrupt sequence

Termination

request

YES

from resource?

YES

SE=1

NO

DIR=1

NO

Data indicated by IOA

(data transfer) to memory

indicated by BAP

Data indicated by BAP

(data transfer) to memory

indicated by IOA

YES

IF=0

NO

Update value

determined

by BW

Update IOA

Update BAP

YES

BF=0

NO

Update value

determined

by BW

(-1)

Decrement DCT

DCT=00

YES

Set S1 and S0 to "01"

Set S1 and S0 to "11"

NO

Set S1 and S0 to "00"

Clear resource

Clear ISE to "0"

Interrupt sequence

interrupt request

Recover CPU operation

Fig. 3.3.11 Flow of EI²OS Operations

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Chapter 3: OPERATION

3.3 Interrupts

Processing by CPU

I²OS Initial setting

Processing by EI²OS

(Interrupt requests) AND (ISE = 1)

Normal end status

Execute job

Transfer data

nterrupt generated by "count out" or

by termination request from resource

Reset extended

intelligent I/O service

(channel switching)

Process data in buffer

Fig. 3.3.12 Procedural Flow for Using EI²OS

197

3.3 Interrupts

3.3.4 Exceptions

In the F²MC-16L series, exceptions are generated by the following sources, and then exception

handling is performed.

(1) Execution of undefined instruction

Exception processing is basically the same as an interrupt; when the generation of an exception event at

the boundary of an instruction is detected, normal processing is suspended and exception processing is

performed. In general, exception processing is generated as the result of an unexpected operation; it is

recommended that exception processing only be used for debugging purposes or for starting up

recovery software in an emergency.

(1) Generation of an exception due to the execution of an undefined instruction

In the F²MC-16L, any code not defined in the instruction map is treated as an undefined instruction.

If an undefined instruction is executed, processing equivalent to that of the software interrupt

instruction "INT 10" is performed. In other words, after the contents of AL, AH, DPR, DTB, ADB,

PCB, PC, and PS are saved into the system stack, the program branches to the routine indicated by

the vector for interrupt #10. In addition, the I flag is cleared and the S flag is set. The value from the

PC register saved into the stack is the address where the undefined instruction is stored. Therefore,

while it is possible to resume processing by using the RETI or RETIQ instruction, doing so is

meaningless since the exception will be generated again.

3.3.5 Low Power Consumption Mode Control Register Access

When writing a word to the low power consumption mode control register, the write should be

executed at an even address. Misoperation may result if the mode is shifted to low power consumption

mode while writing to an odd address.

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Chapter 3: OPERATION

3.4 Memory Access Modes

3.4.1 The Modes

2

The F MC-16L supports various modes according to the access method, the access area, and testing. In

this module, these modes are grouped as follows:

Operation modes

Bus mode

Single chip

· Single chip

· Programming EPROM

· Test functions

■ Operation modes

Operation modes are the modes that control the operating status of the device. The operation mode is

specified by the contents of the mode setting pin MD× and the E× bit in the mode data. An operation

mode can be selected for normal operations, starting an internal testing program, and starting a special

testing function.

■ Bus modes

Bus modes are the modes that control the operation of internal ROM and the operation of external

access functions. The bus mode is specified by the contents of the mode setting pin MD× and the M×

bit in the mode data.

3.4.2 Mode Pins

The mode pins are the three external pins MD2 to MD0. Various combinations of these pins can be used to

specify operations, as shown in Table 3.4.1.

Table 3.4.1 Relationship between Mode Pins and Mode Setting

Mode pin settings

Reset

vector

access

area

External

data bus

width

Mode name

Remarks

MD2

MD1

MD0

0

1

0

1

0

(Reserved: use prohibited)

Internal vector mode

Controlled by mode data after

reset sequence

0

1

Internal (Mode data)

1

0

1

0

1

0

1

(Test mode: use prohibited)

Programming EPROM

–

199

3.4 Memory Access Modes

3.4.3 Mode Data

The mode data is the CPU operation control data located in main memory at FFFFDFH. This data is

fetched while the reset sequence is being executed and is stored in the device's internal mode register.

The contents of the mode register can only be changed during the reset sequence.

The mode set by this register is valid starting from the reset sequence and beyond.

The settings controlled by each bit are shown in Fig. 3.4.1.

7

6

5

4

3

2

1

0

M1 M0 S2 S1

S0

E2 E1 E0

Mode Data

Test function expansion bits

Mode setting bits

Bus mode setting bits

Fig. 3.4.1 Mode Data Structure

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Chapter 3: OPERATION

3.4 Memory Access Modes

■ Test function expansion bits (E2 to E0)

These bits set the test mode for the external pin DC test and the interrupt controller. The relationship

between the bits and their functions is shown in Fig. 3.4.2. Note that some functions are disabled by

certain mode pin settings.

Table 3.4.2 Test Function Expansion Bits and Their Functions

E2

0

E1

0

E0

0

Function

Remarks

Normal operation

0

1

0

1

0

1

0

(Test mode: use prohibited)

1

0

1

0

1

■ Mode setting bits

Set S2, S1, and S0 to "000".

201

3.4 Memory Access Modes

■ Bus mode setting bits

These bits set the operation mode after the reset sequence. Set M1 and M0 to "00".

The correspondence between the access areas and the physical addresses according to the bus mode

specified is shown in Fig. 3.4.2.

Single chip

FFFFFFH

ROM

Model #1

F00000H

010000H

ROM

Model #2

004000H

002000H

: No access

Model #1

: Internal

RAM

000100H

0000C0H

I/O

000000H

Note: "Model" is an address that depends on the model in question.

Fig. 3.4.2 Relationship between Access Areas and the Physical Addresses According to the Bus Mode

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Chapter 3: OPERATION

3.4 Memory Access Modes

The I/O signals on the external pins connected to this module change according to the mode. Table

3.4.3 shows the correspondence of the operation of the external pins related to each mode.

Table 3.4.3 Operation of External Pins Related to Each Mode

Function

Pin name

Programming

EPROM

Single chip

P07 to P00

P17 to P10

P23 to P20

P27 to P24

P30

D07 to D00

A15 to A08

A03 to A00

A07 to A04

A16

P31

CEX

Port

P32

OEX

P33

P34

P35

Not used

P36

P37

203

3.5 Low Power Consumption Modes

The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-

watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, subclock mode, sub

watch mode, sub watch mode, sub stop mode, and hardware standby mode. Aside from the PLL clock

mode, all of the other operating modes are low power consumption modes.

In main clock mode and main sleep mode, only the main clock (main OSC oscillation clock) and the

subclock (sub OSC oscillation clock) operate. In these modes, the main clock divided by 2 is used as the

operation clock, the subclock (sub OSC oscillation clock) is used as the watch clock, and the PLL clock

(VCO oscillation clock) is stopped.

In subclock mode and sub sleep mode, only the subclock (sub OSC oscillation clock) operates. The

subclock is used as the operation clock, and the main clock and the PLL clock are stopped.

In PLL sleep mode and main sleep mode, only the CPU's operation clock is stopped, all clocks other than

the CPU clock operate.

In pseudo-watch mode, only the watch timer and the timebase timer operate.

In PLL watch mode, main watch mode, and sub-watch mode, only the watch timer operates. Only the

subclock is in operation in this mode; the main clock and the PLL clock are stopped. (The difference

among PLL watch mode, main watch mode, and sub-watch mode is that the operating mode upon recovery

from an interrupt is PLL clock mode, main clock mode, or subclock mode, respectively. There are no

differences in the watch mode operations.)

The main stop mode, sub stop mode, and hardware standby mode stop oscillation, making it possible to

retain data while consuming the least amount of power possible. (The difference between main stop mode

and sub stop mode is that the operating mode upon recovery from an interrupt is main clock mode or

subclock mode, respectively. There are no differences in the stop mode operations.)

The CPU intermittent operation function intermittently runs the clock supplied to the CPU when accessing

registers, on-chip memory, on-chip resources, and the external bus. Processing is possible with lower

power consumption by reducing the execution speed of the CPU while supplying a high-speed clock to the

on-chip resources.

The PLL clock multiplier can be selected as either 2, 4, 6, or 8 by setting the CS1 and CS0 bits. The

selected clock divided by two is used as the machine clock.

The status of each chip block in each operating mode is shown in Table 3.5.1.

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Chapter 3: OPERATION

3.5 Low Power Consumption Modes

Table 3.5.1 Power Consumption Mode Operating Statuses

Transition

condition oscillation oscillation

Sub

Main

Exit

method

Peripherals

Clock

CPU

Pins

SCS=0

Reset

Interrupt

Subclock

Operating Stopped

MCS=x

Operating Operating Operating Operating

SCS=0

Sub sleep MCS=x

SLP=1

Reset

Interrupt

Operating Stopped

Operating Operating

SCS=1

Main

Reset

Interrupt

MCS=1

Operating Operating Operating Stopped

sleep

SLP=1

SCS=1

PLL sleep MCS=0

SLP=1

Reset

Interrupt

Pseudo-

watch

(SPL=0)

SCS=1

MCS=0

STP=1

Main-

Stopped

Reset

Interrupt

Operating Operating Stopped

Stopped

tained

Pseudo-

watch

(SPL=1)

SCS=1

MCS=0

STP=1

Reset

Interrupt

Stopped

HI-Z

SCS=x

MCS=x

TMD=0

Watch

(SPL=0)

Main-

tained

Reset

Interrupt

Operating Stopped

Stopped

SCS=x

MCS=x

TMD=0

Watch

(SPL=1)

Reset

Interrupt

HI-Z

MCS=1

or SCS=0 Stopped

STP=1

Stop

(SPL=0)

Main-

tained

Reset

Interrupt

Stopped

MCS=1

or SCS=0 Stopped

STP=1

Stop

(SPL=1)

Reset

Interrupt

HI-Z

Hard-

ware

HSTX=L Stopped

HSTX=H

standby

205

3.5 Low Power Consumption Modes

Fig. 3.5.1 shows the register configuration of the low power consumption mode control register and the

clock selection register.

■ Low power consumption mode control register (LPMCR)

Ü Bit no.

7

6

5

4

3

2

1

0

Address : 0000A0H

LPMCR

STP SLP SPL RST TMD CG1 CG0 SSR

(W) (W) (R/W) (W) (W) (R/W) (R/W) (R/W)

Read/write Þ

Initial valueÞ

(0)

(1)

(0)

■ Clock selection registe(CKSCR)

Ü Bit no.

15

14

13

12

11

10

9

8

CKSCR

Address : 0000A1H

SCM MCM WS1 WS0 SCS MCS CS1 CS0

(R)

(1)

(R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

(1) (1) (1) (1) (1) (0) (0)

Read/write Þ

Initial valueÞ

Fig. 3.5.1 LPMCR/CKSCR

Each operation is explained below.

(1) Sleep mode

● Transition to sleep mode

The standby control circuit is set to sleep mode by writing a "1" to the SLP bit, a "1' to the TMD bit, and

a "0" to the STP bit in the low power consumption mode control register. In sleep mode, only the clock

supplied to the CPU is stopped; in this mode, the CPU stops, but the peripheral circuits continue to

operate.

If an interrupt request is generated when the "1" is written to the SLP bit, the standby control circuit

does not go into sleep mode. In this case, if the CPU is not accepting interrupts, the next instruction is

executed; if the CPU is accepting interrupts, processing branches immediately to the interrupt

processing routine.

The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are

maintained in sleep mode.

● Wake-up from sleep mode

The standby control circuit is used for wake-up from sleep mode when a reset signal is input or when an

interrupt is generated. If a wake-up from sleep mode was done by a reset source, the device enters the

reset state after wake-up from sleep mode is completed.

If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in

sleep mode, the standby control circuit is used for wake-up from sleep mode. Once wake-up from sleep

mode is completed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits,

and the interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU

executes interrupt processing. If the settings do not permit the interrupt to be accepted, then processing

resumes from the instruction that follows the instruction that put the device into sleep mode.

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Chapter 3: OPERATION

3.5 Low Power Consumption Modes

(2) Pseudo-watch mode

● Transition to pseudo-watch mode

The standby control circuit is set to pseudo-watch mode by writing a "1" to the SCS bit and a "0" to the

MCS bit in the clock selection register, and a "1" to the TMD bit and a "1" to the STP bit in the low

power consumption mode control register. In pseudo-watch mode, all clocks stop, except for the source

oscillation (main and sub), the watch timer, and the timebase timer. Practically all chip functions cease.

In addition, the SPL bit in the low power consumption mode control register can be used to control

whether I/O pins maintain their previous states or go to high impedance state in pseudo-watch mode.

If an interrupt request is generated when the "1" is written to the STP bit, the standby control circuit

does not shift to pseudo-watch mode.

The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are hold

in pseudo-watch mode.

● Exit from pseudo-watch mode

The standby control circuit is used for exit from pseudo-watch mode when a reset signal is input or

when an interrupt is generated. If an exit from pseudo-watch mode was performed by a reset source,

the device enters the reset state after exit from pseudo-watch mode.

When recovering from pseudo-watch mode, the standby control circuit is activated first for exit from

pseudo-watch mode, and then begins waiting for the PLL clock oscillation stabilization wait time to

elapse. Therefore, even if the exit from of pseudo-watch mode is due to a reset source, the main clock

is used for the reset sequence.

If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in

pseudo-watch mode, the standby control circuit is activated for exit from pseudo-watch mode. Once

exit from pseudo-watch mode is completed, the interrupt is handled in the normal manner. If the

settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that the interrupt is

accepted, then the CPU executes interrupt processing. If the settings do not permit the interrupt to be

accepted, then processing resumes from the instruction that follows the last instruction that put the

device into pseudo-watch mode.

(3) Watch mode

● Transition to watch mode

The standby control circuit is set to watch mode by writing a "0" to the TMD bit in the low power

consumption mode control register. In watch mode, all clocks stop, except for the sub-source

oscillation and the watch timer. Practically all chip functions cease.

In addition, the SPL bit in the low power consumption mode control register can be used to control

whether I/O pins maintain their previous states or go to high impedance state in watch mode.

If an interrupt request is generated when the "1" is written to the TMD bit, the standby control circuit

does not shift to watch mode.

The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are

maintained in watch mode.

207

3.5 Low Power Consumption Modes

● Exit from watch mode

The standby control circuit is used for exit from watch mode when a reset signal is input or when an

interrupt is generated. If watch mode was released by a reset source, the device enters the reset state

after exit from watch mode.

When recovering from sub-watch mode, the standby control circuit is activated first for exit from watch

mode, and then immediately enters subclock mode. Therefore, even if the wake-up from sub-watch

mode is due to a reset source, the sub-clock is used for the reset sequence.

When recovering from main watch mode or PLL watch mode, the standby control circuit is activated

first for exit from watch mode, and then begins waiting for the main clock oscillation stabilization

period to elapse. Therefore, even if the exit from watch mode is due to a reset source, the sub-clock is

used for the reset sequence.

If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in

watch mode, the standby control circuit is activated for exit from watch mode. Once exit from watch

mode is completed, the interrupt is handled in the normal manner. If the settings of the I flag, ILM bits,

and the interrupt control register (ICR) are all set so that the interrupt is accepted, then the CPU

executes interrupt processing. If the settings do not permit the interrupt to be accepted, then processing

resumes from the instruction that follows the last instruction that put the device into watch mode.

(4) Stop mode

● Transition to stop mode

The standby control circuit is set to stop mode by writing a "0" to the SCS bit and a "1" to the MCS bit

in the clock selection register, and a "1" to the STP bit in the low power consumption mode control

register. In stop mode, all oscillation sources (sub and main) stop. All chip functions cease. As a

result, data can be retained with the barest minimum of power consumption.

In addition, the SPL bit in the LPMCR can be used to control whether I/O pins maintain their previous

states or go to high impedance state in stop mode.

If an interrupt request is generated when the "1" is written to the STP bit, the standby control circuit

does not go into stop mode.

The contents of the accumulator and other dedicated registers, as well as the contents of RAM, are

maintained in stop mode.

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Chapter 3: OPERATION

3.5 Low Power Consumption Modes

● Exiting stop mode

The standby control circuit releases stop mode when a reset signal is input or when an interrupt is

generated. If stop mode was released by a reset source, the device enters the reset state after stop mode

is released.

When recovering from sub-stop mode, the standby control circuit first begins waiting for the sub-clock

oscillation stabilization waiting period to elapse, and then exits stop mode. Therefore, even if the exit

from stop mode is due to a reset source, the reset sequence is executed after the sub-clock oscillation

stabilization waiting period elapses.

When recovering from main stop mode, the standby control circuit first begins waiting for the main

clock oscillation stabilization waiting period to elapse, and then exits stop mode. Therefore, even if the

exit from stop mode is due to a reset source, the reset sequence is executed after the main clock

oscillation stabilization waiting period elapses.

If an interrupt request higher than level 7 is generated by a peripheral circuit, etc., while the device is in

stop mode, the standby control circuit exits stop mode. After exit from sub-stop mode, and after the

sub-clock oscillation stabilization waiting period has elapsed, the interrupt is handled in the normal

manner. If the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that

the interrupt is accepted, then the CPU executes interrupt processing. If the settings do not permit the

interrupt to be accepted, then processing resumes from the instruction that follows the last instruction

that put the device into stop mode.

After exit from main stop mode, and after the main clock oscillation stabilization waiting period

(specified by the WS1 and WS0 bits in the CKSCR) has elapsed, the interrupt is handled in the normal

manner. If the settings of the I flag, ILM bits, and the interrupt control register (ICR) are all set so that

the interrupt is accepted, then the CPU executes interrupt processing. If the settings do not permit the

interrupt to be accepted, then processing resumes from the instruction that follows the last instruction

that put the device into stop mode.

(5) Hardware standby mode

● Transition to hardware standby mode

By setting the HSTX pin to low level, it is possible to set the standby control circuit to hardware

standby mode, regardless of the current status. In hardware standby mode, oscillation stops and all I/O

pins go to high impedance as long as the HSTX pin is low, regardless of any other statuses, including

resets.

Although the contents of internal RAM are maintained in hardware standby mode, the accumulator and

other dedicated registers are all initialized.

● Waking up from hardware standby mode

Wake-up from hardware standby mode can only be executed through the HSTX pin. When the

HSATX pin goes high, the standby control circuit is activated for wake-up from hardware standby

mode and the device begins waiting for oscillation stabilization after the internal reset signal is enabled.

After the main clock oscillation stabilization waiting period elapses, the standby control circuit releases

the internal reset, after which the CPU begins execution, starting from the reset sequence.

209

3.5 Low Power Consumption Modes

(6) CPU intermittent operation function

The CPU intermittent operation function regularly stops the clock supplied to the CPU for a given

period of time when accessing registers, on-chip memory, on-chip resources, and the external bus,

delaying the start of the internal bus cycle. Processing is possible with lower power consumption by

reducing the execution speed of the CPU while supplying a high-speed clock to the on-chip resources.

The CG1 and CG0 bits select the number of pause cycles in the clock supplied to the CPU.

Note that the same clock is used for external bus operations as for resources.

In addition, the instruction execution time when the CPU intermittent operation function is used can be

calculated by adding a compensation factor (the number of register, on-chip memory, on-chip resource,

and external bus access multiplied by the number of pause cycles) to the normal execution time.

(7) Setting the main clock oscillation stabilization waiting period

The WS1 and WS0 bits can be used to set the main clock oscillation stabilization waiting period for

wake-up from stop mode and hardware standby mode. The oscillation stabilization waiting period

should be set in accordance with the type and characteristics of the oscillation circuit and oscillator

connected to the X0 and X1 pins.

These bits are not initialized in the event of a reset, except for a power-on reset. If a power-on reset is

generated, these bits are initialized to "11". Therefore, when power is first applied, the main clock

oscillation stabilization waiting period is set to approximately a count of 2¹⁸pulses of the source

oscillation.

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Chapter 3: OPERATION

3.5 Low Power Consumption Modes

(8) Switching the machine clock

● Main clock/PLL clock switching

Switching between the main clock and the PLL clock is accomplished by writing to the MCS bit in the

CKSCR register.

If the MCS bit is overwritten from a "1" to a "0", the machine clock switches from the main clock to the

PLL clock, once the PLL clock oscillation stabilization waiting period passes (2¹¹machine clocks).

If the MCS bit is overwritten from a "0" to a "1", the machine clock switches from the PLL clock to the

main clock, at the point when the edges of the PLL clock and the main clock match (after 1 to 8 PLL

clocks).

Because the machine clock does not switch immediately after the MCS bit is overwritten, when

performing operations on resources that depend on the machine clock, always reference the MCM bit

and make sure that the machine clock was switched before performing the operation on the resource.

● Main clock/sub-clock switching

Switching between the main clock and the sub-clock is accomplished by writing to the SCS bit in the

CKSCR register.

If the SCS bit is overwritten from a "1" to a "0", the machine clock switches from the main clock to the

sub-clock when the sub-clock edge is detected.

If the SCS bit is overwritten from a "0" to a "1", the machine clock switches from the sub-clock to the

main clock after the main clock oscillation stabilization waiting period elapses.

Because the machine clock does not switch immediately after the SCS bit is overwritten, when

performing operations on resources that depend on the machine clock, always reference the SCM bit

and make sure that the machine clock was switched before performing the operation on the resource.

● Machine clock initialization

The MCS bit and the SCS bit are not initialized by a reset caused by an external pin or the RST bit.

After other types of resets, these bits are each initialized to "1".

(9) State transition

Figs. 3.5.2 to 3.5.5 show the state transitions in low power consumption mode.

In order to keep the state transition diagrams simple, they depict simultaneously occurring events as

occurring in stages. In actuality, however, state transitions occur immediately. For example, when

MCS is set to "1" and SLP is set to "1" simultaneously in PLL clock mode, the state transition diagrams

show the mode changing once to PM transition mode and then to PM transition sleep, but in actuality,

the mode changes immediately from PLL clock mode to PM transition sleep. In addition, when a reset

occurs in sub sleep mode, the state transition diagrams show the mode changing once to sub mode and

then to the main oscillation stabilization period, but in actuality, the mode shifts immediately from sub

sleep mode to the main oscillation stabilization period.

211

3.5 Low Power Consumption Modes

MCS: MCS bit (clock selection register) (PLL clock mode is selected when MCS = 0)

SCS:

STP:

SLP:

SCS bit (clock selection register) (sub-clock mode is selected when SCS = 0)

STP bit (low power consumption mode register) (sleep mode is selected when SLP = 0)

SLP bit (low power consumption mode register) (sleep mode is selected when SLP = 0)

TMD: TMD bit (low power consumption mode register) (watch mode is selected when TMD = 0)

MCM: MCM bit (clock selection register) (PLL clock is in use when MCM = 0)

SCM: SCM bit (clock selection register) (sub-clock is in use when SCM = 0)

SCD:

Sub-clock oscillation stopped (sub-clock oscillation is stopped when SCD = 1)

MCD: Main clock oscillation stopped (main clock oscillation is stopped when MCD = 1)

PCD:

PLL clock oscillation stopped (PLL clock oscillation is stopped when PCD = 1)

Table 3.5.2 List of Transition Conditions

State before transition

Transition conditions

State after transition

Power on

01 Main oscillation stabilization waiting period completed

Main mode

Main oscillation stabili-

zation

05 Main oscillation stabilization waiting period completed

Main mode

06 SCS = 0 written

MS transition mode

MP transition mode

Main sleep

07 SCS = 1•MCS = 0 written

31 TMD = 1•STP = 0•SLP = 1 written

32 TMD = 0 written

Main mode

PLL mode

Main watch transition

Main stop

33 TMD = 1•STP = 1 written

21 SCS = 0 written

PS transition mode

PM transition mode

PLL sleep

20 SCS = 1•MCS = 1 written

59 TMD = 1•STP = 0•SLP = 1 written

58 TMD = 0 written

PLL watch transition P

Pseudo-watch transition

SM transition mode

SP transition mode

57 TMD = 1•STP = 1 written

10 SCS = 1•MCS = 1 written

12 SCS = 1•MCS = 0 written

Main oscillation stabiliza-

tion

11 Reset initiated

Sub mode

42 TMD = 1•STP = 0•SLP = 1 written

43 TMD = 0 written

Sub-sleep

Sub-watch

44 TMD = 1•STP = 1 written

Sub-stop

13 PLL ® main switching timing wait completed

38 TMD = 1•STP = 0•SLP = 1 written

Main mode

PM transition sleep

39 TMD = 0 written and PLL ® main switching timing wait com-

PM transition mode

Main watch transition

Main stop

pleted

40 TMD = 1 and STP = 1 written and PLL ® main switching tim-

ing wait completed

212

Chapter 3: OPERATION

3.5 Low Power Consumption Modes

Table 3.5.2 List of Transition Conditions (Continued)

State before transition

Transition conditions

State after transition

02 Main oscillation stabilization waiting period completed

Main mode

Main oscillation stabiliza-

tion

03 Reset initiated or interrupt

04 SCS = 0 written

Sub mode

SM transition mode

27 TMD = 1•STP = 0•SLP = 1 written

SM transition sleep

28 TMD = 0 and main oscillation stabilization waiting period com-

pleted

Main watch

Main stop

29 TMD = 1 and STP = 1 written and main oscillation stabilization

waiting period completed

16 PLL oscillation stabilization waiting period completed

14 SCS = 1•MCS = 1 written

PLL mode

Main mode

15 SCS = 0 written

MS transition mode

MP transition sleep

PLL watch transition M

Pseudo-watch mode

MP transition mode

SM transition mode

MP transition mode

68 TMD = 1•STP = 0•SLP = 1 written

70 TMD = 0 written

69 TMD = 1•STP=1 written

17 Main oscillation stabilization waiting period completed

18 MCS = 1 written

Main oscillation stabiliza-

tion

19 Reset initiated

SP transition mode

75 TMD = 1•STP = 0•SLP = 1 written

76 TMD = 0 written

SP transition sleep

PLL watch

78 TMD = 1 and STP = 1 written and main oscillation stabilization

waiting period completed

Pseudo-watch mode

09 Main ® sub-clock switching timing wait completed

08 Reset initiated

Sub mode

Main mode

51 TMD = 1•STP = 0•SLP = 1 written

MS transition sleep

Sub watch

MS transition mode

PS transition mode

52 TMD = 0 written and main ® sub switching wait completed

53 TMD = 1 and STP = 1 written and main ® sub switching wait

Sub mode

completed

23 PLL ® main clock switching timing wait completed

22 SCS = 1 written

MS transition mode

PM transition mode

PS transition sleep

Main mode

56 TMD = 1•STP = 0•SLP = 1 written

26 Interrupt or reset initiated

Main sleep

24 Main oscillation stabilization waiting period completed

25 Interrupt or reset initiated

Main sleep

SM transition sleep

SM transition mode

Main sleep

34 PLL ® main clock switching timing wait completed

35 Interrupt or reset initiated

PM transition sleep

PLL sleep

PM transition mode

PLL mode

63 Interrupt or reset initiated

66 PLL oscillation stabilization waiting period completed

67 Interrupt or reset initiated

PLL sleep

MP transition sleep

MP transition mode

MP transition sleep

SP transition mode

Sub mode

73 Main oscillation stabilization waiting period completed

74 Interrupt or reset initiated

SP transition sleep

Sub-sleep

46 Interrupt or reset initiated

49 Main ® sub-clock switching timing wait completed

50 Interrupt or reset initiated

Sub-sleep

MS transition sleep

MS transition mode

213

3.5 Low Power Consumption Modes

Table 3.5.2 List of Transition Conditions (Continued)

State before transition

PS transition sleep

Main watch

Transition conditions

54 PLL ® main clock switching timing wait completed

55 Interrupt or reset initiated

State after transition

MS transition sleep

PS transition mode

SM transition mode

Main watch

30 Interrupt or reset initiated

36 Main ® sub-clock switching timing wait completed

37 Interrupt or reset initiated

Main watch transition

PLL watch

Main mode

77 Interrupt or reset initiated

SP transition mode

PLL watch

72 Main ® sub-clock switching timing wait completed

71 Interrupt or reset initiated

PLL watch transition M

MP transition mode

PLL watch transition M

PLL mode

65 PLL ® main clock switching timing wait completed

64 Interrupt or reset initiated

PLL watch transition P

Sub watch

47 Interrupt or reset initiated

Sub mode

Main oscillation stabiliza-

tion

Main stop

41 Interrupt or reset initiated

Pseudo-watch

62 Interrupt or reset initiated

61 PLL ® main clock switching timing wait completed

60 Interrupt or reset initiated

48 Interrupt

MP transition mode

Pseudo-watch mode

PLL mode

Pseudo-watch transition

Sub oscillation stabilization

Sub stop

Main oscillation stabiliza-

tion

79 Reset initiated

45 Subclock oscillation stabilization waiting period completed

80 Reset initiated

Sub mode

Sub oscillation stabiliza-

tion

Main oscillation stabiliza-

tion

214

Chapter 3: OPERATION

3.5 Low Power Consumption Modes

State Transition Diagrams

Power-on reset

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

SM transition mode

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

SCM=0, MCM=1,

SCD=0, MCD=0,

PCD=1

03

Main oscillation

stabilization period

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

04

02

05

01

10

11

Main mode

MS transition mode

SCS=1, MCS=x,

STP=0, SLP=0,

TMD=1

Sub mode

06

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

SCS=0, MCS=x,

STP=0, SLP=0,

TMD=1

09

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

SCM=0, MCM=1,

SCD=0, MCD=1,

PCD=1

08

07

12

18

13

15

19

PM transition mode

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

MP transition mode

SCS=1, MCS=0,

STP=0, SLP=0,

TMD=1

SP transition mode

SCS=1, MCS=0,

STP=0, SLP=0,

TMD=1

14

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=0

SCM=0, MCM=1,

SCD=0, MCD=0,

PCD=1

17

16

23

20

PLL mode

PS transition mode

SCS=1, MCS=x,

STP=0, SLP=0,

TMD=1

22

SCS=1, MCS=0,

STP=0, SLP=0,

TMD=1

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

21

Fig. 3.5.2 Low Power Consumption Mode Transition Diagram A

215

3.5 Low Power Consumption Modes

SM transition sleep

SCS=1, MCS=1,

STP=0, SLP=1,

TMD=1

Main sleep

SCS=1, MCS=1,

STP=0, SLP=1,

TMD=1

SCM=0, MCM=1,

SCD=0, MCD=0,

PCD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

26

24

25

27

31

Main mode

SM transition mode

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

Main watch

28

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=0

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

SCM=0, MCM=1,

SCD=0, MCD=0,

PCD=1

SCM=0, MCM=1,

SCD=0, MCD=1,

PCD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

30

03

32

29

33

34

PM transition sleep

SCS=1, MCS=1,

STP=0, SLP=1,

TMD=1

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

36

37

05

Main watch transition

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=0

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

Main oscillation

stabilization time

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

35

16

38

39

40

20

PM transition mode

SCS=1, MCS=1,

STP=0, SLP=0,

TMD=1

Main stop

SCS=1, MCS=1,

STP=1, SLP=0,

TMD=1

41

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

SCM=1, MCM=1,

SCD=1, MCD=1,

PCD=1

Fig. 3.5.3 Low Power Consumption Mode Transition Diagram B

216

Chapter 3: OPERATION

3.5 Low Power Consumption Modes

Sub mode

80

45

Sub oscillation

stabilization time

Main oscillation

stabilization time

SCS=0, MCS=x,

STP=0, SLP=0,

TMD=1

SCM=0, MCM=1,

SCD=0, MCD=1,

PCD=1

SCS=0, MCS=x,

STP=0, SLP=0,

TMD=1

SCM=0, MCM=1,

SCD=0, MCD=1,

PCD=1

SCS=1, MCS=x,

STP=0, SLP=0,

TMD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

44

43

42

46

48

79

Sub sleep

Sub watch

Sub stop

SCS=0, MCS=x,

STP=0, SLP=1,

TMD=1

SCM=0, MCM=1,

SCD=0, MCD=1,

PCD=1

SCS=0, MCS=x,

STP=0, SLP=0,

TMD=0

SCM=0, MCM=1,

SCD=0, MCD=1,

PCD=1

SCS=0, MCS=x,

STP=1, SLP=0,

TMD=1

SCM=0, MCM=1,

SCD=1, MCD=1,

PCD=1

47

49

52

53

MS transition sleep

SCS=0, MCS=x,

STP=0, SLP=1,

TMD=1

MS transition mode

SCS=0, MCS=x,

STP=0, SLP=0,

TMD=1

51

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

50

54

23

PM transition sleep

SCS=0, MCS=x,

STP=0, SLP=1,

TMD=1

PM transition mode

SCS=0, MCS=x,

STP=0, SLP=0,

TMD=1

56

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

55

Fig. 3.5.4 Low Power Consumption Mode Transition Diagram C

217

3.5 Low Power Consumption Modes

PLL mode

SCS=1, MCS=0,

STP=0, SLP=0,

TMD=1

SCM=1, MCM=0,

SCD=0, MCD=0,

61

60

Pseudo-watch

transition

Pseudo-watch

mode

SCS=1, MCS=0,

STP=1, SLP=0,

TMD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=0

SCS=1, MCS=0,

STP=1, SLP=0,

TMD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

57

62

PCD=0

58

59

63

PLL sleep

PLL watch

transition P

SCS=1, MCS=0,

STP=0, SLP=1,

TMD=1

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

SCS=1, MCS=0,

STP=0, SLP=0,

TMD=0

SCM=1, MCM=0,

SCD=0, MCD=0,

PCD=0

65

16

66

69

MS transition sleep

SCS=1, MCS=0,

STP=0, SLP=1,

TMD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=0

MP transition mode

SCS=10, MCS=0,

STP=0, SLP=0,

TMD=1

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=0

68

71

PLL watch

transition M

SCS=1, MCS=0,

STP=0, SLP=0,

TMD=0

SCM=1, MCM=1,

SCD=0, MCD=0,

PCD=1

70

67

72

73

17

78

SP transition sleep

SCS=1, MCS=0,

STP=0, SLP=1,

TMD=1

SP transition mode

SCS=1, MCS=0,

STP=0, SLP=0,

TMD=1

PLL watch

77

75

SCS=1, MCS=0,

STP=0, SLP=0,

TMD=0

SCM=0, MCM=1,

SCD=0, MCD=0,

PCD=1

SCM=0, MCM=1,

SCD=0, MCD=0,

PCD=1

SCM=0, MCM=1,

SCD=0, MCD=1,

PCD=1

76

74

Fig. 3.5.5 Low Power Consumption Mode Transition Diagram D

218

Chapter 3: OPERATION

3.6 Pin States for Sleep, Stop, Hold, and Reset

The pin states for the sleep, stop, hold and reset bus modes are shown in Table 3.6.1.

Table 3.6.1 Pin States in Single Chip Mode

Stop

Pin name

P07

Sleep

Hold

Reset

SPL=0

SPL=1

P17 to P10

P27 to P20

P37 to P30

P41, P40

P47 to P43

P53 to P50

P67 to P60

P77 to P70

Note 3

Input

blocked/Out-

put high

impedance

tained

Input not possible/ output

high impedance

Note 2

(This state

not sup-

ported)

tained

Note 1

Input possi-

ble

P06 to P00

P42

Note 1

Input possible

SEG00 to

SEG31

Previous state maintained

L output

COM0 to

COM3

Note1: Same as other ports when functioning as an output port. "Input possible" means that the pin can

function as an input; therefore, the pull-up/pull-down option or input from an external source is

required.

Note2: Indicates that the state that was being output before entering this mode is output as is, or (in the

case of input) that input is not possible. "Output as is" means that an on-chip peripheral circuit

with an output is in operation and that output is generated according to that peripheral circuit;

when outputting data as a port, that output is maintained. "Input not possible" indicates that while

the input gate near the pin is in the enabled state, the internal circuitry is not operating, so the

information on the pin is not accepted internally.

219

4.1 Addressing

Chapter 4:

INSTRUCTIONS

4.1 Addressing

In the F²MC-16L, the address format is determined by either the instruction's effective address

specification, or by the instruction code itself (implied addressing).

4.1.1 Effective Address Field

The address formats specified in the effective address field are shown in Table 4.1.1.

Table 4.1.1 Effective Address Field

Code

Notation

Address format

Default bank

00

01

02

03

04

05

06

07

R0

R1

R2

R3

R4

R5

R6

R7

RW0

RW1

RW2

RW3

RW4

RW5

RW6

RW7

RL0

(RL0)

RL1

(RL1)

RL2

(RL2)

RL3

(RL3)

Register direct

Starting from the left, "ea" corresponds to the

byte, word and long-word types.

None

08

09

0A

0B

@RW0

@RW1

@RW2

@RW3

DTB

ADB

SPB

Register indirect

0C

0D

0E

0F

@RW0+

@RW1+

@RW2+

@RW3+

DTB

ADB

SPB

Register indirect with post-incrementing

Register indirect with 8-bit displacement

Register indirect with 16-bit displacement

10

11

12

13

@RW0+disp8

@RW1+disp8

@RW2+disp8

@RW3+disp8

DTB

ADB

SPB

14

15

16

17

@RW4+disp8

@RW5+disp8

@RW6+disp8

@RW7+disp8

DTB

ADB

SPB

18

19

1A

1B

@RW0+disp16

@RW1+disp16

@RW2+disp16

@RW3+disp16

DTB

ADB

SPB

1C

1D

1E

1F

@RW0+RW7

@RW1+RW7

@PC+disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

DTB

PCB

DTB

220

Chapter 4: INSTRUCTIONS

4.1 Addressing

4.1.2 Addressing Details

(1) Immediate value (#imm)

This format specifies the operand value directly.

#imm4

#imm8

•

#imm6

#imm32

(2) Compressed direct address (dir)

In this format, the operand specifies the low-order 8 bits of the memory address. Bits 8 to 15 of the

address are specified by the DPR. Bits 16 to 23 of the address are indicated by the DTB.

(3) Direct address (addr16)

In this format, the operand specifies the low-order 16 bits of the memory address. Bits 16 to 23 of the

address are indicated by the DTB.

(4) Register direct

This format specifies a direct register as the operand.

General-purpose registers

Byte:

R0, R1, R2, R3, R4, R5, R6, R7

Word:

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

Long word: RL0, RL1, RL2, RL3

Dedicated registers

Accumulator: A, AL

Pointer:

Bank:

SP

PCB, DTB, USB, SSB, ADB

DPR

Page:

Control:

PS, CCR, RP, ILM

*

Regarding the SP, either the USP or the SSP is selected and used, depending on the value of the S

bit in the CCR. In addition, in a branching instruction, the PC is implicitly specified, and is not

described in the instruction operand.

221

4.1 Addressing

(5) Register indirect (@RWj j = 0 to 3)

This format accesses the memory address indicated by the contents of the general-purpose register

RWj. When RW0/RW1 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 is used, bits

16 to 23 of the address are indicated by SPB, and if RW2 is used, bits 16 to 23 of the address are

indicated by ADB.

(6) Register indirect with post-incrementing (@RWj + j = 0 to 3)

This format accesses the memory address indicated by the contents of the general-purpose register

RWj. After the operand operation, RWj is incremented by the data length of the operand (by 1 for a

byte, 2 for a word, and 4 for a long-word). When RW0/RW1 is used, bits 16 to 23 of the address are

indicated by DTB; if RW3 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 is

used, bits 16 to 23 of the address are indicated by ADB. Note that if the post-incremented result is the

address of the register for which the increment specification was made, the value that is referenced

subsequently is the incremented value. In addition, in such a case, if the instruction was a write

instruction, the data written by the instruction is given priority, so the register that was to have been

incremented contains the write data in the end.

è

æ

ê

è

(7) Register indirect with displacement

ê

@RWi + disp8 i = 0 to 7

æ

@RWj + disp16 j = 0 to 3

This format accesses the memory address indicated by the sum of the contents of the general-purpose

register RWj and the displacement value. The displacement value can be one of two types, either a byte

or a word, and is added as a signed value. When RW0, RW1, RW4, or RW5 is used, bits 16 to 23 of the

address are indicated by DTB; if RW3 or RW7 is used, bits 16 to 23 of the address are indicated by

SPB, and if RW2 or RW6 is used, bits 16 to 23 of the address are indicated by ADB.

(8) Register indirect with base index (@RW0 + RW7, @RW1 + RW7)

This format accesses the memory address indicated by the sum of the contents of the general-purpose

register and either RW0 or RW1. Bits 16 to 23 of the address are indicated by DTB.

(9) Program counter indirect with displacement (@PC + disp16)

This format accesses the memory address indicated by the sum of the "instruction address + 4 +

disp16". The displacement value is a word length value. Bits 16 to 23 of the address are indicated by

PCB.

The operand address is generally regarded as "the next instruction address + disp16", but note that this

does not hold true for the instructions indicated below:

•

DBNZ eam, rel

DWBNZ eam, rel

MOV eam, #imm8

MOVW eam, #imm16

CBNE eam, #imm8, rel

CWBNE eam, #imm16, rel

222

Chapter 4: INSTRUCTIONS

4.1 Addressing

(10) Accumulator indirect (@A)

This format has two types: one in which the contents of AL specify bits 00 to 15 of the address and

DTB indicates bits 16 to 23; and one in which the low-order 24 bits of A specify bits 00 to 23 of the

address.

(11) I/O direct (io)

In this format, the memory address of the operand is specified directly by the 8-bit displacement value.

Regardless of the value of DTB and DPR, the I/O space from 000000^Hto 0000FFH is accessed. The

access space specification prefix has no effect on this addressing format.

(12) Long register indirect with displacement (@RLi + disp8 i = 0 to 3)

This format accesses the memory address indicated by the low-order 24 bits of the sum of the contents

of the general-purpose register RLi plus the displacement value. The displacement value is 8 bits, and

is added as a signed numeral.

(13) Compressed direct bit address (dir:bp)

This format specifies the low-order 8 bits of the memory address with the operand. In addition, bits 8 to

15 of the address are indicated by DPR. Finally, bits 16 to 23 of the address are indicated by DTB. The

bit position is indicated by ":bp", with larger numbers being closer to the MSB and smaller numbers

being closer to the LSB.

(14) I/O direct bit address (io:bp)

This format directly specifies a bit within a physical address from 000000^Hto 0000FFH. The bit

position is indicated by ":bp", with larger numbers being closer to the MSB and smaller numbers being

closer to the LSB.

(15) Direct bit address (addr16:bp)

This format directly specifies any bit within a 64-kilobyte region. Bits 16 to 23 of the address are

indicated by DTB. The bit position is indicated by ":bp", with larger numbers being closer to the MSB

and smaller numbers being closer to the LSB.

(16) Register list (rlst)

This format specifies the register that is the target of a stack push/pop instruction.

MSB

LSB

RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0

A register is selected when the corresponding bit is "1",

and is not selected when the corresponding bit is "0".

Fig. 4.1.1 Register List Configuration

223

4.1 Addressing

(17) Program counter relative branching address (rel)

With this format, the address of the destination of a branching instruction is the sum of the value of the

PC and the 8-bit displacement value. If the result exceeds 16 bits, the amount of the overflow is

ignored and the bank register is not incremented or decremented; therefore, the address is kept within a

64-kilobyte bank. This format is used in unconditional and conditional branching instructions. Bits 16

to 23 of the address are indicated by PCB.

(18) Direct branching address (addr16)

With this format, the address of the destination of a branching instruction is specified directly by the

displacement value. The displacement value is 16 bits, and indicates the branching destination within a

logical memory space. This format is used in unconditional branching instructions and subroutine call

instructions. Bits 16 to 23 of the address are indicated by PCB.

(19) Physical direct branching address (addr24)

With this format, the address of the destination of a branching instruction is specified directly by the

displacement value. The displacement value is 24 bits, and specifies the physical address of the

branching destination. This format is used in unconditional branching instructions, subroutine call

instructions, and software interrupt instructions.

(20) Accumulator indirect branching address (@A)

In this format, the 16 bits of the accumulator AL specify the branching destination address. This

address indicates a branching destination within a bank space; in this case, bits 16 to 23 of the address

are indicated by the PCB. In the case of JCTX, however, bits 16 to 23 of the address are indicated by

DTB. This format is used in unconditional branching instructions.

(21) Vector address (#vct)

The contents of the specified vector become the branching destination address. There are two data

lengths for vector numbers: 4 bits and 8 bits. This format is used in subroutine call instructions and

software interrupt instructions.

(22) Indirect specification branching address (@ear)

The word data in the address indicated by "ear" is the branching destination address.

(23) Indirect specification branching address (@eam)

The word data in the address indicated by "eam" is the branching destination address.

224

Chapter 4: INSTRUCTIONS

4.2 Instruction Set

Table 4.2.1 Explanation of Items in Table of Instructions

Item

Explanation

Upper-case letters and symbols: ........ Described as they appear in assembler.

Lower-case letters: ............................. Replaced when described in assembler.

Numbers after lower-case letters: ...... Indicate the bit width within the instruction.

Mnemonic

#

~

Indicates the number of bytes.

Indicates the number of cycles.

See Table 4.2.4 for details about meanings of letters in items.

Indicates the register access count during execution of instruction. This number is used to

compensation the correction value when using the CPU clock gear function.

RG

Indicates the compensation value for calculating the number of actual cycles during execution

of instruction.

The number of actual cycles during execution of instruction is the compensation value

summed with the value in the "~" column.

B

Operation

LH

Indicates operation of instruction.

Indicates special operations involving bits 15 through 08 of the accumulator.

Z:........Transfers "0".

X: .......Sign-extended transfer through sign extension.

-:.........Transfers nothing.

Indicates special operations involving the high-order 16 bits in the accumulator.

*: ........Transfers from AL to AH.

AH

-:.........No transfer.

Z:........Transfers 00 to AH.

X: .......Transfers 00^Hor FFH to AH using sign extension AL.

I

S

T

N

Z

V

C

Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),

N (negative), Z (zero), V (overflow), and C (carry).

*: ........Changes due to execution of instruction.

-:.........No change.

S:........Set by execution of instruction.

R: .......Reset by execution of instruction.

Indicates whether the instruction is a read-modify-write instruction (a single instruction that

reads data from memory, etc., processes the data, and then writes the result to memory.).

*: ........Instruction is a read-modify-write instruction

RMW

-:.........Instruction is not a read-modify-write instruction

Note: A read-modify-write instruction cannot be used on addresses that have different mean-

ings depending on whether they are read or written.

225

4.2 Instruction Set

■ Number of execution cycles

The number of cycles required for the execution of an instruction is obtained by summing the value

shown in the table for the "number of cycles" for the instruction in question, the compensation value

(which depends on certain conditions), and the "number of cycles" needed for the program fetch.

When fetching a program in memory connected to the 16-bit bus, such as on-chip ROM, a program

fetch is performed for each two-byte (word) boundary crossed by the instruction being executed;

therefore, if there is any interference with data access, etc., the number of execution cycles increases.

When fetching a program in memory connected to the 8-bit external data bus, a program fetch is

performed for each byte of the instruction being executed; therefore, if there is any interference with

data access, etc., the number of execution cycles increases.

226

Chapter 4: INSTRUCTIONS

4.2 Instruction Set

Table 4.2.2 Explanation of Symbols in Table of Instructions

Symbol

Explanation

32-bit accumulator

The bit length varies according to the instruction.

Byte:............ Low-order 8 bits of AL

Word: .......... 16 bits of AL

A

Long:........... 32 bits of AL:AH

AH

AL

High-order 16 bits of A

Low-order 16 bits of A

SP

Stack pointer (USP or SSP)

Program counter

PC

PCB

DTB

ADB

SSB

USB

SPB

DPR

brg1

brg2

Ri

Program bank register

Data bank register

Additional data bank register

System stack bank register

User stack bank register

Current stack bank register (SSB or USB)

Direct page register

DTB, ADB, SSB, USB, DPR, PCB, SPB

DTB, ADB, SSB, USB, DPR, SPB

R0, R1, R2, R3, R4, R5, R6, R7

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RW0, RW1, RW2, RW3

RWi

RWj

RLi

RL0, RL1, RL2, RL3

dir

Compact direct addressing

Direct addressing

Physical direct addressing

Bits 0 to 15 of addr24

Bits 16 to 23 of addr24

addr16

addr24

ad24 0-15

ad24 16-23

io

I/O area (000000^Hto 0000FFH)

#imm4

4-bit immediate data

#imm8

8-bit immediate data

#imm16

#imm32

ext(imm8)

16-bit immediate data

32-bit immediate data

16-bit data signed and extended from 8-bit immediate data

disp8

disp16

8-bit displacement

16-bit displacement

227

4.2 Instruction Set

Table 4.2.2 Explanation of Symbols in Table of Instructions (Continued)

Symbol

bp

Explanation

Bit offset value

vct4

vct8

Vector number (0 to 15)

Vector number (0 to 255)

( )b

Bit address

rel

ear

eam

Branch specification relative to PC

Effective addressing (codes 00 to 07)

Effective addressing (codes 08 to 1F)

rlst

Register list

228

Chapter 4: INSTRUCTIONS

4.2 Instruction Set

Table 4.2.3 Effective Address Fields

Number of bytes in

address extension

[Note]

Code

Notation

Address format

00

01

02

03

04

05

06

07

R0

R1

R2

R3

R4

R5

R6

R7

RW0

RW1

RW2

RL0

(RL0)

RL1

Register direct

"ea" corresponds to byte, word, and long-

word types, starting from the left

RW3 (RL11)

–

RW4

RW5

RW6

RW7

RL2

(RL2)

RL3

(RL3)

08

09

0A

0B

@RW0

@RW1

@RW2

@RW3

Register indirect

0

0C

0D

0E

0F

@RW0+

@RW1+

@RW2+

@RW3+

Register indirect with post-incrementing

10

11

12

13

14

15

16

17

@RW0+disp8

@RW1+disp8

@RW2+disp8

@RW3+disp8

@RW4+disp8

@RW5+disp8

@RW6+disp8

@RW7+disp8

Register indirect with 8-bit displacement

Register indirect with 16-bit displacement

1

2

18

19

1A

1B

@RW0+disp16

@RW1+disp16

@RW2+disp16

@RW3+disp16

1C

1D

1E

1F

@RW0+RW7

@RW1+RW7

@PC+disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

0

2

*: The number of bytes for address extension is indicated by the "+" symbol in the "#" (number of

bytes) column in the Table of Instructions and by the number of bytes in the detailed instruction

rules.

229

4.2 Instructn Set

Table 4.2.4 Number of Execution Cycles for Each Form of Addressing

(a)*

Number of accesses for

Number of execution

Code

Operand

each form of

addressing

cycles for each

addressing type

00

|

07

Ri

RWi

RLi

Listed in the instruction Listed in the instruction

set table set table

08

|

0B

@RWj

@RWj+

2

4

2

1

2

1

0C

|

0F

10

|

17

@RWi+disp8

@RWj+disp16

18

|

1B

1C

1D

1E

1F

@RW0+RW7

@RW1+RW7

@PC+disp16

addr16

4

2

1

2

0

*: (a) corresponds to (a) in the “~” (number of cycles) column in the instructions (Tables D.4a to

D.4q)

230

Chapter 4: INSTRUCTIONS

4.2 Instructn Set

Table 4.2.5 Compensation Values for Number of Cycles Used to Calculate Number of Actual

Cycles

(b) Note1

byte

(c)

(d)

Operand

word

long

Internal register

+0

Internal RAM even address

Internal RAM odd address

+0

+2

+0

+4

Even address on external data bus (16 bits)

Odd address on external data bus (16 bits)

+1

+4

+2

+8

External data bus (8 bits)

+1

+4

+8

Note1: "(b)", "(c)", and "(d)" are used in the "~" (number of cycles) column, column B (compensation

value) and in the detailed instruction rules in the Table of Instructions.

Note2: When the external data bus is used, it is necessary to add in the number of weighted cycles used for

ready input and automatic ready.

Table 4.2.6 Compensation Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Instruction

Internal memory

Byte boundary Word boundary

–

+2

+3

–

External data bus (16 bits)

External data bus (8 bits)

+3

Note1: When the external data bus is used, it is necessary to add in the number of weighted cycles used for

ready input and automatic ready.

Note2: Because instruction execution is not slowed down by all program fetches in actuality, these

compensation values should be used for "worst case" calculations.

231

4.2 Instructn Set

4.2.1 F²MC-16L Instruction Set (340 Instructions)

Table 4.2.7 Transfer Instructions (Byte) (41 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

MOV

MOVN

A, dir

A, addr16

A, Ri

A, ear

A, eam

A, io

A, #imm8

A, @A

A, @RLi+disp8

2

3

1

2

2+

2

3

1

3

4

2

0

1

0

2

0

(b)

0

byte (A) ¬ (dir)

byte (A) ¬ (addr16)

byte (A) ¬ (Ri)

byte (A) ¬ (ear)

byte (A) ¬ (eam)

byte (A) ¬ (io)

byte (A) ¬ imm8

byte (A) ¬ ((A))

byte (A) ¬ ((RLi)+disp8)

byte (A) ¬ imm4

Z

*

–

*

–

*

R

*

–

0

3+(a)

3

2

3

10

(b)

0

(b)

0

A, #imm4

1

MOVX

A, dir

A, addr16

A, Ri

A, ear

A, eam

A, io

A, #imm8

A, @A

A, @RWi+disp8

A, @RLi+disp8

2

3

2

2+

2

3

4

2

0

1

0

1

2

(b)

0

byte (A) ¬ (dir)

byte (A) ¬ (addr16)

byte (A) ¬ (Ri)

byte (A) ¬ (ear)

byte (A) ¬ (eam)

byte (A) ¬ (io)

byte (A) ¬ imm8

byte (A) ¬ ((A))

byte (A) ¬ ((RWi)+disp8)

byte (A) ¬ ((RLi)+disp8)

X

*

–

*

–

*

–

0

3+(a)

3

2

3

5

(b)

0

(b)

10

MOV

dir, A

addr16, A

Ri, A

ear, A

eam, A

io, A

@RLi+disp8, A

Ri, ear

Ri, eam

ear, Ri

eam, Ri

Ri, #imm8

io, #imm8

dir, #imm8

ear, #imm8

eam, #imm8

2

3

1

2

2+

2

3

2

2+

2

2+

2

3

3+

2

3

4

2

0

1

0

2

1

2

1

0

1

0

(b)

0

byte (dir) ¬ (A)

byte (addr16) ¬ (A)

byte (Ri) ¬ (A)

byte (ear) ¬ (A)

byte (eam) ¬ (A)

byte (io) ¬ (A)

byte ((RLi)+disp8) ¬ (A)

byte (Ri) ¬ (ear)

byte (Ri) ¬ (eam)

byte (ear) ¬ (Ri)

byte (eam) ¬ (Ri)

byte (Ri) ¬ imm8

byte (io) ¬ imm8

byte (dir) ¬ imm8

byte (ear) ¬ imm8

byte (eam) ¬ imm8

byte ((A)) ¬ (AH)

–

*

–

*

–

*

–

*

–

*

–

0

3+(a)

3

10

3

4+(a)

4

5+(a)

2

(b)

0

(b)

0

(b)

0

(b)

0

(b)

5

2

4+(a)

3

@AL, AH

/

MOV@A, T

XCH

A, ear

2

2+

2

4

2

0

4

2

0

byte (A) « (ear)

byte (A) « (eam)

byte (Ri) « (ear)

byte (Ri) « (eam)

Z

–

A, eam

Ri, ear

Ri. eam

7+(a)

4

9+(a)

2´ (b)

0

2´ (b)

2+

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

232

Chapter 4: INSTRUCTIONS

4.2 Instructn Set

Table 4.2.8 Transfer Instructions (Word/Long-Word) (38 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

MOVW

A, dir

A, addr16

A, SP

A, RWi

A, ear

A, eam

A, io

A, @A

2

3

1

2

2+

2

3

4

1

2

0

1

0

1

2

(c)

0

(c)

0

(c)

word (A) ¬ (dir)

word (A) ¬ (addr16)

word (A) ¬ (SP)

word (A) ¬ (RWi)

word (A) ¬ (ear)

word (A) ¬ (eam)

word (A) ¬ (io)

word (A) ¬ ((A))

word (A) ¬ imm16

word (A) ¬ ((RWi)+disp8)

word (A) ¬ ((RLi)+disp8)

–

*

–

*

–

*

–

3+(a)

3

2

5

10

A, @imm16

A, @RWi+disp8

A, @RLi+dips8

2

3

MOVW

dir, A

addr16, A

SP, A

RWi, A

ear, A

eam, A

io, A

@RWi+disp8, A

@RLi+disp8, A

RWi, ear

RWi, eam

ear, RWi

eam, RWi

RWi, #imm16

io, #imm16

ear, #imm16

eam, #imm16

2

3

1

2

2+

2

3

2

2+

2

2+

3

4

4+

2

3

4

1

2

0

1

0

1

2

1

2

1

0

1

0

(c)

0

(c)

0

(c)

0

(c)

0

word (dir) ¬ (A)

word (addr16) ¬ (A)

word (SP) ¬ (A)

word (RWi) ¬ (A)

word (ear) ¬ (A)

word (eam) ¬ (A)

word (io) ¬ (A)

word ((RWi)+disp8)) ¬ (A)

word ((RLi)+disp8) ¬ (A)

word (RWi) ¬ (ear)

word (RWi ¬ (eam)

word (ear) ¬ (RWi)

word (eam) ¬ (RWi)

word (RWi) ¬ imm16

word (io) ¬ imm16

word (ear) ¬ imm16

word (eam) ¬ imm16

word ((A)) ¬ (AH)

–

*

–

*

–

*

–

*

–

*

–

2

3+(a)

3

5

10

3

4+(a)

4

5+(a)

2

5

2

(c)

0

(c)

4+(a)

3

@AL, AH

/

MOVW@A, T

–

XCHW

A,ear

A, eam

RWi, ear

RWi, eam

2

2+

2

4

2

0

4

2

0

word (A) « (ear)

word (A) « (eam)

word (RWi) « (ear)

word (RWi) « (eam)

–

5+(a)

7

9+(a)

2´ (c)

0

2´ (c)

2+

MOVL

A, ear

A, eam

A, #imm32

2

2+

5

4

5+(a)

3

2

0

(d)

0

long (A) ¬ (ear)

long (A) ¬ (eam)

long (A) ¬ imm32

–

*

–

MOVL

ear, A

eam, A

2

2+

3

2

0

(d)

long (ear) ¬ (A)

long (eam) ¬ (A)

–

*

–

5+(a)

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

233

4.2 Instructn Set

Table 4.2.9 Addition and Subtraction Instructions (Byte/Word/Long-Word) (42 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

ADD

ADDC

ADDDC

SUB

A, #imm8

2

2+

2

2+

1

2

2+

1

2

2+

2

2+

1

2

2+

1

2

5

3

0

1

0

2

0

1

0

1

0

2

0

1

0

(b)

0

(b)

0

2´ (b)

0

(b)

0

(b)

0

(b)

0

2´ (b)

0

(b)

0

byte (A) ¬ (A) + imm8

byte (A) ¬ (A) + (dir)

Z

–

Z

–

Z

–

*

–

-

*

–

-

A ,dir

A ,ear

A, eam

ear, A

eam, A

A

A ,ear

A,eam

A

A, #imm8

A, dir

A, ear

A, eam

ear, A

eam, A

A

A, ear

A, eam

A

byte (A) ¬ (A) + (ear)

byte (A) ¬ (A) + (eam)

byte (ear) ¬ (ear) + (A)

byte (eam) ¬ (eam) + (A)

byte (A) ¬ (AH) + (AL) + (c)

byte (A) ¬ (A) + (ear) + (c)

byte (A) ¬ (A) + (eam) + (c)

byte (A) ¬ (AH) + (AL) + (c)

(decimal)

4+(a)

3

5+(a)

2

3

4+(a)

3

2

5

3

4+(a)

3

5+(a)

2

byte (A) ¬ (A) - imm8

byte (A) ¬ (A) - (dir)

byte (A) ¬ (A) - (ear)

byte (A) ¬ (A) - (eam)

byte (ear) ¬ (ear) - (A)

byte (eam) ¬ (eam) - (A)

byte (A) ¬ (AH) - (AL) - (c)

byte (A) ¬ (A) - (ear) - (c)

byte (A) ¬ (A) - (eam) - (c)

byte (A) ¬ (AH) - (AL) - (c)

(decimal)

*

–

SUBC

SUBDC

3

4+(a)

3

ADDW

ADDCW

SUBW

SUBCW

A

1

2

2+

3

2

2+

2

2+

1

2

2+

2

0

1

0

2

0

1

0

1

0

2

0

1

0

(c)

0

word (A) ¬ (AH) + (AL)

word (A) ¬ (A) + (ear)

word (A) ¬ (A) + (eam)

word (A) ¬ (A) + imm16

word (ear) ¬ (ear) + (A)

word (eam) ¬ (eam) + (A)

word (A) ¬ (A) + (ear) + (c)

word (A) ¬ (A) + (eam) + (c)

word (A) ¬ (AH) - (AL)

word (A) ¬ (A) - (ear)

word (A) ¬ (A) - (eam)

word (A) ¬ (A) - imm16

word (ear) ¬ (ear) - (A)

word (eam) ¬ (eam) - (A)

word (A) ¬ (A) - (ear) - (c)

word (A) ¬ (A) - (eam) - (c)

–

*

–

-

*

–

-

A, ear

A, eam

A, #imm16

ear, A

eam, A

A, ear

A, eam

A

A. ear

A, eam

A, #imm16

ear, A

eam, A

A, ear

A, eam

3

4+(a)

2

3

0

5+(a)

3

4+(a)

2

4+(a)

2

3

2´ (c)

0

(c)

0

(c)

0

3

2

2+

2

5+(a)

3

4+(a)

2´ (c)

0

(c)

*

–

2+

ADDL

SUBL

A, ear

A, eam

A, #imm32

A, ear

A, eam

2

2+

5

2

2+

5

6

7+(a)

4

2

0

2

0

(d)

0

(d)

0

long (A) ¬ (A) + (ear)

long (A) ¬ (A) + (eam)

long (A) ¬ (A) + imm32

long (A) ¬ (A) - (ear)

long (A) ¬ (A) - (eam)

long (A) ¬ (A) - imm32

–

*

–

6

7+(a)

4

A, #imm32

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

234

Chapter 4: INSTRUCTIONS

4.2 Instructn Set

Table 4.2.10 Increment and Decrement Instructions (Byte/Word/Long-Word) (12

Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

INC

ear

eam

2

2+

3

2

0

byte (ear) ¬ (ear) + 1

byte (ear) ¬ (eam) + 1

–

*

–

-

*

5+(a)

2´ (b)

DEC

ear

eam

2

2+

3

2

0

byte (ear) ¬ (ear) - 1

byte (ear) ¬ (eam) - 1

–

*

–

-

*

5+(a)

2´ (b)

INCW

ear

eam

2

2+

3

2

0

word (ear) ¬ (ear) + 1

word (ear) ¬ (eam) + 1

–

*

–

-

*

5+(a)

2´ (c)

DECW

ear

eam

2

2+

3

2

0

word(ear) ¬ (ear) - 1

word(ear) ¬ (eam) -1

–

*

–

-

*

5+(a)

2´ (c)

INCL

ear

eam

2

2+

7

4

0

long (ear) ¬ (ear) + 1

long (ear) ¬ (eam) + 1

–

*

–

-

*

9+(a)

2´ (d)

DECL

ear

eam

2

2+

7

4

0

long (ear) ¬ (ear) - 1

long (ear) ¬ (eam) - 1

–

*

–

-

*

9+(a)

2´ (d)

Table 4.2.11 Compare Instructions (Byte/Word/Long-Word) (11 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

CMP

A

1

2

2+

2

1

2

0

1

0

(b)

0

byte (AH) - (AL)

byte (A) - (ear)

byte (A) - (eam)

byte (A) - imm8

–

*

–

A ,ear

A ,eam

A, #imm8

3+(a)

2

CMPW

A

1

2

2+

1

2

0

1

0

(c)

word (AH) - (AL)

word (A) - (ear)

word (A) - (eam)

word (A) - imm16

–

*

–

A, ear

A, eam

A, #im16

3+(a)

2

3

0

CMPL

A, ear

A, eam

A, #imm32

2

2+

5

6

7+(a)

3

2

0

(d)

0

long (A) - (ear)

long (A) - (eam)

long (A) - imm32

–

*

–

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

235

4.2 Instructn Set

Table 4.2.12 Unsigned Multiplication and Division Instructions (Word/Long-Word) (11 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

DIVU

A

1

*1

0

word (AH) ¸ byte (AL)

–

*

–

byte (AL) ¬ quotient byte (AH) ¬ remainder

word (A) ¸ byte (ear)

byte (A) ¬ quotient byte (ear) ¬ remainder

word (A) ¸ byte (eam)

byte (A) ¬ quotient byte (eam) ¬ remainder

long ¸ word (ear)

DIVU

A ,ear

A ,eam

A, ear

A, eam

2

2+

2

*2

*3

*4

*5

1

0

1

0

*6

0

–

*

–

DIVU

DIVUW

word (A) ¬ quotient word (ear) ¬ remainder

long ¸ word (eam)

2+

*7

word (A) ¬ quotient word (eam) ¬ remainder

–

MUL

MULUW

A

1

2

2+

1

2

2+

*8

*9

*10

*11

*12

*13

0

1

0

1

0

(b)

0

(c)

word (A) ¬ byte (AH) x byte (AL)

word (A) ¬ byte (A) x byte (ear)

word (A) ¬ byte (A) x byte (eam)

long (A) ¬ word (AH) x word (AL)

long (A) ¬ word (A) x word (ear)

long (A) ¬ word (A) x word (earm)

A, ear

A, eam

A

A, ear

A, eam

–

*1:

*2:

*3:

*4:

*5:

*6:

*7:

*8:

*9:

3 when dividing into zero, 7 when an overflow occurs, and 15 normally.

4 when dividing into zero, 8 when an overflow occurs, and 16 normally.

6 + (a) when dividing into zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.

4 when dividing into zero, 7 when an overflow occurs, and 22 normally.

6 + (a) when dividing into zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.

(b) when dividing into zero or when an overflow occurs, and 2 x (b) normally.

(c) when dividing into zero or when an overflow occurs, and 2 x (c) normally.

3 when byte (AH) is zero, and 7 when byte (AH) is not 0.

4 when byte (ear) is zero, and 8 when byte (ear) is not 0.

*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.

*11: 3 when word (AH) is zero, and 11 when word (AH) is not 0.

*12: 4 when word (ear) is zero, and 12 when word (ear) is not 0.

*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not 0.

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

236

Chapter 4: INSTRUCTIONS

4.2 Instructn Set

Table 4.2.13 Logical 1 Instructions (Byte/Word) (39 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

AND

A, #imm8

2

2+

2

2+

2

3

0

1

0

2

0

(b)

byte (A) ¬ (A) and imm8

byte (A) ¬ (A) and (ear)

byte (A) ¬ (A) and (eam)

byte (ear) ¬ (ear) and (A)

byte (eam) ¬ (eam) and (A)

–

*

R

–

-

A ,ear

A ,eam

ear, A

eam, A

4+(a)

3

5+(a)

0

2´ (b)

*

OR

A, #imm8

A, ear

A, eam

ear, A

eam, A

2

2+

2

2+

2

3

0

1

0

2

0

(b)

byte (A) ¬ (A) or imm8

byte (A) ¬ (A) or (ear)

byte (A) ¬ (A) or (eam)

byte (ear) ¬ (ear) or (A)

byte (eam) ¬ (eam) or (A)

–

*

R

–

-

4+(a)

3

5+(a)

0

2´ (b)

*

XOR

NOT

A, #imm8

A, ear

A, eam

ear, A

eam, A

A

2

2+

2

2+

1

2

3

0

1

0

2

0

2

0

(b)

byte (A) ¬ (A) xor imm8

byte (A) ¬ (A) xor (ear)

byte (A) ¬ (A) xor (eam)

byte (ear) ¬ (ear) xor (A)

byte (eam) ¬ (eam) xor (A)

byte (A) ¬ not (A)

–

*

R

–

-

*

–

-

4+(a)

3

5+(a)

2

3

0

2´ (b)

0

ear

eam

2

2+

byte (ear) ¬ not (ear)

byte (eam) ¬ not (eam)

5+(a)

2´ (b)

*

ANDW

A

1

3

2

2+

2

3

0

1

0

2

0

(c)

0

word (A) ¬ (AH) and (A)

word (A) ¬ (A) and imm16

word (A) ¬ (A) and (ear)

word (A) ¬ (A) and (eam)

word (ear) ¬ (ear) and (A)

word (eam) ¬ (eam) and (A)

–

*

R

–

*

A, #imm16

A, ear

A, eam

ear, A

eam, A

4+(a)

3

5+(a)

2+

2´ (c)

ORW

A

1

3

2

2+

2

2+

2

3

0

1

0

2

0

word (A) ¬ (AH) or (A)

word (A) ¬ (A) or imm16

word (A) ¬ (A) or (ear)

word (A) ¬ (A) or (eam)

word (ear) ¬ (ear) or (A)

word (eam) ¬ (eam) or (A)

–

*

R

–

*

A, #imm16

A, ear

A, eam

ear, A

eam, A

4+(a)

3

5+(a)

(c)

0

2´ (c)

XORW

A

1

3

2

2+

2

2+

2

3

0

1

0

2

0

word (A) ¬ (AH) xor (A)

word (A) ¬ (A) xor imm16

word (A) ¬ (A) xor (ear)

word (A) ¬ (A) xor (eam)

word (ear) ¬ (ear) xor (A)

word (eam) ¬ (eam) xor (A)

–

*

R

–

*

A , #imm16

A, ear

A, eam

ear, A

eam, A

4+(a)

3

5+(a)

(c)

0

2´ (c)

NOTW

A

ear

eam

1

2

2+

2

0

2

0

word (A) ¬ not (A)

word (ear) ¬ not (ear)

word (eam) ¬ not (eam)

–

*

R

–

*

5+(a)

2´ (c)

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

237

4.2 Instructn Set

Table 4.2.14 Logical 2 Instructions (Long-Word) (6 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

–

*

R

–

ANDL

A ,ear

A ,eam

2

2+

6

2

0

(d)

long (A) ¬ (A) and (ear)

long (A) ¬ (A) and (eam)

7+(a)

–

*

R

–

ORL

A, ear

A, eam

2

2+

6

2

0

(d)

long (A) ¬ (A) or (ear)

long (A) ¬ (A) or (eam)

7+(a)

–

*

R

–

XORL

A, ear

A, eam

2

2+

6

2

0

(d)

long (A) ¬ (A) xor (ear)

long (A) ¬ (A) xor (eam)

7+(a)

Table 4.2.15 Sign Inversion Instructions (Byte/Word) (6 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

–

NEG

A

1

2

0

byte (A) ¬ 0 - (A)

X

–

*

NEG

ear

eam

2

2+

2

0

byte (ear) ¬ 0 - (ear)

byte eam) ¬ 0 - (eam)

–

*

5+(a)

2´ (b)

NEGW

A

1

2

0

word (A) ¬ 0 - (A)

–

*

–

NEGW

ear

eam

2

2+

2

0

word (ear) ¬ 0 - (ear)

word (eam) ¬ 0 - (eam)

–

*

5+(a)

2´ (c)

Table 4.2.16 Normalize Instruction (Long-Word) (1 Instruction)

Mnemonic

A, R0

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

–

C

–

RMW

–

long (A) ¬ Shift until first digit

is "1"

NRML

2

*1

0

–

-

–

-

*

byte (R0) ¬ Current shift count

*1:

4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases.

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

238

Chapter 4: INSTRUCTIONS

4.2 Instructn Set

Table 4.2.17 Shift Instructions (Byte/Word/Long-Word) (18 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

–

RORC

A

2

0

byte (A) ¬ Right rotation with

–

*

–

*

carry

A

2

0

byte (A) ¬ Left rotation with

–

*

–

*

–

carry

RORC

ROLC

ear

2

3

2

0

2

0

byte (ear) ¬ Right rotation with

carry

byte (eam) ¬ Right rotation

with carry

byte (ear) ¬ Left rotation with

carry

–

*

–

-

eam

ear

2+

2

5+(a)

3

2´ (b)

0

*

-

*

-

eam

2+

5+(a)

2´ (b)

byte (eam) ¬ Left rotation with

*

carry

ASR

LSR

LSL

A, R0

2

*1

1

0

byte (A) ¬ Arithmetic right

barrel shift (A, R0)

byte (A) ¬ Logical right barrel

shift (A, R0)

byte (A) ¬ Logical left barrel

shift (A, R0)

–

*

–

*

–

*

–

ASRW

LSRW

LSLW

A

1

2

0

word (A) ¬ Arithmetic right

shift (A, 1-bit)

word (A) ¬ Logical right shift

(A, 1-bit)

word (A) ¬ Logical left shift (A,

1-bit)

–

*

–

*

R

*

–

*

–

A / SHRW

A / SHLW A

*

ASRW

LSRW

LSLW

A, R0

2

*1

1

0

word (A) ¬ Arithmetic right

barrel shift (A, R0)

word (A) ¬ Logical right barrel

shift (A, R0)

word (A) ¬ Logical left barrel

shift (A, R0)

–

*

–

*

–

*

–

ASRL

LSRL

LSLL

A, R0

2

*2

1

0

long (A) ¬ Arithmetic right

barrel shift (A, R0)

long (A) ¬ Logical right barrel

–

*

–

*

–

*

–

shift (A, R0)

long (A) ¬ Logical left barrel

shift (A, R0)

*1:

*2:

6 when R0 is 0, 5 + (R0) in all other cases.

6 when R0 is 0, 6 + (R0) in all other cases.

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

239

4.2 Instructn Set

Table 4.2.18 Branch 1 Instructions (31 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

BZ / BEQ

BNZ / BNE

BC / BLO

BNC / BHS

BN

BP

BV

BNV

BT

BNT

BLT

BGE

BLE

BGT

BLS

BHI

BRA

rel

2

*1

0

Branch if (Z) = 1

Branch if (Z) = 0

Branch if (c) = 1

Branch if (c) = 0

Branch if (N) = 1

Branch if (N) = 0

Branch if (V) = 1

Branch if (V) = 0

Branch if (T) = 1

Branch if (T) = 0

Branch if (V) xor (N) = 1

Branch if (V) xor (N) = 0

Branch if ((V) xor (N)) or (Z) = 1

Branch if ((V) xor (N)) or (Z) = 0

Branch if (c) or (Z) = 1

–

-

–

Branch if (c) or (Z) = 0

Branch unconditionally

JMP

JMPP

@A

1

3

2

2+

2

2+

4

2

3

2

0

1

0

2

0

(c)

0

(d)

0

word (PC) ¬ (A)

word (PC) ¬ addr16

word (PC) ¬ (ear)

word (PC) ¬ (eam)

word (PC) ¬ (ear), (PCB) ¬ (ear+2)

word (PC) ¬ (eam), (PCB) ¬ (eam+2)

word (PC) ¬ ad24 0-15, (PCB) ¬ ad24 16-23

–

addr16

@ear

@eam

@ear

@eam

addr24

4+(a)

3

6+(a)

4

Note1

CALL

CALLV

CALLP

@ear

Note3

Note4

Note5

Note6

2

2+

3

1

2

5

7+(a)

6

7

8

1

0

2

0

(c)

2´ (c)

(c)

2´ (c)

*2

word (PC) ¬ (ear)

word (PC) ¬ (eam)

word (PC) ¬ addr16

Vector call instruction

word (PC) ¬ (ear) 0-15, (PCB) ¬ (ear)16-23

word (PC) ¬ addr0-15, (PCB) ¬ addr16-23

–

@eam

addr16

#vct4

@ear

@eam

addr24

2+

4

11+(a)

10

2´ (c)

*1:

*2:

4 when branching, 3 when not branching.

3 × (c) + (b)

Note1: Read (word) branch address.

Note2: W: Save (word) into stack; R: read (word) branch address.

Note3: Save (word) into stack.

Note4: W: Save (long-word) into W stack; R: read (long-word) R branch address.

Note5: Save (long-word) into stack.

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

240

Chapter 4: INSTRUCTIONS

4.2 Instructn Set

Table 4.2.19 Branch 2 Instructions (19 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

CBNE

CWBNE

A, #imm8, rel

A, #imm16, rel

3

4

*1

0

Branch if byte (A) ¹ imm8

Branch if word (A) ¹ imm16

–

*

–

CBNE

CWBNE

ear, #imm8, rel

eam, #imm8, rel

ear, #imm16, rel

eam, #imm16, rel

4

4+

5

*2

*3

*4

*3

1

0

1

0

(b)

0

Branch if byte (ear) ¹ imm8

Branch if byte (eam) ¹ imm8

Branch if word (ear) ¹ imm16

Branch if word (eam) ¹ imm16

–

*

–

5+

(c)

DBNZ

ear, rel

eam, rel

3

3+

*5

*6

2

0

Branch if byte (ear) = (ear)-1, (ear) ¹ 0

Branch if byte (eam) = (eam)-1, (eam) ¹ 0

–

*

–

*

2´ (b)

DWBNZ

ear, rel

eam, rel

3

3+

*5

*6

0

Branch if word (ear) = (ear)-1, (ear) ¹ 0

Branch if word (eam) = (eam)-1, (eam) ¹ 0

–

*

–

*

2 ´ (c)

INT

INTP

INT9

RETI

#vct8

addr16

addr24

2

3

4

1

20

16

17

20

15

0

8´ (c)

6´ (c)

8´ (c)

6´ (c)

Software interrupt

–

R

*

S

*

–

*

–

*

–

*

–

*

–

*

–

Return from interrupt processing

LINK

#imm8

2

6

0

(c)

At function entry, saves the old frame pointer

to the stack, sets the new frame pointer, and

reserves the local pointer area.

At function exit, restores the old frame

pointer from the stack.

–

UNLINK

1

5

0

–

RET

RETP

Note1

Note2

1

4

6

0

(c)

(d)

Return from subroutine

–

*1:

*2:

*3:

*4:

*5:

*6:

5 when branching, 4 when not branching

13 when branching, 12 when not branching

7 + (a) when branching, 6 + (a) when not branching

8 when branching, 7 when not branching

7 when branching, 6 when not branching

8 + (a) when branching, 7 + (a) when not branching

Note1: Return from stack (word)

Note2: Return from stack (long)

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

241

4.2 Instructn Set

Table 4.2.20 Other Control Instructions (Byte/Word/Long-Word) (28 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

PUSHW

A

1

2

4

0

(c)

*4

word (SP) ¬ (SP) - 2, ((SP)) ¬ (A)

word (SP) ¬ (SP) - 2, ((SP)) ¬ (AH)

word (SP) ¬ (SP) - 2, ((SP)) ¬ (PS)

(SP) ¬ (SP) - 2n, ((SP)) ¬ (rlst)

–

AH

PS

rist

*3

+&

POPW

A

1

2

3

4

0

(c)

*4

word (A) ¬ ((SP)) , (SP) ¬ (SP) + 2

word (AH) ¬ ((SP)) , (SP) ¬ (SP) + 2

word (PS) ¬ ((SP)) , (SP) ¬ (SP) + 2

(rlst) ¬ ((SP)) , (SP) ¬ (SP)

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

AH

PS

rlst

–

*2

+&

–

JCTX

@A

1

14

0

6´ (c)

Context switch (process switch) instruction

–

*

–

AND

OR

CCR, #imm8

2

3

0

byte (CCR) ¬ (CCR) and imm8

byte (CCR) ¬ (CCR) or imm8

–

*

–

MOV

RP, #imm8

ILM, #imm8

2

0

byte (RP) ¬ imm8

byte (ILM) ¬ imm8

–

MOVEA

RWi, ear

RWi, eam

A, ear

2

2+

2

3

1

0

word (RWi) ¬ ear

word (RWi) ¬ eam

word (A) ¬ ear

–

*

–

2+(a)

1

1+(a)

A, eam

2+

word (A) ¬ eam

*

ADDSP

#imm8

#imm16

2

3

0

word (SP) ¬ (SP)+ext(imm8)

word (SP) ¬ (SP)+imm16

–

MOV

A, brg1

brg2, A

2

*1

1

0

byte (A) ¬ (brg1)

byte (brg2) ¬ (A)

Z

–

*

–

*

–

NOP

ADB

DTB

PCB

SPB

NCC

CMR

1

0

No operation

–

Prefix code for auxiliary AD access

Prefix code for data DT access

Prefix code for program PC access

Prefix code for stack SP access

Prefix code for no flag change

Prefix for common register bank

*1:

PCB, ADB, SSB, USB, and SPB: .....1 cycle

DTB, DPR: ........................................2 cycles

*2:

*3:

*4:

*5:

7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when RLST = 0

29 + 3 × (pop count) - 3 × (last register number to be popped), 8 when RLST = 0

Pop count × (c), or push count × (c)

Pop count, or push count

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

242

Chapter 4: INSTRUCTIONS

4.2 Instructn Set

Table 4.2.21 Bit Manipulation Instructions (21 Instructions)

Mnemonic

A ,dir: bp

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

MOVB

3

4

3

5

4

0

(b)

byte (A) ¬ (dir:bp)b

byte (A) ¬ (addr16:bp)b

byte (A) ¬ (io:bp)b

Z

*

–

*

–

A ,addr16: bp

A, io: bp

MOVB

dir: bp, A

addr16: bp, A

io: bp, A

3

4

3

7

6

0

2´ (b)

bit (dir:bp)b ¬ (A)

bit (addr16:bp)b ¬ (A)

bit (io:bp)b ¬ (A)

–

*

–

*

SETB

dir: bp

addr16: bp

io: bp

3

4

3

7

0

2´ (b)

bit (dir:bp)b ¬

bit (addr16:bp)b ¬

bit (io:bp)b ¬

bit (dir:bp)b ¬

bit (addr16:bp)b ¬

bit (io:bp)b ¬

1

–

*

1

0

1

CLRB

dir: bp

addr16: bp

io: bp

3

4

3

7

0

2´ (b)

0

–

*

0

BBC

dir: bp, rel

addr16: bp, rel

io: bp, rel

4

5

4

*1

*2

0

(b)

Branch if (dir:bp)b = 0

Branch if (addr16:bp)b = 0

Branch if (io:bp)b = 0

–

*

–

BBS

dir:bp, rel

addr16:bp, rel

io:bp, rel

4

5

4

*1

*2

0

(b)

Branch if (dir:bp)b = 1

Branch if (addr16:bp)b = 1

Branch if (io:bp)b = 1

–

*

–

SBBS

WBTS

WBTC

addr16:bp, rel

io:bp

5

3

*3

*4

0

2´ (b)

*5

Branch if (addr16:bp)b = 1, bit = 1

Wait until (io:bp)b = 1

–

*

–

*

–

io:bp

*5

Wait until (io:bp)b = 0

*1:

*2:

*3:

*4:

*5:

8 when branching, 7 when not branching

7 when branching, 6 when not branching

10 when condition is satisfied, 9 when not satisfied

Undefined count

Until condition is satisfied

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

243

4.2 Instructn Set

Table 4.2.22 Accumulator Manipulation Instructions (Byte/Word) (6 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

SWAP

SWAP / XCHW

EXT

EXTW

ZEXT

1

3

2

1

2

1

0

byte (A)0 -7« (A)8-15

word (AH) « (AL)

Byte sign extension

Word sign extension

Byte zero extension

Word zero extention

–

X

–

Z

–

*

–

X

–

Z

–

*

R

–

*

–

A,T

ZEXTW

Table 4.2.23 String Instructions (10 Instructions)

Mnemonic

#

~

RG

B

Operation

LH

AH

I

S

T

N

Z

V

C

RMW

MOVS

MOVSD

/

MOVSI

2

*2

+&

*3

Byte move @AH+ ¬ @AL+, counter = RW0

Byte move @AH- ¬ @AL-, counter = RW0

–

SCEQ

SCEQD

/

SCEQ1

2

*1

+&

*4

Byte search (@AH+) ~ AL, counter = RW0

Byte search (@AH-) ~ AL, counter = RW0

–

*

–

FILS / FILS1

2

6m+6

+&

*3

Byte fill

@AH+ ¬ AL, counter = RW0

–

*

–

MOVSW

MOVSWD

/

MOVSWI

SCWEQI

FILSWI

2

*2

+)

*6

Word move @AH+ ¬ @AL+, counter = RW0

Word move @AH- ¬ @AL-, counter = RW0

–

SCWEQ

SCWEQD

/

2

*1

+)

*7

Word search (@AH+) — AL, counter = RW0

Word search (@AH-) — AL, counter = RW0

–

*

–

FILSW

/

2

6m+6

+)

*6

Word fill @AH+ ¬ AL, counter = RW0

–

*

–

*1:

*2:

*3:

*4:

*5:

*6:

*7:

*8:

m:

5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7n + 5 when match occurs

5 when RW0 is 0, 4 + 8 × (RW0) in any other case

(b) × (RW0)

(b) × n

2 × (RW0)

(c) × (RW0)

(c) × n

2 × (RW0)

RW0 value (counter value)

Loop count

n:

Note: For an explanation of "(a)" to "(d)", see Table 4.2.3 and Table 4.2.4.

244

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

Because the F²MC-16L operation codes each consist of one or two bytes, the instruction map consists of

numerous pages. The structure of the instruction map is shown below.

Basic Page Map

First byte

Bit manipulation

Instructions

Character string

manipulation instructions

Second byte

"ea" instructions x 9

2-byte instructions

Fig. 4.3.1 Structure of F²MC-16L Instruction Map

Instructions that consist of only one byte (such as NOP) are concluded on the basic page. Regarding

instructions that require two bytes (such as MOVS), the existence of the map for the second byte is

indicated when the first byte is referenced, so it is clear that it is necessary to use the following byte to

reference the map for the second byte.

245

4.3 Instruction Map

The correspondence between the actual instruction code and the instruction map is shown below.

May not exist for some instructions

Length differs according to the

instruction

Instruction code

First byte Second byte operand

operand

• • •

[Basic Page Map]

XY

+Z

[Extension page map] Note 1

UV

+W

Note1: Extended page maps are provided for bit manipulation instructions, character string manipulation

instructions, two-byte instructions, and "ea" instructions; multiple-extended-page maps exist for

each type of instruction.

Fig. 4.3.2 Correspondence between Actual Instructions and the Instruction Maps

246

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

247

4.3 Instruction Map

248

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

249

4.3 Instruction Map

250

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

d e t i b i h o r p e s U

251

4.3 Instruction Map

252

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

253

4.3 Instruction Map

254

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

255

4.3 Instruction Map

256

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

257

4.3 Instruction Map

258

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

259

4.3 Instruction Map

260

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

261

4.3 Instruction Map

262

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

263

4.3 Instruction Map

264

Chapter 4: INSTRUCTIONS

4.3 Instruction Map

265

4.3 Instruction Map

266

Chapter 4: INSTRUCTIONS


型号：	MB90623PFS
厂家：	FUJITSU
描述：	Microcontroller 时钟微控制器
文件：	总271页 (文件大小：2636K)
中文：	中文翻译
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