MB90641A_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-13608-1E

16-bit Proprietary Microcontroller

CMOS

F²MC-16L MB90640A Series

MB90641A/P641A

■ DESCRIPTION

MB90640A series includes 16-bit microcontrollers optimally suitable for process control in a wide variety of

industrial and OA equipment. The series uses the F²MC*-16L CPU which is based on the F²MC-16 but with

enhanced high-level language and task switching instructions and additional addressing modes.

The internal peripheral resources consist of a 2-channel serial port incorporating a UART function (and

supporting I/O expansion serial mode), 8/16-bit 2-channel PPG, 5-channel 16-bit reload timer, 8-channel chip

select function, and 8-channel DTP/external interrupts.

Also, multiplexed or non-multiplexed operation can be selected for the address/data bus.

*: F²MC stands for FUJITSU Flexible Microcontroller.

■ FEATURES

F²MC-16L CPU

• Minimum instruction execution time: 58.8 ns/4.25 MHz oscillation (Uses PLL clock multiplication),

maximum multiplier = 4

• Instruction set optimized for controller applications

Upward object code compatibility with F²MC-16 (H)

Wide range of data types (bit/byte/word/long word)

Improved instruction cycles provide increased speed

Additional addressing modes: 23 modes

(Continued)

■ PACKAGE

100-pin Plastic LQFP

100-pin Plastic QFP

(FPT-100P-M05)

(FPT-100P-M06)

MB90640A Series

(Continued)

High code efficiency

Access methods (bank access/linear pointer)

Enhanced multiplication and division instructions (signed instructions added)

High precision operations are enhanced by use of a 32-bit accumulator

Extended intelligent I/O service (access area extended to 64 Kbytes)

Maximum memory space: 16 Mbytes

• Enhanced high level language (C)/multitasking support instructions

Use of a system stack pointer

Enhanced pointer indirect instructions

Barrel shift instructions

Stack check function

• Improved execution speed: Four byte instruction queue

• Powerful interrupt function

• Automatic data transfer function (does not use instructions)

Internal peripherals

• RAM: 2 Kbytes

• General purpose ports Data bus, multiplexed mode: 56 ports max.

Non-multiplexed mode:

Single-chip mode:

48 ports max.

75 ports max.

• UART0, 1 (SCI): 2 channels

For either asynchronous or clocked serial transfer (I/O expansion serial)

• 8/16-bit PPG (programmable pulse generator): 2 channels

• 16-bit reload timer: 5 channels

• Chip select function: 8 channels

• DTP/external interrupts: 8 channels

• Timebase timer/watchdog timer

• PLL clock multiplier function

• CPU intermittent operation function

• Various standby modes

• Packages: LQFP-100 and QFP-100

• CMOS technology

2

MB90640A Series

■ PRODUCT LINEUP

Part number

Item

MB90641A

MB90P641A

Classification

ROM size

Mask ROM

64 Kbytes

One-time PROM

64 Kbytes

RAM size

2 Kbytes

CPU functions

The number of instructions: 340

Instruction bit length:

Instruction length:

Data bit length:

8/16 bits

1 to 7 bytes

1/4/8/16/32 bits

Minimum execution time: 58.8 ns at 4.25 MHz (PLL multiplier = 4)

Interrupt processing time: 941 ns at 17 MHz (minimum)

Ports

8/16-bit data bus, multiplexed mode: 56 ports (max)

8-bit non-multiplexed mode:

Single-chip mode:

48 ports (max)

75 ports (max)

Packages

FPT-100P-M05

FPT-100P-M06

UART0, 1 (SCI)

Two internal UARTs

Full-duplex, double-buffered

Selectable clock synchronous or asynchronous operation

Built-in dedicated baud rate generator

8/16-bit PPG

2 × 8-bit PPG outputs

(1 channel PPG output in 16-bit mode)

16-bit reload timer

16-bit reload timer operation (selectable toggle output, one-shot output)

(Selectable count clock: 0.125 µs, 0.5 µs, or 2.0 µs for a 16 MHz machine cycle)

Selectable event count function, 5 internal channels

Chip select function

8 outputs

DTP/external interrupts

8 inputs

External interrupt mode

(Interrupts can be generated from four different types of request signal)

PLL function

Selectable multiplier: 1/2/3/4

(Set a multiplier that does not exceed the assured operation frequency range.)

External bus terminal

control circuit

Multiplex and non-multiplex between the adress pin and the data pin is selectable.

3

MB90640A Series

■ PIN ASSIGNMENT

(Top view)

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

RST

P22/A02

P23/A03

P24/A04

P25/A05

P26/A06

P27/A07

P30/A08

P31/A09

V^SS

P32/A10

P33/A11

P34/A12

P35/A13

P36/A14

P37/A15

P40/A16

P41/A17

P42/A18

P43/A19

P44/A20

V^CC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P54/WRH

P53/HRQ

P52/HAK

P51/RDY

P50/CLK

PA7/CS7

PA6/CS6

PA5/CS5

PA4/CS4

PA3/CS3

PA2/CS2

PA1/CS1

PA0/CS0

P95

P94

P93

P92/SCK1

P91/SOT1

P90/SIN1

P86/SCK0

P85/SOT0

P84/SIN0

P83/TIM3

P82/TIM2

P45/A21

P46/A22

P47/A23

C

(FPT-100P-M05)

4

MB90640A Series

(Top view)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P20/A00

P21/A01

P22/A02

P23/A03

P24/A04

P25/A05

P26/A06

P27/A07

P30/A08

P31/A09

V^SS

P32/A10

P33/A11

P34/A12

P35/A13

P36/A14

P37/A15

P40/A16

P41/A17

P42/A18

P43/A19

P44/A20

V^CC

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

P57/ALE

P56/RD

P55/WRL

RST

P54/WRH

P53/HRQ

P52/HAK

P51/RDY

P50/CLK

PA7/CS7

PA6/CS6

PA5/CS5

PA4/CS4

PA3/CS3

PA2/CS2

PA1/CS1

PA0/CS0

P95

P94

P93

P92/SCK1

P91/SOT1

P90/SIN1

P86/SCK0

P85/SOT0

P84/SIN0

P83/TIM3

P82/TIM2

HST

P45/A21

P46/A22

P47/A23

C

P71/INT1

P72/INT2

P73/INT3/TIM4

MD2

(FPT-100P-M06)

5

MB90640A Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

LQFP*¹

QFP*²

80,

81

82,

83

X0,

X1

A

Crystal oscillator pins

47 to 49 49 to 51 MD0 to MD2

E

Input pins for specifying an opration mode.

Use these pins by directly connecting V^CCor VSS.

(CMOS)

75

50

77

52

RST

HST

G

External reset request input pin

(CMOS/H)

F

Hardware standby input pin

(CMOS/H)

83 to 90 85 to 92 P00 to P07

J

General purpose I/O ports

This applies in single-chip mode with an external data bus

in 8-bit mode.

(TTL)

D00 to D07

AD00 to AD07

In non-multiplex mode, the I/O pins for the lower 8 bits of

the external data bus.

In multiplexed mode, the I/O pins for the lower 8 bits of the

external address/data bus.

91 to 98 93 to 100 P10 to P17

J

General purpose I/O ports

This applies in non-multiplexed mode with an 8-bit external

(TTL)

data bus and in single-chip mode.

P08 to D15

In non-multiplexed mode with a 16-bit external data bus,

the I/O pins for the upper 8 bits of the external data bus.

AD08 to AD15

In multiplexed mode, the I/O pins for the upper 8 bits of the

external address/data bus.

99,

100,

1 to 6

1,

2,

P20,

P21,

B

General purpose I/O ports

This applies in multiplexed mode.

(CMOS)

3 to 8 P22 to P27

A00,

A01,

In non-multiplexed mode, the output pins for the lower 8

bits of the external address bus.

A02 to A07

7,

8,

9,

10,

P30,

P31,

B

General purpose I/O ports

This applies in multiplexed mode.

(CMOS)

10 to 15 12 to 17 P32 to P37

A08,

A09,

In non-multiplexed mode, the output pins for the upper 8

bits of the external address bus.

A10 to A15

16 to 20, 18 to 22, P40 to P44,

B

General purpose I/O ports

This applies when the upper address control register

specifies port operation.

22 to 24

24 to 26 P45 to P47

(CMOS)

A16 to A20,

A21 to A23

Output pins for A16 to A23 of the external address bus

This applies when the upper address control register

specifies address operation.

*1: FPT-100P-M05

*2: FPT-100P-M06

(Continued)

6

MB90640A Series

Pin no.

Circuit

type

Pin name

P50

Function

LQFP*¹

QFP*²

70

71

72

73

74

72

I

General purpose I/O port

(CMOS)

This applies when CLK output is disabled.

CLK

P51

RDY

P52

HAK

P53

HRQ

P54

CLK output pin

This applies when CLK output is enabled.

73

74

75

76

K

(TTL)

General purpose I/O port

This applies when the external ready function is disabled.

Ready input pin

This applies when the external ready function is enabled.

I

General purpose I/O port

This applies when the hold function is disabled.

(CMOS)

Hold acknowledge output pin

This applies when the hold function is enabled.

K

(TTL)

General purpose I/O port

This applies when the hold function is disabled.

Hold request input pin

This applies when the hold function is enabled.

I

General purpose I/O port

This applies in 8-bit external bus mode or when output is

(CMOS)

disabled for the WRH pin.

WRH

Write strobe output pin for the upper 8 bits of the data bus

This applies in 16-bit external bus mode and when output is

enabled for the WRH pin.

76

78

P55

WRL

P56

I

General purpose I/O port

This applies when output is disabled for the WRL pin.

(CMOS)

Write strobe output pin for the lower 8 bits of the data bus

This applies when output is enabled for the WRL pin.

77

78

79

80

I

General-purpose I/O port

This port is available in the single-chip mode.

(CMOS)

RD

Read strobe output pin for the data bus

P57

I

General-purpose I/O port

(CMOS)

This port is available in the single-chip mode.

ALE

Address latch enable output pin

Open-drain output ports

36 to 39, 38 to 41, P60 to P67

41 to 44 43 to 46

C

(Continued)

*1: FPT-100P-M05

*2: FPT-100P-M06

7

MB90640A Series

Pin no.

Circuit

type

Pin name

Function

General purpose I/O ports

LQFP*¹

QFP*²

26,

27

28,

29

P71,

P72

H

(CMOS/H) This applies in all cases.

INT1,

INT2

External interrupt request input pins

As the inputs operate continuously when external interrupts

are enabled, output to the pins from other functions must

be stopped unless done intentionally.

28

30

P73

H

General purpose I/O ports

(CMOS/H) This applies when output is disabled for reload timers.

INT3

External interrupt request input pins

As the inputs operate continuously when external interrupts

are enabled, output to the pins from other functions must

be stopped unless done intentionally.

TIM4

I/O pins for reload timers

Input is used only as necessary while serving as input for

the reload timer.

It is therefore necessary to stop output beforehand using

other functions unless intentionally used otherwise.

Their function as output terminals for the reload timer is

activated when the output specification is enabled.

29,

30

31,

32

P74,

P75

H

General purpose I/O ports

(CMOS/H) This applies when the waveform outputs for PPG timers 0,

1 are disabled.

INT4,

INT5

External interrupt request input pin

As the input operates continuously when the external

interrupt is enabled, output to the pin from other functions

must be stopped unless done intentionally.

PPG0,

PPG1

Output pins for PPG timers

This applies when the waveform outputs for PPG timers 0,

1 are enabled.

31

33

P76

H

General purpose I/O port

(CMOS/H) This applies in all cases.

INT6

External interrupt request input pin

As the input operates continuously when the external

interrupt is enabled, output to the pin from other functions

must be stopped unless done intentionally.

(Continued)

*1: FPT-100P-M05

*2: FPT-100P-M06

8

MB90640A Series

Pin no.

Circuit

type

Pin name

P80,

Function

LQFP*¹

QFP*²

45,

46

47,

48

H

General purpose I/O ports

P81

(CMOS/H) This applies when output is disabled for reload timers.

INT7,

INT0

External interrupt request input pin

As the input operates continuously when the external

interrupt is enabled, output to the pin from other functions

must be stopped unless done intentionally.

TIM0,

TIM1

I/O pins for reload timers

Input is used only as necessary while serving as input for

the reload timer.

It is therefore necessary to stop output beforehand using

other functions unless intentionally used otherwise.

Their function as output terminals for the reload timer is

activated when the output specification is enabled.

51,

52

53,

54

P82,

P83

D

General purpose I/O ports

(CMOS/H) This applies when output is disabled for reload timers.

TIM2,

TIM3

I/O pins for reload timers

Input is used only as necessary while serving as input for

the reload timer. It is therefore necessary to stop output

beforehand using other functions unless intentionally used

otherwise.

Their function as output terminals for the reload timer is

activated when the output specification is enabled.

53

55

P84

D

General purpose I/O port

This applies in all cases.

(CMOS/H)

SIN0

Serial data input pin for UART0

As the input operates continuously when UART0 is set to

input operation, output to the pin from other functions must

be stopped unless done intentionally.

54

55

56

57

P85

D

General purpose I/O port

This applies when serial data output is disabled for UART0.

(CMOS/H)

SOT0

P86

Serial data output pin for UART0

This applies when serial data output is enabled for UART0.

D

General purpose I/O port

This applies when the UART0 clock output is disabled.

(CMOS/H)

SCK0

Clock I/O pin for UART0

This applies when the UART0 clock output is enabled.

As the input operates continuously when UART0 is set to

input operation, output to the pin from other functions must

be stopped unless done intentionally.

56

58

P90

D

General purpose I/O port

This applies in all cases.

(CMOS/H)

SIN1

Serial data input pin for UART1

As the input operates continuously when UART1 is set to

input operation, output to the pin from other functions must

be stopped unless done intentionally.

(Continued)

*1: FPT-100P-M05

*2: FPT-100P-M06

9

MB90640A Series

(Continued)

Pin no.

Circuit

type

Pin name

Function

General purpose I/O port

LQFP*¹

QFP*²

57

59

P91

D

(CMOS/H) This applies when serial data output is disabled for UART1.

SOT1

P92

Serial data output pin for UART1

This applies when serial data output is enabled for UART1.

58

60

D

General purpose I/O port

(CMOS/H) This applies when the UART1 clock output is disabled.

SCK1

Clock I/O pin for UART1

This applies when the UART1 clock output is enabled.

As the input operates continuously when UART1 is set to

input operation, output to the pin from other functions must

be stopped unless done intentionally.

59 to 61 61 to 63 P93 to P95

25 27

D

General purpose I/O port

(CMOS/H)

C

—

Capacitor pin for stabilizing power supply

Connect about 0.1 µF ceramic capacitor outside ROM.

MB90P641 doesn’t need to be connected the capacitor.

It isn’t problem even the capacitor is connected to

MB90P641A.

62 to 69 64 to 71 PA0 to PA7

CS0 to CS7

I

General purpose I/O ports

(CMOS/H) This applies for pins with chip select output disabled by the

chip select control register.

Output pins for the chip select function

This applies for pins with chip select output enabled by the

chip select control register.

21,

32,

33,

82

23,

34,

35,

84

V^CC

Power

supply

Power supply for the digital circuits

9,

34,

35,

40,

79

11,

36,

37,

42,

81

V^SS

Power

supply

Ground level for the digital circuits

*1: FPT-100P-M05

*2: FPT-100P-M06

10

MB90640A Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

• Max. 3 to 34 MHz

X1

• Oscillation feedback resistance:approximately

Clock input

1 MΩ

X0

Standby control

B

• CMOS level I/O

With standby control

• Pull-up resistor option

Digital output

R

Digital input

Standby control

C

• N-channel open-drain output

• CMOS level hysteresis input

• Pull-up resistor option

Digital output

R

Digital input

Standby control

D

• CMOS level output

• CMOS level hysteresis input

With standby control

• Pull-up resistor option

Digital output

R

Digital input

Standby control

Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in

the standby state.

(Continued)

11

MB90640A Series

Type

Circuit

Remarks

E

• CMOS level input

No standby control

• Pull-up resistor option

R

Digital input

F

• CMOS level hysteresis input

No standby control

• Pull-up resistor option

R

Digital input

G

H

I

• CMOS level hysteresis input

No standby control

• With pull-up resistor

R

Digital input

• CMOS level output

• CMOS level hysteresis input

No standby control

Digital output

• Pull-up resistor option

R

Digital input

• CMOS level output

• CMOS level hysteresis input

• Pull-up resistor approximately 50 kΩ

• Pin goes to high impedance during stop mode.

Standby control

Digital output

R

Digital input

Standby control

Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in

the standby state.

(Continued)

12

MB90640A Series

(Continued)

Type

Circuit

Remarks

J

• CMOS level output

• TTL level input

With standby control

• Pull-up resistor option

Digital output

R

Digital input

Standby control

K

• CMOS level output

• TTL level input

• Pull-up resistor approximately 50 kΩ

• Pin goes to high impedance during stop mode.

Standby control

Digital output

R

Digital input

Standby control

Note: For pins with pull-up resistors, the resistance is disconnected when the pin outputs the “L” level or when in

the standby state.

13

MB90640A Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or less than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in “■ Electrical Characteristics” is applied between V^CCand VSS.

When latchup occurs, power supply current increases rapidlly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the anaolg power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (V^CC) when the analog system power supply is truned on and off.

2. Treatment of Unused Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resister.

3. Cautions when Using an External Clock

Drive the X0 pin only when using an external clock.

• Using an external clock

X0

OPEN

X1

MB90640A

4. Power Supply Pins

When there are several VCC and VSS pins, those pins that should have the same electric potential are connected

within the device when the device is designed in order to prevent misoperation, such as latchup. However, all

of those pins must be connected to the power supply and ground externally in order to reduce unnecessary

emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the

total output current standards.

In addition, give a due consideration to the connection in that current supply be connected to V^CCand VSS with

the lowest possible impedance.

Finally, it is recommended to connect a ceramic capacitor of about 0.1 µF between V^CCand VSS near this device

as a bypass capacitor.

5. Crystal Oscillation Circuit

Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit

board so that the bypass capacitor connecting X0, X1 and the crystal oscillator (or ceramic oscillator) to ground

is located as close to the device as possible, and possibly take care not to cross over the other wiring with this

wiring.

In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded

by ground provides stable operation, such an arrangement is strongly recommended.

14

MB90640A Series

■ PROGRAMMING TO THE ONE-TIME PROM ON THE MB90P641A

MB90P641A has a function PROM mode function equivalent to MBM27C1000/1000A, so it can be written by

general ROM writer using special adapter. But take attention it doesn’t corsespond to the elctronic signature

(the device identification code) mode.

1. Programming Procedure

Memory map in the PROM mode is as below. Write option data to the option setting erea refering to the 6 PROM

option bit map.

PROM mode

Normal operating made

FFFFFF^H

1FFFF^H

Program area

(PROM)

Program area

(PROM)

Address*¹

Address*²

010000H

0002CH

00000^H

Option

setting area

ROM image

Mirror

004000H

000000H

Product

MB90P641A

Address^*1

10000^H

Address^*2

Number of bytes

64 Kbytes

FF0000H

Note: The 00 bank ROM image is 48 Kbyes. (This is a ROM image for FF4000H to FFFFFFH.

Only when the ROM mirror function selecting resister is enable.)

Porocedure of the programing to the one-time PROM microcomputer is as below.

(1) Set the EPROM programmer for the MBM27C1000/1000A.

(2) Load the program data into the EPROM programmer at address*¹to 1FFFFH. When specify the PROM

option, load the option data to 00000^Hto 00002CH to refering to “6. PROM Option Bitmap”.

(3) Insert the device in the socket adapter, and mount the socket adapter on the EPROM programmer. Pay

attention to the orientation of the device and of the socket adapter when doing so.

(4) Program to 00000^Hto 1FFFFH.

Notes: • Because the mask ROM products do not have a PROM mode, they cannot read date from the EPROM

programmer.

• Contact the sales department when purchasing an EPROM programmer.

15

MB90640A Series

2. Program Mode

In the MB90P641A, all of the bits are set to “1” when the IC is shipped from Fujitsu and after erasure. To input

data, program the IC by selectively setting the desired bits to “0”. Bits cannot be set to “1” electrically.

3. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

one-time PROM with microcontroller program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

4. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked one-time PROM microcomputer, due to its

nature. For this reason, a programming yield of 100% cannot be assured at all times.

5. EPROM Programmer Socket Adapter and Recommended Programmer Manuffacturer

Part no.

Package

MB90P641APF

QFP-100

MB90P641APFV

LQFP-100

Compatible socket adapter

Sun Hayato Co., Ltd.

ROM-100QF-32DP

-FFMC-16L

ROM-100SQF-32DP

-FFMC-16L

Recommended

1890A

1891

Recommended

Minato

Electronics

programmer

manufacturer

and programmer Inc.

1930

Recommended

name

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

Minato Electronics Inc.: TEL: USA (1)-916-348-6066

JAPAN (81)-45-591-5611

16

MB90640A Series

6. PROM Option Bitmap

Address

Bit 7

Bit 6

RST

Pull-up

Bit 5

Bit 4

MD 1

Pull-up

Bit 3

MD 1

Pull-down Pull-up

Bit 2

Bit 1

MD 0

Pull-down

Bit 0

Vacancy

MD 0

Vacancy

00000H

1: No

0: Yes

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

00004H

00008H

0000CH

00010H

00014H

0001CH

00020H

00024H

00028H

0002CH

P17

P16

P15

P14

P13

P12

P11

P10

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P27

P26

P25

P24

P23

P22

P21

P20

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P47

P46

P45

P44

P43

P42

P41

P40

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P57

P56

P55

P54

P53

P52

P51

P50

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P76

P75

P74

P73

P72

P71

Vacancy

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P86

P85

P84

P83

P82

P81

P80

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P95

P94

P93

P92

P91

P90

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Note: Write data “1” to the vacant bit and the adress other than above.

17

MB90640A Series

■ BLOCK DIAGRAM

X0, X1

RST

HST

MD0 to MD2

CPU

7

Clock control

circuit

F²MC-16L family core

Interrupt controller

RAM

8/16-bit PPG

(output switching) × 1channel

PPG0

PPG1

Communication prescaler

UART

2

SIN0, SIN1

SOT0, SOT1

SCK0, SCK1

ROM

8

24

16

INT0 to INT7

DTP/external interrupts

A00 to A23

D00 to D15

ALE

RD

WRL, WRH

HRQ

2

External bus Interface

5

TIM0 to TIM4

CS0 to CS7

16-bit reload timer

HAK

RDY

CLK

8

Chip select functions

I/O ports

Ohter pins

8

6

7

6

8

AD00 to AD15, C,

VCC, VSS

P00 P10 P20 P30 P40 P50 P60 P71 P80 P90 PA0

to to to to to to to to to to to

P07 P17 P27 P37 P47 P57 P67 P76 P86 P95 PA7

18

MB90640A Series

■ MEMORY MAP

Internal ROM/

external bus mode

External ROM/

external bus mode

Single chip mode

ROM area

FFFFFFH

ROM area

FF0000H

F00000H

00FFFFH

ROM area

(FF bank image)

004000H

002000H

Address #1

RAM

Registers

000100H

0000C0H

Peripherals

000000H

Type

Address #1

MB90641A

000900

H

MB90P641A

000900

H

: Internal access memory

: External access memory

: No access

Note: When disable output upper address A23 to A16 of MB90640A series, the maximum acceptable size

becomes 64 Kbytes.

19

MB90640A Series

■ F²MC-16L CPU PROGRAMMING MODEL

• Dedicated registers

Accumulator

AH

AL

USP

SSP

PS

User stack pointer

System stack pointer

Processor status

Program counter

PC

Direct page register

DPR

Program bank register

Data bank register

PCB

DTB

USB

SSB

ADB

User stack bank register

System stack bank register

Additional data bank register

8 bits

16 bits

32 bits

• General-purpose registers

32 banks (max.)

R7

R5

R3

R1

R6

RW7

RW6

RW5

RW4

RL3

RL2

RL1

RL0

R4

R2

R0

RW3

RW2

RW1

RW0

000180 ^H+ RP × 10 H →

16 bits

• Processor status (PS)

ILM

RP

—

I

S

T

N

Z

V

C

CCR

20

MB90640A Series

■ I/O MAP

Read/

Address

Name

Register

Port 0 data register

Resource name

Initial value

write*^4,*⁵

000000^HPDR0

000001H PDR1

000002H PDR2

000003H PDR3

000004H PDR4

000005H PDR5

000006H PDR6

000007H PDR7

000008H PDR8

000009H PDR9

00000AH PDRA

R/W*

R/W

Port 0^*8

Port 1^*7

Port 2^*6

Port 3^*6

Port 4

X X X X X X X X B

1 1 1 1 1 1 1 1 B

– X X X X X X X B

– – X X X X X X B

X X X X X X X – B

Port 1 data register

Port 2 data register

Port 3 data register

Port 4 data register

Port 5 data register

Port 6 data register

Port 7 data register

Port 8 data register

Port 9 data register

Port A data register

Port 5^*8

Port 6

Port 7

Port 8

Port 9

Port A^*8

00000BH

—

Vacancy

*3

—

to 0FH

000010^HDDR0

000011H DDR1

000012H DDR2

000013H DDR3

000014H DDR4

000015H DDR5

000016H DDR6

000017H DDR7

000018H DDR8

000019H DDR9

00001AH DDRA

Port 0 direction register

Port 1 direction register

Port 2 direction register

Port 3 direction register

Port 4 direction register

Port 5 direction register

Port 6 direction register

Port 7 direction register

Port 8 direction register

Port 9 direction register

Port A direction register

R/W*

R/W

Port 0^*8

Port 1^*7

Port 2^*6

Port 3^*6

Port 4

0 0 0 0 0 0 0 0 B

1 1 1 1 1 1 1 1 B

– 0 0 0 0 0 0 – B

– 0 0 0 0 0 0 0 B

– – 0 0 0 0 0 0 B

0 0 0 0 0 0 0 0 B

Port 5^*8

Port 6

Port 7

Port 8

Port 9

Port A^*8

00001BH

—

Vacancy

*3

—

to 1FH

000020^HSMR0

000021H SCR0

Serial mode register 0

Serial control register 0

R/W!

0 0 0 0 0 0 0 0 B

0 0 0 0 0 1 0 0 B

UART0 (SCI)

SIDR0/

000022H

Input data register 0/

output data register 0

R/W

X X X X X X X X ^B

SODR0

000023H SSR0

000024H SMR1

000025H SCR1

Serial status register 0

Serial mode register 1

Serial control register 1

R/W!

0 0 0 0 1 – 0 0 B

0 0 0 0 0 0 0 0 B

0 0 0 0 0 1 0 0 B

UART1 (SCI)

SIDR1/

000026H

Input data register 1/

output data register 1

R/W

X X X X X X X X ^B

SODR1

000027H SSR1

Serial status register 1

R/W!

0 0 0 0 1 – 0 0 B

(Continued)

21

MB90640A Series

Read/

Address

Name

Register

Resource name

Initial value

write*^4,*⁵

000028^HENIR

000029H EIRR

Interrupt/DTP enable register

Interrupt/DTP request register

R/W

0 0 0 0 0 0 0 0 B

X X X X X X X X B

0 0 0 0 0 0 0 0 ^B

0 0 0 0 0 0 0 0 B

DTP/external

interrupt

00002AH

ELVR

Interrupt level setting register

Vacancy

R/W

00002BH

00002CH

—

*3

R/W

*3

—

8/16-bit PPG0

8/16-bit PPG1

—

to 2FH

PPG0 operation mode control

register

000030^HPPGC0

0 – 0 0 0 0 0 1 B

0 0 0 0 0 0 0 1 B

—

PPG1 operation mode control

register

000031H PPGC1

000032H,

—

Vacancy

33^H

000034^H

PRLL0/

X X X X X X X X ^B

X X X X X X X X B

X X X X X X X X ^B

X X X X X X X X B

0 0 0 0 0 0 0 0 ^B

– – – – 0 0 0 0 B

X X X X X X X X ^B

X X X X X X X X B

0 0 0 0 0 0 0 0 ^B

– – – – 0 0 0 0 B

X X X X X X X X ^B

X X X X X X X X B

PPG0 reload register

R/W

R/W!

R/W

R/W!

8/16-bit PPG0

8/16-bit PPG1

PRLH0

000035H

000036H

PRLL1/

PPG1 reload register

PRLH1

000037H

000038H

TMCSR0 Timer control status register

000039H

00003AH

00003BH

00003CH

00003DH

00003EH

00003FH

16-bit reload

timer 0

TMR0/

16-bit timer register/

TMRLR0 16-bit reload register

TMCSR1 Timer control status register

16-bit reload

timer 1

TMR1/

16-bit timer register/

R/W

*3

TMRLR1 16-bit reload register

000040H

to 47H

—

Vacancy

—

000048^HCSCR0

000049H CSCR1

00004AH CSCR2

00004BH CSCR3

00004CH CSCR4

00004DH CSCR5

00004EH CSCR6

00004FH CSCR7

Chip select control register 0

Chip select control register 1

Chip select control register 2

Chip select control register 3

Chip select control register 4

Chip select control register 5

Chip select control register 6

Chip select control register 7

Vacancy

R/W

*3

– – – – 0 0 0 0 B

—

Chip select

function

000050H

—

UART0 (SCI) machine clock division

control register

000051^HCDCR0

W

UART0 (SCI)

– – – – 1 1 1 1 B

(Continued)

22

MB90640A Series

Read/

Address

Name

Register

Resource name

—

Initial value

—

write*^4,*⁵

000052^H

—

Vacancy

*3

W

UART1 (SCI) machine clock division

control register

000053^HCDCR1

UART1 (SCI)

– – – – 1 1 1 1 B

000054H

—

Vacancy

*3

—

to 57H

000058^H

0 0 0 0 0 0 0 0 ^B

– – – – 0 0 0 0 B

X X X X X X X X ^B

X X X X X X X X B

0 0 0 0 0 0 0 0 ^B

– – – – 0 0 0 0 B

X X X X X X X X ^B

X X X X X X X X B

0 0 0 0 0 0 0 0 ^B

– – – – 0 0 0 0 B

X X X X X X X X ^B

X X X X X X X X B

0 0 0 1 0 0 0 0 ^B

0 0 1 1 0 0 1 0 B

– – – – 0 1 0 0 B

TMCSR2 Timer control status register

R/W!

000059H

00005AH

00005BH

00005CH

00005DH

00005EH

00005FH

000060H

000061H

000062H

000063H

000064H

16-bit reload

timer 2

TMR2/

16-bit timer register/

R/W

R/W!

R/W

R/W!

R/W

TMRLR2 16-bit reload register

TMCSR3 Timer control status register

16-bit reload

timer 3

TMR3/

16-bit timer register/

TMRLR3 16-bit reload register

TMCSR4 Timer control status register

16-bit reload

timer 4

TMR4/

16-bit timer register/

TMRLR4 16-bit reload register

16-bit reload

timer

000065H TPCR

000066H

Timer pin control register

Vacancy

R/W

000067H

—

*3

W

—

to 6EH

ROM

ROM mirror functional selection

module

00006F^HROMM

– – – – – – – * B

mirror function^*9

000070H

—

Vacancy

*3

—

to 8FH

000090^H

—

Reserved system area

*1

to 9EH

Delayed interrupt generation/

release register

Delayed interrupt

generation module

00009F^HDIRR

R/W

– – – – – – – 0 B

Low power consumption mode

control register

Low power

consumption

controller circuits

0000A0H LPMCR

0000A1H CKSCR

R/W!

*3

0 0 0 1 1 0 0 0 ^B

1 1 1 1 1 1 0 0 B

—

Clock selection register

Vacancy

0000A2H

—

to A4H

Auto-ready function selection

register

External bus pin

controller circuits

0000A5^HARSR

W

0 0 1 1 – – 0 0 B

(Continued)

23

MB90640A Series

(Continued)

Read/

Address

Name

Register

Resource name

Initial value

write*^4,*⁵

External address output control

register

0000A6^HHACR

W

0 0 0 0 0 0 0 0 B

External bus pin

controller circuits

0000A7H ECSR

0000A8H WDTC

0000A9H TBTC

Bus control signal selection register

Watchdog timer control register

Timebase timer control register

W

– 0 0 * 0 0 0 0 B

X X X X X 1 1 1 B

1 – – 0 0 1 0 0 B

R/W!

Watchdog timer

Timebase timer

0000AAH

—

Vacancy

*3

—

to AFH

0000B0^HICR00

0000B1H ICR01

0000B2H ICR02

0000B3H ICR03

0000B4H ICR04

0000B5H ICR05

0000B6H ICR06

0000B7H ICR07

0000B8H ICR08

0000B9H ICR09

Interrupt control register 00

Interrupt control register 01

Interrupt control register 02

Interrupt control register 03

Interrupt control register 04

Interrupt control register 05

Interrupt control register 06

Interrupt control register 07

Interrupt control register 08

Interrupt control register 09

Vacancy

R/W!

*3

0 0 0 0 0 1 1 1 B

—

Interrupt

controller

0000BAH

0000BB^HICR11

0000BCH

—

Interrupt control register 11

Vacancy

R/W!

*3

0 0 0 0 0 1 1 1 B

—

0000BD^HICR13

0000BEH ICR14

0000BFH ICR15

Interrupt control register 13

Interrupt control register 14

Interrupt control register 15

R/W!

0 0 0 0 0 1 1 1 B

0000C0H

to FFH

(External area)^*2

Initial values

0: The initial value for this bit is “0”.

1: The initial value for this bit is “1”.

*: The initial value for this bit is “1” or “0”. (Determined by the level of the MD0 to MD2 pins.)

X: The initial value for this bit is undefined.

–: This bit is not used. The initial value is undefined.

*1: Access prohibited.

*2: This is the only external access area in the area below address 0000FF^H. Access this address as an external

I/O area.

*3: Areas marked as “Vacancy” in the I/O map are reserved areas. These areas are accessed by internal access.

No access signals are output on the external bus.

*4: The R/W! symbol intheread/writecolumn indicatesthat somebitsareread-onlyorwrite-only. Seetheresource’s

register list for details.

(Continued)

24

MB90640A Series

(Continued)

*5: Using a read-modify-write instruction (such as the bit set instruction) to access one of the registers indicated

by R/W!, R/W*, or W in the read/write column sets the specified bit to the desired value. However, this can

cause misoperation if the other register bits include write-only bits. Therefore, do not use read-modify-write

instructions to access these registers.

*6: This register is only available when the address/data bus is in multiplex mode and in single-chip mode. Access

to the register is prohibited in non-multiplex mode.

*7: This register is only available when the external data bus is in 8-bit mode and in single-chip mode. Access to

the register is prohibited in 16-bit mode.

*8: All bits of DDR0/PDR0, 6-bit/7-bit of DDR5/PDR5 and 0-bit of DDRA/PDRA are available only in single-chip

mode.

*9: The initial value of this register in MB90V640A is “0” and that of in MB90P641A, MB90641A is “1”.

Note: The initial values listed for write-only bits are the initial values set by a reset. Take attention that they are not

the values returned by a read.

Also, LPMCR/CKSCR/WDTC are sometimes initialized and sometimes not initialized, depending on the reset

type. The listed initial values are for when these registers are initialized.

25

MB90640A Series

■ INTERRUPT VECTOR AND INTERRUPT CONTROL REGISTER

ASSIGNMENTS TO INTERRUPT SOURCES

Interrupt vector

Interrupt control register

I²OS

Interrupt source

support

Number

Address

FFFFDCH

FFFFD8H

FFFFD4H

FFFFD0H

ICR

—

Address

Reset

×

#08

08^H

09^H

0A^H

0B^H

—

INT 9 instruction

Exception

#09

#10

#11

—

DTP/external interrupt #0

ICR00

0000B0H

DTP/external interrupt #1

DTP/external interrupt #2

DTP/external interrupt #3

16-bit reload timer #2

#13

#15

#17

#18

#19

#20

#21

#22

#23

#24

#25

0DH

0FH

11H

12H

13H

14H

15H

16H

17H

18H

19H

FFFFC8H

FFFFC0H

FFFFB8H

FFFFB4H

FFFFB0H

FFFFACH

FFFFA8H

FFFFA4H

FFFFA0H

FFFF9CH

FFFF98H

ICR01

ICR02

0000B1H

0000B2H

ICR03

ICR04

ICR05

ICR06

0000B3H

0000B4H

0000B5H

0000B6H

DTP/external interrupt #4

16-bit reload timer #3

DTP/external interrupt #5

16-bit reload timer #4

DTP/external interrupt #6

UART0 • send complete

DTP/external interrupt #7

ICR07

ICR08

ICR09

0000B7H

0000B8H

0000B9H

UART1 • send complete

8/16-bit PPG #0

#26

#27

#28

#29

1AH

1BH

1CH

1DH

FFFF94H

FFFF90H

FFFF8CH

FFFF88H

×

8/16-bit PPG #1

16-bit reload timer #0

16-bit reload timer #1

#30

1EH

FFFF84H

Vacancy

#31

#34

#35

#37

1FH

22H

23H

25H

FFFF80H

FFFF74H

FFFF70H

FFFF68H

ICR10

ICR11

ICR12

ICR13

0000BAH

0000BBH

0000BCH

0000BDH

Timebase timer interval interrupt

Vacancy

×

—

UART1 • receive complete

UART0 • receive complete

#39

#42

27H

2AH

FFFF60H

FFFF54H

ICR14

ICR15

0000BEH

0000BFH

Delayed interrupt generation module

×

: indicates that the interrupt request flag is cleared by the I²OS interrupt clear signal (no stop request).

: indicates that the interrupt request flag is cleared by the I²OS interrupt clear signal (with stop request).

× : indicates that the interrupt request flag is not cleared by the I²OS interrupt clear signal.

Note: Do not specify I²OS activation in interrupt control registers that do not support I²OS.

26

MB90640A Series

■ PERIPHERAL RESOURCES

1. Parallel Port

The MB90640A series has 75 I/O pins, and 8 open-drain output pins.

Ports 0 to 5 and ports 7 to 9 and A are I/O ports. The ports are inputs when the corresponding direction register

bit is “0” and outputs when the corresponding bit is “1”.

Port 0 is only available in single-chip mode.

Port 1 is only available when in data bus 8-bit mode of non-multiplex mode or in single-chip mode.

Ports 2 and 3 are only available when the address/data bus is in multiplex mode and single-chip mode.

Port 6 is an open-drain port.

(1) Register Details

• Port data registers

• Port data register

Address : PDR1: 000001H

PDR3: 000003H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0

R/W R/W R/W R/W R/W R/W R/W R/W

bit 8

Initial value

PDR5: 000005H

XXXXXXXXB

PDR7: 000007H

PDR9: 000009H

Address : PDR0: 000000H

PDR2: 000002H

bit 7

PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0

R/W R/W R/W R/W R/W R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

PDR4: 000004H

XXXXXXXXB

PDR6: 000006H

PDR8: 000008H

PDRA: 00000AH

R/W : Readable and writable

X

: Indeterminate

Note: No register bit is provided for bits 0, 7 of port 7.

No register bit is provided for bit 7 of port 8.

No register bits are provided for bits 7, 6 of port 9.

Port 0 is only available in single-chip mode.

Bits 7, 6 of port 5 and bit 0 of port A are only available in single-chip mode.

Port 1 is only available when the external data bus is in 8-bit mode and single-chip mode.

Ports 2, 3 are only available in multiplex mode and single-chip mode.

Each port pin except port 6 can be specified as either an input or output by its corresponding direction register

when the pin is not set for use by a peripheral. When a port is set as an input, reading the data register always

reads the value corresponding to the pin level. When a port is set as an output, reading the data register reads the

data register latch value. The same applies when reading using a read-modify-write instruction.

When used as control outputs, reading the data register reads the control output value, irrespective of the direction

register value.

27

MB90640A Series

Notes: • If read-modify-write instructions (bit set instruction, etc.) are used to access this register, the bit that is the

focus of the instruction is set to the prescribed value, but the contents of the output register corresponding

to any other bits for which the input setting has been made are overwritten with the current input value of

the corresponding pin. Therefore, when switching a pin that was being used for input over to output, first

write the desired value to PDR, and then set the data DDR as output direction.

• Reading and writing an I/O port differs from reading and writing memory as follows:

Input mode

Reads: The read data is the level of the corresponding pin.

Writes: The write data is stored in the output latch. The data is not output to the pin.

Output mode

Reads: The read data is the value stored in the PDR.

Writes: The write data is both stored in the output latch and output to the pin.

• Take attention that the operation of R/W in port 6 is different from that of in other port.

Port 6 (P67 to P60) is an general-purpose I/O port with an open-drain output. When port 6 is used as a general-

purpose port, always be sure to set the corresponding bits in DDR6 to “0”.

When port 6 is used as an input port, it is necessary set the output port data register value to “1” in order to turn

off the open-drain output transistor; it is also necessary to connect a pull-up resistor to the external pins.

In addition, depending on the instruction used to read these bits, one of the following two different operations is

performed:

• When read by a read-modify-write instruction:

The contents of the output port data register are read. Even if pins are forcibly set to “0” externally, the contents

of the bits not specified by the instruction do not change.

• When read by any other instruction:

The pin level can be read.

When used as output ports, the pin values can be changed by writing the desired value to the corresponding

output port data register.

In addition, the pin which corresponds to the bit of which port 6 direction register is set to “1” can be read “0”.

• Port direction registers

• Port direction register

Address : DDR1 : 000011H

DDR3 : 000013H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0

R/W R/W R/W R/W R/W R/W R/W R/W

bit 8

Initial value

00000000B

DDR5 : 000015H

DDR7 : 000017H

DDR9 : 000019H

Address : DDR0: 000010H

bit 7

DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0

R/W R/W R/W R/W R/W R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00000000B

DDR2

DDR4

DDR8

DDRA

: 000012H

: 000014H

: 000018H

: 00001AH

R/W: Readable and writable

28

MB90640A Series

Note: No register bit is provided for bits 0, 7 of port 7.

No register bit is provided for bit 7 of port 8.

No register bits are provided for bits 6, 7 of port 9.

Port 1 is only available in single-chip mode.

Port 1 is only available when the external data bus is in 8-bit mode and single-chip mode.

Ports 2, 3 are only available in multiplex mode and single-chip mode.

When pins are used as ports, the register bits control the corresponding pins as follows.

0: Input mode

1: Output mode

Bits are set to “0” by a reset.

• Port 6 direction register

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

DD67 DD66 DD65 DD64 DD63 DD62 DD61 DD60

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value

11111111B

Address : DDR6: 000016H

R/W: Readable and writable

Controls each pin of port 6 as follows.

0: Port input mode

1: Analog input mode

Bits are set to “1” by a reset.

29

MB90640A Series

(2) Block Diagrams

• I/O port

Data register read

Data register

Data register write

Direction register

Direction register write

Direction register read

• Open-drain port

RMW

(Read-modify-write instruction)

Data register read

Data register

DDR6

Data register write

DDR6 register write

DDR6 register read

30

MB90640A Series

(3) Port Pin Allocation

Ports 1, 4, and 5 on the MB90640A series share pins with the external bus. The pin functions are determined

by the bus mode and register settings.

Function

Non-multiplex mode

Multiplex mode

External address control

Pin name

Enable (address)

External bus width

Disable (port)

Enable (address)

External bus width

Disable (port)

External bus width

8 bits

16 bits

8 bits

16 bits

8 bits

16 bits

8 bits

16 bits

D07 to D00/

AD07 to AD00

D07 to D00

AD07 to AD00

P17 to P10/

D15 to D08/

AD15 to AD08

D15 to D08

AD15 to AD08

Port

A15 to A08

P27 to P20/

A07 to A00

Port

P37 to P30/

A15 to A08

P47 to P40/

A23 to A16

Port

A23 to A16

Port

P57/ALE

RD

ALE

RD

ALE

RD

P55/WRL

P54/WRH

P53/HRQ

P52/HAK

P51/RDY

P50/CLK

WRL

Port

WRH

Port

WRH

Port

WRH

Port

WRH

HRQ

HAK

RDY

CLK

HRQ

HAK

RDY

CLK

Notes: • The upperaddress, WRL, WRH, HAK, HRQ, RDY, and CLKcan be setforuse as portsbyfunction selection.

• The pins mentioned above can be used as a port in single-chip mode.

31

MB90640A Series

2. UART0, 1 (SCI)

UART0, 1 are serial I/O ports that can be used for CLK asynchronous (start-stop synchronization) or CLK

synchronous (I/O expansion serial) data transfer. The ports have the following features.

• Full duplex, double buffered

• Supports CLK asynchronous (start-stop synchronization) and CLK synchronous (I/O expansion serial) data

transfer

• Multi-processor mode support

• Built-in dedicated baud rate generator

CLK asynchronous: 62500 bps/31250 bps/19230 bps/9615 bps/4808 bps/2404 bps/1202 bps

CLK synchronous: 2 Mbps/1 Mbps/500 kbps/250 kbps

• Supports flexible baud rate setting using an external clock

• Error detect function (parity, framing, and overrun)

• NRZ type transmission signal

• Intelligent I/O service support

(1) Register Configuration

• Serial mode register 0, 1

bit 7

bit 6

bit 5

CS2

W

bit 4

CS1

W

bit 3

CS0

W

bit 2

—

bit 1

SCKE SOE

R/W R/W

bit 0

Initial value

00000-00B

Address :

: 000020^H

SMR1: 000024H

SMR0

MD1 MD0

R/W R/W

—

• Serial control register 0, 1

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

00000100B

Address : SCR0: 000021H

SCR1: 000025H

PEN

P

SBL

R/W

CL

A/D

REC RXE

R/W R/W

TXE

R/W

R/W R/W

• Input data register 0, 1/output data register 0, 1

Address :

SIDR0 (read) /

SODR0 (write)

: 000022^H

bit 7

D7

bit 6

D6

bit 5

D5

bit 4

D4

bit 3

D3

bit 2

D2

bit 1

D1

bit 0

Initial value

D0

XXXXXXXXB

SIDR1 (read) /

SODR1 (write)

: 000026H

R/W R/W

R/W

R/W R/W

R/W

• Serial status register 0, 1

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

00001-00B

Address : SSR0: 000023H

SSR1: 000027H

PE

R

ORE FRE RDRF TDRE

—

RIE

TIE

R

R/W

• Machine clock division control register for UART0, 1 (SCI)

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

----1111B

Address :

: 000051H

: 000053H

CDCR0

CDCR1

—

DIV3 DIV2 DIV1 DIV0

W

R/W: Readable and writable

R : Read only

W : Write only

— : Unused

X : Indeterminate

32

MB90640A Series

(2) Block Diagram

Control signals

Receive interrupt

(to CPU)

Dedicated baud

rate generator

SCK

Transmit interrupt

(to CPU)

Transmit clock

16-bit timer 0

(Internal connection)

Clock select

circuit

Receive clock

External clock

Receive control circuit

Transmit control circuit

Start bit

detect circuit

SIN

Transmit start circuit

Transmit bit counter

Receive bit counter

Receive parity

counter

Transmit parity

counter

SOT

Receive status

evaluation circuit

Receive shifter

Transmit shifter

Receive

complete

Transmit

start

Receive error

indication signal

SODR

SIDR

for EI²OS (to CPU)

Internal data bus

MD1

MD0

CS2

CS1

CS0

PEN

P

PE

ORE

SMR

register

SCR

register

SBL

CL

SSR

register

FRE

RDRF

TDRE

A/D

REC

RXE

TXE

SCKE

SOE

RIE

TIE

Control signals

33

MB90640A Series

3. 8/16-bit PPG

8/16-bit PPG contains the 8-bit reload timer module. The block performs PPG output in which the pulse output

is controlled by the operation of the timer.

The hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two

external pulse output pins, and two interrupt outputs. The PPG has the following functions.

• 8-bit PPG output in 2-channel independent operation mode: Two independent PPG output channels are

available.

• 16-bit PPG output operation mode: One 16-bit PPG output channel is available.

• 8+8-bit PPG output operation mode: Variable-period 8-bit PPG output operation is available by using the

output of channel 0 as the clock input to channel 1.

• PPG output operation: Outputs pulse waveforms with variable period and duty ratio.

Can be used as a D/A converter in conjunction with an external circuit.

(1) Register Configuration

• PPG0 operation mode control register

bit 7

PEN0

R/W

bit 6

—

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

0-000001B

Address : PPGC0: 000030^H

POE0 PIE0 PUF0 PCM1 PCM0

Reserved

—

R/W

R/W R/W

—

• PPG1 operation mode control register

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

00000001B

Address :PPGC1

: 000031^H

PEN1 PCS1 POE1 PIE1 PUF1 MD1 MD0 Reserved

R/W R/W

R/W

R/W R/W

—

• PPG0, PPG1 reload register H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

R/W

Initial value

Address :PRLH0

PRLH1

: 000035H

: 000037H

XXXXXXXXB

R/W R/W

R/W

R/W R/W

• PPG0, PPG1 reload register L

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

Address :PRLL0

PRLL1

: 000034^H

: 000036H

XXXXXXXXB

R/W R/W

R/W

R/W R/W

R/W

R/W: Readable and writable

— : Unused

X

: Indeterminate

34

MB90640A Series

(2) Block Diagram

• 8/16-bit PPG (channel 0)

Output enable

PPG0

Peripheral clock divided by 16

Peripheral clock divided by 4

Peripheral clock

PPG0

output latch

Invert

Clear

PEN0

S

R

Count clock

selection

Q

PCNT (down-counter)

Reload

IRQ

Timebase counter output

Main clock divided by 512

ch.1 borrow

L/H selector

L/H select

PRLL0

PRLH0

PRLBH0

PIE 0

PUF0

L-side data bus

H-side data bus

PPGC0

(Operation mode control)

35

MB90640A Series

• 8/16-bit PPG (channel 1)

Output enable

PPG1

Peripheral clock

PPG1

output latch

Invert

Clear

Count clock

selection

PEN1

channel 0 borrow

S

R

Timebase counter output

Main clock divided by 512

Q

PCNT (down-counter)

Reload

IRQ

L/H selector

L/H select

PRLL1

PRLH1

PRLBH1

PIE1

PUF1

L-side data bus

H-side data bus

PPGC1

(Operation mode control)

36

MB90640A Series

4. 16-bit Reload Timer (with Event Count Function)

The 16-bit reload timers consists of a 16-bit down-counter, a 16-bit reload register, input pin (TIN), output pin

(TOT), and a control register. The input clock can be selected from one external clock and three types of internal

clock. The output (TOT) outputs a toggle waveform in reload mode and a rectangular waveform during counting

in one-shot mode. The input (TIN) functions as the event input in event count mode and as the trigger input or

gate input in internal clock mode.

Input and output of timer pin TIM0 to TIM4 are set by way of the timer pin control register.

This product has five internal 16-bit reload timer channels.

(1) Register Configuration

• Timer control status register upper

Address :

TMCSR0: 000039H

TMCSR1: 00003DH

TMCSR2: 000059H

TMCSR3: 00005DH

TMCSR4: 000061H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

CSL1 CSL0 MOD2 MOD1

R/W R/W R/W R/W

Initial value

----0000B

—

• Timer control status register lower

Address :

TMCSR0: 000038^H

TMCSR1: 00003CH

TMCSR2: 000058H

TMCSR3: 00005CH

TMCSR4: 000060H

bit 7

MOD0 OUTE OUTL RELD INTE

R/W R/W R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

UF

bit 1

bit 0

Initial value

00000000B

CNTE TRG

R/W R/W

R/W

• 16-bit timer register upper/16-bit reload register upper

Address :

TMR0/TMRLR0: 00003B^H

TMR1/TMRLR1: 00003FH

TMR2/TMRLR2: 00005BH

TMR3/TMRLR3: 00005FH

TMR4/TMRLR4: 000063H

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

XXXXXXXXB

R/W R/W

R/W

R/W R/W

R/W

• 16-bit timer register lower/16-bit reload register lower

Address :

TMR0/TMRLR0: 00003A^H

TMR1/TMRLR1: 00003EH

TMR2/TMRLR2: 00005AH

TMR3/TMRLR3: 00005EH

TMR4/TMRLR4: 000062H

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

XXXXXXXXB

R/W R/W

R/W

R/W R/W

R/W

R/W: Readable and writable

— : Unused

X

: Indeterminate

37

MB90640A Series

• Timer pin control register upper

bit 7

bit 6

—

bit 5

—

bit 4

—

bit 3

OTE4 CSC4 CSB4 CSA4

R/W R/W R/W R/W

bit 2

bit 1

bit 0

Initial value

----0100B

: 000066H

TPCR

Address :

—

• Timer pin control register middle

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

OTE3 CSC3 CSB3 CSA3 OTE2 CSC2 CSB2 CSA2

R/W R/W R/W R/W R/W R/W R/W R/W

bit 8

Initial value

00110010B

: 000065^H

TPCR

Address :

• Timer pin control register lower

bit 7

OTE1 CSC1 CSB1 CSA1 OTE0 CSC0 CSB0 CSA0

R/W R/W R/W R/W R/W R/W R/W R/W

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00010000B

: 000064^H

TPCR

Address :

R/W: Readable and writable

— : Unused

X

: Indeterminate

38

MB90640A Series

(2) Block Diagram

16

16-bit reload register

16-bit down-counter

8

Reload

RELD

OUTE

OUTL

INTE

16

UF

2

OUT

CTL

GATE

UF

IRQ

CSL1

Clock selector

CNTE

TRG

Clear

CSL0

I²OSCLR

2

Re-trigger

IN CTL

TIN0 to TIN4

EXCK

Output enable

3

TOT0 to TOT4

φ

Prescaler

Clear

—

2¹2³2⁵

MOD2

MOD1

MOD0

Serial baud rate

A/D converter

Peripheral clock

3

TIN0

TOT0

16-bit reload timer 0

16-bit reload timer 1

16-bit reload timer 2

16-bit reload timer 3

16-bit reload timer 4

TIM0

TIM1

TIM2

TIM3

TIM4

TIN1

TOT1

TIN2

TOT2

TIN3

TOT3

TIN4

TOT4

Note: Timer channel and direction (I/O) can be selected for each pin.

39

MB90640A Series

5. Chip Select Function

This module generates chip select signals to simplify connection of memory or I/O devices.

The module has 8 chip select output pins. The hardware outputs the chip select signals from the pins when it

detects access of an address in the areas specified in the pin registers.

(1) Register Configuration

• Chip select control register 1, 3, 5, 7

Address :

CSCR1: 000049H

CSCR3: 00004BH

CSCR5: 00004DH

CSCR7: 00004FH

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

ACTL OPEL CSA1 CSA0

R/W R/W R/W R/W R/W

Initial value

----0000B

—

R/W R/W

R/W

• Chip select control register 0, 2, 4, 6

Address :

CSCR0: 000048^H

CSCR2: 00004AH

CSCR4: 00004CH

CSCR6: 00004EH

bit 7

—

bit 6

—

bit 5

bit 4

—

bit 3

ACTL OPEL CSA1 CSA0

R/W R/W R/W

bit 2

bit 1

bit 0

Initial value

----0000B

—

R/W R/W

R/W

R/W R/W

R/W : Readable and writable

— : Unused

(2) Block Diagram

Address (from CPU)

A16 A15 A08 A07

A23

A00

Address decoder

Decode signal

Program area

Decode

CS0

(For the program ROM area)

Chip select control register 0

Chip select control register 1

Selection setting

Selector

CS1

Chip select control register 6

Chip select control register 7

Selector

Selection setting

CS6

CS7

40

MB90640A Series

6. DTP/External Interrupts

The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F²MC-16L

CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the

requests to the F²MC-16L CPU to activate the extended intelligent I/O service or interrupt processing. Two

request levels (“H” and “L”) are provided for extended intelligent I/O service. For external interrupt requests,

generation of interrupts on a rising or falling edge as well as on “H”, “L” levels can be selected, giving a total of

four types.

(1) Register Configuration

• Interrupt/DTP enable register

bit 7

EN7

bit 6

EN6

bit 5

EN5

R/W

bit 4

EN4

bit 3

EN3

bit 2

EN2

bit 1

EN1

bit 0

EN0

R/W

Initial value

00000000

Address :

ENIR: 000028

H

B

R/W R/W

• Interrupt/DTP source register

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

XXXXXXXX

Address :EIRR

: 000029

H

ER7

ER6

ER5

R/W

ER4

ER3

ER2

ER1

ER0

R/W

B

R/W R/W

• Request level setting register upper

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

LA4

R/W

Initial value

Address :

ELVR: 00002B

H

LB7

LA7

LB6

R/W

LA6

LB5

LA5

LB4

00000000

B

R/W R/W

• Request level setting register lower

bit 7

LB3

bit 6

LA3

bit 5

bit 4

LA2

bit 3

LB1

bit 2

LA1

bit 1

LB0

bit 0

Initial value

00000000

Address :

ELVR: 00002A

H

LB2

R/W

LA0

R/W

B

R/W R/W

R/W : Readable and writable

X : Indeterminate

(2) Block Diagram

8

Interrupt/DTP enable register

Request F/F

Interrupt input

8

Gate

Edge detect circuit

Request input

Interrupt/DTP register

Request level setting register

41

MB90640A Series

7. Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate the task switching interrupt. Interrupt requests to

the F²MC-16L CPU can be generated and cleared by software using this module.

(1) Register Configuration

• Delayed interrupt generation/release register

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

R0

Initial value

-------0B

Address : DIRR

: 00009FH

—

R/W

R/W: Readable and writable

— : Unused

(2) Block Diagram

Delayed interrupt generation/release

register

Interrupt latch

42

MB90640A Series

8. ROM Mirror Functional Selection Module

ROM mirror function selecting module can be refered to the upper 48 Kbytes of FF bank which is wired ROM

at 00 bank by selecting the resister setting.

(1) Register Configuration

• ROM mirror functional selection module

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

MI

Initial value

-------*B

Address : ROMM

—

: 00006FH

W

W : Write only

— : Unused

* : “1” or “0” (determined owing to the MD0 to MD2 pin level)

Notes: • The initial value of MB90V640A is “0” and that of MB90P641A, MB90641A is “1”.

• Not to access to this register while address 04000^Hto 00FFFFH are in operation.

(2) Block Diagram

ROM mirror functional selection module

Address area

Address

FF bank

00 bank

Data

ROM

43

MB90640A Series

9. Watchdog Timer and Timebase Timer

The watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller.

The watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source.

In addition to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. The timebase

timer uses the main clock, regardless of the value of the MCS bit in the CKSCR register.

(1) Register Configuration

• Watchdog timer control register

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

XXXXX111B

Address : WDTC: 0000A8H

PONR STBR WRST ERST SRST WTE WT1 WT0

R

W

• Timebase timer control register

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

1--00100B

Address : TBTC: 0000A9H Reserved

—

TBIE TBOF TBR TBC1 TBC0

R/W R/W

W

R/W

R/W: Readable and writable

R

: Read only

W : Write only

— : Unused

X

: Indeterminate

(2) Block Diagram

Main clock

(OSC oscillator)

TBTC

TBC1

TBC0

TBR

2¹²

Clock input

2¹⁴

Selector

2¹⁶

2¹⁹

TBTRES

Timebase timer

2¹²2¹⁴2¹⁶2¹⁹

S

R

TBIE

TBOF

AND

Q

Timebase

interrupt

WDTC

WT1

Watchdog reset

activation circuit

2-bit counter

OF

WDGRST

To internal reset

activation circuit

Selector

WT0

CLR

WTE

PONR

STBR

WRST

ERST

SRST

From power-on detection

From hardware standby

control circuit

RST pin

From the RST bit of the

STBYC register

44

MB90640A Series

10. Low-power Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization

Delay Time, and Clock Multiplier Function)

The following operation modes are available: PLL clock mode, PLL sleep mode, timer mode, main clock mode,

main sleep mode, stop mode, and hardware standby mode. Operation modes other than PLL clock mode are

classified as low-power consumption modes.

In main clock mode and main sleep mode, the device operates on the main clock only (OSC oscillator clock).

The PLL clock (VCO oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the

operating clock.

In PLL sleep mode and main sleep mode, the CPU’s operating clock only is stopped and other elements continue

to operate.

In timer mode, only the timebase timer operates.

Stop mode and hardware standby mode stop the oscillator. These modes maintain existing data with minimum

power consumption.

TheCPUintermittentoperationfunctionprovidesanintermittentclocktotheCPUwhenregister, internalmemory,

internal resource, or external bus access is performed. This function reduces power consumption by lowering

the CPU execution speed while still providing a high-speed clock to internal resources.

The PLL clock multiplier ratio can be set to 1, 2, 3, 4 by the CS1, CS0 bits.

The WS1, WS0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from

stop mode or hardware standby mode.

(1) Register Configuration

• Low-power consumption mode control register

bit 7

STP

W

bit 6

SLP

W

bit 5

SPL

R/W

bit 4

bit 3

bit 2

bit 1

bit 0

Initial value

00011000B

Address : LPMCR

: 0000A0H

RST Reserved CG1 CG0 Reserved

W

—

R/W R/W

—

• Clock select register

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

Reserved MCM WS1 WS0 Reserved MCS CS1

bit 8

CS0

R/W

Initial value

11111100B

Address : CKSCR

: 0000A1H

—

R

R/W

—

R/W R/W

R/W: Readable and writable

R : Read only

W : Write only

45

MB90640A Series

(2) Block Diagram

CKSCR

Main clock

PLL multiplier

circuit

(OSC oscillator)

MCM

MCS

CPU clock

1

2

3

4

1/2

CPU clock

generator

CKSCR

CS1

CPU

clock selector

0/9/17/33

Intermittent

cycle selection

CS0

LPMCR

CG1

Cycle selection circuit

for the CPU intermittent

operation function

CG0

Peripheral clock

HST pin

LPMCR

SLP

Peripheral

clock

generator

Standby control circuit

STP

RST Release HST activate

Interrupt request

or RST

CKSCR

WS1

2⁴

Clock input

Timebase timer

2¹²2¹⁴2¹⁶2¹⁹

Oscillation

stabilization

delay time

selector

2¹³

2¹⁵

2¹⁸

Timebase clock

Pin Hi-Z

WS0

LPMCR

SPL

Pin high impedance control circuit

RST pin

LPMCR

RST

Internal reset

generation circuit

Internal RST

To watchdog timer

WDGRST

46

MB90640A Series

• State transition diagram for clock selection

Power-on

Main

Main → PLLX

MCS = 0

MCM = 1

(1)

(2)

(3)

MCS = 1

MCM = 1

CS1/0 = XX

(6)

(7)

CS1/0 = XX

PLL1 → Main

MCS = 1

PLL multiplier = 1

MCS = 0

MCM = 0

CS1/0 = 00

MCM = 0

CS1/0 = 00

(6)

(7)

PLL2 → Main

MCS = 1

MCM = 0

PLL multiplier = 2

MCS = 0

MCM = 0

(6)

CS1/0 = 01

(4)

PLL3 → Main

MCS = 1

MCM = 0

PLL multiplier = 3

MCS = 0

MCM = 0

(5)

(7)

(6)

CS1/0 = 10

PLL4 → Main

MCS = 1

PLL multiplier = 4

MCS = 0

MCM = 0

CS1/0 = 11

MCM = 0

CS1/0 = 11

(6)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

MCS bit cleared

PLL clock oscillation stabilization delay complete and CS1/0 = 00

PLL clock oscillation stabilization delay complete and CS1/0 = 01

PLL clock oscillation stabilization delay complete and CS1/0 = 10

PLL clock oscillation stabilization delay complete and CS1/0 = 11

MCS bit set (including a hardware standby or watchdog reset)

PLL clock and main clock synchronized timing

47

MB90640A Series

11. Interrupt Controller

The interrupt control registers are located in the interrupt controller. An interrupt control register is provided for

each I/O with an interrupt function. The registers have the following three functions.

• Set the interrupt level of the corresponding peripheral.

• Select whether to treat interrupts from the corresponding peripheral as standard interrupts or activate the

extended intelligent I/O service.

• Select the extended intelligent I/O service channel.

(1) Register Configuration

• Interrupt control register 01, 03, 05, 07, 09, 11, 13, 15

: 0000B1^H

: 0000B3H

: 0000B5H

: 0000B7H

: 0000B9H

: 0000BBH

: 0000BDH

: 0000BFH

Address : ICR01

ICR03

ICR05

ICR07

ICR09

ICR11

ICR13

ICR15

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

ICS1 ICS0

bit 8

IL0

Initial value

00000111B

or

ICS3 ICS2

ISE

IL2

IL1

S1

S0

W

R/W

R/W R/W

R/W

• Interrupt control register 00, 02, 04, 06, 08, 10, 12, 14

: 0000B0^H

: 0000B2H

: 0000B4H

: 0000B6H

: 0000B8H

: 0000BEH

Address : ICR00

ICR02

ICR04

ICR06

ICR08

ICR14

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

ICS1 ICS0

bit 8

IL0

Initial value

00000111B

or

ICS3 ICS2

ISE

IL2

IL1

S1

S0

W

R/W

R/W R/W

R/W

R/W: Readable and writable

W : Write only

Note: Do not access these registers using read-modify-write instructions as this can cause misoperation.

48

MB90640A Series

(2) Block Diagram

32

4

Determine priority

of interrupt or I²OS

ISE

IL2

IL1

IL0

Interrupt

/I²OS request

4

(peripheral resource)

3

(CPU)

Interrupt level

I²OS selection

4

I²OS vector selection

I²OS vector

(CPU)

4

ICS3 ICS2 ICS1 ICS0

4

Detect I²OS

completion condition

2

S1

S0

I²OS completion condition

2

49

MB90640A Series

12. External Bus Terminal Control Circuit

This circuit controls the external bus terminals intended to extend outwardly the CPU’s address/data bus.

(1) Register Configuration

• Register for selection of AUTO ready function

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

0011--00

Address : ARSR

: 0000A5

IOR1 IOR0 HMR1 HMR0

—

LMR1 LMR0

B

H

W

• Register for control of external address output

bit 7

E23

W

bit 6

E22

W

bit 5

E21

W

bit 4

E20

W

bit 3

E19

W

bit 2

E18

W

bit 1

E17

W

bit 0

E16

W

Initial value

00000000

Address : HACR: 0000A6

H

B

• Register for selection of bus control signal

bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9

bit 8

Initial value

-00*0000

: 0000A7

H

Address : ECSR

—

LMBS WRE HMBS IOBS HDE RYE CKE

B

W

W: Write only

—: Unused

X : Indeterminate

* : “1” or “0” (determined owing to the MD0 to MD2 pin level)

(2) Block Diagram

Port 5

Port 4

Port 3

Port 2

Port 1

Port 0

Port 5 pin

Port 4 pin

Port 3 pin

Port 2 pin

Port 1 pin

Port 0 pin

Port 0 data register

Port 0 direction register

RB

Data control

Access control

50

MB90640A Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Rating

(VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

Unit

Remarks

Min.

Max.

VSS + 6.0

VCC + 0.3

15

Power supply voltage

V^CC

VI

VSS – 0.3

V

Input voltage*¹

VSS – 0.3

V

Output voltage*¹

VO

VSS – 0.3

—

V

“L” level maximum output current*²

“L” level average output current*³

“L” level total maximum output current

“L” level total average output current*⁴

“H” level maximum output current*²

“H” level average output current*³

“H” level total maximum output current

“H” level total average output current*⁴

IOL

mA

mW

°C

IOLAV

ΣI^OL

ΣIOLAV

IOH

—

4

—

100

—

50

—

–15

IOHAV

ΣI^OH

ΣIOHAV

—

–4

—

–100

–50

—

+150

+400

+85

MB90641A

MB90P641A

Power consumption

P^D

—

Operating temperature

Storage temperature

T^A

–40

–55

Tstg

+150

°C

*1: VI and VO must not exceed VCC + 0.3 V.

*2: The maximum output current must not be exceeded at any individual pin.

*3: The average output current is the operating current running through an appropriate pin × the operating rate.

*4: The average total output current is the operating current running through all the appropriate pins × the operating

rate.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

51

MB90640A Series

2. Recommended Operating Conditions

(VSS = AVSS = 0.0 V)

Value

Parameter

Symbol

V^CC

Unit

Remarks

For normal operation

Min.

4.5

Max.

5.5

V

Power supply voltage

V^CC

V^IH

3.5

5.5

To maintain statuses in stop mode

TTL level input pins

CMOS level input pins

Hysteresis input pins*

MD input pin

2.2

VCC + 0.3

0.8

V^IHC

V^IHS

V^IHM

V^IL

0.7 VCC

0.8 VCC

VCC – 0.3

VSS – 0.3

“H” level input voltage

“L” level input voltage

TTL level input pins

CMOS level input pins

Hysteresis input pins*

MD input pin

V^ILC

V^ILS

V^ILM

0.3 VCC

0.2 VCC

VSS + 0.3

Use the ceramic capacitor or the

capacitor which has the similar

frequency characteristic as ceramic

capacitor.

Smoothing capacitor

C^S

0.1

1.0

µF

When attach the smoothing capacitor

to V^CC, use the capacitor whose

capacitance is larger than C^S.

Operating temperature T^A

–40

+85

°C

* : Target pins are P60 to P67, P71 to P76, P80 to P86, P90 to P95, HST, and RST. (When used as general purpose

pins)

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

52

MB90640A Series

3. DC Characteristics

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

“H” level output

voltage

Other than VCC = 4.5 V,

P60 to P67 I^OH= –4.0 mA

VCC – 0.5

V^OH

V^OL

I^IL

—

V

“L” level output

voltage

All output

pins

VCC = 4.5 V,

I^OL= 4.0 mA

—

0.4

5

Input leakage

current

Other than VCC = 5.5 V,

P60 to P67 V^SS< VI < VCC

–5

µA

Open-drain

output leakage I^leak

current

P60 to P67

—

0.1

5

µA

Pull-up

R^UP

—

15

50

100

200

kΩ

resistance

Pull-down

R^DOWN

resistance

MB90V640A/

P641A

—

50

15

25

5

70

20

30

10

20

mA

µA

Internal 16 MHz operation

Normal operation

I^CC

MB90641A

MB90V640A/

P641A

Power supply

current*

Internal 16 MHz operation

Sleep mode

ICCS

VCC = 5.0 V

MB90641A

MB90V640A/

P641A

0.1

5

TA = +25°C

Stop mode

ICCH

MB90641A

µA

Input

capacitance

Other than

V^CC, VSS, C

C^IN

—

10

—

pF

* : Because the current values are tentative values, they are subject to change without notice due to our efforts to

improve the characteristics of these devices.

53

MB90640A Series

4. AC Characteristics

(1) Clock Timing

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min.

3

Max.

17

Source oscillation frequency F^C

Source oscillation cycle time t^C

X0, X1

—

MHz

ns

58.8

333

Frequency variation ratio*

(when locked)

∆f

—

5

%

The duty ratio

P^WH

PWL

Input clock pulse width

X0

10

—

ns should be in the

range 30 to 70%

Input clock rise time and fall

time

t^cr

tcf

X0

—

5

ns

MHz

ns

Internal operating clock

frequency

f^CP

t^CP

1.5

17

Internal operating clock cycle

time

—

58.8

666

* : The frequency variation ratio is the maximum variation from the specified central frequency when the multiplier

PLL is locked. The value is expressed as a proportion.

+α

ı α ı

Central frequency f0

∆f =

× 100 (%)

f⁰

–α

• Clock timing

tC

0.8 VCC

0.2 VCC

PWH

PWL

tcf

tcr

54

MB90640A Series

• PLL operation assurance range

Relationship between the internal operating clock frequency and supply voltage

5.5

4.5

1.5

4

8

17

Internal clock f^CP(MHz)

: Normal operation assurance range : PLL operation assurance range

Relationship between the oscillation frequency and internal operating clock frequency

Multiply Multiply

by 4

by 3

17

16

Multiply by 1

Multiply by 2

12

9

8

No multiplier

4

3 4

8

Oscillation clock F^C(MHz)

16 17

55

MB90640A Series

The AC characteristics are for the following measurement reference voltages.

• Input signal waveform

• Output signal waveform

Hysteresis input pins

0.8 V^CC

Output pins

2.4 V

0.2 VCC

0.8 V

Other than hysteresis/MD input pins

0.7 V^CC

0.3 VCC

(2) Clock Output Timing

(V^CC= 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name

Conditions

Unit Remarks

Min.

t^CP

Max.

—

Cycle time

CLK ↑ → CLK ↓

t^CYC

ns

CLK

—

t^CHCL

tCP/2 – 20

tCP/2 + 20

t^CP: See “ (1) Clock Timing.”

tCYC

tCHCL

2.4 V

CLK

0.8 V

56

MB90640A Series

(3) Recommended Resonator Manufacturers

• Sample application of piezoelectric resonator (FAR family)

X 0

X 1

R

FAR^*1

*2

C 1

*2

*1: Fujitsu Acoustic Resonator

C 2

Temperature

characteristics of

FAR frequency

Initial deviation of

FAR frequency

(T^A= +25°C)

FAR part number

(built-in capacitor type)

Frequency Dumping

Loading

capacitors*²

(MHz)

resistor

(T^A= –20°C to +60°C)

FAR-C4CC-02000-L20

FAR-C4CA-04000-M01

FAR-C4CB-08000-M02

FAR-C4CB-10000-M02

FAR-C4CB-16000-M02

2.00

4.00

1 kΩ

—

±0.5%

8.00

—

Built-in

10.00

16.00

—

Inquiry: FUJITSU LIMITED

57

MB90640A Series

• Sample application of ceramic resonator

X 0

X 1

R

*

C 1

C 2

Resonator

manufacturer*

Frequency

(MHz)

Resonator

C¹(pF)

C²(pF)

R

KBR-2.0MS

PBRC2.00A

KBR-4.0MSA

KBR-4.0MKS

PBRC4.00A

PBRC4.00B

KBR-6.0MSA

KBR-6.0MKS

PBRC6.00A

PBRC6.00B

KBR-8.0M

150

Not required

680 Ω

2.00

33

Built-in

33

Built-in

33

680 Ω

4.00

680 Ω

Built-in

33

Built-in

33

680 Ω

Not required

560 Ω

Built-in

33

Built-in

33

6.00

8.00

Kyocera

Corporation

Built-in

33

Built-in

33

PBRC8.00A

PBRC8.00B

KBR-10.0M

PBRC10.00B

KBR-12.0M

PBRC12.00B

33

Not required

330 Ω

Built-in

33

Built-in

33

10.00

12.00

Built-in

33

Built-in

33

680 Ω

330 Ω

Built-in

680 Ω

(Continued)

58

MB90640A Series

(Continued)

Resonator

Frequency

(MHz)

Resonator

CSA2.00MG040

C¹(pF)

C2 (pF)

R

manufacturer

100

Built-in

100

Built-in

100

Not required

2.00

4.00

CST2.00MG040

CSA4.00MG040

CST4.00MGW040

CSA6.00MG

Built-in

30

Built-in

30

6.00

CST6.00MGW

Built-in

30

Built-in

30

CSA8.00MTZ

8.00

CST8.00MTW

Built-in

30

Built-in

30

Murata Mfg. Co.,

Ltd.

CSA10.00MTZ

CST10.00MTW

CSA12.00MTZ

CST12.00MTW

CSA16.00MXZ040

CST16.00MXW0C3

CSA20.00MXZ040

CSA24.00MXZ040

CSA32.00MXZ040

10.00

12.00

16.00

Built-in

30

Built-in

30

Built-in

15

Built-in

15

Built-in

10

Built-in

10

20.00

24.00

32.00

5

Inquiry: Kyocera Corporation

• AVX Corporation

North American Sales Headquarters: TEL 1-803-448-9411

• AVX Limited

European Sales Headquarters: TEL 44-1252-770000

• AVX/Kyocera H.K. Ltd.

Asian Sales Headquarters: TEL 852-363-3303

Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc.: TEL 1-404-436-1300

• Murata Europe Management GmbH: TEL 49-911-66870

• Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233

59

MB90640A Series

(4) Reset and Hardware Standby Inputs

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Reset input time

Symbol Pin name Conditions

Unit Remarks

Min.

16 tCP

Max.

—

t^RSTL

t^HSTL

RST

HST

—

ns

Hardware standby input time

tCP: See “ (1) Clock Timing.”

—

t

RSTL, tHSTL

RST

HST

0.2 VCC

0.2 V^CC

• Conditions for measurement of AC reference

CL: Load capacity during testing

For CLK and ALE, C^L= 30 pF

For address and data buses (AD15 to AD00), RD and WR, CL = 80 pF

CL

60

MB90640A Series

(5) Power on Supply Specifications (Power-on Reset)

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min.

Max.

Power supply rise time

t^R

VCC

—

0.05

30

ms

For repetition of

the operation

Power supply cut-off time

t^OFF

50

—

* : VCC should be lower than 0.2 V before power supply rise.

Notes: • The above values are the values required for a power-on reset.

• When HST = “L”, this standard must be followed to turn on power supply for power-on reset whether or

not necessary.

• The device has built-in registers which are initialized only by power-on reset. For possible initialization of

these registers, turn on power supply according to this standard.

t^R

tOFF

2.7 V

VCC

0.2 V

Abrupt changes in the power supply voltage may cause a power-on reset.

When changing the power supply voltage during operation, the change should be

as smooth as possible, as shown in the following figure.

5.0 V

VCC

The gradient should be no

more than 50 mV/ms.

3.5 V

V^SS

Holding RAM data

61

MB90640A Series

(6) Bus Timing (Read)

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

ALE pulse width

Symbol Pin name Conditions

Unit Remarks

Min.

Max.

—

t^LHLL

ALE

—

tCP/2 – 20

tCP/2 – 15

tCP – 15

ns

Valid address → ALE ↓ time t^AVLL

ALE ↓ → address valid time t^LLAX

Address

—

Valid address → RD ↓ time

tAVRL

—

Valid address → valid data

input

Address/

data

t^AVDV

—

5 t^CP/2 – 60

ns

RD pulse width

tRLRH

tRLDV

tRHDX

tRHLH

RD

—

3 tCP/2 – 20

—

ns

RD ↓ → valid data input

RD ↑ → data hold time

RD ↑ → ALE ↑ time

Data

—

0

3 tCP/2 – 60

Data

—

RD, ALE

tCP/2 – 15

Address,

RD

RD ↑ → address valid time

tRHAX

—

tCP/2 – 10

t^CP/2 – 20

—

ns

Address,

CLK

Valid address → CLK ↑ time t^AVCH

RD ↓ → CLK ↑ time

ALE ↓ → RD ↓ time

tRLCH

tLLRL

RD, CLK

ALE, RD

—

tCP/2 – 20

tCP/2 – 15

—

ns

tCP: See “ (1) Clock Timing.”

62

MB90640A Series

tAVCH

tRLCH

2.4 V

CLK

ALE

tLLAX

tAVLL

tRHLH

2.4 V

t^LHLL

2.4 V

0.8 V

2.4 V

tAVRL

tRLRH

2.4 V

RD

0.8 V

Multiplex mode

tRHAX

tLLRL

2.4 V

0.8 V

2.4 V

0.8 V

A23 to

A16

tRLDV

tAVDV

tRHDX

2.2 V

0.8 V

2.4 V

0.8 V

2.2 V

2.4 V

0.8 V

Address

Read data

0.8 V

Non-multiplex mode

t^RHAX

2.4 V

0.8 V

2.4 V

0.8 V

A23 to

A00

tRLDV

tAVDV

tRHDX

2.2 V

0.8 V

2.2 V

0.8 V

D15 to

D00

Read data

63

MB90640A Series

(7) Bus Timing (Write)

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min.

Max.

—

Valid address → WR ↓ time tAVWL

Address

—

tCP – 15

ns

WR pulse width

tWLWH

WRL, WRH

3 tCP/2 – 20

—

Valid data output → WR ↑

time

t^DVWH

Data

—

3 tCP/2 – 20

20

—

ns

Multiplex

mode

WR ↑ → data hold time

tWHDX

Data

—

Non-multiplex

mode

30

—

ns

WR ↑ → address valid time tWHAX

Address

tCP/2 – 10

t^CP/2 – 15

WRL,WRH,

ALE

WR ↑ → ALE ↑ time

tWHLH

tWLCH

—

WRL,WRH,

CLK

WR ↓ → CLK ↑ time

t^CP/2 – 20

—

ns

tCP: See “ (1) Clock Timing.”

t

WLCH

2.4 V

CLK

ALE

t

WHLH

2.4 V

t

WLWH

t

AVWL

2.4 V

WR

(WRL, WRH)

0.8 V

t

WHAX

Multiplex mode

2.4 V

0.8 V

A23 to

A16

0.8 V

t

DVWH

t

WHDX

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

AD15 to

AD00

Address

Write data

t

WHAX

Non-multiplex mode

2.4 V

0.8 V

2.4 V

0.8 V

A23 to

A00

t

t^WW^HH^DD^XX

t

DVWH

2.4 V

0.8 V

2.4 V

0.8 V

D15 to

D00

Write data

64

MB90640A Series

(8) Ready Input Timing

Parameter

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Pin name

Conditions

Unit Remarks

Min.

45

Max.

—

RDY setup time

RDY hold time

t^RYHS

RDY

t^RYHH

V^CC= 5.0 V ±10%

—

ns

0

—

Note: Use the auto-ready function if the setup time at fall of the RDY is too short.

CLK

ALE

2.4 V

RD/WR

tRYHS

RDY

(Wait cycle)

0.2 VCC

tRYHS

RDY

(No wait cycle)

0.8 VCC

tRYHH

65

MB90640A Series

(9) Hold Timing

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name Conditions

Unit

Remarks

Min.

30

Max.

tCP

Pin floating → HAK ↓ time

HAK ↑ → pin valid time

tXHAL

tHAHV

HAK

—

ns

tCP

2 tCP

tCP: See “ (1) Clock Timing.”

Note: After reading HRQ, more than one cycle is required before changing HAK.

2.4 V

HAK

0.8 V

tXHAL

tHAHV

High impedance

66

MB90640A Series

(10) I/O Extended Serial Timing

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol

t^SCYC

t^SLOV

Pin name

Conditions

Unit Remarks

Min.

Max.

Serial clock cycle time

SCK0, SCK1

8 t^CP

—

ns

SCK0, SCK1

SOT0, SOT1

SCK ↓ → SOT delay time

–80

100

60

80

—

C^L= 80 pF + 1 TTL

for the internal shift

clock mode output

pin.

SCK0, SCK1

SIN0, SIN1

Valid SIN → SCK ↑

t^IVSH

ns

SCK0, SCK1

SIN0, SIN1

SCK ↑ → valid SIN hold time t^SHIX

Serial clock “H” pulse width

Serial clock “L” pulse width

t^SHSL

t^SLSH

SCK0, SCK1

4 t^CP

—

ns

4 tCP

SCK0, SCK1 C^L= 80 pF + 1 TTL

SOT0, SOT1 for the external shift

SCK ↓ → SOT delay time

Valid SIN → SCK ↑

t^SLOV

t^IVSH

—

60

150

—

ns

clock mode output

SCK0, SCK1

pin.

SIN0, SIN1

SCK0, SCK1

SIN0, SIN1

SCK ↑ → valid SIN hold time t^SHIX

—

Notes: • These are the AC characteristics for CLK synchronous mode.

• C^Lis the load capacitance connected to the pin at testing.

• t^CPis the machine cycle period (unit: ns).

• The values in the upper table are targets.

67

MB90640A Series

• Internal shift clock mode

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

0.8 V

SOT

tIVSH

tSHIX

0.8 V^CC

0.2 V^CC

0.8 VCC

0.2 VCC

SIN

• External shift clock mode

tSLSH

tSHSL

0.8 V^CC

0.8 VCC

SCK

0.2 VCC

tSLOV

2.4 V

0.8 V

SOT

tIVSH

tSHIX

0.8 VCC

0.2 V^CC

0.8 VCC

0.2 VCC

SIN

68

MB90640A Series

(11) Timer Input Timing

Parameter

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Pin name

Conditions

Unit Remarks

Min.

Max.

t^TIWH

Input pulse width

TIM0 to TIM4

tTIWL

—

4 tCP

—

ns

tCP: See “ (1) Clock Timing.”

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

tTIWH

tTIWL

(12) Timer Output Timing

Parameter

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Symbol Pin name

Conditions

Unit Remarks

Min.

Max.

CLK ↑ → T^OUTchange timing tTO

TIM0 to TIM4

—

30

—

ns

2.4 V

CLK

T^OUT

2.4 V

0.8 V

tTO

69

MB90640A Series

(13) Trigger Input Timing

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name

t^TRGLINT0 to INT7

Conditions

Unit Remarks

Min.

Max.

Input pulse width

tCP: See “ (1) Clock Timing.”

—

5 tCP

—

ns

0.8 VCC

0.2 VCC

tTRGH

tTRGL

(14) Chip Select Output Timing

(VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)

Value

Parameter

Symbol Pin name

Conditions

Unit Remarks

Min.

Max.

Chip select enabled →

Valid data input time

CS0 to CS7

t^SVDV

—

5 t^CP/2 – 60 ns

D15 to D00

RD ↑ →

Chip select enabled time

CS0 to CS7

t^RHSV

RD

tCP/2 – 10

t^CP/2 – 20

—

ns

WR ↑ →

Chip select enabled time

CS0 to CS7

t^WHSV

WR

Enabled chip select →

CLK ↑ time

CS0 to CS7

t^SVCH

CLK

tCP: See “ (1) Clock Timing.”

70

MB90640A Series

t^SVCH

2.4 V

CLK

RD

2.4 V

tRHSV

2.4 V

A23 to A00

CS0 to CS7

0.8 V

tSVDV

2.4 V

Read data

D15 to D00

0.8 V

tWHSV

2.4 V

WR

(WRL, WRH)

Write data

D15 to D00

71

MB90640A Series

■ EXAMPLES CHARACTERISTICS

1. MB90641A

(1) “H” Level Output Voltage

(2) “L” Level Output Voltage

V

CC

-

V

OH vs.

I

OH

V

OL vs.

I

OL

V

OL (V)

V

CC

- VOH (V)

0.45

V

CC = 3.0 V

0.4

V

CC = 3.0 V

T

A

= +25°C

0.4

T

A

= +25°C

0.35

0.3

V

CC = 3.5 V

= 4.0 V

V

CC = 3.5 V

0.35

0.3

V^CC= 4.5 V

V

= 4.0 V

^CC= 5.0 V

V

^CC= 4.5 V

V^CC= 5.0 V

V^CC= 5.5 V

V

0.25

0.2

V^CC= 5.5 V

0.25

0.2

0.15

0.1

0.15

0.1

0.05

0.0

0.05

0.0

2

3

4

5

6

–2

–3

–4

–5

–6

OH (mA)

I

OL (mA)

I

(3) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(4) “H” Level Input Voltage/“L” Level Input

Voltage (Hysteresis Input)

V^INvs. VCC

V^IN(V)

5.0

4.5

4.0

VIN vs. VCC

V^IN(V)

5.0

TA = +25°C

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

TA = +25°C

VIHS

VILS

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

3

3.5

4

4.5

5

5.5

V^CC(V)

VIHS : Thershold when input voltage in hysteresis

characteristics is set to “H” level

3

3.5

4

4.5

5

5.5

V^CC(V)

V^ILS: Thershold when input voltage in hysteresis

characteristics is set to “L” level

(5) Power Supply Current (f^CP= Internal Frequency)

ICC vs. VCC

I^CCSvs. VCC

TA = +25°C

f^CP= 16 MHz

ICC (mA)

24

22

ICCS (mA)

TA = +25°C

6

5

4

3

2

1

0

20

18

16

14

12

10

8

6

4

2

0

f^CP= 16 MHz

f^CP= 8 MHz

fCP = 4 MHz

f^CP= 2 MHz

f^CP= 4 MHz

f^CP= 2 MHz

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

72

MB90640A Series

2. MB90P641A

(1) “H” Level Output Voltage

(2) “L” Level Output Voltage

V^OHvs. IOH

VOH (V)

V^OLvs. IOL

VOL (V)

1.0

V^CC= 2.7 V

V^CC= 3.0 V

0.9

TA = +25°C

V^CC= 2.7 V

V^CC= 3.0 V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V^CC= 3.5 V

V^CC= 4.0 V

V^CC= 4.5 V

V^CC= 5.0 V

V^CC= 3.5 V

V^CC= 4.0 V

V^CC= 4.5 V

V^CC= 5.0 V

–2

–4

–6

–8

I^OH(mA)

2

4

6

8

I^OL(mA)

(3) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(4) “H” Level Input Voltage/“L” Level Input

Voltage (Hysteresis Input)

VIN vs. VCC

V^IN(V)

5.0

V^INvs. VCC

V^IN(V)

5.0

T

A = +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

TA = +25°C

4.5

VIHS

VILS

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2

3

4

5

6

VCC (V)

2

3

4

5

6

VIHS : Thershold when input voltage in hysteresis

characteristics is set to “H” level

V^CC(V)

V^ILS: Thershold when input voltage in hysteresis

characteristics is set to “L” level

73

MB90640A Series

(5) Power Supply Current (f^CP= internal frequency)

ICC (mA)

70

65

60

55

50

45

40

35

30

25

20

15

10

5

ICC vs. VCC

TA = +25°C

ICCS (mA)

ICCS vs. VCC

15

14

13

12

11

10

9

8

7

6

5

TA = +25°C

f^CP= 16 MHz

f^CP= 12.5 MHz

f^CP= 8 MHz

f^CP= 4 MHz

f^CP= 8 MHz

f^CP= 4 MHz

4

3

2

1

0

3.0

4.0

5.0

6.0

V^CC(V)

3.0

4.0

5.0

6.0

V^CC(V)

(6) Pull-up Resistance

R vs. V^CC

R (kΩ)

1000

TA = +25°C

100

10

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V^CC(V)

74

MB90640A Series

■ INSTRUCTIONS (340 INSTRUCTIONS)

Table 1 Explanation of Items in Tables of Instructions

Meaning

Upper-case letters and symbols: Represented as they appear in assembler.

Item

Mnemonic

Lower-case letters: Replaced when described in assembler.

Numbers after lower-case letters:Indicate the bit width within the instruction.

#

~

Indicates the number of bytes.

Indicates the number of cycles.

m: When branching

n : When not branching

See Table 4 for details about meanings of other letters in items.

RG

B

Indicates the number of accesses to the register during execution of the instruction.

It is used calculate a correction value for intermittent operation of CPU.

Indicates the correction value for calculating the number of actual cycles during execution of the

instruction. (Table 5)

The number of actual cycles during execution of the instruction is the correction value summed

with the value in the “~” column.

Operation

LH

Indicates the operation of instruction.

Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator.

Z : Transfers “0”.

X : Extends with a sign before transferring.

– : Transfers nothing.

AH

Indicates special operations involving the upper 16 bits in the accumulator.

* : Transfers from AL to AH.

– : No transfer.

Z : Transfers 00^Hto AH.

X : Transfers 00^Hor FFH to AH by signing and extending AL.

I

S

Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit),

N (negative), Z (zero), V (overflow), and C (carry).

* : Changes due to execution of instruction.

– : No change.

S : Set by execution of instruction.

R : Reset by execution of instruction.

T

N

Z

V

C

RMW

Indicates whether the instruction is a read-modify-write instruction. (a single instruction that

reads data from memory, etc., processes the data, and then writes the result to memory.)

* : Instruction is a read-modify-write instruction.

– : Instruction is not a read-modify-write instruction.

Note: A read-modify-write instruction cannot be used on addresses that have different

meanings depending on whether they are read or written.

75

MB90640A Series

Table 2 Explanation of Symbols in Tables of Instructions

Meaning

Symbol

A

32-bit accumulator

The bit length varies according to the instruction.

Byte : Lower 8 bits of AL

Word : 16 bits of AL

Long : 32 bits of AL:AH

AH

AL

Upper 16 bits of A

Lower 16 bits of A

SP

PC

Stack pointer (USP or SSP)

Program counter

PCB

DTB

ADB

SSB

USB

SPB

DPR

brg1

brg2

Ri

Program bank register

Data bank register

Additional data bank register

System stack bank register

User stack bank register

Current stack bank register (SSB or USB)

Direct page register

DTB, ADB, SSB, USB, DPR, PCB, SPB

DTB, ADB, SSB, USB, DPR, SPB

R0, R1, R2, R3, R4, R5, R6, R7

RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7

RW0, RW1, RW2, RW3

RWi

RWj

RLi

RL0, RL1, RL2, RL3

dir

Compact direct addressing

addr16

addr24

ad24 0 to 15

ad24 16 to 23

Direct addressing

Physical direct addressing

Bit 0 to bit 15 of addr24

Bit 16 to bit 23 of addr24

io

I/O area (000000^Hto 0000FFH)

imm4

imm8

4-bit immediate data

8-bit immediate data

imm16

imm32

ext (imm8)

16-bit immediate data

32-bit immediate data

16-bit data signed and extended from 8-bit immediate data

disp8

disp16

8-bit displacement

16-bit displacement

bp

Bit offset

vct4

vct8

Vector number (0 to 15)

Vector number (0 to 255)

( )b

Bit address

(Continued)

76

MB90640A Series

(Continued)

Symbol

Meaning

rel

Branch specification relative to PC

ear

eam

Effective addressing (codes 00 to 07)

Effective addressing (codes 08 to 1F)

rlst

Register list

Table 3 Effective Address Fields

Address format

Number of bytes in address

extension *

Code

Notation

00

01

02

03

04

05

06

07

R0

RW0

RW1

RW2

RW3

RW4

RW5

RW6

RW7

RL0 Register direct

(RL0)

RL1 “ea” corresponds to byte, word, and

(RL1) long-word types, starting from the

RL2 left

(RL2)

RL3

R1

R2

R3

R4

R5

R6

R7

—

(RL3)

08

09

0A

0B

@RW0

Register indirect

@RW1

@RW2

@RW3

0

0C

0D

0E

0F

@RW0 +

@RW1 +

@RW2 +

@RW3 +

Register indirect with post-increment

10

11

12

13

14

15

16

17

@RW0 + disp8

@RW1 + disp8

@RW2 + disp8

@RW3 + disp8

@RW4 + disp8

@RW5 + disp8

@RW6 + disp8

@RW7 + disp8

Register indirect with 8-bit

displacement

1

18

19

1A

1B

@RW0 + disp16

@RW1 + disp16

@RW2 + disp16

@RW3 + disp16

Register indirect with 16-bit

displacement

2

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

Register indirect with index

PC indirect with 16-bit displacement

Direct address

0

2

Note: The number of bytes in the address extension is indicated by the “+” symbol in the “#” (number of bytes)

column in the tables of instructions.

77

MB90640A Series

Table 4 Number of Execution Cycles for Each Type of Addressing

(a)

Number of register

accesses for each type of

addressing

Code

Operand

Number of execution cycles

for each type of addressing

Ri

RWi

00 to 07

Listed in tables of instructions Listed in tables of instructions

RLi

08 to 0B

0C to 0F

10 to 17

18 to 1B

@RWj

2

4

2

1

2

1

@RWj +

@RWi + disp8

@RWj + disp16

1C

1D

1E

1F

@RW0 + RW7

@RW1 + RW7

@PC + disp16

addr16

4

2

1

2

0

Note: “(a)” is used in the “~” (number of states) column and column B (correction value) in the tables of instructions.

Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles

(b) byte

(c) word

(d) long

Operand

Number

of cycles

Number

of cycles

Number

of cycles

Number

of access

Number

of access

Number

of access

Internal register

+0

1

+0

1

+0

2

Internal memory even address

Internal memory odd address

+0

1

+0

+2

1

2

+0

+4

2

4

Even address on external data bus (16 bits)

Odd address on external data bus (16 bits)

+1

1

+1

+4

1

2

+2

+8

2

4

External data bus (8 bits)

+1

1

+4

2

+8

4

Notes: • “(b)”, “(c)”, and “(d)” are used in the “~” (number of states) column and column B (correction value) in the

tables of instructions.

• When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles

Instruction

Internal memory

Byte boundary

Word boundary

—

+3

+2

+3

—

External data bus (16 bits)

External data bus (8 bits)

Notes: • When the external data bus is used, it is necessary to add in the number of wait cycles used for ready

input and automatic ready.

• Because instruction execution is not slowed down by all program fetches in actuality, these correction

values should be used for “worst case” calculations.

78

MB90640A Series

Table 7 Transfer Instructions (Byte) [41 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

byte (A) ← (dir)

byte (A) ← (addr16)

byte (A) ← (Ri)

byte (A) ← (ear)

byte (A) ← (eam)

byte (A) ← (io)

byte (A) ← imm8

byte (A) ← ((A))

byte (A) ← ((RLi)+disp8)

byte (A) ← imm4

MOV

A, dir

A, addr16

A, Ri

A, ear

A, eam

A, io

A, #imm8

A, @A

A, @RLi+disp8

2

3

1

2

3

4

2

0

1

(b)

0

Z

*

–

*

–

*

–

0

2+ 3+ (a) 0

(b)

0

(b)

0

2

3

1

3

2

3

10

0

2

0

MOVN A, #imm4

1

R

byte (A) ← (dir)

byte (A) ← (addr16)

byte (A) ← (Ri)

byte (A) ← (ear)

byte (A) ← (eam)

byte (A) ← (io)

byte (A) ← imm8

byte (A) ← ((A))

byte (A) ← ((RWi)+disp8)

byte (A) ← ((RLi)+disp8)

MOVX A, dir

MOVX A, addr16

MOVX A, Ri

MOVX A, ear

MOVX A, eam

MOVX A, io

MOVX A, #imm8

MOVX A, @A

MOVX A,@RWi+disp8

MOVX A, @RLi+disp8

2

3

2

3

4

2

0

1

(b)

0

X

*

–

*

–

*

–

0

2+ 3+ (a) 0

(b)

0

(b)

2

3

2

3

5

10

0

1

2

byte (dir) ← (A)

byte (addr16) ← (A)

byte (Ri) ← (A)

byte (ear) ← (A)

byte (eam) ← (A)

byte (io) ← (A)

byte ((RLi) +disp8) ← (A)

byte (Ri) ← (ear)

byte (Ri) ← (eam)

byte (ear) ← (Ri)

byte (eam) ← (Ri)

byte (Ri) ← imm8

byte (io) ← imm8

byte (dir) ← imm8

byte (ear) ← imm8

byte (eam) ← imm8

byte ((A)) ← (AH)

MOV

dir, A

addr16, A

Ri, A

ear, A

eam, A

io, A

@RLi+disp8, A

Ri, ear

Ri, eam

ear, Ri

eam, Ri

Ri, #imm8

io, #imm8

dir, #imm8

ear, #imm8

eam, #imm8

@AL, AH

2

3

1

2

3

4

2

0

1

(b)

0

–

*

–

*

–

*

–

*

–

*

–

0

2+ 3+ (a) 0

(b)

0

(b)

0

(b)

0

(b)

0

(b)

2

3

2

3

10

3

0

2

2+ 4+ (a) 1

2

2+ 5+ (a) 1

2

3

4

2

5

2

1

0

1

3+ 4+ (a) 0

2

3

0

/MOV @A, T

byte (A) ↔ (ear)

byte (A) ↔ (eam)

byte (Ri) ↔ (ear)

byte (Ri) ↔ (eam)

XCH

A, ear

2

4

2

0

Z

–

A, eam

Ri, ear

Ri, eam

2+ 5+ (a) 0 2× (b)

2

2+ 9+ (a) 2 2× (b)

7

4

0

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

79

MB90640A Series

Table 8 Transfer Instructions (Word/Long Word) [38 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

MOVW A, dir

MOVW A, addr16

MOVW A, SP

MOVW A, RWi

MOVW A, ear

MOVW A, eam

MOVW A, io

MOVW A, @A

#

~

B

Operation

2

3

1

2

3

4

1

2

0

1

(c) word (A) ← (dir)

(c) word (A) ← (addr16)

0

(c) word (A) ← (eam)

(c) word (A) ← (io)

(c) word (A) ← ((A))

0

(c)

–

*

–

*

–

*

–

word (A) ← (SP)

word (A) ← (RWi)

word (A) ← (ear)

2+ 3+ (a) 0

2

3

2

3

2

5

10

0

1

2

MOVW A, #imm16

MOVW A, @RWi+disp8

MOVW A, @RLi+disp8

word (A) ← imm16

word (A) ← ((RWi) +disp8)

word (A) ← ((RLi) +disp8)

MOVW dir, A

MOVW addr16, A

MOVW SP, A

MOVW RWi, A

MOVW ear, A

MOVW eam, A

MOVW io, A

MOVW @RWi+disp8, A

MOVW @RLi+disp8, A

MOVW RWi, ear

MOVW RWi, eam

MOVW ear, RWi

MOVW eam, RWi

MOVW RWi, #imm16

MOVW io, #imm16

MOVW ear, #imm16

MOVW eam, #imm16

2

3

1

2

3

4

1

2

0

1

(c) word (dir) ← (A)

(c) word (addr16) ← (A)

–

*

–

*

–

*

–

*

–

0

word (SP) ← (A)

word (RWi) ← (A)

word (ear) ← (A)

2+ 3+ (a) 0

(c) word (eam) ← (A)

(c) word (io) ← (A)

2

3

2

3

5

10

3

0

1

2

word ((RWi) +disp8) ← (A)

word ((RLi) +disp8) ← (A)

(c)

(0) word (RWi) ← (ear)

(c) word (RWi) ← (eam)

2+ 4+ (a) 1

2

2+ 5+ (a) 1

3

4

2

0

word (ear) ← (RWi)

(c) word (eam) ← (RWi)

word (RWi) ← imm16

(c) word (io) ← imm16

word (ear) ← imm16

2

5

2

1

0

1

0

4+ 4+ (a) 0

(c) word (eam) ← imm16

MOVW AL, AH

/MOVW @A, T

2

3

0

(c) word ((A)) ← (AH)

–

*

–

XCHW A, ear

2

4

2

0

word (A) ↔ (ear)

–

XCHW A, eam

XCHW RWi, ear

XCHW RWi, eam

2+ 5+ (a) 0 2× (c) word (A) ↔ (eam)

word (RWi) ↔ (ear)

2+ 9+ (a) 2 2× (c) word (RWi) ↔ (eam)

2

7

4

0

MOVL A, ear

MOVL A, eam

MOVL A, #imm32

2

4

2

0

long (A) ← (ear)

–

*

–

2+ 5+ (a) 0

5

(d) long (A) ← (eam)

3

0

long (A) ← imm32

long (ear) ← (A)

MOVL ear, A

MOVL eam, A

2

4

2

–

*

–

2+ 5+ (a) 0

(d) long (eam) ← (A)

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

80

MB90640A Series

Table 9 Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

ADD A,#imm8

#

~

B

Operation

2

5

3

0

1

0

byte (A) ← (A) +imm8

Z

–

Z

–

Z

–

*

–

*

–

*

ADD

ADDC

A, dir

A, ear

A, eam

ear, A

eam, A

A

(b) byte (A) ← (A) +(dir)

byte (A) ← (A) +(ear)

(b) byte (A) ← (A) +(eam)

byte (ear) ← (ear) + (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) + (A)

0

2+ 4+ (a) 0

2

3

2

0

1

2

3

0

1

0

byte (A) ← (AH) + (AL) + (C)

byte (A) ← (A) + (ear) + (C)

ADDC A, ear

ADDC A, eam

ADDDC A

2+ 4+ (a) 0

(b) byte (A) ← (A) + (eam) + (C)

0

byte (A) ← (AH) + (AL) + (C) (decimal)

1

2

3

2

5

3

0

1

SUB

A, #imm8

byte (A) ← (A) –imm8

(b) byte (A) ← (A) – (dir)

byte (A) ← (A) – (ear)

(b) byte (A) ← (A) – (eam)

byte (ear) ← (ear) – (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) – (A)

SUB

SUBC

A, dir

A, ear

A, eam

ear, A

eam, A

A

0

2+ 4+ (a) 0

2

3

2

0

1

2

3

0

1

0

byte (A) ← (AH) – (AL) – (C)

byte (A) ← (A) – (ear) – (C)

–

SUBC A, ear

SUBC A, eam

SUBDC A

2+ 4+ (a) 0

(b) byte (A) ← (A) – (eam) – (C)

0

byte (A) ← (AH) – (AL) – (C) (decimal)

1

3

0

ADDW A

ADDW A, ear

1

2

3

0

1

0

word (A) ← (AH) + (AL)

word (A) ← (A) +(ear)

(c) word (A) ← (A) +(eam)

–

*

–

*

–

*

ADDW A, eam

2+ 4+ (a) 0

3

2

ADDW

A, #imm16

2

3

0

2

0

word (A) ← (A) +imm16

word (ear) ← (ear) + (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) + (A)

word (A) ← (A) + (ear) + (C)

(c) word (A) ← (A) + (eam) + (C)

ADDW ear, A

ADDW eam, A

ADDCWA, ear

ADDCWA, eam

SUBW A

2

3

1

0

2+ 4+ (a) 0

1

2

2+ 4+ (a) 0

3

2

3

0

1

0

word (A) ← (AH) – (AL)

word (A) ← (A) – (ear)

(c) word (A) ← (A) – (eam)

SUBW A, ear

SUBW A, eam

SUBW

A, #imm16

2

3

0

2

0

word (A) ← (A) –imm16

word (ear) ← (ear) – (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) – (A)

word (A) ← (A) – (ear) – (C)

(c) word (A) ← (A) – (eam) – (C)

SUBW ear, A

SUBW eam, A

SUBCW A, ear

SUBCW A, eam

2

3

1

0

–

2+ 4+ (a) 0

ADDL A, ear

ADDL A, eam

2

6

2

0

long (A) ← (A) + (ear)

–

*

–

2+ 7+ (a) 0

5

2

2+ 7+ (a) 0

5

(d) long (A) ← (A) + (eam)

0

ADDL

A, #imm32

4

6

0

2

long (A) ← (A) +imm32

long (A) ← (A) – (ear)

SUBL A, ear

SUBL A, eam

(d) long (A) ← (A) – (eam)

long (A) ← (A) –imm32

SUBL

A, #imm32

4

0

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

81

MB90640A Series

Table 10 Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

INC

ear

eam

2

0

byte (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) +1

DEC

ear

eam

2

3

2

0

byte (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) –1

INCW ear

INCW eam

2

3

2

0

word (ear) ← (ear) +1

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) +1

DECW ear

DECW eam

2

3

2

0

word (ear) ← (ear) –1

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) –1

INCL ear

INCL eam

2

7

4

0

long (ear) ← (ear) +1

–

*

–

*

2+ 9+ (a) 0 2× (d) long (eam) ← (eam) +1

DECL ear

DECL eam

2

7

4

0

long (ear) ← (ear) –1

–

*

–

*

2+ 9+ (a) 0 2× (d) long (eam) ← (eam) –1

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

Table 11 Compare Instructions (Byte/Word/Long Word) [11 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

CMP

A

1

2

1

2

0

1

0

byte (AH) – (AL)

byte (A) ← (ear)

–

*

–

CMP

A, ear

A, eam

A, #imm8

2+ 3+ (a) 0

2

(b) byte (A) ← (eam)

0

2

0

byte (A) ← imm8

CMPW A

1

2

1

2

0

1

0

word (AH) – (AL)

word (A) ← (ear)

–

*

–

CMPW A, ear

CMPW A, eam

CMPW A, #imm16

2+ 3+ (a) 0

3

(c) word (A) ← (eam)

0

2

0

word (A) ← imm16

CMPL A, ear

CMPL A, eam

CMPL A, #imm32

2

6

2

0

word (A) ← (ear)

–

*

–

2+ 7+ (a) 0

5

(d) word (A) ← (eam)

word (A) ← imm32

3

0

Note: Foranexplanationof“(a)”to “(d)”, refertoTable 4, “NumberofExecution CyclesforEachTypeofAddressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

82

MB90640A Series

Table 12 Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

DIVU

A

1

*1

0

0 word (AH) /byte (AL)

–

*

–

Quotient → byte (AL) Remainder → byte (AH)

2

DIVU

A, ear

A, eam

2

2+

2

1

0

1

0

0 word (A)/byte (ear)

–

*

–

*

Quotient → byte (A) Remainder → byte (ear)

6

3

word (A)/byte (eam)

Quotient → byte (A) Remainder → byte (eam)

*

4

DIVUW A, ear

DIVUW A, eam

long (A)/word (ear)

Quotient → word (A) Remainder → word (ear)

0

*

7

5

2+

long (A)/word (eam)

Quotient → word (A) Remainder → word (eam)

*

MULU

A

8

1

2

2+

0

1

0

byte (AH) *byte (AL) → word (A)

byte (A) *byte (ear) → word (A)

byte (A) *byte (eam) → word (A)

–

0

(b)

*

A, ear

A, eam

9

*

10

*

MULUW

A

11

1

2

2+

0

1

0

word (AH) *word (AL) → long (A)

word (A) *word (ear) → long (A)

word (A) *word (eam) → long (A)

–

0

(c)

*

MULUW A, ear

MULUW A, eam

12

13

*1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally.

*2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally.

*3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally.

*4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally.

*5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally.

*6: (b) when the result is zero or when an overflow occurs, and 2 × (b) normally.

*7: (c) when the result is zero or when an overflow occurs, and 2 × (c) normally.

*8: 3 when byte (AH) is zero, and 7 when byte (AH) is not zero.

*9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero.

*10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0.

*11: 3 when word (AH) is zero, and 11 when word (AH) is not zero.

*12: 4 when word (ear) is zero, and 12 when word (ear) is not zero.

*13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

83

MB90640A Series

Table 13 Logical 1 Instructions (Byte/Word) [39 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

AND A, #imm8

#

~

B

Operation

2

3

0

1

0

byte (A) ← (A) and imm8

byte (A) ← (A) and (ear)

–

*

R

–

*

AND

A, ear

A, eam

ear, A

2+ 4+ (a) 0

(b) byte (A) ← (A) and (eam)

0

2

3

2

byte (ear) ← (ear) and (A)

eam, A

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) and (A) –

OR

A, #imm8

A, ear

A, eam

ear, A

eam, A

2

3

0

1

0

byte (A) ← (A) or imm8

byte (A) ← (A) or (ear)

–

*

R

–

*

2+ 4+ (a) 0

(b) byte (A) ← (A) or (eam)

byte (ear) ← (ear) or (A)

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) or (A)

2

3

2

0

XOR A, #imm8

XOR A, ear

XOR A, eam

XOR ear, A

XOR eam, A

2

3

0

1

0

byte (A) ← (A) xor imm8

byte (A) ← (A) xor (ear)

–

*

R

–

*

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (b) byte (eam) ← (eam) xor (A) –

(b) byte (A) ← (A) xor (eam)

byte (ear) ← (ear) xor (A)

3

2

0

NOT

A

ear

eam

1

2

3

0

2

0

byte (A) ← not (A)

byte (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← not (eam)

ANDW A

1

3

2

3

0

1

0

word (A) ← (AH) and (A)

word (A) ← (A) and imm16

word (A) ← (A) and (ear)

–

*

R

–

*

ANDW A, #imm16

ANDW A, ear

ANDW A, eam

ANDW ear, A

ANDW eam, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) and (A) –

(c) word (A) ← (A) and (eam)

0

3

2

word (ear) ← (ear) and (A)

ORW

A

1

3

2

3

0

1

0

word (A) ← (AH) or (A)

word (A) ← (A) or imm16

word (A) ← (A) or (ear)

–

*

R

–

*

ORW A, #imm16

ORW A, ear

ORW A, eam

ORW ear, A

2+ 4+ (a) 0

2

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) or (A) –

(c) word (A) ← (A) or (eam)

word (ear) ← (ear) or (A)

3

2

0

ORW eam, A

XORW A

1

3

2

3

0

1

0

word (A) ← (AH) xor (A)

word (A) ← (A) xor imm16

word (A) ← (A) xor (ear)

–

*

R

–

*

XORW A, #imm16

XORW A, ear

XORW A, eam

XORW ear, A

XORW eam, A

2+ 4+ (a) 0

(c) word (A) ← (A) xor (eam)

word (ear) ← (ear) xor (A)

2+ 5+ (a) 0 2× (c) word (eam) ← (eam) xor (A)

2

3

2

0

NOTW A

NOTW ear

NOTW eam

1

2

3

0

2

0

word (A) ← not (A)

word (ear) ← not (ear)

–

*

R

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

84

MB90640A Series

Table 14 Logical 2 Instructions (Long Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

ANDL A, ear

ANDL A, eam

2

6

2

0

long (A) ← (A) and (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) and (eam)

ORL

A, ear

A, eam

2

6

2

0

long (A) ← (A) or (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) or (eam)

XORL A, ea

XORL A, eam

2

6

2

0

long (A) ← (A) xor (ear)

–

*

R

–

2+ 7+ (a) 0

(d) long (A) ← (A) xor (eam)

Table 15 Sign Inversion Instructions (Byte/Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

NEG

A

1

2

0

byte (A) ← 0 – (A)

X

–

*

–

NEG ear

NEG eam

2

3

2

0

byte (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a) 0 2× (b) byte (eam) ← 0 – (eam)

NEGW A

1

2

0

word (A) ← 0 – (A)

–

*

–

NEGW ear

NEGW eam

2

3

2

0

word (ear) ← 0 – (ear)

–

*

–

*

2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam)

Table 16 Normalize Instruction (Long Word) [1 Instruction]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

1

long (A) ← Shift until first digit is “1”

byte (R0) ← Current shift count

NRML A, R0

2

1

0

–

*

–

*

*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count).

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

85

MB90640A Series

Table 17 Shift Instructions (Byte/Word/Long Word) [18 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

RORC A

ROLC

2

0

byte (A) ← Right rotation with carry

byte (A) ← Left rotation with carry

–

*

–

*

–

A

RORC ear

RORC eam

ROLC ear

ROLC eam

2

2+

2

3

2

0

byte (ear) ← Right rotation with carry –

–

*

–

*

–

*

–

5+ (a)

byte (eam) ← Right rotation with carry

0 2× (b)

–

3

5+ (a)

2

0

byte (ear) ← Left rotation with carry

2+

0 2× (b) byte (eam) ← Left rotation with carry

*

1

ASR

LSR

LSL

A, R0

byte (A) ← Arithmetic right barrel shift (A, R0)

2

1

0

–

*

–

*

–

*

–

*

1

byte (A) ← Logical right barrel shift (A, R0)

byte (A) ← Logical left barrel shift (A, R0)

*

1

*

ASRW A

word (A) ← Arithmetic right shift (A, 1 bit)

word (A) ← Logical right shift (A, 1 bit)

word (A) ← Logical left shift (A, 1 bit)

1

2

0

–

*

–

*

R

*

–

*

–

LSRW A/SHRW A

LSLW A/SHLW A

1

ASRW A, R0

LSRW A, R0

LSLW A, R0

word (A) ← Arithmetic right barrel shift (A, R0)

word (A) ← Logical right barrel shift (A, R0)

word (A) ← Logical left barrel shift (A, R0)

2

1

0

–

*

–

*

–

*

–

*

1

*

1

*

2

ASRL A, R0

LSRL A, R0

LSLL A, R0

long (A) ← Arithmetic right shift (A, R0)

long (A) ← Logical right barrel shift (A, R0)

long (A) ← Logical left barrel shift (A, R0)

2

1

0

–

*

–

*

–

*

–

*

2

*

2

*

*1: 6 when R0 is 0, 5 + (R0) in all other cases.

*2: 6 when R0 is 0, 6 + (R0) in all other cases.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

86

MB90640A Series

Table 18 Branch 1 Instructions [31 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

1

BZ/BEQ

BNZ/BNE rel

BC/BLO

BNC/BHS rel

rel

2

0

Branch when (Z) = 1

Branch when (Z) = 0

Branch when (C) = 1

Branch when (C) = 0

Branch when (N) = 1

Branch when (N) = 0

Branch when (V) = 1

Branch when (V) = 0

Branch when (T) = 1

Branch when (T) = 0

Branch when (V) xor (N) = 1

Branch when (V) xor (N) = 0

Branch when ((V) xor (N)) or (Z) = 1

Branch when ((V) xor (N)) or (Z) = 0

–

*

1

*

1

rel

*

1

BN

BP

BV

BNV

BT

BNT

BLT

BGE

BLE

BGT

BLS

BHI

BRA

rel

1

*

1

*

1

*

1

*

1

Branch when (C) or (Z) = 1

Branch when (C) or (Z) = 0

Branch unconditionally

1

*

2

3

JMP

@A

1

3

2

2+

2

2+

4

0

1

0

2

0

word (PC) ← (A)

word (PC) ← addr16

word (PC) ← (ear)

–

addr16

@ear

@eam

3

4+ (a)

5

6+ (a)

4

(c) word (PC) ← (eam)

0

(d)

0

JMPP @ear *³

JMPP @eam *³

JMPP addr24

word (PC) ← (ear), (PCB) ← (ear +2)

word (PC) ← (eam), (PCB) ← (eam +2)

word (PC) ← ad24 0 to 15,

(PCB) ← ad24 16 to 23

CALL @ear *⁴

CALL @eam *⁴

CALL addr16 *⁵

CALLV #vct4 *⁵

CALLP @ear *⁶

6

7+ (a)

6

7

10

2

2+

3

1

2

1

0

2

(c) word (PC) ← (ear)

2× (c) word (PC) ← (eam)

(c) word (PC) ← addr16

2× (c) Vector call instruction

2× (c) word (PC) ← (ear) 0 to 15

–

(PCB) ← (ear) 16 to 23

2

CALLP @eam *⁶

CALLP addr24 *⁷

11+ (a)

10

2+

4

0

word (PC) ← (eam) 0 to 15

(PCB) ← (eam) 16 to 23

word (PC) ← addr0 to 15,

(PCB) ← addr16 to 23

–

*

2× (c)

*1: 4 when branching, 3 when not branching.

*2: (b) + 3 × (c)

*3: Read (word) branch address.

*4: W: Save (word) to stack; R: read (word) branch address.

*5: Save (word) to stack.

*6: W: Save (long word) to W stack; R: read (long word) R branch address.

*7: Save (long word) to stack.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

87

MB90640A Series

Table 19 Branch 2 Instructions [19 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

1

CBNE

A, #imm8, rel

Branch when byte (A) ≠ imm8

Branch when word (A) ≠ imm16

3

4

0

–

*

–

*

1

CWBNE A, #imm16, rel

*

2

CBNE

ear, #imm8, rel

eam, #imm8, rel*⁹

Branch when byte (ear) ≠ imm8

Branch when byte (eam) ≠ imm8

Branch when word (ear) ≠ imm16

Branch when word (eam) ≠ imm16

4

4+

5

*

1

0

1

0

(b)

0

–

*

–

3

*

4

CWBNE ear, #imm16, rel

CWBNE eam, #imm16, rel*⁹

*

3

5+

(c)

*

5

3

2

0

Branch when byte (ear) =

(ear) – 1, and (ear) ≠ 0

–

*

–

*

DBNZ ear, rel

*

6

*

3+

2 2× (b) Branch when byte (eam) =

(eam) – 1, and (eam) ≠ 0

DBNZ eam, rel

5

3

*

2

0

Branch when word (ear) =

(ear) – 1, and (ear) ≠ 0

–

*

–

*

DWBNZ ear, rel

DWBNZ eam, rel

6

3+

2× (c) Branch when word (eam) =

*

(eam) – 1, and (eam) ≠ 0

2

3

4

1

0

8× (c) Software interrupt

6× (c) Software interrupt

8× (c) Software interrupt

6× (c) Return from interrupt

–

R

*

S

*

–

*

–

*

–

*

–

*

–

*

–

20

16

17

20

15

INT

INTP

INT9

RETI

#vct8

addr16

addr24

2

0

(c) At constant entry, save old

frame pointer to stack, set

new frame pointer, and

–

6

LINK

#local8

allocate local pointer area

(c) At constant entry, retrieve

old frame pointer from stack.

1

0

–

5

UNLINK

RET *⁷

1

0

(c) Return from subroutine

(d) Return from subroutine

–

4

6

RETP *⁸

*1: 5 when branching, 4 when not branching

*2: 13 when branching, 12 when not branching

*3: 7 + (a) when branching, 6 + (a) when not branching

*4: 8 when branching, 7 when not branching

*5: 7 when branching, 6 when not branching

*6: 8 + (a) when branching, 7 + (a) when not branching

*7: Retrieve (word) from stack

*8: Retrieve (long word) from stack

*9: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

88

MB90640A Series

Table 20 Other Control Instructions (Byte/Word/Long Word) [36 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

PUSHW

A

PUSHW AH

PUSHW PS

PUSHW rlst

word (SP) ← (SP) –2, ((SP)) ← (A)

word (SP) ← (SP) –2, ((SP)) ← (AH)

word (SP) ← (SP) –2, ((SP)) ← (PS)

(SP) ← (SP) –2n, ((SP)) ← (rlst)

1

2

4

0

(c)

–

3

5

4

*

word (A) ← ((SP)), (SP) ← (SP) +2

word (AH) ← ((SP)), (SP) ← (SP) +2

word (PS) ← ((SP)), (SP) ← (SP) +2

(rlst) ← ((SP)), (SP) ← (SP) +2n

POPW A

1

2

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

*

–

3

4

0

(c)

POPW AH

POPW PS

POPW rlst

–

2

5

4

–

*

JCTX @A

1

Context switch instruction

0 6× (c)

–

*

–

14

AND

OR

CCR, #imm8

2

byte (CCR) ← (CCR) and imm8 –

–

*

–

3

0

byte (CCR) ← (CCR) or imm8

–

MOV RP, #imm8

MOV ILM, #imm8

2

byte (RP) ←imm8

byte (ILM) ←imm8

–

2

0

MOVEA RWi, ear

MOVEA RWi, eam 2+

MOVEA A, ear

MOVEA A, eam

2

word (RWi) ←ear

word (RWi) ←eam

word (A) ←ear

word (A) ←eam

–

*

–

3

1

0

2+ (a) 1

2

2+

1

0

*

1+ (a) 0

ADDSP #imm8

ADDSP #imm16

2

3

word (SP) ← (SP) +ext (imm8)

word (SP) ← (SP) +imm16

–

3

0

1

MOV A, brgl

MOV brg2, A

2

byte (A) ← (brgl)

byte (brg2) ← (A)

Z

–

*

–

*

–

0

*

1

NOP

ADB

DTB

PCB

SPB

NCC

CMR

1

No operation

–

0

1

Prefix code for accessing AD space

Prefix code for accessing DT space

Prefix code for accessing PC space

Prefix code for accessing SP space

Prefix code for no flag change

Prefix code for common register bank

*1: PCB, ADB, SSB, USB, and SPB : 1 state

DTB, DPR : 2 states

*2: 7 + 3 × (pop count) + 2 × (last register number to be popped), 7 when rlst = 0 (no transfer register)

*3: 29 + (push count) – 3 × (last register number to be pushed), 8 when rlst = 0 (no transfer register)

*4: Pop count × (c), or push count × (c)

*5: Pop count or push count.

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

89

MB90640A Series

Table 21 Bit Manipulation Instructions [21 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

MOVB A, dir:bp

3

4

3

5

4

0

(b) byte (A) ← (dir:bp) b

(b) byte (A) ← (addr16:bp) b

(b) byte (A) ← (io:bp) b

Z

*

–

*

–

MOVB

A, addr16:bp

MOVB A, io:bp

MOVB dir:bp, A

3

4

3

7

6

0 2× (b) bit (dir:bp) b ← (A)

0 2× (b) bit (addr16:bp) b ← (A)

0 2× (b) bit (io:bp) b ← (A)

–

*

–

*

MOVB

addr16:bp, A

MOVB io:bp, A

SETB dir:bp

SETB addr16:bp

SETB io:bp

3

4

3

7

0 2× (b) bit (dir:bp) b ← 1

0 2× (b) bit (addr16:bp) b ← 1

0 2× (b) bit (io:bp) b ← 1

–

*

CLRB dir:bp

CLRB addr16:bp

CLRB io:bp

3

4

3

7

0 2× (b) bit (dir:bp) b ← 0

0 2× (b) bit (addr16:bp) b ← 0

0 2× (b) bit (io:bp) b ← 0

–

*

1

BBC

dir:bp, rel

4

5

4

0

(b) Branch when (dir:bp) b = 0

(b) Branch when (addr16:bp) b = 0

(b) Branch when (io:bp) b = 0

–

*

–

*

1

BBC

addr16:bp, rel

*

2

BBC

io:bp, rel

*

1

BBS

dir:bp, rel

4

5

4

0

(b) Branch when (dir:bp) b = 1

(b) Branch when (addr16:bp) b = 1

(b) Branch when (io:bp) b = 1

–

*

–

*

BBS

addr16:bp, rel

1

*

2

BBS

io:bp, rel

*

3

SBBS

addr16:bp, rel

Branch when (addr16:bp) b = 1, bit = 1

5

3

0 2× (b)

–

*

–

*

5

4

WBTS io:bp

WBTC io:bp

0

Wait until (io:bp) b = 1

Wait until (io:bp) b = 0

–

*

4

5

*

*1: 8 when branching, 7 when not branching

*2: 7 when branching, 6 when not branching

*3: 10 when condition is satisfied, 9 when not satisfied

*4: Undefined count

*5: Until condition is satisfied

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

90

MB90640A Series

Table 22 Accumulator Manipulation Instructions (Byte/Word) [6 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

SWAP

SWAPW/XCHW AL, AH

EXT

EXTW

ZEXT

ZEXTW

#

~

B

Operation

1

3

2

1

2

1

0

0 byte (A) 0 to 7 ↔ (A) 8 to 15

0 word (AH) ↔ (AL)

0 byte sign extension

0 word sign extension

0 byte zero extension

0 word zero extension

–

X

–

Z

–

*

–

X

–

Z

–

*

R

–

*

–

*

Table 23 String Instructions [10 Instructions]

RG

LH AH

I

S

T

N

Z

V

C

RMW

Mnemonic

#

~

B

Operation

2

5

3

Byte transfer @AH+ ← @AL+, counter = RW0

Byte transfer @AH– ← @AL–, counter = RW0

MOVS/MOVSI

MOVSD

2

–

*

2

5

3

*

1

5

4

Byte retrieval (@AH+) – AL, counter = RW0

Byte retrieval (@AH–) – AL, counter = RW0

SCEQ/SCEQI

SCEQD

2

*

–

*

–

1

5

4

*

5

3

Byte filling @AH+ ← AL, counter = RW0

6m +6

FISL/FILSI

2

–

*

–

*

2

8

6

MOVSW/MOVSWI

Word transfer @AH+ ← @AL+, counter = RW0

Word transfer @AH– ← @AL–, counter = RW0

2

–

*

2

8

6

MOVSWD

*

1

8

7

SCWEQ/SCWEQI

Word retrieval (@AH+) – AL, counter = RW0

Word retrieval (@AH–) – AL, counter = RW0

2

*

–

*

–

1

8

7

SCWEQD

*

8

6

Word filling @AH+ ← AL, counter = RW0

6m +6

FILSW/FILSWI

2

–

*

–

*

m: RW0 value (counter value)

n: Loop count

*1: 5 when RW0 is 0, 4 + 7 × (RW0) for count out, and 7 × n + 5 when match occurs

*2: 5 when RW0 is 0, 4 + 8 × (RW0) in any other case

*3: (b) × (RW0) + (b) × (RW0) when accessing different areas for the source and destination, calculate (b) separately

for each.

*4: (b) × n

*5: 2 × (RW0)

*6: (c) × (RW0) + (c) × (RW0) when accessing different areas for the source and destination, calculate (c) separately

for each.

*7: (c) × n

*8: 2 × (RW0)

Note: For an explanation of “(a)” to “(d)”, refer to Table 4, “Number of Execution Cycles for Each Type of Addressing,”

and Table 5, “Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles.”

91

MB90640A Series

■ ORDERING INFORMATION

Part number

Package

Remarks

MB90641APFV

MB90P641APFV

100-pin Plastic LQFP

(FPT-100P-M05)

MB90641APF

MB90P641APF

100-pin Plastic QFP

(FPT-100P-M06)

92

MB90640A Series

■ PACKAGE DIMENSIONS

100-pin Plastic LQFP

(FPT-100P-M05)

1.50−⁺0⁰.^.210⁰

.059 −⁺.^.0⁰⁰04⁸

16.00±0.20(.630±.008)SQ

(Mounting height)

75

51

14.00±0.10(.551±.004)SQ

76

50

12.00

(.472)

REF

15.00

(.591)

NOM

Details of "A" part

0.15(.006)

INDEX

100

26

0.15(.006)MAX

0.40(.016)MAX

"B"

1

25

LEAD No.

"A"

0.50(.0197)TYP

0.18−⁺0⁰.^.003⁸

0.127 ⁺−0⁰.^.002⁵

.005−⁺.^.0⁰⁰01²

M

Details of "B" part

0.08(.003)

.007 −⁺.^.0⁰⁰01³

0.10±0.10

(STAND OFF)

(.004±.004)

0.50±0.20(.020±.008)

0~10˚

0.10(.004)

C

Dimensions in mm (inches)

1995 FUJITSU LIMITED F100007S-2C-3

100-pin Plastic QFP

(FPT-100P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

80

51

81

50

12.35(.486)

REF

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

16.30±0.40

(.642±.016)

INDEX

31

100

"A"

1

30

LEAD No.

0.65(.0256)TYP

0.30±0.10

(.012±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.13(.005)

Details of "A" part

0.25(.010)

0.30(.012)

"B"

0.10(.004)

0

10°

0.18(.007)MAX

0.53(.021)MAX

18.85(.742)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

C

Dimensions in mm (inches)

1994 FUJITSU LIMITED F100008-3C-2

93

MB90640A Series

MEMO

94

MB90640A Series

MEMO

95

MB90640A Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: (044) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: (044) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document presented

as examples of semiconductor device applications, and are not

intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the

use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

Fax: (408) 922-9179

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and measurement

equipment, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded (such

as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have inherently a certain rate of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required

for export of those products from Japan.

Fax: (65) 281-0220

http://www.fmap.com.sg/

F9803

FUJITSU LIMITED Printed in Japan

96


型号：	MB90641A
厂家：	FUJITSU
描述：	16-bit Proprietary Microcontroller 16位微控制器专有微控制器
文件：	总96页 (文件大小：1456K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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