MB89P875_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12516-4E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89870 Series

MB89875/P875/PV870

■ DESCRIPTION

The MB89870 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the

microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed

control stages, timers, a PWM timer, a serial interface, an A/D converter, an external interrupt, an LCD controller/

driver, and a watch prescaler.

■ FEATURES

• F²MC-8L family CPU core

• Dual-clock control system

• Maximum memory space: 64 Kbytes

• Minimum execution time: 0.4 µs/10 MHz

• Interrupt processing time: 3.6 µs/10 MHz

• I/O ports: max. 45 channels

• 21-bit timebase timer

• 8-bit PWM timer: 1 channel, 1 output channel

• 8/16-bit timer/counter: 2 channels (16 bits × 1 channel)

• 8-bit serial I/O: 1 channel

• 10-bit A/D converter: 8 channels

• OP amp: 4 channels

• External interrupt (wake-up function): 8 channels

(Continued)

■ PACKAGE

80-pin Plastic LQFP

80-pin Plastic QFP

80-pin Ceramic MQFP

(FPT-80P-M05)

(FPT-80P-M06)

(MQP-80C-P01)

MB89870 Series

(Continued)

• Watch prescaler (15 bits)

• LCD controller/driver: 16 to 24 segments × 2 to 4 commons

• Power-on reset function

• Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode)

• LQFP-80 (0.50-mm pitch) and QFP-80 (0.80-mm pitch) package

■ PRODUCT LINEUP

Part number

MB89P875

MB89PV870

MB89875

Parameter

Classification

Mass production product

(mask ROM product)

Piggyback/evaluation product

(for development)

One-time PROM product

ROM size

16 K × 8 bits

(internal mask ROM)

16 K × 8 bits

(internal PROM)

32 K × 8 bits

(external ROM)

RAM size

512 × 8 bits

1 K × 8 bits

LCD display RAM

CPU functions

12 × 8 bits

Number of instructions:

Instruction bit length:

Instruction length:

Data bit length:

136

8 bits

1 to 3 bytes

1, 8, 16 bits

Minimum execution time: 0.4 µs/10 MHz to 6.4 µs/10 MHz, 61.0 µs/32.768 kHz

Interrupt processing time: 3.6 µs/10 MHz to 57.6 µs/10 MHz, 549.3 µs/32.768 kHz

Ports

General-purpose I/O ports (CMOS): 45 (42 ports also serve as peripherals and 8 ports are

also an N-ch open-drain type.)

8-bit interval timer operation (square output capable, operating clock cycle: 0.4 µs to 3.3 ms) × 1 channel

8-bit PWM timer

Timers

7/8-bit resolution PWM operation (conversion cycle: 51.2 µs to 839 ms) × 1 channel

8-bit timer operation (operating clock cycle) × 2 channels

16-bit timer operation (operating clock cycle) × 1 channel

8-bit Serial I/O

8 bits

LSB first/MSB first selectable

One clock selectable from four operation clocks

(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)

LCD controller

24 segments × 4 commons

10-bit A/D

converter

10-bit resolution × 8 channels

A/D conversion mode (conversion time: 13.2 µs)

Sense mode (conversion time: 7.2 µs)

OP amps

4 channels

The output can be used for A/D converter input.

(Continued)

2

MB89870 Series

(Continued)

Part number

MB89P875

MB89PV870

MB89875

Parameter

External

interrupt

8 independent channels (edge selection, interrupt vector, and source flag)

Rising edge/falling edge selectable (4 channels)

Rising edge/falling edge/both edges selectable (4 channels)

Used also for wake-up from stop/sleep mode (Edge detection is also permitted in stop mode.)

Low-power

Consumption

(Standby mode)

Subclock mode, sleep mode, watch mode, and stop mode

CMOS

Process

Operating voltage*

EPROM for use

2.2 V to 6.0 V

2.7 V to 6.0 V

MBM27C256A-20TV

* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

■ PACKAGE AND CORRESPONDING PRODUCTS

MB89875

MB89P875

Package

MB89PV870

FPT-80P-M05

FPT-80P-M06

MQP-80C-P01

×

: Available

× : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

3

MB89870 Series

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

Take particular care on the following points:

• On the MB89PV870, the program area starts from address 8006^Hbut on the MB89P875 and MB89875 starts

from 8000^H.

(On the MB89P875, addresses BFF0^Hto BFF6^Hcomprise the option setting area, option settings can be read

by reading these addresses. On the MB89PV870 and MB89875, addresses 8000^Hto 8006^Hcould also be

used as a program ROM. However, do not use these addresses in order to maintain compatibility of the

MB89P875.)

2. Current Consumption

• In the case of the MB89PV870, add the current consumed by the EPROM which is connected to the top socket.

• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume

more current than the product with a mask ROM.

However, the current consumption in sleep/stop modes is the same. (For more information, see sections

“■ Electrical Characteristics” and “■ Example Characteristics.”)

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options.”

Take particular care on the following points:

• A pull-up resistor cannot be selectable for P30 to P37 if they are used as the analog input pin for an A/D

converter.

• A pull-up resistor cannot be selectable for P10 to P17, and P34 to P37 if an OP amp is used.

• A pull-up resistor is not selectable for P40 to P47 and P23, P24 if they are used as LCD pins.

• Options are fixed on the MB89PV870.

4

MB89870 Series

■ PIN ASSIGNMENT

(Top view)

P46/SEG22

P47/SEG23

AV^SS

1

2

3

4

5

6

7

8

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SEG1

SEG0

COM0

COM1

COM2/P24

COM3/P23

V3

V^CC

V2

V1

V0

V^SS

P22

P21

P20

X1A

X0A

P57/SCK

P56/SO

P55/SI

AVR

AVCC

P30/AN0

P31/AN1

P32/AN2

P33/AN3

P34/AN4/OUT0

P35/AN5/OUT1

P36/AN6/OUT2

V^SS

9

10

11

12

13

14

15

16

17

18

19

20

P37/AN7/OUT3

X1

X0

MOD1

MOD0

RST

P00/INT0

(FPT-80P-M05)

5

MB89870 Series

(Top view)

P44/SEG20

P45/SEG21

P46/SEG22

P47/SEG23

AV^SS

1

2

3

4

5

6

7

8

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SEG3

SEG2

SEG1

SEG0

COM0

COM1

COM2/P24

COM3/P23

V3

V^CC

V2

V1

V0

V^SS

P22

P21

P20

X1A

X0A

AVR

AV^CC

P30/AN0

P31/AN1

P32/AN2

P33/AN3

P34/AN4/OUT0

P35/AN5/OUT1

P36/AN6/OUT2

V^SS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P37/AN7/OUT3

X1

X0

MOD1

MOD0

RST

P57/SCK

P56/SO

P55/SI

P54/BUZ

P53/EC

P00/INT0

P01/INT1

P02/INT2

(FPT-80P-M06)

6

MB89870 Series

(Top view)

P44/SEG20

P45/SEG21

P46/SEG22

P47/SEG23

AV^SS

1

2

3

4

5

6

7

8

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SEG3

SEG2

SEG1

SEG0

COM0

COM1

COM2/P24

COM3/P23

V3

V^CC

V2

V1

V0

V^SS

P22

P21

P20

X1A

X0A

AVR

AV^CC

P30/AN0

P31/AN1

P32/AN2

P33/AN3

P34/AN4/OUT0

P35/AN5/OUT1

P36/AN6/OUT2

V^SS

101

102

103

104

105

106

107

108

109

93

92

91

90

89

88

87

86

85

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

P37/AN7/OUT3

X1

X0

MOD1

MOD0

RST

P57/SCK

P56/SO

P55/SI

P54/BUZ

P53/EC

P00/INT0

P01/INT1

P02/INT2

Each pin inside the dashed line

is for the MB89PV870 only.

(MQP-80C-P01)

• Pin assignment on package top (MB89PV870 only)

Pin no.

81

Pin name

N.C.

V^PP

Pin no.

89

Pin name

A2

Pin no.

97

Pin name

N.C.

O4

Pin no.

Pin name

OE

105

106

107

108

109

110

111

112

82

90

A1

98

N.C.

A11

A9

83

A12

A7

91

A0

99

O5

84

92

N.C.

O1

100

101

102

103

104

O6

85

A6

93

O7

A8

86

A5

94

O2

O8

A13

A14

V^CC

87

A4

95

O3

CE

88

A3

96

V^SS

A10

N.C.: Internally connected. Do not use.

7

MB89870 Series

■ PIN DESCRIPTION

Pin no.

Circuit

type

Pin name

Function

QFP^*2

LQFP^*1

MQFP^*3

15

16

44

45

17

18

19

17

18

46

47

19

20

21

X1

A

B

C

J

Main clock crystal oscillator pins (max. 10 MHz)

X0

X0A

X1A

MOD1

MOD0

RST

Subclock crystal oscillator pins (32.768 kHz)

Operating mode selection pins

Connect to V^SS(GND) when using.

Reset I/O pin

“L” is output from this pin by an internal source.

The internal circuit is initialized by the input of “L”.

20 to 27

22 to 29

P00/INT0 to

P07/INT7

D

E

General-purpose I/O ports

Also serve as an external interrupt input (wake-up

function).

External interrupt input is hysteresis input.

28,

29,

30,

31,

32,

33,

34,

35

30,

31,

32,

33,

34,

35,

36,

37

P10/IN0–,

P11/IN0+,

P12/IN1–,

P13/IN1+,

P14/IN2–,

P15/IN2+,

P16/IN3–,

P17/IN3+

General-purpose I/O ports

Also serve as the input for the OP amp

46 to 48

6 to 9

48 to 50

8 to 11

P20 to P22

F

E

General-purpose I/O ports

P30/AN0 to

P33/AN3

General-purpose I/O ports

Also serve as the input for the A/D converter.

10 to 14

12 to 16

P34/AN4/OUT0 to

P37/AN7/OUT3

G

H

F

General-purpose I/O ports

Also serve as the A/D converter input and the

output for the OP amp.

75 to 80,

1,2

77 to 80,

1 to 4

P40/SEG16 to

P47/SEG23

General-purpose I/O ports

Also serve as an LCD controller/driver segment

output.

36

38

P50/PWM

General-purpose I/O port

The output type can be switched between N-ch

open-drain and CMOS. Also serves as an 8-bit

PWM timer.

37,

38,

39

39,

40,

41

P51/TO2,

P52/TO1,

P53/EC

F

General-purpose I/O ports

The output type can be switched between N-ch

open-drain and CMOS. Also serves as an 8/16-bit

timer/counter.

(Continued)

*1: FPT-80P-M05

*2: FPT-80P-M06

*3: MQP-80C-P01

8

MB89870 Series

(Continued)

Pin no.

Circuit

type

Pin name

P54/BUZ

Function

QFP^*2

LQFP^*1

MQFP^*3

40

42

F

General-purpose I/O port

The output type can be switched between N-ch

open-drain and CMOS. Also serves as a buzzer

output.

41,

42,

43

43,

44,

45

P55/SI,

P56/SO,

P57/SCK

F

General-purpose I/O ports

The output type can be switched between N-ch

open-drain and CMOS. Also serve as an 8-bit serial

I/O.

59 to 74

61 to 76

SEG15 to SEG0

I

LCD controller/driver segment output pins

LCD controller/driver common output pins

58,

57

60,

59

COM0,

COM1

56,

55

58,

57

COM2/P24,

COM3/P23

H

LCD controller/driver common output pins

These pins can be used as general-purpose I/O

ports when they are not used as common output

pins.

50 to 54

52 to 56

V3 to V0

AV^CC

AVR

AV^SS

V^CC

—

LCD driving power supply pins

5

4

7

6

A/D converter and OP amp power supply pin

A/D converter reference voltage input pin

A/D converter and OP amp power supply (GND) pin

Power supply pin

3

5

53

55

13,

49

15,

51

V^SS

Power supply (GND) pins

*1: FPT-80P-M05

*2: FPT-80P-M06

*3: MQP-80C-P01

9

MB89870 Series

• External EPROM pins (MB89PV870 only)

Pin no.

Pin name

V^PP

I/O

O

Function

82

“H” level output pin

Address output pins

83

84

85

86

87

88

89

90

91

A12

A7

A6

A5

A4

A3

A2

A1

A0

O

93

94

95

O1

O2

O3

I

Data input pins

96

V^SS

O

I

Power supply (GND) pin

Data input pins

98

99

100

101

102

O4

O5

O6

O7

O8

103

CE

O

ROM chip enable pin

Outputs “H” during standby.

104

105

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

107

108

109

A11

A9

A8

O

Address output pins

110

111

112

A13

A14

V^CC

O

EPROM power supply pin

81

92

N.C.

—

Internally connected pins

Be sure to leave them open.

97

106

10

MB89870 Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

A

Main clock

X1

• At an oscillation feedback resistor of approximately

1 MΩ/5.0 V

N-ch P-ch

X0

P-ch

N-ch

Main clock control signal

B

Subclock

X1A

X0A

• At an oscillation feedback resistor of approximately

4.5 MΩ/5.0 V

N-ch P-ch

P-ch

N-ch

Subclock control signal

C

D

• CMOS hysteresis input

• CMOS I/O (when selected as general-purpose ports)

• Hysteresis input (when selected as an external

interrupt input)

R

P-ch

• Pull-up resistor optional at approximately 50 kΩ/5.0 V

P-ch

N-ch

E

• Analog input

R

P-ch

N-ch

• CMOS I/O (when selected as general-purpose ports)

• Pull-up resistor optional at approximately 50 kΩ/5.0 V

Analog input

P-ch

N-ch

(Continued)

11

MB89870 Series

(Continued)

Type

Circuit

Remarks

F

• CMOS I/O (when selected as general-purpose ports)

• P50 to P57 are output only and can be switched

between CMOS output and N-ch open-drain output.

• Pull-up resistor optional at approximately 50 kΩ/5.0 V

R

P-ch

N-ch

G

• Analog input

• Analog output

• CMOS I/O (when selected as general-purpose ports)

• Pull-up resistor optional at approximately 50 kΩ/5.0 V

R

P-ch

N-ch

Analog output

P-ch

N-ch

H

• LCD controller/driver output

• CMOS I/O (when selected as general-purpose ports)

• Pull-up resistor optional at approximately 50 kΩ/5.0 V

P-ch

N-ch

R

P-ch

N-ch

P-ch

N-ch

I

• LCD controller/driver output

P-ch

N-ch

P-ch

N-ch

J

• At an output pull-up resistor (P-ch) of approximately

50 kΩ/5.0 V

R

• CMOS hysteresis input

P-ch

N-ch

12

MB89870 Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than V^CCor lower than V^SSis applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between V^CCand V^SS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog power supply (AV^CCand AVR) and analog input from exceeding the digital

power supply (V^CC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AV^CC= DAVC = V^CCand AV^SS= AVR = V^SSeven if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although V^CCpower supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard V^CCvalue at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and

wake-up from stop mode.

13

MB89870 Series

■ PROGRAMMING TO THE EPROM ON THE MB89P875

The MB89P875 is an OTPROM version of the MB89870 series.

1. Features

• 16-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode such as 16-Kbyte PROM, option area is diagrammed below.

Address

0000H

Single chip

EPROM mode

(Corresponding address on the EPROM programmer)

I/O

0080H

0280H

RAM

Not available

BFF0^H

BFF6^H

C000H

3FF0H

Not available

Option area

3FF6^H

Vacancy

4000H

EPROM

16 KB

PROM

16 KB

FFFF^H

7FFFH

3. Programming to the EPROM

In EPROM mode, the MB89P875 functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by

using the dedicated socket adapter. When the operating ROM area for a single chip is 16 Kbytes (C000^Hto

FFFF^H) the PROM can be programmed as follows:

• Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 4000^Hto 7FFF^H(note that addresses C000^Hto FFFF^H

while operating as a single chip assign to 4000^Hto 7FFF^Hin EPROM mode).

Load option data into addresses 3FF0^Hto 3FF6^Hof the EPROM programmer. (For information about each

corresponding option, see “7. Setting OTPROM Options.”)

(3) Program to 3FF0^Hto 7FFF^Hwith the EPROM programmer.

14

MB89870 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. EPROM Programmer Socket Adapter

Recommended programmer

manufacturer and programmer name

Compatible socket adapter

Minato

Electronics Inc.

Part No.

Package

Advantest Corp.

Sun Hayato Co., Ltd.

1890A

R4945A

MB89P875PFV

MB89P875PF

LQFP-80

QFP-80

ROM-80SQF-28DP-8L

ROM-80QF-28DP-8L3

Recommended

Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403

FAX (81)-3-5396-9106

Minato Electronics Inc.: TEL: USA (1)-916-348-6066

JAPAN (81)-45-591-5611

Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111

15

MB89870 Series

7. Setting OTPROM Options

The programming procedure is the same as that for the PROM. Options can be set by programming values at

the addresses shown on the memory map. The relationship between bits and options is shown on the following

bit map:

• OTPROM option bit map

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Single/dual-

clock system

1: Dual clock

0: Single

Oscillation stabilization time

Vacancy

Reset pin

output

1: Yes

Power-on

reset

1: Yes

0: No

3FF0^H

Readable

00: 2¹⁸/F^CH

01: 2¹⁷/F^CH

10: 2¹³/F^CH

11: 0

and writable and writable and writable

0: No

clock

P07

P06

P05

P04

P03

P02

P01

P00

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

3FF1^H

3FF2^H

3FF3^H

3FF4^H

3FF5^H

3FF6^H

Vacancy

P44 to P47 P40 to P43 P16, P17

P14, P15

Pull-up

1: No

P12, P13

Pull-up

1: No

P10, P11

Pull-up

1: No

Pull-up

1: No

Pull-up

1: No

Pull-up

1: No

Readable

and writable and writable 0: Yes

Readable

0: Yes

P37

P36

P35

P34

P33

P32

P31

P30

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

P57

P56

P55

P54

P53

P52

P51

P50

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Vacancy

P24

Pull-up

1: No

P23

P22

P21

P20

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Pull-up

1: No

0: Yes

Readable

and writable and writable and writable 0: Yes

Vacancy

Reserved bit

Readable

and writable and writable and writable and writable and writable and writable and writable and writable

Note: Each bit is set to ‘1’ as the initialized value.

16

MB89870 Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TV

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato

Co., Ltd.) listed below.

Package

Compatible socket part number

ROM-32LC-28DP-YG

LCC-32 (Rectangle)

LCC-32 (Square)

ROM-32LC-28DP-S

Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403

FAX (81)-3-5396-9106

3. Memory Space

Memory space in 32-Kbyte PROM is diagrammed below.

Address

0000H

Single chip

I/O

Corresponding addresses on the

EPROM programmer

0080H

0480H

8000^H

8006H

RAM

Not available

0000H

Not available

0006^H

PROM

32 KB

PROM

32 KB

FFFF^H

7FFFH

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0006^Hto 7FFF^H.

(3) Program to 0000^Hto 7FFF^Hwith the EPROM programmer.

17

MB89870 Series

■ BLOCK DIAGRAM

I/O port

Timebase timer

8-bit PWM timer

P50/PWM

P51/TO2

X0

X1

Main clock oscillator

Clock controller

8-bit timer/counter 2

8-bit timer/counter 1

Subclock oscillator

(32.768 kHz)

X0A

X1A

P52/TO1

P53/EC

Reset circuit

(Watchdog)

RST

Buzzer output

8-bit serial I/O

P54/BUZ

I/O port

P55/SI

P56/SO

P57/SCK

8

P40/SEG16 to

P47/SEG23

LCD controller/driver

3

2

COM2/P24,

COM3/P23

P20 to P22

I/O port

2

COM0, COM1

SEG0 to SEG15

V0 to V3

COM: 2 to 4

16

SEG: 16 to 24

8

4

8

4

External interrupt

P00/INT0 to

P07/INT7

4

10-bit A/D converter

P30/AN0 to

P33/AN3

LCD display RAM

P34/AN4/OUT0

(12 × 8 bits)

–

+

P10/IN0–

P11/IN0+

RAM

P35/AN5/OUT1

–

+

P12/IN1–

P13/IN1+

F²MC-8L

CPU

P36/AN6/OUT2

–

+

P14/IN2–

P15/IN2+

ROM

Other pins

P37/AN7/OUT3

MOD × 2, V^CC× 1

–

+

P16/IN3–

P17/IN3+

V

SS × 2

AV^CC, AVSS, AVR

18

MB89870 Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89870 series offer a memory space of 64 Kbytes for storing all of I/O, data, and

program areas. The I/O area is located at the lowest address. The data area is provided immediately above the

I/O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89870 series is structured as illustrated below.

• Memory Space

MB89P875

I/O

MB89PV870

I/O

MB89875

I/O

0000H

0080H

0100H

0000H

0080H

0000^H

0080H

0100H

RAM

1 KB

RAM

512 B

RAM

512 B

0100H

0200H

Register

0200H

0280H

0200H

0280^H

Not available

0480H

8000H

Not available

BFF0H

C000H

External ROM

32 KB

PROM

16 KB

ROM

16 KB

FFFF^H

FFFFH

19

MB89870 Series

2. Registers

The F²MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC):

Accumulator (A):

A 16-bit register for indicating instruction storage positions

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX):

Extra pointer (EP):

Stack pointer (SP):

Program status (PS):

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

16 bits

Initial value

FFFD^H

: Program counter

: Accumulator

PC

A

Indeterminate

: Temporary accumulator

: Index register

T

IX

: Extra pointer

EP

SP

PS

: Stack pointer

: Program status

I-flag = 0, IL1,0 = 11

The other bit values are indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR). (See the diagram below.)

• Structure of the Program Status Register

15

14

13

12

11

10

9

8

7

6

I

5

4

3

2

Z

1

0

PS

RP

Vacancy Vacancy Vacancy

H

IL1, 0

N

V

C

RP

CCR

20

MB89870 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

• Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

Lower OP codes

“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0

↓

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared

to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low

N-flag: Set to ‘1’ if the MSB becomes to ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit

is cleared to ‘0’.

Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared otherwise.

V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.

21

MB89870 Series

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used on the MB89875 (RAM 512 × 8 bits). The bank currently

in use is indicated by the register bank pointer (RP).

Note: The number of register banks that can be used varies with the RAM size.

• Register Bank Configuraiton

This address = 0100H + 8 × (RP)

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

32 banks

Memory area

22

MB89870 Series

■ I/O MAP

Address

00^H

01^H

02^H

03^H

04^H

05^H

06^H

07^H

08^H

09^H

0A^H

0B^H

0C^H

0D^H

0E^H

0F^H

10^H

11^H

12^H

13^H

14^H

15^H

16^H

17^H

18^H

19^H

1A^H

1B^H

1C^H

1D^H

1E^H

1F^H

Read/write

R/W

W

Register name

PDR0

Register description

Port 0 data register

DDR0

Port 0 data direction register

Port 1 data register

Port 1 data direction register

Port 2 data register

Port 2 data direction register

Vacancy

R/W

W

PDR1

DDR1

R/W

PDR2

DDR2

R/W

SCC

SMC

System clock control register

Standby control register

Watchdog timer control register

Timebase timer control register

Watch prescaler control register

Port 3 data register

Port 3 data direction register

Port 4 data register

Port 4 data direction register

Vacancy

WDTE

TBCR

WCR

PDR3

DDR3

PDR4

DDR4

Vacancy

R/W

PDR5

DDR5

Port 5 data register

Port 5 data direction register

Vacancy

R/W

CHG5

Port 5 switching register

Vacancy

W

R/W

W

ICR3

CNTR

COMP

Port 3 input control register

PWM control register

PWM compare register

(Continued)

23

MB89870 Series

(Continued)

Address

20^H

Read/write

Register name

Register description

Vacancy

21^H

22^H

23^H

24^H

R/W

T2CR

T1CR

T2DR

T1DR

SMR

Timer 2 control register

Timer 1 control register

Timer 2 data register

25^H

26^H

27^H

Timer 1 data register

28^H

Serial mode register

29^H

SDR

Serial data register

2A^H

Vacancy

2B^H

Vacancy

2C^H

R/W

OPC

ADC1

ADC2

ADCH

ADCL

EIE1

OP amp control register

A/D converter control register 1

A/D converter control register 2

A/D converter data register H

A/D converter data register L

External interrupt 1 enable register

External interrupt 1 flag register

External interrupt 2 enable register

Vacancy

2D^H

2E^H

2F^H

30^H

31^H

32^H

EIF1

33^H

EIE2

34^Hto 5F^H

60^Hto 6B^H

6C^Hto 6F^H

70^H

R/W

VRAM

Display data RAM

Vacancy

R/W

LCR1

LCR2

LCD controller/driver control register 1

LCD controller/driver control register 2

Vacancy

71^H

72^Hto 7B^H

7C^H

W

ILR1

ILR2

ILR3

Interrupt level setting register 1

Interrupt level setting register 2

Interrupt level setting register 3

Vacancy

7D^H

7E^H

7F^H

Note: Do not use vacancies.

24

MB89870 Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AV^SS= V^SS= 0.0 V)

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

V^CC

AV^CC

Power supply voltage

V^SS– 0.3

V^SS+ 7.0

V

*

A/D converter reference input

voltage

AVR

V^SS+ 7.0

LCD power supply voltage

Input voltage

V0 to V3 V^SS– 0.3

V^SS+ 7.0

V^CC+ 0.3

V

V0 to V3 must not exceed V^CC.

V^I

V^SS– 0.3

Output voltage

V^O

“L” level maximum output

current

I^OL

20

4

mA

Average value (operating

current × operating rate)

“L” level average output current

I^OLAV

∑I^OL

∑I^OLAV

I^OH

“L” level total maximum output

current

100

40

“L” level total average output

current

Average value (operating

current × operating rate)

“H” level maximum output

current

–20

–4

Average value (operating

current × operating rate)

“H” level average output current

I^OHAV

∑I^OH

∑I^OHAV

“H” level total maximum output

current

–50

–20

“H” level total average output

current

Average value (operating

current × operating rate)

Power consumption

Operating temperature

Storage temperature

P^D

300

+85

mW

°C

T^A

–40

–55

Tstg

+150

°C

* : Use AV^CCand V^CCset at the same voltage.

Take care so that AVR does not exceed AV^CC+ 0.3 V and AV^CCdoes not exceed V^CC, such as when power is

turned on.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

25

MB89870 Series

2. Recommended Operating Conditions

(AV^SS= V^SS= 0.0 V)

Remarks

Value

Symbol

Unit

Parameter

Min.

Max.

Normal operation assurance range*

MB89875

2.2*

6.0*

V

V^CC

AV^CC

Power supply voltage

Normal operation assurance range

MB89PV870/P875

2.7

1.5

0.0

6.0

V

Retains the RAM state in stop mode

A/D converter reference input

voltage

AVR

AV^CC

LCD power supply range

(The optimum value is dependent on

the LCD element in use.)

LCD power supply voltage

V0 to V3

T^A

V^SS

V^CC

V

Operating temperature

–40

+85

°C

* : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1

and “5. A/D Converter Electrical Characteristics.”

26

MB89870 Series

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

6

Analog accuracy assured in the

AVCC = 3.5 V to 6.0 V range

5

Operation assurance range

4

3

2

1

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Main clock operating frequency (at an instruction cycle of 4/F^CH) (MHz)

0.4

4.0 2.0

0.8

Minimum execution time (instruction cycle) (ms)

Note: The shaded area is assured only for the MB89875.

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/F^CH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

27

MB89870 Series

3. DC Characteristics

(AV^CC= V^CC= 5.0 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Parameter Symbol

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

P20 to P24,

V^IH

P30 to P37, P40 to P47,

P50 to P52, P54, P56

0.7 V^CC

V^CC+ 0.3

V

“H” level input

voltage

P00 to P07, P10 to P17,

MOD0, MOD1, RST,

P53, P55, P57

V^IHS

0.8 V^CC

V^SS− 0.3

V^CC+ 0.3

0.3 V^CC

0.2 V^CC

V

P20 to P24,

P30 to P37, P40 to P47,

P50 to P52, P54, P56

V^IL

“L” level input

voltage

P00 to P07, P10 to P17,

MOD0, MOD1, RST,

P53, P55, P57

V^ILS

—

Open-drain

output

N-ch open-

V^D

P50 to P57

V^SS− 0.3

V^CC– 0.3

V

drain

application

voltage

“H” level

output

voltage

P00 to P07, P10 to P17,

P20 to P24, P30 to P37, I^OH= –2.0 mA

P40 to P47, P50 to P57

V^OH

4.0

V

“L” level

output

voltage

P00 to P07, P10 to P17,

P20 to P24, P30 to P37, I^OL= 4.0 mA

P40 to P47, P50 to P57

V^OL

0.4

±5

Input leakage

current

(Hi-Z output

leakage

P00 to P07, P10 to P17,

P20 to P24, P30 to P37, 0.0 V < V^I<

P40 to P47, P50 to P57 V^CC

MOD0, MOD1, RST

With pull-up

resistor

I^LI

µA

current)

P00 to P07, P10 to P17,

P20 to P24, P30 to P37, V^I= 0.0 V

P40 to P47, P50 to P57

Pull-up

resistance

With pull-up

kΩ

R^PULL

25

50

100

resistor

(Continued)

28

MB89870 Series

(AV^CC= V^CC= 5.0 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

F^CH= 10 MHz

V^CC= 5.0 V

t^inst= 0.4 µs

I^CC1

—

12

20

mA

*2

MB89875/

mA

F^CH= 10 MHz

V^CC= 3.0 V

t^inst*2= 6.4 µs

—

1.0

1.5

2

PV870

I^CC2

2.5

mA MB89P875

F^CH= 10 MHz

V^CC= 5.0 V

t^inst= 0.4 µs

I^CCS1

I^CCS2

I^CCL

—

3

7

mA

*2

F^CH= 10 MHz

V^CC= 3.0 V

0.5

1.5

mA

*2

t^inst= 6.4 µs

MB89875/

µA

F^CL= 32.768 kHz,

V^CC= 3.0 V

Subclock mode

—

50

100

700

PV870

500

µA MB89P875

V^CC

F^CL= 32.768 kHz,

V^CC= 3.0 V

Subclock sleep

mode

I^CCLS

—

15

3

50

µA

Power supply

current^*1

F^CL= 32.768 kHz,

V^CC= 3.0 V

• Watch mode

• Main clock stop

mode at dual-

clock system

I^CCT

—

15

µA

T^A= +25°C

• Subclock stop

mode

• Main clock stop

mode at single-

clock system

I^CCH

—

1

µA

F^CH= 10 MHz,

when A/D

conversion is

activated

I^A

—

1.5

—

3

1

mA

AV^CC

F^CH= 10 MHz,

T^A= +25°C,

when A/D

I^AH

µA

conversion is

stopped

(Continued)

29

MB89870 Series

(Continued)

(AV^CC= V^CC= 5.0 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Parameter

Symbol

Pin name

Condition

Unit Remarks

Min.

Typ.

Max.

Between

V^CCand V0

at V^CC= 5.0 V

LCD divided

resistance

R^LCD

300

500

750

kΩ

COM0 to 3 output

impedance

R^VCOM

COM0 to 3

—

2.5

15

V1 to V3 = 5.0 V

SEG0 to 24

output

R^VSEG

SEG0 to 24

impedance

LCD controller/

driver leakage

current

V0 to V3, COM0 to 3

SEG0 to SEG24

I^LCDL

—

±1

µA

Other than AV^CC,

AV^SS, V^CC, and V^SS

Input capacitance C^IN

f = 1 MHz

10

pF

*1: The power supply current is measured at the external clock.

*2: For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

Note: For pins which serve as the LCD and ports (P23, P24 and P40 to P47), see the port parameter when these

pins are used as ports and the LCD parameter when they are used as LCD pins.

30

MB89870 Series

4. AC Characteristics

(1) Reset Timing

(V^CC= +5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Condition

Unit

Remarks

Parameter

Min.

Max.

RST “L” pulse width

t^ZLZH

—

48 t^HCYL

—

ns

tZLZH

RST

0.2 VCC

(2) Power-on Reset

Parameter

(AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Condition

Unit

Remarks

Min.

Max.

50

Power supply rising time

Power supply cutoff time

t^R

—

1

ms

Power-on reset function only

Due to repeated operations

—

t^OFF

—

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is

recommended.

tOFF

t^R

2.0 V

0.2 V

V

CC

31

MB89870 Series

(3) Clock Timing

(AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol Pin name Condition

Unit

Remarks

Parameter

Clock frequency

Clock cycle time

Min.

1

Typ.

—

Max.

10

F^CH

X0, X1

MHz

kHz

ns

F^CL

X0A, X1A

X0, X1

—

32.768

—

t^HCYL

t^LCYL

100

—

1000

—

X0A, X1A

30.5

µs

—

Input clock pulse

width

P^WH

P^WL

X0

20

—

ns

External clock

Input clock rising/

falling time

t^CR

t^CF

10

32

MB89870 Series

X0 and X1 Timing and Conditions

t^HCYL

PWH

P_WL

t^CR

tCF

0.8 VCC

X0

0.2 VCC

Main Clock Conditions

When a crystal

or

ceramic resonator is used

When an external clock is used

X0

X1

X0

X1

Open

X0A and X1A Timing and Conditions

tLCYL

X0A

0.2 VCC

Subclock Conditions

When a crystal

or

ceramic resonator is used

X0A

X1A

33

MB89870 Series

(4) Instruction Cycle

Symbol

Value (typical)

4/F^CH, 8/F^CH, 16/F^CH, 64/F^CHµs

2/F^CLµs

Unit

Remarks

Parameter

(4/F^CH) t^inst= 0.4 µs when operating at

F^CH= 10 MHz

Instruction cycle

(minimum execution time)

t^inst

t^inst= 61.036 µs when operating at

F^CL= 32.768 kHz

Note: When operating at 10 MHz, the cycle varies with the set execution time.

(5) Serial I/O Timing

(V^CC= +5.0 V±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Min.

Symbol Pin name

Condition

Unit Remarks

Parameter

Max.

—

Serial clock cycle time

SCK ↓ → SO time

t^SCYC

t^SLOV

t^IVSH

t^SHIX

t^SHSL

t^SLSH

t^SLOV

t^IVSH

t^SHIX

SCK

2 t^inst*

–200

µs

ns

µs

ns

µs

SCK, SO

SI, SCK

SCK, SI

200

—

Internal shift

clock mode

Valid SI → SCK ↑

1/2 t^inst*

1 t^inst*

0

SCK ↑ → valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

SCK ↓ → SO time

—

SCK

—

External shift

clock mode

SCK, SO

SI, SCK

SCK, SI

200

—

Valid SI → SCK ↑

1/2 t^inst*

SCK ↑ → valid SI hold time

—

* : For information on t^inst, see “(4) Instruction Cycle.”

Internal Shift Clock Mode

tSCYC

2.4 V

SCK

0.8 V

tSLOV

2.4 V

SO

0.8 V

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

SI

0.2 VCC

External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

SCK

0.2 VCC

tSLOV

2.4 V

0.8 V

SO

SI

tIVSH

tSHIX

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

34

MB89870 Series

(6) Peripheral Input Timing

Parameter

(V^CC= +5.0 V ±10%, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Symbol

Pin name

Unit Remarks

Min.

1 t^inst*

2 t^inst*

Max.

—

Peripheral input “H” pulse width 1

Peripheral input “L” pulse width 1

Peripheral input “H” pulse width 2

Peripheral input “L” pulse width 2

t^ILIH1

t^IHIL1

t^ILIH2

t^IHIL2

µs

EC

—

INT7 to INT0

—

* : For information on t^inst,see “(4) Instruction Cycle.”

tIHIL1

tILIH1

EC

0.8 VCC

0.2 V^CC

0.8 VCC

0.2 VCC

tIHIL2

tILIH2

INT7 to INT0

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

35

MB89870 Series

5. A/D Converter Electrical Characteristics

(AV^CC= V^CC= +3.5 V to +6.0 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

Typ.

—

name

Symbol

Remarks

Parameter

Resolution

Condition

Unit

Min.

—

Max.

10

—

bit

Total error

—

±3.0

±2.0

±1.5

LSB

—

Linearity error

—

Differential linearity error

Zero transition voltage

—

AVR = AV^CC

V^OT

AV^SS– 1.5 LSB AV^SS+ 0.5 LSB AV^SS+ 2.5 LSB mV

AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB mV

Full-scale transition

voltage

—

V^FST

Interchannel disparity

—

4.0

—

LSB

A/D mode conversion

time

33 t^inst*

µs

—

Sense mode conversion

time

—

18 t^inst*

—

µs

—

Analog port input

current

AN0

to

I^AIN

10

µA

AN7

Analog input voltage

Reference voltage

—

0.0

—

AVR

AV^CC

V

AVR = 5.0 V,

when A/D

conversion

is activated

I^R

—

200

—

µA

AVR

Reference voltage

supply current

AVR = 5.0 V,

when A/D

conversion

is stopped

I^RH

1

* : For information on t^inst, see “(4) Instruction Cycle” in “4. AC Characteristics.”

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

When the number of bits is 10, analog voltage can be divided into 2¹⁰= 1024.

• Linearity error (unit: LSB)

The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with

the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values

36

MB89870 Series

Digital output

Theoretical conversion value

Actual conversion value

11 1111 1111

11 1111 1110

•

(1 LSB × N + V^OT)

AVR

1024

•

1 LSB =

•

V^NT– (1 LSB × N + VOT)

•

Linearity error =

•

1 LSB

•

V( N + 1 ) T – VNT

•

– 1

Differential linearity error =

Total error =

•

1 LSB

Linearity error

•

VNT – (1 LSB × N + 1 LSB)

•

1 LSB

•

00 0000 0010

00 0000 0001

00 0000 0000

VOT

VNT

V(N + 1)T

VFST

Analog input

7. Notes on Using A/D Converter

• Input impedance of the analog input pins

The A/D converter used for the MB89870 series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

• Analog Input Equivalent Circuit

Sample hold circuit

.

C = 33 pF

.

Analog input pin

Comparator

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

.

R = 6 kΩ

.

Close for 8 instruction cycles after activating

A/D conversion.

Analog channel selector

• Error

The smaller the | AVR – AV^SS|, the greater the error would become relatively.

37

MB89870 Series

8. OP Amp Electrical Characteristics

(1) AV^CC= 5.0 V

(AV^CC= V^CC= 4.5 V to 5.5 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

name

Parameter

Symbol

Condition

Unit Remarks

Min.

Typ.

Max.

0.5 V^CC–

1.25

0.5 V^CC+

1.25

IN0± to

IN3±

I/O voltage range

—

0.5 V^CC

V

Minimum load

resistance

—

100

—

kΩ

Maximum load

resistance

—

–10

—

0

100

+10

—

pF

mV

Offset voltage

Gain-bandwidth

production

1.8

MHz

DC gain

—

75

—

dB

Slew rate

0.9

V/µs

(2) AV^CC= 3.0 V

(AV^CC= V^CC= 2.7 V to 3.3 V, AV^SS= V^SS= 0.0 V, T^A= –40°C to +85°C)

Value

name

Parameter

Symbol

Condition

Unit Remarks

Min.

Typ.

Max.

0.5 V^CC–

0.35

IN0± to

IN3±

I/O voltage range

—

0.5

V^CC– 1.20

V

Minimum load

resistance

—

250

—

kΩ

Maximum load

resistance

—

–10

—

0

100

+10

—

µA

mV

Offset voltage

Gain-bandwidth

production

0.5

MHz

DC gain

—

75

—

dB

Slew rate

0.1

V/µs

38

MB89870 Series

■ EXAMPLE CHARACTERISTICS

(1) “L” Level Output Voltage

(2) “H” Level Output Voltage

VOL vs. IOL

V^OL(V)

VCC – VOH vs. IOH

TA = +25 °C

V^CC– VOH (V)

1.0

VCC = 2.5 V

TA = +25 °C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VCC = 2.5 V

V^CC= 3.0 V

0.5

V^CC= 3.0 V

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

0.4

0.3

0.2

0.1

0.0

V^CC= 4.0 V

V^CC= 5.0 V

V^CC= 6.0 V

10

I^OL(mA)

0

1

2

3

4

5

6

7

8

9

0.0

–0.5 –1.0 –1.5 –2.0 –2.5 –3.0

I^OH(mA)

(3) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input)

(4) “H” Level Input Voltage/“L” Level Input

Voltage (Hysteresis Input)

VIN vs. VCC

V^IN(V)

VIN vs. VCC

V^IN(V)

5.0

TA = +25°C

4.5

4.0

TA = +25 °C

4.5

3.5

VIHS

4.0

3.5

3.0

2.5

2.0

1.5

3.0

2.5

VILS

2.0

1.5

1.0

0.5

0.0

1.0

0.5

0.0

0

1

2

3

4

5

6

7

V^CC(V)

VIHS: Threshold when input voltage in hysteresis

characteristics is set to “H” level

0

1

2

3

4

5

6

7

V^CC(V)

V^ILS: Threshold when input voltage in hysteresis

characteristics is set to “L” level

39

MB89870 Series

(5) Power Supply Current (External Clock)

ICCS1 vs. VCC, ICCS2 vs. V CC

ICC1 vs. VCC, ICC2 vs. VCC

I^CCS(mA)

5.0

I^CC(mA)

16

Divide by 4 (ICC1)

FCH = 10 MHz

T^A= +25°C

FCH = 10 MHz

T^A= +25°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

14

12

10

8

Divide by 4 (I^CC1)

Divide by 8

6

Divide by 16

4

Divide by 64 (ICC2)

2

Divide by 64 (ICC2)

0.5

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V^CC(V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V^CC(V)

ICCLS vs. VCC

ICCL vs. VCC

I^CCLS(µA)

I^CCL(µA)

50

200

TA = +25 °C

45

40

35

30

25

20

15

10

5

180

160

140

120

100

80

60

40

20

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V^CC(V)

(Continued)

40

MB89870 Series

(Continued)

ICCT vs. VCC

ICCH vs. VCC

I

CCT (µA)

20

ICCH (µA)

2.0

TA = +25 ¡C

TA = +25 °C

18

16

14

12

10

8

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

6

4

2

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

V^CC(V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

VCC (V)

IA vs. AVCC

I^Rvs. AVR

IA (mA)

5.0

I^R(µA)

200

TA = +25 °C

F^CH= 10 MHz

TA = + 25 °C

4.5

4.0

180

160

140

120

100

80

3.5

3.0

2.5

2.0

60

1.5

1.0

40

20

0.5

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

AV^CC(V)

AVR (V)

(6) Pull-up Resistance

RPULL vs. VCC

R^PULL(kΩ)

1000

TA = +25 °C

100

10

1

2

3

4

5

6

V^CC(V)

41

MB89870 Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

AH

AL

Lower 8 bits of accumulator A (8 bits)

T

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

TH

TL

IX

EP

PC

SP

PS

dr

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

CCR

RP

Ri

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )

(( × ))

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

42

MB89870 Series

Columns indicate the following:

Mnemonic:

~:

Assembler notation of an instruction

The number of instructions

The number of bytes

#:

Operation:

TL, TH, AH:

Operation of an instruction

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

43

MB89870 Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

–

AL

–

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

F0

Notes: • During byte transfer to A, T ← A is restricted to low bytes.

• Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

44

MB89870 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

A

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

45

MB89870 Series

(Continued)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

46

MB89870 Series

■ INSTRUCTION MAP

47

MB89870 Series

■ MASK OPTIONS

Part number

MB89875

MB89P875

MB89PV870

No.

Specify when

ordering masking

Set with EPROM

programmer

Specifying procedure

Setting not possible

Pull-up resistors

Specify by pin

P00 to P07, P10 to P17,

P20 to P24, P30 to P37,

P40 to P47, P50 to P57

(in 2-pin unit for P10 (in 2-pin unit for P10 Fixed to without pull-

to P17, and in 4-pin to P17, and in 4-pin up resistor

unit for P40 to P47) unit for P40 to P47)

1

Power-on reset selection

Fixed to with power-

on reset

2

3

With power-on reset

Without power-on reset

Selectable

Selection of the oscillation

stabilization time initial value

2¹⁸/F^CH(Approx. 26.2 ms)

2¹⁷/F^CH(Approx. 13.1 ms)

2¹³/F^CH(Approx. 0.8 ms)

2⁴/F^CH(Approx. 0 ms)

Fixed to 2¹⁸/F^CH

(Approx. 26.2 ms)

Selectable

Selection either single- or dual-clock

system

Fixed to dual-clock

system

4

5

Selectable

Single clock

Dual Clock

Reset pin output

With reset output

Without reset output

Fixed to with reset

output

Notes: • Reset is input asynchronized with the internal clock whether with or without power-on reset.

• P30 to P37 should be set to without pull-up resistor when an A/D conveter is used.

• P10 to P17, P34 to P37 should be set to without pull-up resistor when an OP amp is used.

• P40 to P47 and P23 and P24 should be set to without pull-up resistor when an LCD controller/driver is used.

■ ORDERING INFORMATION

Part number

MB89875PFV

Package

Remarks

80-pin Plastic LQFP

(FPT-80P-M05)

MB89P875PFV

MB89875PF

MB89P875PF

80-pin Plastic QFP

(FPT-80P-M06)

80-pin Ceramic MQFP

(MQP-80C-P01)

MB89PV870CF

48

MB89870 Series

■ PACKAGE DIMENSIONS

80-pin Plastic LQFP

(FPT-80P-M05)

14.00±0.20(.551±.008)SQ

12.00±0.10(.472±.004)SQ

1.50 –⁺0⁰.^.1²0⁰

.059 ⁺^–.^.⁰⁰⁰⁰⁴⁸

(Mounting height)

60

41

61

40

13.00

(.512)

NOM

9.50

(.374)

REF

INDEX

80

21

1

20

LEAD No.

Details of "A" part

"A"

0.50±0.08

(.0197±.0031)

0.18 –⁺0⁰.^.0⁰3⁸

.007 ⁺^–.^.⁰⁰⁰⁰¹³

0.127 ⁺–0⁰.^.0⁰2⁵

.005 ⁺^–.^.⁰⁰⁰⁰¹²

0.10±0.10

(.004±.004)

(STAND OFF)

0.50±0.20(.020±.008)

0.10(.004)

0

10°

C

Dimensions in mm (inches)

1995 FUJITSU LIMITED F80008S-2C-5

80-pin Plastic QFP

(FPT-80P-M06)

23.90±0.40(.941±.016)

20.00±0.20(.787±.008)

3.35(.132)MAX

(Mounting height)

0.05(.002)MIN

(STAND OFF)

64

41

65

40

12.00(.472)

16.30±0.40

14.00±0.20 17.90±0.40

(.551±.008) (.705±.016)

REF

(.642±.016)

INDEX

80

25

"A"

1

24

LEAD No.

0.80(.0315)TYP

0.35±0.10

(.014±.004)

0.15±0.05(.006±.002)

Details of "B" part

M

0.16(.006)

Details of "A" part

0.25(.010)

"B"

0.10(.004)

0.30(.012)

0.18(.007)MAX

0.58(.023)MAX

0

10°

18.40(.724)REF

0.80±0.20

(.031±.008)

22.30±0.40(.878±.016)

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED F80010S-3C-2

49

MB89870 Series

80-pin Ceramic MQFP

(MQP-80C-P01)

18.70(.736)TYP

12.00(.472)TYP

16.30±0.33

(.642±.013)

15.58±0.20

(.613±.008)

1.50(.059)TYP

1.00(.040)TYP

0.80±0.25

(.0315±.010)

INDEX AREA

1.20 –⁺0⁰.^.2⁴0⁰

4.50(.177)

TYP

0.80±0.25

(.0315±.010)

.047 –⁺.^.0⁰0¹8⁶

1.27±0.13

(.050±.005)

INDEX AREA

18.12±0.20

(.713±.008)

22.30±0.33

(.878±.013)

12.02(.473)

TYP

18.40(.724)

REF

10.16(.400)

TYP

14.22(.560)

TYP

0.30(.012)

24.70(.972)

TYP

INDEX

6.00(.236)

TYP

0.40±0.10

(.016±.004)

1.27±0.13

(.050±.005)

0.30(.012)TYP

0.40±0.10

(.016±.004)

1.20 –⁺0⁰.^.2⁴0⁰

.047 –⁺.^.0⁰0¹8⁶

1.50(.059)

TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

1.00(.040)

TYP

0.15±0.05 8.70(.343)

(.006±.002) MAX

Dimensions in mm (inches)

C

1994 FUJITSU LIMITED M80001SC-4-2

50

MB89870 Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

KAWASAKI PLANT, 4-1-1, Kamikodanaka

Nakahara-ku, Kawasaki-shi

Kanagawa 211-8588, Japan

Tel: 81(44) 754-3763

The contents of this document are subject to change without

notice. Customers are advised to consult with FUJITSU sales

representatives before ordering.

Fax: 81(44) 754-3329

http://www.fujitsu.co.jp/

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications,

and are not intended to be incorporated in devices for actual use.

Also, FUJITSU is unable to assume responsibility for

infringement of any patent rights or other rights of third parties

arising from the use of this information or circuit diagrams.

North and South America

FUJITSU MICROELECTRONICS, INC.

Semiconductor Division

3545 North First Street

San Jose, CA 95134-1804, USA

Tel: (408) 922-9000

FUJITSU semiconductor devices are intended for use in

standard applications (computers, office automation and other

office equipment, industrial, communications, and

Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608

measurement equipment, personal or household devices, etc.).

CAUTION:

Fax: (408) 922-9179

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage,

or where extremely high levels of reliability are demanded

(such as aerospace systems, atomic energy controls, sea floor

repeaters, vehicle operating controls, medical devices for life

support, etc.) are requested to consult with FUJITSU sales

representatives before such use. The company will not be

responsible for damages arising from such use without prior

approval.

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH

Am Siebenstein 6-10

D-63303 Dreieich-Buchschlag

Germany

Tel: (06103) 690-0

Fax: (06103) 690-122

Any semiconductor devices have an inherent chance of

failure. You must protect against injury, damage or loss from

such failures by incorporating safety design measures into your

facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating

conditions.

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD

#05-08, 151 Lorong Chuan

New Tech Park

Singapore 556741

Tel: (65) 281-0770

Fax: (65) 281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for

export of those products from Japan.

http://www.fmap.com.sg/

F9812

FUJITSU LIMITED Printed in Japan

51


型号：	MB89P875
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器
文件：	总51页 (文件大小：684K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89P875 [FUJITSU]

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