MB84VR5E4J4J1-85-PBS

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50215-1E

3Stacked MCP (Multi-Chip Package) FLASH & FCRAM & FCRAM

CMOS

64M (×16) FLASH MEMORY &

32M (×16) Mobile FCRAM^TM&

32M (×16) Mobile FCRAM^TM

MB84VR5E4J4J1^-85

■ FEATURES

• Power Supply Voltage of 2.7 to 3.1 V

• High Performance

85 ns maximum access time (Flash)

85 ns maximum access time (FCRAM_1 : 32M)

85 ns maximum access time (FCRAM_2 : 32M)

• Operating Temperature

–25 °C to +85 °C

• Package 85-ball BGA

(Continued)

■ PRODUCT LINEUP

Flash Memory

FCRAM(1)

FCRAM(2)

+0.1 V

–0.3 V

+0.1 V

–0.3 V

+0.1 V

V^CCf* = 3.0 V

–0.3 V

Supply Voltage (V)

VCCr_1* = 3.0 V

VCCr_2* = 3.0 V

Max Address Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

85

35

85

45

85

45

*: All of VCCf , VCCr_1 and VCCr_2 must be the same level when either part is being accessed.

■ PACKAGE

85-ball plastic FBGA

BGA-85P-M02

MB84VR5E4J4J1^-85

(Continued)

FLASH MEMORY

• Simultaneous Read/Write Operations (Dual Bank)

• FlexBank^TM

Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)

Bank B : 24 Mbit (64 KB × 48)

Bank C : 24 Mbit (64 KB × 48)

Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)

Two virtual Banks are chosen from the combination of four physical banks

Host system can program or erase in one bank, then read immediately and simultaneously read from the other

bank between read and write operations

Read-while-erase

Read-while-program

• Minimum 100,000 Write/Erase Cycles

• Sector Erase Architecture

Sixteen 4 K words and one hundred twenty-six 32 K word.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Embedded Erase^TMAlgorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program^TMAlgorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready-Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, the device automatically switches to low power mode.

• Low V^CCf Write Inhibit ≤ 2.5 V

• Hidden ROM (Hi-ROM) Region

256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

At V^IL, allows protection of 2 of 8 Kbytes on both ends of each boot sector, regardless of sector protection/

unprotection status.

At VIH, allows removal of boot sector protection

At V^ACC, increases program performance

• Program Suspend/Resume

Suspends the program operation to allow to read in another address

• Erase Suspend/Resume

Suspends the erase operation to allow to read in another sector within the same device

• Please Refer to “MBM29DL640E” Datasheet for Detailed Function

(Continued)

2

MB84VR5E4J4J1^-85

(Continued)

FCRAM_1 and FCRAM_2 (32M)

• Power Dissipation

Operating : 30 mA Max

Standby : 100 µA Max

• Four Power Down Mode

Sleep

NAP

: 10 µA Max

: 60 µA Max

8M Partial : 70 µA Max

• Power Down Control by CE2r_1 or CE2r_2

• Byte Write Control: LB (DQ⁷-DQ⁰), UB (DQ¹⁵-DQ⁸)

• 4 Words Address Access Capability

FlexBank^TMis a trademark of Fujitsu Limited, Japan.

Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

Mobile FCRAM^TMis a trademark of Fujitsu Limited, Japan.

3

MB84VR5E4J4J1^-85

■ PIN ASSIGNMENT

(Top View)

Marking side

A12

N.C

A11

N.C

A10

N.C

B12

N.C

B11

N.C

B10

N.C

L12

N.C

L11

N.C

L10

N.C

M12

N.C

M11

N.C

M10

N.C

D10

A15

D9

E10

A21

E9

F10

N.C

F9

G10

A16

G9

H10

VCCf

H9

J10

VSS

J9

C9

A11

C8

K9

A12

D8

A13

E8

A14 PE_1 DQ15 DQ7 DQ14

F8 G8 H8 J8 K8

A10 DQ6 DQ13 DQ12 DQ5

F7 G7

H7 J7 K7

A19

D7

A9

A8

C7

E7

WE CE2r_1 A20 PE_2 CE2r_2 DQ4 VCCr_1 N.C.

F6

CE1r_2 VCCr_2

F5 G5

A17 DQ1

G6

C6

WP/ACC

C5

D6

RESET

D5

E6

RY/BY

E5

H6

DQ3

H5

J6

VCCf

J5

K6

DQ11

K5

LB

UB

A18

E4

DQ9 DQ10 DQ2

C4

D4

F4

A4

F3

A1

G4

H4

OE

H3

J4

K4

A7

A6

A5

VSS

DQ0 DQ8

J3

A3

N.C.

A2

B3

N.C.

B2

D3

E3

L3

M3

G3

A0

A2

CEf CE1r_1

N.C. N.C.

L2

M2

N.C. N.C.

A3

C2

N.C.

A1

N.C.

B1

N.C.

L1

M1

N.C.

(BGA-85P-M02)

4

MB84VR5E4J4J1^-85

■ PIN DESCRIPTION

Input/

Output

Pin No.

Pin name

Description

D10,G10,

C9,D9,E9,F9,

C8,D8,E8,F8,E7

E5,F5,D4,E4,F4,C4,

D3,E3,F3,G3,

A²⁰to A0

I

Address Inputs (Common)

E10

A²¹

Address Inputs (Flash)

H9,J9,K9,

G8,H8,J8,K8,

H7,H6,K6,

G5,H5,J5,K5,

J4,K4,

DQ¹⁵to DQ0

I/O

Data Inputs/Outputs (Common)

H3

J3

CEf

CE1r_1

CE1r_2

CE2r_1

CE2r_2

OE

I

Chip Enable (Flash)

Chip Enable (FCRAM_1)

F6

D7

G7

H4

C7

E6

D5

C5

D6

C6

G9

F7

I

Chip Enable (FCRAM_2)

I

Chip Enable (FCRAM_1)

I

Chip Enable (FCRAM_2)

I

Output Enable (Common)

WE

I

Write Enable (Common)

RY/BY

UB

O

I

Ready/Busy Output (Flash) Open Drain Output

Upper Byte Control (FCRAM_1 & FCRAM_2)

Lower Byte Control (FCRAM_1 & FCRAM_2)

Hardware Reset Pin/Sector Protection Unlock (Flash)

Write Protect / Acceleration (Flash)

Partial Enable (FCRAM_1)

LB

I

RESET

WP/ACC

PE_1

PE_2

I

Partial Enable (FCRAM_2)

A12,B12,L12,M12,

A11,B11,L11,M11,

A10,B10,F10,L10,M10,

K7,A3,B3,L3,M3,

A2,B2,C2,L2,M2,

A1,B1,L1,M1

N.C.

—

No Internal Connection

G4,J10

J6,H10

J7

V^SS

Power Device Ground (Common)

VCCf

Power Device Power Supply (Flash)

Power Device Power Supply (FCRAM_1)

Power Device Power Supply (FCRAM_2)

VCCr_1

VCCr_2

G6

5

MB84VR5E4J4J1^-85

■ BLOCK DIAGRAM

V^CCf

V^SS

A²¹to A⁰

RY/BY

A²¹to A⁰

64 M bit

Flash Memory

WP/ACC

RESET

CEf

DQ¹⁵to DQ⁰

V^CCr_1

V^SS

A²⁰to A⁰

32 M bit

FCRAM_1

LB

UB

WE

OE

CE1r_1

CE2r_2

PE_1

V^CCr_2

V^SS

A²⁰to A⁰

PE_2

CE1r_2

CE2r_2

32 M bit

FCRAM_2

6

MB84VR5E4J4J1^-85

■ DEVICE BUS OPERATIONS

WP/

Operation

A²¹to

A⁰

DQ⁷to DQ¹⁵to

DQ⁰DQ⁸

ACC

CE1r_1 CE2r_1 CE1r_2 CE2r_2

PE_1 PE_2

RESET

CEf

OE WE LB

UB

*^1,*²

13

*

Full Standby

High-Z High-Z

H

L

H

L

H

L

H

X

H

X

H

X

H

X

H

X

X*¹¹

X

Output

Disable *³

H

Read from

L

H

L

X

H

X

L

H

L

H

L

X

H

Valid DOUT

DOUT

DIN

H

X

Flash *⁴

Write to

Flash

Valid

DIN

Read from

FCRAM_1 *⁵

L *¹⁰L *¹⁰

H

Valid DOUT

D^IN

DOUT

L

H

L

DIN

Write to

FCRAM_1 *⁵

High-Z

H

L

H

X

H

L

X

H

L

H

L

H

Valid

H

X

High-Z

H

DIN

Read from

FCRAM_2 *⁵

L *¹⁰L *¹⁰

Valid DOUT

DOUT

L

H

L

DIN

Valid High-Z

DIN

Write to

FCRAM_2

H

High-Z

H

FLASH

Temporary

Sector

Group

X

VID

X

Unprotection

6

*

Flash

Hardware

Reset

High-Z High-Z

X

H

X

H

X

H

X

H

X

L

X

L

FLASH

Boot Block

Sector Write

Protection

X

FCRAM_1

SIngle

Cycle

PowerDown

Program

KEY

*

High-Z High-Z

H

X

L

H

X

12

FCRAM_2

SIngle

Cycle

PowerDown

Program

KEY

*

H

L

H

X

L

X

H

X

H

X

H

L

High-Z High-Z

H

X

12

FCRAM_1

KEY

NO READ *^7,

H

12

*

8

*

(Continued)

7

MB84VR5E4J4J1^-85

(Continued)

WP/

Operation

A²¹to

A⁰

DQ⁷to DQ¹⁵to

DQ⁰DQ⁸

ACC

CE1r_1 CE2r_1 CE1r_2 CE2r_2

PE_1 PE_2

RESET

CEf

OE WE LB

UB

*^1,*²

13

*

FCRAM_2

NO READ

*^7,*⁸

KEY

*

High-Z High-Z

H

L

X

H

L

H

X

H

X

L

X

H

X

H

X

H

X

H

X

H

X

12

FCRAM_1

Power

Down *⁹

X

FCRAM_2

Power

Down *⁹

X

Legend: L = VIL, H = VIH, X = VIL or VIH. See “■DC CHARACTERISTICS” for voltage levels.

*1: Other operations except for indicated this column are inhibited.

*2: Do not apply for a following state two or more on the same time.

1)CEf = VIL, 2) CE1r_1 = VIL and CE2r_1 = VIH,

3) CE1r_2 = VIL and CE2r_2 = VIH

*3: FCRAM Output Disable condition should not be kept longer than 1µs.

*4: WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*5: FCRAM LB, UB control at Read operation is not supported.

*6: Used for the extended sector group protections.

*7: The FCRAM Power Down Program can be performed one time after compliance of Power-UP timings and it

should not be re-programmed after regular Read or Write.

*8: Used for FCRAM Multi Cycle Power Program that requires special sequence.

Please refer to FCRAM timing diagram for the detail.

*9: FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High state.

I^PDr current and data retention depends on the selection of Power Down Program.

*10:Either or both LB and UB must be Low for FCRAM Read Operation.

*11:Can be either V^ILor VIH but must be valid before Read or Write

*12:See “FCRAM Power Down Program Key Table” in next page.

*13:Protect “outer most” 2x8K bytes (4 words) on both ends of the boot block sectors.

8

MB84VR5E4J4J1^-85

FCRAM Power Down Program Key Table

Basic Key Table

Definition

A16

A17

A18

A19

A20

KEY

Mode Select

Area Select

A18 A19 A20

AREA

L

H

L

X

H

TOP ^*2

RESERVED

BOTTOM ^*3

H

A16

L

A17

L

MODE

NAP ^*4

L

H

RESERVED

8M Partial

SLEEP ^{*4, *5}

H

L

H

Available Key Table

A16

A17

A18

A19

A20

Data Retention

MODE

NAP

Area

Mode Select

Area Select

L

H

L

X

L

X

L

X

L

None

Top 8M only

Bottom 8M only

None

8M Partial

SLEEP

L

H

X

H

X

H

X

H

*1: The Power Down Program can be performed one time after compliance of Power-up timings and it

should not be re-programmed after regular Read or Write.

Unspecified addresses, A0 to A15, can be either High or Low during the programming.

The RESERVED key should not be used.

*2: TOP area is from the lowest address location. (i.e., A[20:0] = L)

*3: BOTTOM area is from the highest address location. (i.e., A[20:0] = H)

*4: NAP and SLEEP do not retain the data and Area Select is ignored.

*5: Default state. Power Down Program to this SLEEP mode can be omitted.

9

MB84VR5E4J4J1^-85

■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY

• Sixteen 4K words, and one hundred twenty-six 32 K words.

• Individual-sector, multiple-sector, or bulk-erase capability.

Word Mode

000000h

200000h

208000h

210000h

218000h

220000h

228000h

230000h

238000h

240000h

248000h

250000h

258000h

260000h

268000h

270000h

278000h

280000h

288000h

290000h

298000h

2A0000h

2A8000h

2B0000h

2B8000h

2C0000h

2C8000h

2D0000h

2D8000h

2E0000h

2E8000h

2F0000h

2F8000h

300000h

308000h

310000h

318000h

320000h

328000h

330000h

338000h

340000h

348000h

350000h

358000h

360000h

368000h

370000h

378000h

380000h

388000h

390000h

398000h

3A0000h

3A8000h

3B0000h

3B8000h

3C0000h

3C8000h

3D0000h

3D8000h

3E0000h

3E8000h

3F0000h

3F8000h

3F9000h

3FA000h

3FB000h

3FC000h

3FD000h

3FE000h

3FF000h

3FFFFFh

SA0 : 8KB (4KW)

SA1 : 8KB (4KW)

SA2 : 8KB (4KW)

SA3 : 8KB (4KW)

SA4 : 8KB (4KW)

SA5 : 8KB (4KW)

SA6 : 8KB (4KW)

SA7 : 8KB (4KW)

SA8 : 64KB (32KW)

SA9 : 64KB (32KW)

SA10 : 64KB (32KW)

SA11 : 64KB (32KW)

SA12 : 64KB (32KW)

SA13 : 64KB (32KW)

SA14 : 64KB (32KW)

SA15 : 64KB (32KW)

SA16 : 64KB (32KW)

SA17 : 64KB (32KW)

SA18 : 64KB (32KW)

SA19 : 64KB (32KW)

SA20 : 64KB (32KW)

SA21 : 64KB (32KW)

SA22 : 64KB (32KW)

SA23 : 64KB (32KW)

SA24 : 64KB (32KW)

SA25 : 64KB (32KW)

SA26 : 64KB (32KW)

SA27 : 64KB (32KW)

SA28 : 64KB (32KW)

SA29 : 64KB (32KW)

SA30 : 64KB (32KW)

SA31 : 64KB (32KW)

SA32 : 64KB (32KW)

SA33 : 64KB (32KW)

SA34 : 64KB (32KW)

SA35 : 64KB (32KW)

SA36 : 64KB (32KW)

SA37 : 64KB (32KW)

SA38 : 64KB (32KW)

SA39 : 64KB (32KW)

SA40 : 64KB (32KW)

SA41 : 64KB (32KW)

SA42 : 64KB (32KW)

SA43 : 64KB (32KW)

SA44 : 64KB (32KW)

SA45 : 64KB (32KW)

SA46 : 64KB (32KW)

SA47 : 64KB (32KW)

SA48 : 64KB (32KW)

SA49 : 64KB (32KW)

SA50 : 64KB (32KW)

SA51 : 64KB (32KW)

SA52 : 64KB (32KW)

SA53 : 64KB (32KW)

SA54 : 64KB (32KW)

SA55 : 64KB (32KW)

SA56 : 64KB (32KW)

SA57 : 64KB (32KW)

SA58 : 64KB (32KW)

SA59 : 64KB (32KW)

SA60 : 64KB (32KW)

SA61 : 64KB (32KW)

SA62 : 64KB (32KW)

SA63 : 64KB (32KW)

SA64 : 64KB (32KW)

SA65 : 64KB (32KW)

SA66 : 64KB (32KW)

SA67 : 64KB (32KW)

SA68 : 64KB (32KW)

SA69 : 64KB (32KW)

SA70 : 64KB (32KW)

SA71 : 64KB (32KW)

SA72 : 64KB (32KW)

SA73 : 64KB (32KW)

SA74 : 64KB (32KW)

SA75 : 64KB (32KW)

SA76 : 64KB (32KW)

SA77 : 64KB (32KW)

SA78 : 64KB (32KW)

SA79 : 64KB (32KW)

SA80 : 64KB (32KW)

SA81 : 64KB (32KW)

SA82 : 64KB (32KW)

SA83 : 64KB (32KW)

SA84 : 64KB (32KW)

SA85 : 64KB (32KW)

SA86 : 64KB (32KW)

SA87 : 64KB (32KW)

SA88 : 64KB (32KW)

SA89 : 64KB (32KW)

SA90 : 64KB (32KW)

SA91 : 64KB (32KW)

SA92 : 64KB (32KW)

SA93 : 64KB (32KW)

SA94 : 64KB (32KW)

SA95 : 64KB (32KW)

SA96 : 64KB (32KW)

SA97 : 64KB (32KW)

SA98 : 64KB (32KW)

SA99 : 64KB (32KW)

SA100 : 64KB (32KW)

SA101 : 64KB (32KW)

SA102 : 64KB (32KW)

SA103 : 64KB (32KW)

SA104 : 64KB (32KW)

SA105 : 64KB (32KW)

SA106 : 64KB (32KW)

SA107 : 64KB (32KW)

SA108 : 64KB (32KW)

SA109 : 64KB (32KW)

SA110 : 64KB (32KW)

SA111 : 64KB (32KW)

SA112 : 64KB (32KW)

SA113 : 64KB (32KW)

SA114 : 64KB (32KW)

SA115 : 64KB (32KW)

SA116 : 64KB (32KW)

SA117 : 64KB (32KW)

SA118 : 64KB (32KW)

SA119 : 64KB (32KW)

SA120 : 64KB (32KW)

SA121 : 64KB (32KW)

SA122 : 64KB (32KW)

SA123 : 64KB (32KW)

SA124 : 64KB (32KW)

SA125 : 64KB (32KW)

SA126 : 64KB (32KW)

SA127 : 64KB (32KW)

SA128 : 64KB (32KW)

SA129 : 64KB (32KW)

SA130 : 64KB (32KW)

SA131 : 64KB (32KW)

SA132 : 64KB (32KW)

SA133 : 64KB (32KW)

SA134 : 8KB (4KW)

SA135 : 8KB (4KW)

SA136 : 8KB (4KW)

SA137 : 8KB (4KW)

SA138 : 8KB (4KW)

SA139 : 8KB (4KW)

SA140 : 8KB (4KW)

SA141 : 8KB (4KW)

001000h

002000h

003000h

004000h

005000h

006000h

007000h

008000h

010000h

018000h

020000h

028000h

030000h

038000h

040000h

048000h

050000h

058000h

060000h

068000h

070000h

078000h

080000h

088000h

090000h

098000h

0A0000h

0A8000h

0B0000h

0B8000h

0C0000h

0C8000h

0D0000h

0D8000h

0E0000h

0E8000h

0F0000h

0F8000h

100000h

108000h

110000h

118000h

120000h

128000h

130000h

138000h

140000h

148000h

150000h

158000h

160000h

168000h

170000h

178000h

180000h

188000h

190000h

198000h

1A0000h

1A8000h

1B0000h

1B8000h

1C0000h

1C8000h

1D0000h

1D8000h

1E0000h

1E8000h

1F0000h

1F8000h

1FFFFFh

Bank A

Bank C

Bank B

Bank D

Sector Architecture

10

MB84VR5E4J4J1^-85

Example of Virtual Banks Combination

Bank 1

Bank 2

Combination

Bank

Splits

Combination

Volume

Sector Size

Volume

Sector Size

Bank B

+

8 of 8 Kbyte / 4 K word

1

2

3

4

8M bit

Bank A

+

56 Mbit

Bank C

+

Bank D

+

15 of 64 Kbyte / 32 K word

111 of 64 Kbyte / 32 K word

Bank A

+

Bank D

16 of 8 Kbyte / 4 K word

Bank B

+

Bank C

16 Mbit

24 Mbit

32 Mbit

+

48 Mbit

96 of 64 Kbyte / 32 K word

30 of 64 Kbyte / 32 K word

Bank A

+

Bank C

+

16 of 8 Kbyte / 4 K word

Bank B

48 of 64 Kbyte / 32 K word 40 Mbit

+

78 of 64 Kbyte / 32 K word

Bank D

Bank A

+

8 of 8 Kbyte / 4 K word

Bank C

+

8 of 8 Kbyte / 4 K word

+

32 Mbit

+

Bank B

63 of 64 Kbyte / 32 K word

Bank D

63 of 64 Kbyte / 32 K word

Bank A: Address 000000h to 07FFFFh

Bank B: Address 080000h to 1FFFFFh

Bank C: Address 200000h to 37FFFFh

Bank D: Address 380000h to 3FFFFFh

Sector Address Tables

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

0

A²⁰

0

A¹⁹

0

A¹⁸

0

1

A¹⁷

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

1

X

A¹³

0

1

0

1

X

A¹²

0

1

0

1

0

1

0

1

X

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

006000h to 006FFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 067FFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

(Continued)

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Bank A

11

MB84VR5E4J4J1^-85

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

0

A²⁰

0

1

A¹⁹

1

0

1

A¹⁸

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

A¹³

X

A¹²

X

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1FFFFFh

(Continued)

Bank B

12

MB84VR5E4J4J1^-85

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

1

A²⁰

0

1

A¹⁹

0

1

0

A¹⁸

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

A¹³

X

A¹²

X

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

200000h to 207FFFh

208000h to 20FFFFh

210000h to 217FFFh

218000h to 21FFFFh

220000h to 227FFFh

228000h to 22FFFFh

230000h to 237FFFh

238000h to 23FFFFh

240000h to 247FFFh

248000h to 24FFFFh

250000h to 257FFFh

258000h to 25FFFFh

260000h to 267FFFh

268000h to 26FFFFh

270000h to 277FFFh

278000h to 27FFFFh

280000h to 287FFFh

288000h to 28FFFFh

290000h to 297FFFh

298000h to 29FFFFh

2A0000h to 2A7FFFh

2A8000h to 2AFFFFh

2B0000h to 2B7FFFh

2B8000h to 2BFFFFh

2C0000h to 2C7FFFh

2C8000h to 2CFFFFh

2D0000h to 2D7FFFh

2D8000h to 2DFFFFh

2E0000h to 2E7FFFh

2E8000h to 2EFFFFh

2F0000h to 2F7FFFh

2F8000h to 2FFFFFh

300000h to 307FFFh

308000h to 30FFFFh

310000h to 317FFFh

318000h to 31FFFFh

320000h to 327FFFh

328000h to 32FFFFh

330000h to 337FFFh

338000h to 33FFFFh

340000h to 347FFFh

348000h to 34FFFFh

350000h to 357FFFh

358000h to 35FFFFh

360000h to 367FFFh

368000h to 36FFFFh

370000h to 377FFFh

378000h to 37FFFFh

(Continued)

Bank C

13

MB84VR5E4J4J1^-85

(Continued)

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

1

A²⁰

1

A¹⁹

1

A¹⁸

0

1

A¹⁷

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

1

A¹³

X

0

1

0

1

A¹²

X

0

1

0

1

0

1

0

1

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

380000h to 387FFFh

388000h to 38FFFFh

390000h to 397FFFh

398000h to 39FFFFh

3A0000h to 3A7FFFh

3A8000h to 3AFFFFh

3B0000h to 3B7FFFh

3B8000h to 3BFFFFh

3C0000h to 3C7FFFh

3C8000h to 3CFFFFh

3D0000h to 3D7FFFh

3D8000h to 3DFFFFh

3E0000h to 3E7FFFh

3E8000h to 3EFFFFh

3F0000h to 3F7FFFh

3F8000h to 3F8FFFh

3F9000h to 3F9FFFh

3FA000h to 3FAFFFh

3FB000h to 3FBFFFh

3FC000h to 3FCFFFh

3FD000h to 3FDFFFh

3FE000h to 3FEFFFh

3FF000h to 3FFFFFh

Bank D

14

MB84VR5E4J4J1^-85

Sector Group Addresses

Sector Group

SGA0

A²¹

0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

0

1

SGA8

0

1

0

X

SA8 to SA10

1

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

SGA38

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

X

0

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SA67 to SA70

SA71 to SA74

SA75 to SA78

SA79 to SA82

SA83 to SA86

SA87 to SA90

SA91 to SA94

SA95 to SA98

SA99 to SA102

SA103 to SA106

SA107 to SA110

SA111 to SA114

SA115 to SA118

SA119 to SA122

SA123 to SA126

SA127 to SA130

SGA39

1

0

1

X

SA131 to SA133

1

0

SGA40

SGA41

SGA42

SGA43

SGA44

SGA45

SGA46

SGA47

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

15

MB84VR5E4J4J1^-85

Flash Memory Autoselect Codes

Type

A²¹to A¹²

BA

A⁶

L

A³

L

A²

L

A¹

L

A⁰

L

Code (HEX)

04h

Manufacture’s Code

Device Code

BA

L

H

L

227Eh

2202h

BA

L

H

Extended Device

Code *²

BA

L

H

2201h

Sector Group

Protection

Sector Group

Addresses

L

H

L

01h*¹

Legend: L = V^IL, H = VIH. See DC Characteristics for voltage levels.

*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore the system may continue reading out

these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.

16

MB84VR5E4J4J1^-85

Flash Memory Command Definitions

Fourth Bus

Read/Write

Cycle

Bus

Write

Cycles

Req’d

First Bus

Second Bus Third Bus

Fifth Bus

Write Cycle Write Cycle

Sixth Bus

Command

Sequence

Write Cycle Write Cycle Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset

1

3

XXXh F0h

—

555h AAh 2AAh 55h 555h F0h

(BA)

RA

RD

Autoselect

3

4

1

555h AAh 2AAh 55h

90h

—

PA

—

PD

—

555h

Program

555h AAh 2AAh 55h 555h A0h

Program

Suspend

BA

B0h

30h

—

Program

Resume

1

6

—

Chip Erase

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h

Sector

Erase

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h

SA

—

30h

—

Erase

Suspend

1

BA

B0h

30h

—

Erase

Resume

—

Extended

Sector

Group

Protection *²

4

XXXh 60h

SPA

60h

SPA

40h

SPA

SD

—

Set to

Fast Mode

3

2

555h AAh 2AAh 55h 555h 20h

—

Fast

Program *¹

XXXh A0h

PA

PD

—

Reset from

Fast

Mode *¹

4

*

2

BA

90h XXXh

—

F0h

(BA)

55h

Query

1

3

4

98h

—

Hi-ROM

Entry

555h AAh 2AAh 55h 555h 88h

Hi-ROM

Program *³

(HRA)

PA

555h AAh 2AAh 55h 555h A0h

PD

Hi-ROM

Exit *³

(HRBA)

555h

555h AAh 2AAh 55h

90h XXXh 00h

(Continued)

17

MB84VR5E4J4J1^-85

(Continued)

*1: This command is valid during Fast Mode.

*2: This command is valid while RESET = VID.

*3: This command is valid during Hi-ROM mode.

*4: The data “00h” is also acceptable.

Notes : 1. Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA),

Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).

2. RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and

A12 will uniquely select any sector.

BA = Bank Address (A21, A20, A19)

3. RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

4. SPA =Sector group address to be protected. Set sector group address and (A⁶, A3, A2, A1, A0) = (0, 0, 0,

1, 0).

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

5. HRA = Address of the Hi-ROM area: 000000h to 00007Fh

6. HRBA =Bank Address of the Hi-ROM area (A21 = A20 = A19 = VIL)

7. The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0

8. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

9. The command combinations not described in “Flash Memory Command Definitions” are illegal.

18

MB84VR5E4J4J1^-85

■ ABSOLUTE MAXIMUM RATINGS

Rating

Unit

Parameter

Symbol

Min

–55

–25

Max

Storage Temperature

Tstg

T^A

+125

°C

V

Ambient Temperature with Power Applied

+85

V^CCf +0.3

V^CCr_1 +0.3

VCCr_2 +0.3

Voltage with Respect to Ground All pins

except RESET,WP/ACC *¹

VIN, VOUT

–0.3

V

VCCf, VCCr_1,

VCCr_2

V^CCf/VCCr_1/VCCr_2 Supply *¹

–0.3

+3.3

V

RESET *²

VIN

–0.5

+ 13.0

+10.5

V

WP/ACC *³

*1: Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot

VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr_1 +

0.3 V or VCCr_2 + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr_1 +

1.0 V or VCCr_2 + 1.0 V for periods of up to 20 ns.

*2: Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions RESET pins may undershoot VSS

to –2.0 V for periods of up to 20 ns.

Voltage difference between input and supply voltage (VIN-VCCf) does not exceed +9.0 V.

Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.

*3: Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot

Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min

–25

+2.7

Max

+85

Ambient Temperature

T^A

°C

V

V^CCf/VCCr_1/VCCr_2 Supply Voltages VCCf, VCCr_1,VCCr_2

+3.1

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

19

MB84VR5E4J4J1^-85

■ DC CHARACTERISTICS

Value

Symbol

Parameter

Conditions

Unit

Min Typ Max

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCCf, VCCr_1,VCCr_2

VOUT = VSS to VCCf, VCCr_1,VCCr_2

–1.0

—

+1.0 µA

ILO

RESET Inputs Leakage

Current

VCCf = VCCf Max,

RESET = 12.5 V

ILIT

ILIA

—

35

20

µA

VCCf = VCCf Max,

WP/ACC = VACC Max

ACC Input Leakage Current

mA

tCYCLE =5MHz

—

18

7

mA

Flash V^CCActive Current

(Read) *¹

CEf = VIL,

OE = VIH

ICC1f

tCYCLE =1MHz

Flash VCC Active Current

(Program/Erase) *²

ICC2f

ICC3f

ICC4f

ICC5f

IACC

CEf = VIL, OE = VIH

—

40

58

40

mA

Flash V^CCActive Current

(Read-While-Program) *⁵

Flash V^CCActive Current

(Read-While-Erase) *⁵

Flash V^CCActive Current

(Erase-Suspend-Program)

WP/ACC Acceleration

Program Current

VCCf = VCCf Max,

WP/ACC = VACC Max

—

20

25

V^CCr_1 = VCCr_1 Max or

VCCr_2 = VCCr_2 Max,

t^RC/ tWC =Min

FCRAM V^CCActive Current

ICC1r

CE1r_1 = VIL,CE2r_1 = VIH or

CE1r_2 = VIL, CE2r_2 = VIH,

VIN = VIH or VIL, IOUT = 0 mA

mA

t^RC/ tWC =1µs.

—

3.0

VCCf = VCCf Max, CEf = VCCf ± 0.3 V

RESET = VCCf ± 0.3 V,

WP/ACC = VCCf± 0.3 V

Flash V^CCStandby Current

ISB1f

ISB2f

—

1

5

µA

Flash V^CCStandby Current

(RESET)

VCCf = VCCf Max, RESET = VSS ± 0.3 V,

WP/ACC = VCCf± 0.3 V

V^CCf = VCCf Max, CEf = VSS ± 0.3 V

RESET = VCCf ± 0.3 V,

WP/ACC = VCCf± 0.3 V,

Flash V^CCCurrent (Automatic

Sleep Mode) *³

ISB3f

—

1

5

µA

VIN = VCCf± 0.3 V or VSS ± 0.3 V

V^CCr_1 = VCCr_1 Max or

VCCr_2 = VCCr_2 Max,

CE1r_1 > VCCr_1 – 0.2V or

CE2r_1 > VCCr_1– 0.2V,

CE1r_2 > VCCr_2 – 0.2V or

CE2r_2 > VCCr_2– 0.2V,

VIN < 0.2 V or VCCr_1 – 0.2 V or

VCCr_2 – 0.2 V

FCRAM V^CCStandby Current

ISB1r

—

100 µA

(Continued)

20

MB84VR5E4J4J1^-85

(Continued)

Parameter

Value

Unit

Symbol

Conditions

VCCr_1 = VCCr_1 Max or

VCCr_2 = VCCr_2 Max,

CE1r_1 > VCCr_1 – 0.2V or

CE1r_2 > VCCr_2 – 0.2V,

CE2r_1 < 0.2V, or

Min Typ Max

I^PDSr

I^PDNr

Sleep

NAP

—

10

60

µA

FCRAM V^CCPower Down

Current

I^PD8r

8M Partial

—

70

µA

CE2r_2 < 0.2V,

VIN Cycle time = tRC Min

Input Low Level

Input High Level

V^IL

V^IH

—

–0.3

2.4

—

0.5

V

VCC+

0.3 *⁶

—

Voltage for Sector Protec-

tion, and Temporary Sector

Unprotection (RESET) *⁴

VID

—

11.5

8.5

—

12.5

9.5

V

Voltage for WP/ACC Sector

Protection/Unprotection

and Program Acceleration

VACC

—

9.0

4

*

V^OLf

V^OLr

VCCf = VCCf Min, IOL=4.0 mA

Flash

—

0.45

0.4

V

VCCr_1 = VCCr_1 Min or

VCCr_2 = VCCr_2 Min,

IOL =1.0 mA

Output Low Voltage Level

Output High Voltage Level

FCRAM

VCCf–

0.4

V^OHf

V^OHr

VLKO

VCCf = VCCf Min, IOH=–0.1 mA

Flash

—

V

VCCr_1 = VCCr_1 Min or

VCCr_2 = VCCr_2 Min,

IOH =– 0.5 mA

FCRAM

2.1

2.3

Flash Low V^CCf Lock-Out

Voltage

—

2.5

*1: ICC current listed includes both the DC operating current and the frequency dependent component.

*2: ICC active while Embedded Algorithm (program or erase) is in progress.

*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.

*4: Applicable for only V^CCf applying.

*5: Embedded Algorithm (program or erase) is in progress. (@5 MHz)

*6: VCC indicates lower of VCCf or VCCr_1 or VCCr_2.

21

MB84VR5E4J4J1^-85

■ AC CHARACTERISTICS

• CE Timing

Symbol

JEDEC Standard

Value

Parameter

Condition

Unit

Min

0

Max

—

CE Recover Time

CE Hold Time

—

tCCR

—

ns

tCHOLD

3

—

CE1r_1, CE1r_2 High to WE Invalid

time for Standby Entry

—

tCHWX

—

5

—

ns

• Timing Diagram for alternating RAM to Flash

CEf

tCCR

CE1r_1 or

CE1r_2

WE

tCHWX

tCHOLD

tCCR

CE2r_1 or

CE2r_2

22

MB84VR5E4J4J1^-85

• Read Only Operations Characteristics (Flash)

Symbol

Value (Note)

Parameter

Condition

Unit

JEDEC

Standard

Min

Max

Read Cycle Time

t^AVAV

tRC

—

85

—

ns

CEf = VIL

OE = VIL

Address to Output Delay

tAVQV

tACC

—

85

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

tEHQZ

t^GHQZ

tCEf

tOE

tDF

OE = VIL

—

85

35

30

ns

—

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

tAXQX

tOH

—

0

—

ns

µs

RESET Pin Low to Read Mode

—

tREADY

—

20

Note: Test Conditions– Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V or V^CCf

Timing measurement reference level

Input: 0.5×VCCf

Output: 0.5×VCCf

23

MB84VR5E4J4J1^-85

• Read Cycle (Flash)

tRC

Address Stable

Address

tACC

CEf

OE

tOE

t^DF

tOEH

WE

tCE

High-Z

DQ

Output Valid

tRC

Address

Address Stable

tACC

CEf

tRH

tCE

tRP

RESET

DQ

tOH

High-Z

Output Valid

24

MB84VR5E4J4J1^-85

• Erase/Program Operations (Flash)

Symbol

JEDEC Standard Min

Value

Typ

—

Parameter

Unit

Max

—

Write Cycle Time

t^AVAV

tAVWL

—

tWC

tAS

85

0

ns

Address Setup Time (WE to Addr.)

Address Setup Time to CEf Low During Toggle Bit Polling

Address Hold Time (WE to Addr.)

—

tASO

tAH

15

45

—

tWLAX

—

Address Hold Time from CEf or OE High During Toggle Bit

Polling

—

tAHT

0

—

ns

Data Setup Time

Data Hold Time

tDVWH

tWHDX

tDS

tDH

35

0

—

16

1

—

85

—

90

—

20

ns

µs

s

Read

Output Enable Hold Time

0

—

t^OEH

Toggle and Data Polling

10

20

0

CEf High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write (OE to CEf)

Read Recover Time Before Write (OE to WE)

WE Setup Time (CEf to WE)

CEf Setup Time (WE to CEf)

WE Hold Time (CEf to WE)

CEf Hold Time (WE to CEf)

Write Pulse Width

—

tCEPH

tOEPH

tGHEL

tGHWL

tWS

tGHEL

tGHWL

tWLEL

tELWL

tEHWH

tWHEH

tWLWH

tELEH

tWHWL

tEHEL

tWHWH1

tWHWH2

—

0

tCS

0

tWH

0

tCH

0

tWP

35

30

—

50

4

CEf Pulse Width

tCP

Write Pulse Width High

tWPH

tCPH

tWHWH1

tWHWH2

tVCS

tVLHT

tVIDR

tVACCR

tRB

CEf Pulse Width High

Word Programming Operation

Sector Erase Operation *¹

VCCf Setup Time

Voltage Transition Time *²

Rise Time to VID *²

—

µs

ns

µs

—

500

0

Rise Time to VACC

—

Recover Time from RY/BY

RESET Pulse Width

—

tRP

500

—

200

—

50

—

Delay Time from Embedded Output Enable

RESET High Level Period Before Read

Program/Erase Valid to RY/BY Delay

Erase Time-out Time *³

—

tEOE

tRH

—

tBUSY

tTOW

tSPD

—

Erase Suspend Transition Time *⁴

—

*1: This does not include the preprogramming time.

*2: This timing is for Sector group Protection Operation.

*3: The time between writes must be less than “t^TOW” otherwise that command will not be accepted and erasure will

start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the execution

of the Sector Erase command(s).

*4: When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum

of “t^SPD” to suspend the erase operation.

25

MB84VR5E4J4J1^-85

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

555h

PA

Address

CEf

tWC

tRC

tAS

tAH

tCH

tCS

tCEf

OE

tGHWL

tOE

tWHWH1

tWP

tWPH

WE

tOH

tDS

tDH

PD

DOUT

A0h

DQ7

DQ

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

26

MB84VR5E4J4J1^-85

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

Data Polling

Address

PA

555h

tWC

tAH

tAS

WE

tWS

tWH

OE

tGHEL

tWHWH1

tCP

tCPH

CEf

tDS

tDH

PD

D^OUT

DQ7

A0h

DQ

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at byte address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates the last two bus cycles out of four bus cycle sequence.

27

MB84VR5E4J4J1^-85

• AC Waveforms Chip/Sector Erase Operations (Flash)

SA*

2AAh

555h

2AAh

555h

Address

CEf

tWC

tAS

tAH

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

30h for Sector Erase

10h/

30h

AAh

55h

80h

55h

DQ

tVCS

VCCf

*: SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase.

28

MB84VR5E4J4J1^-85

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CEf

tCH

t^DF

tOE

OE

tOEH

WE

tCEf

*

High-Z

DQ⁷=

Valid Data

Data In

DQ⁷

DQ7

tWHWH1 or tWHWH2

DQ⁶to DQ⁰

Valid Data

DQ6 to DQ0 = Output Flag

DQ6 to DQ0

RY/BY

tBUSY

tEOE

*: DQ7 = Valid Data (the device has completed the Embedded operation.)

29

MB84VR5E4J4J1^-85

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

Address

tAHT

tASO

tAHT

tAS

CEf

tCEPH

WE

OE

tOEH

tOEPH

tOE

tCE

tDH

*

Toggle

Data

Toggle

Data

Toggle

Data

Stop

Toggling

Output

Valid

DQ6/DQ2

RY/BY

Data

tBUSY

*: DQ6 stops toggling (the device has completed the Embedded operation).

30

MB84VR5E4J4J1^-85

• Bank-to-Bank Read/Write Timing Diagram (Flash)

Read

t^RC

Command

t^WC

Read

t^RC

Command

t^WC

Read

t^RC

Read

t^RC

BA2

(PA)

BA2

(PA)

Addresses

CEf

BA1

(555h)

t^ACC

t^CE

t^AS

t^AH

t^AHT

t^OE

t^CEPH

OE

WE

DQ

t^DF

t^GHWL

t^OEH

t^WP

t^DH

t^DS

t^DF

Valid

Intput

Valid

Output

Valid

Output

Valid

Output

Status

Intput

(A0h)

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1: Address corresponding to Bank 1.

BA2: Address corresponding to Bank 2.

31

MB84VR5E4J4J1^-85

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

The rising edge of the last write pulse

WE

Entire programming

or erase operations

RY/BY

tBUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

RY/BY

tRP

tRB

tREADY

32

MB84VR5E4J4J1^-85

• Temporary Sector Unprotection (Flash)

VCCf

tVIDR

tVCS

tVLHT

V^ID

3 V

VIH

RESET

CEf

WE

tVLHT

Program or Erase Command Sequence

RY/BY

Unprotection Period

• Acceleration Mode Timing Diagram (Flash)

VCCf

tVACCR

tVCS

tVLHT

V^ACC

V^CCf

WP/ACC

CEf

WE

tVLHT

RY/BY

Acceleration Mode Period

33

MB84VR5E4J4J1^-85

• Extended Sector Group Protection (Flash)

VCCf

tVCS

RESET

tVLHT

tVIDR

tWC

Address

SPAX

SPAY

A6, A3, A2, A0

A¹

CEf

OE

TIME-OUT

tWP

WE

Data

60h

40h

01h

60h

tOE

SPAX: Sector Group Address to be protected

SPAY: Next Group Sector Address to be protected

TIME-OUT: Time-Out window = 250 µs (Min)

34

MB84VR5E4J4J1^-85

• READ Operation (FCRAM_1 or FCRAM_2)

Value

Parameter

Symbol

Unit

Notes

Min

90

—

5

Max

—

Read Cycle Time

t^RC

tCE

ns

Chip Enable Access Time

85

40

85

—

*1,*3

*1

Output Enable Access Time

Chip Enable Access Time

tOE

tAA

*1,*4

*1

Output Data Hold Time

tOH

CE1r_1or CE1r_2 Low to Output Low-Z

OE Low to Output Low-Z

tCLZ

5

—

*2

tOLZ

0

—

*2

CE1r_1or CE1r_2 High to Output High-Z

OE High to Output High-Z

tCHZ

—

–5

40

10

–5

10

—

85

45

–5

0

25

20

—

*2

tOHZ

tASC

*2

Address Setup Time to CE1r_1or CE1r_2 Low

*5

tASO

tASO[ABS]

tBSC

—

*3,*6

*7

Address Setup Time to OE

—

LB / UB Setup Time to CE1r_1or CE1r_2 Low

LB / UB Setup Time to OE Low

—

*5

tBSO

tAX

—

Address Invalid Time

5

ns

*4,*8

*4

Address Hold Time from CE1r_1or CE1r_2 Low

Address Hold Time from OE Low

tCLAH

tOLAH

tCHAH

tOHAH

tCHBH

tOHBH

tCLOL

tOLCH

tCP

—

*4,*9

Address Hold Time from CE1r_1or CE1r_2 High

Address Hold Time from OE High

—

LB / UB Hold Time from CE1r_1or CE1r_2 High

LB / UB Hold Time from OE High

—

0

—

CE1r_1or CE1r_2 Low to OE Low Delay Time

OE Low to CE1r_1or CE1r_2 High Delay Time

CE1r_1or CE1r_2 High Pulse Width

40

45

18

40

18

1000

—

ns *3,*6,*9,*10

ns

*9

—

t^OP

1000

—

*6,*9,*10

*7

OE High Pulse Width

tOP[ABS]

*1 : Output load is 30pF.

*2 : Output load is 5pF.

*3 : t^CEis applicable if OE is brought to Low before CE1r_1 or CE1r_2 goes Low and is also applicable if actual value

of both or either tASO or tCLOL is shorter than specified value.

*4 : Applicable only to A0 and A1 when both CE1r_1 or CE1r_2 and OE are kept at Low for the address access.

*5 : Applicable if OE is brought to Low before CE1r_1 or CE1r_2 goes Low.

*6 : tASO, tCLOL(Min) and tOP(Min) are reference values when the access time is determined by tOE.

If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of

subtracting actual value from specified minimum value.

For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(Min), during OE control

access (i.e., CE1r_1 or CE1r_2 stays Low), the tOE become tOE(Max) + tASO(Min) – tASO(actual).

*7 : tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access.

*8 : t^AXis applicable when both A0 and A1 are switched from previous state.

*9 : If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become

tRC(Min) – tCLOL(actual) or tRC(Min) – tOP(actual).

*10 : Maximum value is applicable if CE1r_1 or CE1r_2 is kept at Low.

35

MB84VR5E4J4J1^-85

• WRITE Operation (FCRAM_1 or FCRAM_2)

Value

Parameter

Symbol

Unit

Notes

Min

90

0

Max

—

Write Cycle Time

t^WC

tAS

ns

*1

*2

Address Setup Time

Address Hold Time

—

t^AH

40

0

—

CE1r_1or CE1r_2 Write Setup Time

CE1r_1or CE1r_2 Write Hold Time

WE Setup Time

tCS

1000

—

tCH

0

tWS

0

WE Hold Time

tWH

0

—

LB and UB Setup Time

LB and UB Hold Time

OE Setup Time

tBS

0

—

tBH

–5

0

—

tOES

t^OEH

tOEH[ABS]

tOHCL

tOHAH

tCW

1000

—

*3

*3, *4

*5

40

18

–3

–5

55

10

15

0

OE Hold Time

OE High to CE1r_1or CE1r_2 Low Setup Time

OE High to Address Hold Time

CE1r_1or CE1r_2 Write Pulse Width

WE Write Pulse Width

—

*6

—

*7

—

*1, *8

*1, *9

*1, *3, *9

tWP

—

CE1r_1or CE1r_2 Write Recovery Time

WE Write Recovery Time

tWRC

tWR

—

1000

—

Data Setup Time

t^DS

Data Hold Time

tDH

—

CE1r_1or CE1r_2 High Pulse Width

tCP

18

—

*9

*1 : Minimum value must be equal or greater then the sum of actual t^CW(or tWP) and tWRC (or tWR).

*2 : New write address is valid from either CE1r_1or CE1r_2 or WE is bought to High.

*3 : t^OEHis specified from end of tWC(Min). The tOEH(Min) is a reference value when the access time is determined

by tOE.If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of

subtracting actual value from specified minimum value.

*4 : t^OEH(Max) is applicable if CE1r_1or CE1r_2 is kept at Low and both WE and OE are kept at High.

*5 : tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r_1or CE1r_2 stays Low.

*6 : t^OHCL(Min) must be satisfied if read operation is not performed prior to write operation.

In case OE is disabled after tOHCL(Min), WE Low must be asserted after tRC(Min) from CE1r_1or CE1r_2 Low.

In other words, read operation is initiated if tOHCL (Min) is not satisfied.

*7 : Applicable if CE1r_1or CE1r_2 stays Low after read operation.

*8 : tCW and tWP is applicable if write operation is initiated by CE1r_1or CE1r_2 and WE, respectively.

*9 : t^WRCand tWR is applicable if write operation is terminated by CE1r_1or CE1r_2 and WE, respectively.

tWR(Min) can be ignored if CE1r_1or CE1r_2 is brought to High together or after WE is brought to High. In such

case, the tCP(Min) must be satisfied.

36

MB84VR5E4J4J1^-85

• Power Down and Power Down Program Parameters (FCRAM_1 or FCRAM_2)

Value

Min

Parameter

Symbol

Unit Note

Max

—

CE2r_1 or CE2r_2 Low Setup Time for Power Down Entry

CE2r_1 or CE2r_2 Low Hold Time after Power Down Entry

t^CSP

10

ns

tC2LP

100

—

CE1r_1or CE1r_2 High Hold Time following CE2r_1 or CE2r_2

High after Power Down Exit[SLEEP mode only]

tCHH

tCHHN

tCHS

350

1

—

µs

ns

CE1r_1or CE1r_2 High Setup Time following CE2r_1 or CE2r_2

High after Power Down Exit[Except for SLEEP mode]

CE1r_1or CE1r_2 High Setup Time following CE2r_1 or CE2r_2

High after Power Down Exit

10

CE1r_1or CE1r_2 High to PE_1 or PE_2 Low Setup Time

PE_1 or PE_2 Power Down Program Pulse Width

PE_1 or PE_2 High to CE1r_1or CE1r_2 Low Hold Time

Address Setup Time to PE_1 or PE_2 High

tEPS

tEP

90

15

0

—

ns

*

tEPH

tEAS

tEAH

Address Setup Time from PE_1 or PE_2 High

*: Applicable to Single Cycle Power Down Program.

• Other Timing Parameters (FCRAM_1 or FCRAM_2)

Parameter

Value

Symbol

Unit Note

Min

Max

CE1r_1or CE1r_2 High to OE Invalid Time for Standby Entry

CE1r_1or CE1r_2 High to WE Invalid Time for Standby Entry

tCHOX

tCHWX

10

—

ns

5

—

ns

*1

CE2r_1 or CE2r_2 Low Hold Time after Power-up

CE2r_1 or CE2r_2 High Hold Time after Power-up

t^C2LH

50

—

µs

*2

*3

tC2HL

CE1r_1or CE1r_2 High Hold Time following CE2r_1 or CE2r_2

High after Power-up

tCHH

350

1

—

µs

*2

*4

Input Transition Time

t^T

25

ns

*1: When the parameter t^CHWXis not satisfied, unintended data may be written into any of the address.

*2: Must satisfy tCHH(Min) after tC2LH(Min).

*3: Requires Power Down mode entry and exit after tC2HL.

*4: The input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5 ns, it may violate

AC specification of some timing parameters.

• AC Test Conditions (FCRAM_1 or FCRAM_2)

Symbol

V^IH

Description

Input High Level

Test Setup

Value

2.3

0.4

1.3

5

Unit

V

Note

VCCr_1or VCCr_2 = 2.7 V to 3.1 V

Between VIL and VIH

VIL

Input Low Level

V

VREF

tT

Input Timing Measurement Level

Input Transition Time

V

ns

37

MB84VR5E4J4J1^-85

• READ Timing #1 (OE Control Access) (FCRAM_1 or FCRAM_2)

tRC

Address

Address Valid

tOHAH

tASO

tCE

tOHAH

CE1r_1 or

CE1r_2

tOLCH

tOE

tOP

tCLOL

tOE

OE

tASO

tBSO

tOHBH

tBSO

tOHBH

LB / UB

tOHZ

tOH

tOHZ

tOH

tOLZ

DQ

(Output)

Valid Data Output

Note : CE2r_1 or CE2r_2, PE_1 or PE_2 and WE must be High during the entire read cycle.

Either or both LB and UB must be Low when both CE1r_1 or CE1r_2 and OE are Low.

38

MB84VR5E4J4J1^-85

• READ Timing #2 (CE1r_1 or CE1r_2 Control Access) (FCRAM_1 or FCRAM_2)

tRC

Address

Address Valid

tCHAH

tASC

tCE

tCHAH

tASC

tCE

CE1r_1 or

CE1r_2

tCP

OE

tBSC

tCHBH

tBSC

tCHBH

LB / UB

tCHZ

tOH

tCHZ

tOH

tCLZ

DQ

(Output)

Valid Data Output

Note : CE2r_1 or CE2r_2, PE_1 or PE_2 and WE must be High during the entire read cycle.

Either or both LB and UB must be Low when both CE1r_1 or CE1r_2 and OE are Low.

39

MB84VR5E4J4J1^-85

• READ Timing #3 (Address Access after OE Control Access) (FCRAM_1 or FCRAM_2)

tRC

Address

(A20-A2)

Address Valid

Address Valid (No change)

Address

(A1, A0)

Address Valid

tOHAH

tASO

tOLAH

tAA

tAX

CE1r_1 or

CE1r_2

tOE

tOHZ

OE

tBSO

tOHBH

tOH

LB / UB

tOLZ

tOH

DQ

(Output)

Valid Data Output

Note : CE2r_1 or CE2r_2, PE_1 or PE_2 and WE must be High during the entire read cycle.

Either or both LB and UB must be Low when both CE1r_1 or CE1r_2 and OE are Low.

40

MB84VR5E4J4J1^-85

• READ Timing #4 (Address Access after CE1r_1 or CE1r_2 Control Access) (FCRAM_1 or FCRAM_2)

tRC

Address

(A20-A2)

Address Valid

Address Valid (No change)

Address

(A1, A0)

Address Valid

tASC

tCHAH

tCLAH

tAA

tAX

CE1r_1 or

CE1r_2

tCE

tCHZ

OE

tBSC

tCHBH

tOH

LB / UB

tOH

tCLZ

DQ

(Output)

Valid Data Output

Note : CE2r_1 or CE2r_2, PE_1 or PE_2 and WE must be High during the entire read cycle.

Either or both LB and UB must be Low when both CE1r_1 or CE1r_2 and OE are Low.

41

MB84VR5E4J4J1^-85

• WRITE Timing #1 (CE1r_1 or CE1r_2 Control) (FCRAM_1 or FCRAM_2)

tWC

Address

Address Valid

tAS

tAH

tAS

CE1r_1 or

CE1r_2

tCW

tWRC

tWS

tWH

tBH

tWS

WE

tBS

UB, LB

tOHCL

OE

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r_1 or CE2r_2 and PE_1 or PE_2 must be High during the entire write cycle.

42

MB84VR5E4J4J1^-85

• WRITE Timing #2-1 (WE Control, Single Write Operation) (FCRAM_1 or FCRAM_2)

tWC

Address

Address Valid

tOHAH

tAS

tCS

tAH

tAS

tCH

CE1r_1 or

CE1r_2

tCP

tOHCL

tWP

tWR

WE

UB, LB

OE

tOHBH

tBS

tBH

tOES

tOHZ

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r_1 or CE2r_2 and PE_1 or PE_2 must be High during the entire write cycle.

43

MB84VR5E4J4J1^-85

• WRITE Timing #2-2 (WE Control, Continuous Write Operation) (FCRAM_1 or FCRAM_2)

tWC

Address

Address Valid

tOHAH

tAS

tAH

tAS

CE1r_1 or

CE1r_2

tOHCL

tCS

tWP

tWR

WE

UB, LB

OE

tOHBH

tBS

tBH

tBS

tOES

tOHZ

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r_1 or CE2r_2 and PE_1 or PE_2 must be High during the entire write cycle.

44

MB84VR5E4J4J1^-85

• READ / WRITE Timing #1-1 (CE1r_1 or CE1r_2 Control) (FCRAM_1 or FCRAM_2)

tWC

Address

WRITE Address

READ Address

tCHAH

tAS

tAH

tASC

tWS

CE1r_1 or

CE1r_2

tCP

tWRC

tWH

tCW

tWH

t^WS

tCLOL

tBSO

WE

UB, LB

OE

tCHBH

tBS

tBH

tOHCL

tCHZ

tDH

tOH

tDS

tOLZ

DQ

READ Data Output

WRITE Data Input

Note : Write address is valid from either CE1r_1 or CE1r_2 or WE of the last falling edge.

45

MB84VR5E4J4J1^-85

• READ / WRITE Timing #1-2 (CE1r_1 or CE1r_2 Control) (FCRAM_1 or FCRAM_2)

tRC

Address

READ Address

WRITE Address

tASC

tCHAH

tAS

tWRC

CE1r_1 or

CE1r_2

tWRC(Min)

tWH

tCP

tWS

tCE

tWH

tWS

WE

UB, LB

OE

tBH

tBSC

tCHBH

tBS

tOEH

tOHCL

tCHZ

tDH

tCLZ

tOH

DQ

WRITE Data Input

READ Data Output

Note : The tOEH is specified from the time satisfied both tWRC and tWR(Min).

46

MB84VR5E4J4J1^-85

• READ(OE Control) / WRITE(WE Control) Timing #2-1 (FCRAM_1 or FCRAM_2)

tWC

Address

READ Address

WRITE Address

tOHAH

tAS

tAH

tASO

CE1r_1 or

CE1r_2

Low

tWP

tWR

WE

UB, LB

OE

tBS

tBH

tOES

tOHZ

tOEH

tOLZ

tOH

tDS

tDH

DQ

READ Data Output

WRITE Data Input

Note : CE1r_1 or CE1r_2 can be tied to Low for WE and OE controlled operation.

When CE1r_1 or CE1r_2 is tied to Low, output is exclusively controlled by OE.

47

MB84VR5E4J4J1^-85

• READ(OE Control) / WRITE(WE Control) Timing #2-2 (FCRAM_1 or FCRAM_2)

tRC

Address

READ Address Valid

WRITE Address

tOHAH

tAS

tASO

CE1r_1 or

CE1r_2

Low

tWR

tBH

tOEH

WE

UB, LB

OE

tBSO

tOHBH

tBS

tOE

tOES

tOHZ

tOH

tDH

tOLZ

DQ

WRITE Data Input

READ Data Output

Note : CE1r_1 or CE1r_2 can be tied to Low for WE and OE controlled operation.

When CE1r_1 or CE1r_2 is tied to Low, output is exclusively controlled by OE.

48

MB84VR5E4J4J1^-85

• SINGLE CYCLE POWER DOWN PROGRAM Timing (FCRAM_1 or FCRAM_2)

CE1r_1 or

CE1r_2

tEPS

tEP

tEPH

PE_1 or

PE_2

tEAH

tEAS

Address

(A20-A16)

KEY

Note : CE2r_1 or CE2r_2 must be High for Single Cycle Power Down Programming.

Any other inputs not specified above can be either High or Low.

• MULTIPLE CYCLE POWER DOWN PROGRAM Timing (FCRAM_1 or FCRAM_2)

tRC

tCP

tRC

tCP

tRC

tCP

tRC

tCP

tRC

KEY ^*3

KEY

Valid Address

tCE

Address

tBSC

tCHBH

CE1r_1 or

CE1r_2^*1

tBSO

tOHBH

tOE

OE

LB / UB

tOLZ

tCLZ

DQ

(Output)

No Read Standby No Read Standby No Read Standby No Read Standby

Entry Cycle #1 ^*2

Entry Cycle #2 Entry Cycle #3 Entry Cycle #4

Read ^*4

*1: CE2r_1 or CE2r_2, PE_1 or PE_2 and WE must be High for Multiple Cycle Power Down Programming.

Any other inputs not specified above can be either High or Low.

*2: Each No Read timing must comply with normal Read timings except that CE1r_1 or CE1r_2 must be

brought to High after one No Read cycle.

*3: The Key input of all four entry cycles must be the sole Key input.

*4: Programming will be finished after the standby cycle of 4th entry cycle and both Read or Write operation

can be performed after t^CP(Min) of 4th entry cycle.

49

MB84VR5E4J4J1^-85

• POWER DOWN Entry and Exit Timing (FCRAM_1 or FCRAM_2)

CE1r_1 or

CE1r_2

tCHS

CE2r_1 or

CE2r_2

tCSP

tC2LP

tCHH (tCHHN)

High-Z

DQ

Power Down Entry

Power Down Mode

Power Down Exit

Note : This Power Down mode can be also used for Power-up #2 below except that tCHHN can not be used

at Power-up timing.

• POWER-UP Timing #1 (FCRAM_1 or FCRAM_2)

CE1r_1 or

CE1r_2

tCHS

tC2LH

tCHH

CE2r_1 or

CE2r_2

VCCr_1 or

VCCr_2

VCCr_1 Min or

VCCr_2 Min

0 V

Note : The t^C2LHspecifies after VCCr_1 or VCCr_2 reaches specified minimum level.

• POWER-UP Timing #2 (FCRAM_1 or FCRAM_2)

CE1r_1 or

CE1r_2

tCHS

tCSP

tC2HL

tC2LP

tCHH

CE2r_1 or

CE2r_2

tC2HL

V^CCr_1 or

VCCr_2

V^CCr_1 Min or

VCCr_2 Min

0 V

Note : The t^C2HLspecifies from CE2r_1 or CE2r_2 Low to High transition after VCCr_1 or VCCr_2 reaches

specified minimum level.

CE1r_1 or CE1r_2 must be brought to High prior to or together with CE2r_1 or CE2r_2 Low to High

transition.

50

MB84VR5E4J4J1^-85

• Standby Entry Timing after Read or Write (FCRAM_1 or FCRAM_2)

CE1r_1 or

CE1r_2

tCHOX

tCHWX

OE

WE

Active (Read)

Standby

Active (Write)

Standby

Note : Both t^CHOXand tCHWX define the earliest entry timing for Standby mode. If either of timing is not

satisfied, it takes tRC (Min) period from either last address transition of A0 and A1, or CE1r_1 or

CE1r_2 Low to High transition.

51

MB84VR5E4J4J1^-85

■ ERASE AND PROGRAMMING PERFORMANCE (Flash)

Value

Parameter

Unit

Remarks

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

—

1

10

s

Excludes system-level over-

head

Byte Programming Time

Word Programming Time

—

8

300

360

µs

Excludes system-level over-

head

16

Excludes system-level over-

head

Chip Programming Time

Erase/Program Cycle

—

200

—

s

100,000

cycle

52

MB84VR5E4J4J1^-85

■ DATA RETENTION Low VCCr_1 or VCCr_2 Characteristics (FCRAM_1 or FCRAM_2)

Value

Parameter

Symbol

Test Conditions

Unit

Min

Max

CE1r_1 = CE2r_1 ≥ VCCr_1 – 0.2 V or,

CE1r_1 = CE2r_1 = VIH,

CE1r_2 = CE2r_2 ≥ VCCr_2 – 0.2 V or,

CE1r_2 = CE2r_2 = VIH,

V^CCr_1 or VCCr_2 Data Retention

Supply Voltage

VDR

2.3

3.1

V

2.3 V ≤ VCCr_1 ≤ 2.7 V or

2.3 V ≤ VCCr_2 ≤ 2.7 V,

I^DR

CE1r_1 = CE2r_1 = VIH *or

CE1r_2 = CE2r_2 = VIH *,

VIN = VIH * or VIL, IOUT=0 mA

—

1.5

mA

V^CCr_1 or VCCr_2 Data Retention

Supply Current

2.3 V ≤ VCCr_1 ≤ 2.7 V or

2.3 V ≤ VCCr_2 ≤ 2.7 V,

CE1r_1 = CE2r_1 ≥ VCCr_1 – 0.2 V or

CE1r_2 = CE2r_2 ≥ VCCr_2 – 0.2 V

VIN ≤ 0.2 V or VIN ≥ VCCr_2 – 0.2 V or

VIN ≤ 0.2 V or VIN ≥ VCCr_1 – 0.2 V,

IOUT=0 mA

I^DR1

—

0

100

—

µA

2.7 V ≤ VCCr_1 ≤ 3.1 V or

2.7 V ≤ VCCr_2 ≤ 3.1 V

at data retention entry

Data Retention Setup Time

t^DRS

ns

2.7 V ≤ VCCr_1 ≤ 3.1 V or

2.7 V ≤ VCCr_2 ≤ 3.1 V

after data retention

Data Retention Recovery Time

t^DRR

90

—

ns

V^CCr_1 or VCCr_2 Voltage Transi-

tion Time

∆V/∆t

—

0.5

V/µs

* : 2.0 ≤ VIH ≤ VCCr_1 + 0.3 V or VCCr_2 + 0.3 V

53

MB84VR5E4J4J1^-85

• Data Retention Timing

tDRS

tDRR

3.1 V

∆V/∆t

VCCr_1 or VCCr_2

2.7 V

CE2r_1 or CE2r_2

2.3 V

>VCCr_1 - 0.2 V

or VCCr_2 - 0.2 V

or VIH* Min

CE1r_1 or CE1r_2

0.4 V

VSS

Data Retention Mode

Data bus must be in High-Z at data retention entry.

* : 2.0 V ≤ V^IH≤ VCCr_1

■ PIN CAPACITANCE

Value

Typ

Parameter

Symbol

Condition

Unit

Min

Max

18.0

20.0

Input Capacitance

C^IN

C^OUT

C^IN2

CIN3

VIN = 0

pF

Output Capacitance

VOUT = 0

VIN = 0

Control Pin Capacitance

WP/ACC Pin Capacitance

Note: Test conditions TA = 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of package are created with acute angles.

■ CAUTION

• The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when use

autoselect and sector protect function are used. Then the high voltage (VID) can be applied to RESET.

• Without the high voltage (V^ID), sector protection can be achieved by using “Extended sector protect” command.

54

MB84VR5E4J4J1^-85

■ ORDERING INFORMATION

1

-85

MB84VR5E4J4J

-PBS

PACKAGE TYPE

PBS = 85-ball BGA

SPEED OPTION

Device Revision

DEVICE NUMBER/DESCRIPTON

64 Mega-bit (4M x 16bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

32 Mega-bit (2M x 16bit) FCRAM

55

MB84VR5E4J4J1^-85

■ PACKAGE DIMENSION

85-ball plastic FBGA

(BGA-85P-M02)

+0.10

85-ø0.40 ^–0.05

+.004

85-ø.016

–.002

M

0.08(.003)

S AB

10.80±0.10(.425±.004)

0.20(.008)

S

A

B

+0.20

1.10 ^–0.10

0.4(.016)

REF

0.8(.031)

REF

(SEATED HEIGHT)

.043 –⁺.^.0⁰0⁰4⁸

12

11

10

9

0.8(.031)

REF

8

A

7

10.40±0.10

(.409±.004)

6

5

0.4(.016)

REF

4

3

2

0.10(.004)

S

1

M

L K J H G F E D C B A

0.10±0.05

(.004±.002)

(STAND OFF)

INDEX-MARK AREA

INDEX BALL

0.20(.008)

S

A

S

0.10(.004)

S

C

2001 FUJITSU LIMITED B85002S-c-1-1

Dimensions in mm (inches)

56

MB84VR5E4J4J1^-85

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Marketing Division

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Electronic Devices

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3353

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

Fax: +81-3-5322-3386

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

Fax: +1-408-922-9179

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

http://www.fme.fujitsu.com/

Asia Pacific

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

http://www.fmal.fujitsu.com/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0112

FUJITSU LIMITED Printed in Japan


型号：	MB84VR5E4J4J1-85-PBS
厂家：	FUJITSU
描述：	Memory Circuit, Flash+SRAM, 4MX16, CMOS, PBGA85, PLASTIC, FBGA-85 静态存储器内存集成电路
文件：	总57页 (文件大小：1096K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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