MB84VZ128C-70PBS_技术文档

TM

SPANSION MCP

Data Sheet

September 2003

This document specifies SPANSION^TMmemory products that are now offered by both Advanced Micro Devices and

Fujitsu. Although the document is marked with the name of the company that originally developed the specification,

these products will be offered to customers of both AMD and Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a SPANSION^TMproduct. Future routine

revisions will occur when appropriate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about SPANSION^TMmemory

solutions.

FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-50226-1E

4Stacked MCP (Multi-Chip Package) FLASH & FLASH & FCRAM & SRAM

CMOS

128M (×16) Page Mode FLASH MEMORY &

64M (×16) FLASH MEMORY &

64M (×16) Mobile FCRAM^TM&

8M (×16) STATIC RAM

MB84VZ128B/C-70

■ FEATURES

• Power Supply Voltage of 2.7 V to 3.1 V

• High Performance

20 ns maximum Page read access time, 70 ns maximum random access time (Flash_1)

70 ns maximum access time (Flash_2)

65 ns maximum access time (FCRAM)

70 ns maximum access time (SRAM)

(Continued)

■ PRODUCT LINEUP

Flash_1

Flash_2

FCRAM

SRAM

+0.1 V

–0.3 V

+0.1 V

–0.3 V

+0.1 V

–0.3 V

+0.1V

–0.3 V

Supply Voltage (V)

VCCf_1* = 3.0 V

VCCf_2* = 3.0 V

VCCr* = 3.0 V

VCCs* = 3.0 V

Max Random Address

Access Time (ns)

70

20

70

65

70

Max Page Address

Access Time (ns)

Max CE Access Time (ns)

Max OE Access Time (ns)

70

25

70

30

65

40

70

35

* : All of VCCf_1, VCCf_2, VCCr and VCCs must be the same level when either part is being accessed.

■ PACKAGE

115-ball plastic FBGA

(BGA-115P-M03)

MB84VZ128B/C-70

(Continued)

• Operating Temperature

–30 °C to +85 °C

• Package 115-ball FBGA

— FLASH MEMORY_1

• 0.13 µm Process Technology

• Dual Chip Enable (CE0f, CE1f)

CE0fcontrols64Mbits(BankAandBankB)regionandCE1fcontrols64Mbits(BankCandBankD)bitsregion.

• Single 3.0 V Read, Program and Erase

Minimized system level power requirements

• Simultaneous Read/Write Operations (Dual Bank)

1

• FlexBank^TM

*

Bank A(CE0f): 16M bit (4 KW × 8 and 32 KW ×31)

Bank B(CE0f): 48M bit (32 KW × 96)

Bank C(CE1f): 48M bit (32 KW × 96)

Bank D(CE1f): 16M bit (4 KW × 8 and 32 KW ×31)

• High Performance Page Mode

20 ns maximum page access time (70 ns random access time)

• 8 words Page Access Capability

• Minimum 100,000 Program/Erase Cycles

• Sector Erase Architecture

Eight 4K words, two hundred fifty-four 32K words, eight 8K words sectors.

Any combination of sectors can be concurrently erased. Also supports full chip erase

• Dual Boot Block

Sixteen 4K words boot block sectors, eight at the top of the address range and eight at the bottom of the

address range

• WP/ACC Input Pin

At V^IL, allows protection of “outermost” 2 × 4K words on both ends of boot sectors, regardless of sector

protection/unprotection status

At V^IH, allows removal of boot sector protection

At VACC, increases program performance

• Embedded Erase^TM*²Algorithms

Automatically preprograms and erases the chip or any sector

• Embedded Program^TM*²Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready/Busy Output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, the device automatically switches itself to low power mode

• Low V^CCWrite Inhibit ≤ 2.5 V

• Program Suspend/Resume

Suspends the program operation to allow a read in another byte

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Hardware Reset Pin (RESET)

Hardware method to reset the device for reading array data

(Continued)

2

MB84VZ128B/C-70

(Continued)

• New Sector Protection

Persistent Sector Protection

Password Sector Protection

— FLASH MEMORY_2

• Simultaneous Read/Write Operations (Dual Bank)

1

• FlexBank^TM

*

Bank A : 8M bit (8 KB × 8 and 64 KB × 15)

Bank B : 24M bit (64 KB × 48)

Bank C : 24M bit (64 KB × 48)

Bank D : 8M bit (8 KB × 8 and 64 KB × 15)

Two virtual Banks are chosen from the combination of four physical banks.

Host system can program or erase in one bank, and then read immediately and simultaneously from the other

bank with zero latency between read and write operations.

Read-while-erase

Read-while-program

• Minimum 100,000 Program/Erase Cycles

• Sector Erase Architecture

Sixteen 4K word and one hundred twenty-six 32K word sectors in word.

Any combination of sectors can be concurrently erased. It also supports full chip erase.

• HiddenROM Region

256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC Input Pin

AtV^IL, allowsprotectionof“outermost”2× 8Kbytesonbothendsofbootsectors, regardlessofsectorprotection/

unprotection status

At V^IH, allows removal of boot sector protection

At VACC, increases program performance

• Embedded Erase^TM*²Algorithms

Automatically preprograms and erases the chip or any sector

• Embedded Program^TM*²Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion

• Ready/Busy Output (RY/BY_2)

Hardware method for detection of program or erase cycle completion

• Automatic Sleep Mode

When addresses remain stable, the device automatically switches itself to low power mode.

• Low V^CCf write Inhibit ≤ 2.5 V

• Program Suspend/Resume

Suspends the program operation to allow a read in another byte

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Please Refer to “MBM29DL64DF” Datasheet in Detailed Function.

(Continued)

3

MB84VZ128B/C-70

(Continued)

3

— FCRAM^TM

*

• Power Dissipation

Operating : 25 mA Max

Standby

: 200 µA Max

• Power Down Mode

Sleep

NAP

: 10 µA Max

: 65 µA Max

16M Partial : 85 µA Max

• Power Down Control by CE2r

• Byte Write Control: LB(DQ⁷to DQ⁰), UB(DQ¹⁵to DQ⁸)

• 8 words Address Access Capability

— SRAM

• Power Dissipation

Operating: 50 mA Max

Standby : 15 µA Max

• Power Down Features using CE1s and CE2s

• Data Retention Supply Voltage: 1.5 V to 3.1 V

• CE1s and CE2s Chip Select

• Byte Data Control: LB (DQ⁷to DQ⁰), UB (DQ¹⁵to DQ⁸)

*1: FlexBank^TMis a trademark of Fujitsu Limited, Japan.

*2: Embedded Erase^TMand Embedded Program^TMare trademarks of Advanced Micro Devices, Inc.

*3: Mobile FCRAM^TMis a trademark of Fujitsu Limited, Japan.

4

MB84VZ128B/C-70

■ PIN ASSIGNMENT

(Top View)

Marking Side

A10

B10

C10

N.C.

D10

N.C.

E10

F10

G10

N.C.

H10

N.C.

J10

K10

L10

M10

N.C.

N10

N.C.

P10

N.C.

A9

B9

C9

D9

E9

F9

G9

H9

J9

K9

L9

M9

N9

P9

N.C.

A15

A21

N.C.

A16

N.C.

VSS

N.C.

C8

D8

A11

D7

A8

E8

A12

E7

F8

A13

F7

G8

A14

G7

H8

PE

J8

DQ15

J7

K8

DQ7

K7

L8

DQ14

L7

M8

N.C.

M7

N.C.

C7

H7

N.C.

C6

A19

E6

A9

A10

G6

DQ6

H6

DQ13

J6

DQ12

K6

DQ5

L6

N.C.

M6

D6

WE

D5

F6

N.C.

C5

CE2r

E5

A20

F5

CEf1_1

G5

CE2s

H5

DQ4

J5

VCCr

K5

N.C.

L5

N.C.

M5

CEf_2 WP/ACC RESET_1 RY/BY_1

CE1s

G4

VCCs

H4

DQ3

J4

VCCf_1

K4

DQ11

L4

VCCf_2

M4

C4

RY/BY_2

C3

D4

LB

E4

UB

E3

F4

A18

F3

A17

G3

DQ1

H3

DQ9

J3

DQ10

K3

DQ2

L3

VSS

D3

M3

VSS

A7

A6

A5

A4

VSS

H2

OE

DQ0

K2

DQ8

L2

RESET_2

M2

A2

B2

C2

D2

E2

F2

G2

J2

N2

N.C.

N1

P2

N.C.

P1

CEf0_1

N.C.

A1

N.C.

B1

N.C.

D1

A3

A2

A1

A0

N.C.

L1

N.C.

M1

CE1r

K1

E1

F1

G1

H1

J1

N.C.

(BGA-115P-M03)

5

MB84VZ128B/C-70

■ PIN DESCRIPTION

Input/

Pin name

Description

Output

A¹⁸to A0

A²¹to A19

DQ15 to DQ0

CE0f_1

CE1f_1

CEf_2

CE1r

I

Address Inputs (Common)

I

Address Inputs (FCRAM & Flash_1& Flash_2 )

Data Inputs/Outputs (Common)

Chip Enable (Flash_1)

I/O

I

Chip Enable (Flash_1)

I

Chip Enable (Flash_2)

I

Chip Enable (FCRAM)

CE1s

I

Chip Enable (SRAM)

CE2r

I

Chip Enable (FCRAM)

CE2s

I

Chip Enable (SRAM)

OE

I

Output Enable (Common)

WE

I

Write Enable (Common)

RY/BY_1

RY/BY_2

UB

O

Ready/Busy Output (Flash_1) Open Drain Output

Ready/Busy Output (Flash_2) Open Drain Output

Upper Byte Control (FCRAM & SRAM)

Lower Byte Control (FCRAM & SRAM)

Hardware Reset Pin/Sector Protection Unlock (Flash_1)

Hardware Reset Pin/Sector Protection Unlock (Flash_2)

Write Protect / Acceleration (Flash_1& Flash_2)

Partial Enable (FCRAM)

O

I

LB

I

RESET_1

RESET_2

WP/ACC

PE

I

N.C.

—

No Internal Connection

VSS

Power

Device Ground (Common)

V^CCf_1

V^CCf_2

VCCr

Device Power Supply (Flash_1)

Device Power Supply (Flash_2)

Device Power Supply (FCRAM)

Device Power Supply (SRAM)

VCCs

6

MB84VZ128B/C-70

■ BLOCK DIAGRAM

V^CCf_1

V^SS

A²¹to A⁰

RY/BY_1

128M bit

Page Mode

Flash Memory_1

RESET_1

CE0f_1

CE1f_1

V^CCf_2

V^SS

A²¹to A⁰

RY/BY_2

64M bit

Flash Memory_2

WP/ACC

RESET_2

CEf_2

DQ¹⁵to DQ⁰

V^CCr

V^SS

A²¹to A⁰

64M bit

FCRAM

LB

UB

WE

OE

CE1r

CE2r

PE

V^CCs

V^SS

A¹⁸to A⁰

8M bit

SRAM

CE1s

CE2s

7

MB84VZ128B/C-70

■ DEVICE BUS OPERATIONS

Operation*^1,*²

H

X

H

X

L

X

L

Full Standby

H

L

H

L

H

L

H

L

H

X

H

X

H

X

H

X

High-Z High-Z

H

X

X*¹⁰

H

X

H

X

H

X

H

L

H

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

H

X

L

X

L

X

L

X

L

X

L

X

L

X

L

X

L

X

L

X

L

Output Disable*³

H

X

H

L

H

X

H

L

H

L

H

L

H

L

X

H

Valid DOUT

Valid D^OUT

Valid DOUT

DOUT

DIN

H

X

Read from Flash_1 *⁴

Read from Flash_2 *⁴

Write to Flash _1

H

L

H

L

H

L

H

L

Valid

DIN

D^IN

DIN

H

L

DIN

Write to Flash_2

H

L

X

L

X

L

DIN

Read from FCRAM *⁵

H

Valid DOUT

D^IN

DOUT

DIN

9

*

L

H

L

H

X

L

X

L

H

Valid High-Z D^IN

DIN High-Z

H

L

Write to FCRAM

H

L

H

L

H

X

L

D^IN

DIN

H

L

Valid High-Z DIN

DIN High-Z

H

L

D^OUT

DOUT

Read from SRAM

Write to SRAM

H

L

H

L

H

L

Valid High-Z DOUT

DOUT High-Z

H

X

H

L

D^IN

DIN

L

H

L

Valid High-Z DIN

DIN High-Z

H

(Continued)

8

MB84VZ128B/C-70

(Continued)

Operation*^1,*²

Flash_1 Temporary Sector

Group Unprotection *⁶

X

VID

X

Flash_ 2 Temporary Sector

Group Unprotection *⁶

X

VID

H

X

H

X

L

X

L

High- High-

Flash_1 Hardware Reset

Flash_2 Hardware Reset

X

H

X

L

X

Z

High- High-

X

H

X

H

X

H

X

H

X

H

X

L

X

H

L

X

H

X

L

Z

Flash_1 or 2 Boot Block

Sector Write Protection

X

H

X

H

X

L

KEY High- High-

FCRAM Power Down

Program

X

11

Z

*

X

L

High- High-

FCRAM NO READ *⁷

H

X

H

X

H

X

L

H

L

H

X

H

X

H

X

H

X

Valid

X

H

X

H

X

Z

FCRAM Power Down *⁸

X

Legend: L = VIL, H = VIH, X = VIL or VIH. See “■ DC CHARCTERISTICS for voltage levels”.

*1 : Other operations except for indicated this column are inhibited.

*2 : Do not apply for two or more states of the following conditions at the same time;

• CE0f_1 = VIL

• CE1f_1 = VIL

• CEf_2 = VIL

• CE1r = VIL and CE2r = VIH

• CE1s = VIL and CE2s = VIH

*3 : FCRAM Output Disable condition should not be kept longer than 1µs.

*4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.

*5 : FCRAM LB, UB control at Read operation is not supported.

*6 : It is also used for the extended sector group protections.

*7 : The FCRAM Power Down Program can be performed one time after compliance of Power-UP timings and it

should not be re-programmed after regular Read or Write.

*8 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state.

I^PDr current and data retention depends on the selection of Power Down Program.

*9 : Either or both LB and UB must be Low for FCRAM Read Operation.

*10 : Can be either V^ILor VIH but must be valid before Read or Write.

*11 : See “FCRAM Power Down Program Key Table” in “■ 64 M FCRAM for MCP”.

*12 : Protect “outer most” 2 × 8K bytes ( 4 words ) on both ends of the boot block sectors.

9

MB84VZ128B/C-70

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Unit

Min

–55

–30

Max

+125

Storage Temperature

Tstg

T^A

°C

V

Ambient Temperature with Power Applied

+85

VCCf_1 +0.3

V^CCf_2 +0.3

V^CCr +0.3

VCCs +0.3

V

Voltage with Respect to Ground All pins

except RESET_1 or RESET_2,WP/ACC *¹

VIN, VOUT

–0.3

V

VCCf_1,VCCf_2,

VCCr, VCCs

V^CCf_1/VCCf_2/VCCr/VCCs Supply *¹

–0.3

+3.3

V

RESET_1 or RESET_2 *²

WP/ACC *³

VIN

–0.5

+ 13.0

+10.5

V

*1 : Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot

VSS to –1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf_1 + 0.3 V or

VCCf_2 + 0.3 V or VCCr + 0.3 V or VCCs + 0.3 V. During voltage transitions, input or I/O pins may overshoot to

VCCf_1 + 2.0 V or VCCf_2 + 2.0 V or VCCr + 1.0 V or VCCs + 2.0 V for periods of up to 20 ns.

*2 : Minimum DC input voltage on RESET_1 or RESET_2 pin is –0.5 V. During voltage transitions RESET_1 or

RESET_2 pins may undershoot VSS to –2.0 V for periods of up to 20 ns.

Voltage difference between input and supply voltage (VIN-VCCf_1 or VCCf_2) does not exceed +9.0 V.

Maximum DC input voltage on RESET_1 or RESET_2 pins is +13.0 V which may overshoot to +14.0 V for

periods of up to 20 ns.

*3 : Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot

Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may

overshoot to +12.0 V for periods of up to 20 ns, when VCCf_1 or VCCf_2 is applied.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Value

Parameter

Symbol

Unit

Min

Max

Ambient Temperature

T^A

–25

+85

°C

V

VCCf_1/VCCf_2/VCCr/VCCs Supply

Voltages

VCCf_1,VCCf_2,VCCr,VCCs

+2.7

+3.1

Note: Operating ranges define those limits between which the functionality of the device is guaranteed.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

10

MB84VZ128B/C-70

■ DC CHARACTERISTICS

Value

Unit

Sym-

bol

Parameter

Conditions

Min

–1.0

Typ Max

Input Leakage Current

Output Leakage Current

I^LI

VIN = VSS to VCCf_1,VCCr, VCCs

VOUT = VSS to VCCf_1,VCCr, VCCs

—

+1.0

µA

ILO

RESET Inputs Leakage

Current

(Flash_1 & Flash_2)

VCCf = VCCf Max,

RESET = 12.5 V

I^LIT

—

35

µA

WP/ACC Acceleration

Program Current

(Flash_1 & Flash_2)

VCCf = VCCf Max,

WP/ACC = VACC Max

IACC

—

20

45

mA

CE (CE0f or CE1f) = VIL,

OEf= VIH

f = 10 MHz

f = 5 MHz

Flash_1 V^CCActive Current

(Read) *¹

ICC1f1

CE (CE0f or CE1f) = VIL,

OEf= VIH

—

25

mA

Flash_1 VCC Active Current *²

Flash_1 V^CCCurrent (Standby)

ICC2f1 CE (CE0f or CE1f) = VIL, OEf= VIH

VCCf = VCCf Max,

CE0f, CE1f = VCCf ± 0.3 V

ISB1f1

—

1

5

µA

RESET= VCCf ± 0.3 V,

WP/ACC = VCCf ± 0.3 V

VCCf = VCCf Max,

ISB2f1

Flash_1 V^CCCurrent (Standby,Reset)

RESET= VSS ± 0.3 V,

VCCf = VCCf Max,

Flash_1 VCC Current

CE0f, CE1f= VSS ± 0.3 V,

ISB3f1

(Automatic Sleep Mode)*³

RESET= VCCf ± 0.3 V,

VIN = VCCf ± 0.3 V or VSSf ± 0.3 V

Flash_1 VCC Active Current

(Read-while-Program)*⁵

ICC3f1 CE (CE0f or CE1f) = VIL, OEf = VIH

—

45

25

mA

Flash_1 V^CCActive Current

(Read-while-Erase)*⁵

ICC4f1 CE (CE0f or CE1f) = VIL, OEf = VIH

ICC5f1 CE (CE0f or CE1f) = VIL, OEf = VIH

Flash_1 V^CCActive Current

(Erase-Suspend-Program)

tCYCLE =5 MHz

—

18

4

mA

Flash_2 V^CCActive Current

(Read) *¹

CEf = VIL,

OE = VIH

ICC1f2

t^CYCLE=1 MHz

Flash_2 V^CCActive Current

(Program/Erase) *²

ICC2f2

ICC3f2

ICC4f2

ICC5f2

CEf = VIL, OE = VIH

—

30

48

30

mA

Flash_2 V^CCActive Current

(Read-While-Program) *⁵

Flash_2 VCC Active Current

(Read-While-Erase) *⁵

Flash_2 VCC Active Current

(Erase-Suspend-Program)

VCCf = VCCf Max, CEf = VCCf ± 0.3 V

RESET = VCCf ± 0.3 V,

WP/ACC = VCCf ± 0.3 V

Flash_2 V^CCStandby Current

ISB1f

ISB2f

—

1 *⁷

5 *⁷

µA

Flash_2 VCC Standby Current

(RESET)

VCCf = VCCf Max, RESET = VSS ± 0.3 V,

(Continued)

11

MB84VZ128B/C-70

(Continued)

Value

Typ

Sym-

Parameter

bol

Conditions

Unit

Min

Max

V^CCf = VCCf Max, CEf = VSS ± 0.3 V

RESET = VCCf ± 0.3 V,

VIN = VCCf ± 0.3 V or VSS ± 0.3 V

Flash_2 V^CCCurrent (Automatic

Sleep Mode) *³

ISB3f

—

1 *⁷

5 *⁷

µA

VCCr = VCCr Max,

tRC / tWC =Min

—

25

3

FCRAM VCC Active Current

SRAM VCC Active Current

ICC1r

ICC1s

ICC2s

CE1r = VIL, CE2r = VIH,

VIN = VIH or VIL, IOUT = 0 mA

mA

t^RC/ tWC =1 µs

VCCs = VCCs Max,

CE1s = VIL, CE2s = VIH

tCYCLE =10 MHz

—

50

tCYCLE =10 MHz

—

50

10

mA

CE1s = 0.2 V,

CE2s = V^CCs – 0.2 V

t^CYCLE=1 MHz

VCCr = VCCr Max,CE1r > VCCr – 0.2 V,

CE2r > VCCr– 0.2 V,

VIN < 0.2 V or VCCr – 0.2 V

FCRAM V^CCStandby Current

ISB1r

—

200

µA

I^PDSr

IPDNr

I^PD8r

Sleep

NAP

—

10

65

85

µA

V^CCr = VCCr Max,

FCRAM V^CCPower Down

Current

CE1r > VCCr – 0.2 V,

CE2r < 0.2 V,

VIN Cycle time = tRC Min

16M Partial

SRAM V^CCStandby

Current

I^SB1s

CE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V

—

15

µA

V

SRAM V^CCStandby

Current

I^SB2s CE2s < 0.2 V

VILf_1

V^CC×

0.3 *⁶

Flash_1

–0.5

V^ILf_2

–0.5

–0.3

—

0.6

0.5

V

Flash_2

FCRAM

Input Low Level

—

VILr

VCC ×

V^ILs

VIHf_1

VIHf_2

VIHr

–0.3

—

V

SRAM

Flash_1

Flash_2

FCRAM

SRAM

0.22 *⁶

0.7 ×

VCC

VCC+

0.3 *⁶

VCC+

0.3 *⁶

2.0

2.2

2.4

Input High Level

—

VCC +

0.3 *⁶

VCC+

0.3 *⁶

VIHs

Voltage for Sector Protection,

and Temporary Sector Unpro-

tection (RESET) *⁴

VID

—

11.5

8.5

—

12.5

9.5

V

Voltage for WP/ACC Sector

Protection/Unprotection and

Program Acceleration *⁴

VACC

9.0

(Continued)

12

MB84VZ128B/C-70

(Continued)

Parameter

Value

Unit

Sym-

bol

Conditions

Min

Typ

Max

0.15 ×

VCC*⁶

V^OLf_1

Flash_1

—

V

VCCf = VCCf Min, IOL = 4.0 mA

VOLf_2

V^OLr

Flash_2

FCRAM

SRAM

—

0.45

0.4

V

Output Low Voltage Level

Output High Voltage Level

VCCr = VCCr Min, IOL = 1.0 mA

VCCs = VCCs Min, IOL = 1.0 mA

V^OLs

0.4

VCCf ×

0.85 *⁶

VOHf_1

Flash_1

Flash_2

—

V

VCCf = VCCf Min, IOH = –0.1 mA

VCCr = VCCr Min, IOH = –0.5 mA

VCCf –

0.4 *⁶

VOHf_2

VOHr

FCRAM

SRAM

2.2

2.1

—

V

V^OHs VCCs = VCCs Min, IOH = –0.5 mA

V^LKO

Flash Low V^CCf Lock-Out

Voltage

—

2.3

2.4

2.5

V

Legend: Flash means Flash_1 or Flash_2, VCCf means VCCf_1 or VCCf_2, VSSf means VSSf_1 or VSSf_2, CEf means

CEf_1 or CEf _2, RESET means RESET_1 or RESET_2

*1: The I^CCcurrent listed includes both the DC operating current and the frequency dependent component.

*2: I^CCactive while Embedded Algorithm (program or erase) is in progress.

*3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns.

*4: Applicable for only VCCf applying.

*5: Embedded Alogorithm (program or erase) is in progress. (@5 MHz)

*6: V^CCindicates lower of VCCf_1 or VCCf_2 or VCCs or VCCr.

*7: Actual Standby Current is twice of what is indicated in the table, due to two Flash memory chips embedment

withn one device.

13

MB84VZ128B/C-70

■ AC CHARACTERISTICS

• CE Timing

Symbol

Value

Parameter

Condition

Unit

JEDEC

Standard

tCCR

Min

0

Max

—

CE Recover Time

CE Hold Time

—

ns

tCHOLD

3

—

CE1r, CE1s High to WE Invalid time

for Standby Entry

—

t^CHWX

—

10

—

ns

• Timing Diagram for alternating RAM to Flash_1 or Flash_2

CE0f_1 or

CE1f_1 or

CEf_2

tCCR

CE1r or

CE1s

WE

tCHWX

tCHOLD

tCCR

CE2r or

CE2s

• Flash_1 Characteristics

Please refer to “128M Page Flash Memory for MCP“ part. In this part, Flash means Flash_1, V^CCf means

VCCf_1, VSSf means VSSf_1, CE0f means CE0f_1, CE1f means CE1f_1, RESET means RESET_1

• Flash_2 Characteristics

Please refer to “64M Flash Memory for MCP“ part. In this part, Flash means Flash_2, V^CCf means VCCf_2,

VSSf means VSSf_2, CEf means CEf _2, RESET means RESET_2

• FCRAM Characteristics

Please refer to “■64M FCRAM for MCP”.

• SRAM Characteristics,

Please refer to “■8M SRAM for MCP”.

14

MB84VZ128B/C-70

■ 128 M PAGE FLASH MEMORY for MCP

1. Flexible Sector-erase Architecture on Flash Memory (128M Page Flash)

• Sixteen 4K words, and two hundred fifty-four 32K words.

• Individual-sector, multiple-sector, or bulk-erase capability.

CE0f

CE1f

200000h

208000h

210000h

218000h

220000h

228000h

230000h

238000h

240000h

248000h

250000h

258000h

260000h

268000h

270000h

278000h

280000h

288000h

290000h

298000h

2A0000h

2A8000h

2B0000h

2B8000h

2C0000h

2C8000h

2D0000h

2D8000h

2E0000h

2E8000h

2F0000h

2F8000h

300000h

308000h

310000h

318000h

320000h

328000h

330000h

338000h

340000h

348000h

350000h

358000h

360000h

368000h

370000h

378000h

380000h

388000h

390000h

398000h

3A0000h

3A8000h

3B0000h

3B8000h

3C0000h

3C8000h

3D0000h

3D8000h

3E0000h

3E8000h

3F0000h

3F8000h

3FFFFFh

400000h

408000h

410000h

418000h

420000h

428000h

430000h

438000h

440000h

448000h

450000h

458000h

460000h

468000h

470000h

478000h

480000h

488000h

490000h

498000h

4A0000h

4A8000h

4B0000h

4B8000h

4C0000h

4C8000h

4D0000h

4D8000h

4E0000h

4E8000h

4F0000h

4F8000h

500000h

508000h

510000h

518000h

520000h

528000h

530000h

538000h

540000h

548000h

550000h

558000h

560000h

568000h

570000h

578000h

580000h

588000h

590000h

598000h

5A0000h

5A8000h

5B0000h

5B8000h

5C0000h

5C8000h

5D0000h

5D8000h

5E0000h

5E8000h

5F0000h

5F8000h

5FFFFFh

600000h

608000h

610000h

618000h

620000h

628000h

630000h

638000h

640000h

648000h

650000h

658000h

660000h

668000h

670000h

678000h

680000h

688000h

690000h

698000h

6A0000h

6A8000h

6B0000h

6B8000h

6C0000h

6C8000h

6D0000h

6D8000h

6E0000h

6E8000h

6F0000h

6F8000h

700000h

708000h

710000h

718000h

720000h

728000h

730000h

738000h

740000h

748000h

750000h

758000h

760000h

768000h

770000h

778000h

780000h

788000h

790000h

798000h

7A0000h

7A8000h

7B0000h

7B8000h

7C0000h

7C8000h

7D0000h

7D8000h

7E0000h

7E8000h

7F0000h

7F8000h

7F9000h

7FA000h

7FB000h

7FC000h

7FD000h

7FE000h

7FF000h

7FFFFFh

000000h

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

:

8KB

SA71 : 64KB

SA72 : 64KB

SA73 : 64KB

SA74 : 64KB

SA75 : 64KB

SA76 : 64KB

SA77 : 64KB

SA78 : 64KB

SA79 : 64KB

SA80 : 64KB

SA81 : 64KB

SA82 : 64KB

SA83 : 64KB

SA84 : 64KB

SA85 : 64KB

SA86 : 64KB

SA87 : 64KB

SA88 : 64KB

SA89 : 64KB

SA90 : 64KB

SA91 : 64KB

SA92 : 64KB

SA93 : 64KB

SA94 : 64KB

SA95 : 64KB

SA96 : 64KB

SA97 : 64KB

SA98 : 64KB

SA99 : 64KB

SA100: 64KB

SA101: 64KB

SA102: 64KB

SA103: 64KB

SA104: 64KB

SA105: 64KB

SA106: 64KB

SA107: 64KB

SA108: 64KB

SA109: 64KB

SA110: 64KB

SA111: 64KB

SA112: 64KB

SA113: 64KB

SA114: 64KB

SA115: 64KB

SA116: 64KB

SA117: 64KB

SA118: 64KB

SA119: 64KB

SA120: 64KB

SA121: 64KB

SA122: 64KB

SA123: 64KB

SA124: 64KB

SA125: 64KB

SA126: 64KB

SA127: 64KB

SA128: 64KB

SA129: 64KB

SA130: 64KB

SA131: 64KB

SA132: 64KB

SA133: 64KB

SA134: 64KB

SA135: 64KB

SA136: 64KB

SA137: 64KB

SA138: 64KB

SA139: 64KB

SA140: 64KB

SA141: 64KB

SA142: 64KB

SA143: 64KB

SA144: 64KB

SA145: 64KB

SA146: 64KB

SA147: 64KB

SA148: 64KB

SA149: 64KB

SA150: 64KB

SA151: 64KB

SA152: 64KB

SA153: 64KB

SA154: 64KB

SA155: 64KB

SA156: 64KB

SA157: 64KB

SA158: 64KB

SA159: 64KB

SA160: 64KB

SA161: 64KB

SA162: 64KB

SA163: 64KB

SA164: 64KB

SA165: 64KB

SA166: 64KB

SA167: 64KB

SA168: 64KB

SA169: 64KB

SA170: 64KB

SA171: 64KB

SA172: 64KB

SA173: 64KB

SA174: 64KB

SA175: 64KB

SA176: 64KB

SA177: 64KB

SA178: 64KB

SA179: 64KB

SA170: 64KB

SA181: 64KB

SA182: 64KB

SA183: 64KB

SA184: 64KB

SA185: 64KB

SA186: 64KB

SA187: 64KB

SA188: 64KB

SA189: 64KB

SA190: 64KB

SA191: 64KB

SA192: 64KB

SA193: 64KB

SA194: 64KB

SA195: 64KB

SA196: 64KB

SA197: 64KB

SA198: 64KB

SA199: 64KB

SA200: 64KB

SA201: 64KB

SA202: 64KB

SA203: 64KB

SA204: 64KB

SA205: 64KB

SA206: 64KB

SA207: 64KB

SA208: 64KB

SA209: 64KB

SA210: 64KB

SA211: 64KB

SA212: 64KB

SA213: 64KB

SA214: 64KB

SA215: 64KB

SA216: 64KB

SA217: 64KB

SA218: 64KB

SA219: 64KB

SA220: 64KB

SA221: 64KB

SA222: 64KB

SA223: 64KB

SA224: 64KB

SA225: 64KB

SA226: 64KB

SA227: 64KB

SA228: 64KB

SA229: 64KB

SA230: 64KB

SA231: 64KB

SA232: 64KB

SA233: 64KB

SA234: 64KB

SA235: 64KB

SA236: 64KB

SA237: 64KB

SA238: 64KB

SA239: 64KB

SA240: 64KB

SA241: 64KB

SA242: 64KB

SA243: 64KB

SA244: 64KB

SA245: 64KB

SA246: 64KB

SA247: 64KB

SA248: 64KB

SA249: 64KB

SA250: 64KB

SA251: 64KB

SA252: 64KB

SA253: 64KB

SA254: 64KB

SA255: 64KB

SA256: 64KB

SA257: 64KB

SA258: 64KB

SA259: 64KB

SA260: 64KB

SA261: 64KB

SA262: 8KB

SA263: 8KB

SA264: 8KB

SA265: 8KB

SA266: 8KB

SA267: 8KB

SA268: 8KB

SA269: 8KB

001000h

002000h

003000h

004000h

005000h

006000h

007000h

008000h

010000h

018000h

020000h

028000h

030000h

038000h

040000h

048000h

050000h

058000h

060000h

068000h

070000h

078000h

080000h

088000h

090000h

098000h

0A0000h

0A8000h

0B0000h

0B8000h

0C0000h

0C8000h

0D0000h

0D8000h

0E0000h

0E8000h

0F0000h

0F8000h

100000h

108000h

110000h

118000h

120000h

128000h

130000h

138000h

140000h

148000h

150000h

158000h

160000h

168000h

170000h

178000h

180000h

188000h

190000h

198000h

1A0000h

1A8000h

1B0000h

1B8000h

1C0000h

1C8000h

1D0000h

1D8000h

1E0000h

1E8000h

1F0000h

1F8000h

1FFFFFh

SA8 : 64KB

SA9 : 64KB

SA10 : 64KB

SA11 : 64KB

SA12 : 64KB

SA13 : 64KB

SA14 : 64KB

SA15 : 64KB

SA16 : 64KB

SA17 : 64KB

SA18 : 64KB

SA19 : 64KB

SA20 : 64KB

SA21 : 64KB

SA22 : 64KB

SA23 : 64KB

SA24 : 64KB

SA25 : 64KB

SA26 : 64KB

SA27 : 64KB

SA28 : 64KB

SA29 : 64KB

SA30 : 64KB

SA31 : 64KB

SA32 : 64KB

SA33 : 64KB

SA34 : 64KB

SA35 : 64KB

SA36 : 64KB

SA37 : 64KB

SA38 : 64KB

SA39 : 64KB

SA40 : 64KB

SA41 : 64KB

SA42 : 64KB

SA43 : 64KB

SA44 : 64KB

SA45 : 64KB

SA46 : 64KB

SA47 : 64KB

SA48 : 64KB

SA49 : 64KB

SA50 : 64KB

SA51 : 64KB

SA52 : 64KB

SA53 : 64KB

SA54 : 64KB

SA55 : 64KB

SA56 : 64KB

SA57 : 64KB

SA58 : 64KB

SA59 : 64KB

SA60 : 64KB

SA61 : 64KB

SA62 : 64KB

SA63 : 64KB

SA64 : 64KB

SA65 : 64KB

SA66 : 64KB

SA67 : 64KB

SA68 : 64KB

SA69 : 64KB

SA70 : 64KB

15

MB84VZ128B/C-70

• FlexBank^TMArchitecture (128M Page Flash)

Bank 1

Bank

Bank 2

Combination

Splits

Volume

16M bit

48M bit

16M bit

Combination

Volume

112M bit

80M bit

112M bit

1

2

3

4

Bank A

Remainder (Bank B, C, D)

Remainder (Bank A, C, D)

Remainder (Bank A, B, D)

Remainder (Bank A, B, C)

Bank B

Bank C

Bank D

• Example of Virtual Banks Combination (128M Page Flash)

Bank 1

Bank

Bank 2

Splits

Volume

Combination

Sector Size

Volume

Combination

Sector Size

Bank B

+

Bank C

+

8 × 4K word

+

31 x 32K word

8 x 4K word

+

223 x 32K word

1

2

3

4

16M bit

Bank A

112M bit

Bank D

Bank A

+

Bank D

16 x 4K word

+

62 x 32K word

Bank B

+

Bank C

32M bit

48M bit

64M bit

96M bit

80M bit

64M bit

192 x 32K word

Bank A

+

Bank C

+

16 x 4K word

+

158 x 32K word

Bank B

96 x 32K word

Bank D

Bank A

+

8 x 4K word

+

Bank C

+

8 x 4K word

+

Bank B

127 x 32K word

Bank D

127 x 32K word

Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which

a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,

neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected) .

Meanwhile the system would get to read from either Bank C or Bank D.

16

MB84VZ128B/C-70

• Simultaneous Operation(Dual CE) (128M Page Flash)

The device features functions that enable reading of data from one memory bank while a program or erase

operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features

(read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank

address (A²¹, A20) with zero latency. The device consists of the following four banks :

CE0f controll: Bank A : 8 x 4 KW and 31 x 32 KW; Bank B : 96 x 32 KW

CE1f controll: Bank C : 96 x 32 KW; Bank D : 8 x 4 KW and 31 x 32 KW.

The possible combinations for simultaneous operation is show as following table. (Refer to Figure 11 Bank-to-

Bank Read/Write Timing Diagram.)

• Simultaneous Operation for Dual CE (128M Page Flash)

Bank 1 (CE0f) Status

16M bit

Bank 2 (CE0f) Status Bank 1 (CE1f) Status Bank 2 (CE1f) Status

Case

48M bit

16M bit

1

2

Read mode

Autoselect mode

Read mode

3

Autoselect mode

Read mode

4

Read mode

Autoselect mode

Read mode

5

Read mode

Autoselect mode

Read mode

6

Program mode

Read mode

7

Program mode

Read mode

8

Read mode

Program mode

Read mode

9

Read mode

Program mode

Read mode

10

11

12

13

14*

15*

16*

17*

18*

19*

20*

21*

22*

23*

Erase Mode

Read mode

Erase Mode

Read mode

Erase Mode

Read mode

Erase Mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

Read mode

Multiple Erase Mode

* : Multiple Erase Mode requires muliple sector erase sequence which is followed by writes of the Sector Erase

command to addresses in other sectors desired to be concurrently erased. The time between writes must be

less than "t^TOW".

17

MB84VZ128B/C-70

2. Flexible Sector-erase Architecture

• Sector Address Tables (Bank A) (128M Page Flash)

Sector Address

Chip

Enable

Bank

Addre

ss

Sector

Size

(Kwords)

(× 16)

Address Range

Bank

Sector

CE0f CE1f

A

21

A20

A

19

A18

A

17

A16

A15

A14

A13

A12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

006000h to 006FFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 06FFFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

Bank A

18

MB84VZ128B/C-70

• Sector Address Tables (Bank B) (128M Page Flash)

Sector Address

Chip

Sector

Bank

(× 16)

Enable

Bank

Sector

Size

Address

Address Range

(Kwords)

CE0f CE1f

A21

A20

A19

A

18

A17

A

16

A15

A14

A13

A12

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

0

1

0

1

0

X

32

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1FFFFFh

200000h to 207FFFh

208000h to 20FFFFh

210000h to 217FFFh

218000h to 21FFFFh

220000h to 227FFFh

228000h to 22FFFFh

230000h to 237FFFh

(Continued)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

Bank B

19

MB84VZ128B/C-70

Sector Address

Chip

Enable

Sector

Size

(Kwords)

(× 16)

Address Range

Bank

Sector

Bank

Address

CE0f CE1f

A21

A20

A19

A

18

A17

A

16

A15

A

14

A13

A

12

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

0

1

0

1

X

32

238000h to 23FFFFh

240000h to 247FFFh

248000h to 24FFFFh

250000h to 257FFFh

258000h to 25FFFFh

260000h to 267FFFh

268000h to 26FFFFh

270000h to 277FFFh

278000h to 27FFFFh

280000h to 287FFFh

288000h to 28FFFFh

290000h to 297FFFh

298000h to 29FFFFh

2A0000h to 2A7FFFh

2A8000h to 2AFFFFh

2B0000h to 2B7FFFh

2B8000h to 2BFFFFh

2C0000h to 2C7FFFh

2C8000h to 2CFFFFh

2D0000h to 2D7FFFh

2D8000h to 2DFFFFh

2E0000h to 2E7FFFh

2E8000h to 2EFFFFh

2F0000h to 2F7FFFh

2F8000h to 2FFFFFh

300000h to 307FFFh

308000h to 30FFFFh

310000h to 317FFFh

318000h to 31FFFFh

320000h to 327FFFh

328000h to 32FFFFh

330000h to 337FFFh

338000h to 33FFFFh

340000h to 347FFFh

348000h to 34FFFFh

350000h to 357FFFh

358000h to 35FFFFh

360000h to 367FFFh

368000h to 36FFFFh

(Continued)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

SA95

SA96

SA97

SA98

Bank B

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

20

MB84VZ128B/C-70

(Continued)

Sector Address

Chip

Enable

Sector

(× 16)

Bank

Sector

Size

Bank

Address

Address Range

(Kwords)

CE0f CE1f

A

21

A20

A19

A

18

A17

A

16

A15

A

14

A13

A12

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

0

1

0

1

0

X

32

370000h to 377FFFh

378000h to 37FFFFh

380000h to 387FFFh

388000h to 38FFFFh

390000h to 397FFFh

398000h to 39FFFFh

3A0000h to 3A7FFFh

3A8000h to 3AFFFFh

3B0000h to 3B7FFFh

3B8000h to 3BFFFFh

3C0000h to 3C7FFFh

3C8000h to 3CFFFFh

3D0000h to 3D7FFFh

3D8000h to 3DFFFFh

3E0000h to 3E7FFFh

3E8000h to 3EFFFFh

3F0000h to 3F7FFFh

3F8000h to 3FFFFFh

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Bank B

21

MB84VZ128B/C-70

• Sector Address Tables (Bank C) (128M Page Flash)

Sector Address

Chip

Enable

Sector

Size

(Kwords)

(× 16)

Address Range

Bank

Sector

Bank

Address

CE0f CE1f

A21

A

20

A19

A

18

A17

A

16

A15

A14

A13

A12

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

1

0

X

32

400000h to 407FFFh

408000h to 40FFFFh

410000h to 417FFFh

418000h to 41FFFFh

420000h to 427FFFh

428000h to 42FFFFh

430000h to 437FFFh

438000h to 43FFFFh

440000h to 447FFFh

448000h to 44FFFFh

450000h to 457FFFh

458000h to 45FFFFh

460000h to 467FFFh

468000h to 46FFFFh

470000h to 477FFFh

478000h to 47FFFFh

480000h to 487FFFh

488000h to 48FFFFh

490000h to 497FFFh

498000h to 49FFFFh

4A0000h to 4A7FFFh

4A8000h to 4AFFFFh

4B0000h to 4B7FFFh

4B8000h to 4BFFFFh

4C0000h to 4C7FFFh

4C8000h to 4CFFFFh

4D0000h to 4D7FFFh

4D8000h to 4DFFFFh

4E0000h to 4E7FFFh

4E8000h to 4EFFFFh

4F0000h to 4F7FFFh

4F8000h to 4FFFFFh

500000h to 507FFFh

508000h to 50FFFFh

510000h to 517FFFh

518000h to 51FFFFh

520000h to 527FFFh

528000h to 52FFFFh

530000h to 537FFFh

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

Bank C

(Continued)

22

MB84VZ128B/C-70

Sector Address

Chip

Enable

Sector

(× 16)

Bank

Sector

Size

Bank

Address

Address Range

(Kwords)

CE0f CE1f

A21

A20

A

19

A

18

A

17

A

16

A15

A14

A13

A12

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

1

0

1

0

1

X

32

538000h to 53FFFFh

540000h to 547FFFh

548000h to 54FFFFh

550000h to 557FFFh

558000h to 55FFFFh

560000h to 567FFFh

568000h to 56FFFFh

570000h to 577FFFh

578000h to 57FFFFh

580000h to 587FFFh

588000h to 58FFFFh

590000h to 597FFFh

598000h to 59FFFFh

5A0000h to 5A7FFFh

5A8000h to 5AFFFFh

5B0000h to 5B7FFFh

5B8000h to 5BFFFFh

5C0000h to 5C7FFFh

5C8000h to 5CFFFFh

6D0000h to 5D7FFFh

6D8000h to 5DFFFFh

5E0000h to 5E7FFFh

5E8000h to 5EFFFFh

5F0000h to 5F7FFFh

5F8000h to 5FFFFFh

600000h to 607FFFh

608000h to 60FFFFh

610000h to 617FFFh

618000h to 61FFFFh

620000h to 627FFFh

628000h to 62FFFFh

630000h to 637FFFh

638000h to 63FFFFh

640000h to 647FFFh

648000h to 64FFFFh

650000h to 657FFFh

658000h to 65FFFFh

660000h to 667FFFh

668000h to 66FFFFh

(Continued)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Bank C

23

MB84VZ128B/C-70

(Continued)

Sector Address

Chip

Enable

Sector

Size

(Kwords)

(× 16)

Address Range

Bank

Sector

Bank

Address

CE0f CE1f

A21

A

20

A19

A

18

A17

A

16

A15

A14

A13

A12

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

1

0

1

0

1

0

X

32

670000h to 677FFFh

678000h to 67FFFFh

680000h to 687FFFh

688000h to 68FFFFh

690000h to 697FFFh

698000h to 69FFFFh

6A0000h to 6A7FFFh

6A8000h to 6AFFFFh

6B0000h to 6B7FFFh

8B8000h to 6BFFFFh

6C0000h to 6C7FFFh

6C8000h to 6CFFFFh

6D0000h to 6D7FFFh

6D8000h to 6DFFFFh

6E0000h to 6E7FFFh

6E8000h to 6EFFFFh

6F0000h to 6F7FFFh

6F8000h to 6FFFFFh

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Bank C

24

MB84VZ128B/C-70

• Sector Address Tables (Bank D) (128M Page Flash)

Sector Address

Chip

Enable

Sector

(× 16)

Bank

Sector

Size

Bank

Address

Address Range

(Kwords)

CE0f CE1f

A

21

A20

A19

A18

A17

A16

A15

A

14

A13

A

12

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

1

0

1

0

X

32

4

700000h to 707FFFh

708000h to 70FFFFh

710000h to 717FFFh

718000h to 71FFFFh

720000h to 727FFFh

728000h to 72FFFFh

730000h to 737FFFh

738000h to 73FFFFh

740000h to 747FFFh

748000h to 74FFFFh

750000h to 757FFFh

758000h to 75FFFFh

760000h to 767FFFh

768000h to 76FFFFh

770000h to 777FFFh

778000h to 77FFFFh

780000h to 787FFFh

788000h to 78FFFFh

790000h to 797FFFh

798000h to 79FFFFh

7A0000h to 7A7FFFh

7A8000h to 7AFFFFh

7B0000h to 7B7FFFh

7B8000h to 7BFFFFh

7C0000h to 7C7FFFh

7C8000h to 7CFFFFh

7D0000h to 7D7FFFh

7D8000h to 7DFFFFh

7E0000h to 7E7FFFh

7E8000h to 7EFFFFh

7F0000h to 7F7FFFh

7F8000h to 7F8FFFh

7F9000h to 7F9FFFh

7FA000h to 7FAFFFh

7FB000h to 7FBFFFh

7FC000h to 7FCFFFh

7FD000h to 7FDFFFh

7FE000h to 7FEFFFh

7FF000h to 7FFFFFh

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

Bank D

0

1

0

1

0

1

0

1

0

1

0

1

4

25

MB84VZ128B/C-70

• Sector Group Address Table (128M Page Flash)

Sector Group CE0f CE1f

A²¹

0

1

A²⁰

0

1

0

1

A¹⁹

0

1

0

1

0

1

0

1

A¹⁸

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

A¹⁵

0

A¹⁴

0

A¹³

0

A¹²

0

Sectors

SA0

SGA0

SGA1

0

1

0

1

SA1

SGA2

0

1

0

SA2

SGA3

0

1

SA3

SGA4

0

1

0

SA4

SGA5

0

1

0

1

SA5

SGA6

0

1

0

SA6

SGA7

0

1

SA7

SGA8

0

1

X

SA8

SGA9

1

0

SA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

SGA38

SGA39

SGA40

SGA41

1

SA10

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SA67 to SA70

SA71 to SA74

SA75 to SA78

SA79 to SA82

SA83 to SA86

SA87 to SA90

SA91 to SA94

SA95 to SA98

SA99 to SA102

SA103 to SA106

SA107 to SA110

SA111 to SA114

SA115 to SA118

SA119 to SA122

SA123 to SA126

SA127 to SA130

SA131 to SA134

(Continued)

26

MB84VZ128B/C-70

(Continued)

Sector Group CE0f CE1f

A²¹

0

1

A²⁰

0

1

0

1

A¹⁹

0

1

0

1

0

1

0

1

A¹⁸

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

X

0

A¹⁵

X

0

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

Sectors

SGA42

SGA43

SGA44

SGA45

SGA46

SGA47

SGA48

SGA49

SGA50

SGA51

SGA52

SGA53

SGA54

SGA55

SGA56

SGA57

SGA58

SGA59

SGA60

SGA61

SGA62

SGA63

SGA64

SGA65

SGA66

SGA67

SGA68

SGA69

SGA70

SGA71

SGA72

SGA73

SGA74

SGA75

SGA76

SGA77

SGA78

SGA79

SGA80

SGA81

SGA82

SGA83

1

0

SA135 to SA138

SA139 to SA142

SA143 to SA146

SA147 to SA150

SA151 to SA154

SA155 to SA158

SA159 to SA162

SA163 to SA166

SA167 to SA170

SA171 to SA174

SA175 to SA178

SA179 to SA182

SA183 to SA186

SA187 to SA190

SA191 to SA194

SA195 to SA198

SA199 to SA202

SA203 to SA206

SA207 to SA210

SA211 to SA214

SA215 to SA218

SA219 to SA222

SA223 to SA226

SA227 to SA230

SA231 to SA234

SA235 to SA238

SA239 to SA242

SA243 to SA246

SA247 to SA250

SA251 to SA254

SA255 to SA258

SA259

0

1

SA260

1

0

SA261

1

SA262

1

0

1

SA263

1

0

1

0

SA264

1

0

1

SA265

1

0

SA266

1

0

1

SA267

1

0

SA268

1

SA269

27

MB84VZ128B/C-70

• Sector Group Protection Verify Autoselect Codes (128M Page Flash)

Type

Manufacture’s Code

Device Code

A²²to A¹²

BA

A⁷A⁶A⁵A⁴A³A²A¹A⁰

Code (HEX)

04h

L

X

L

H

L

BA

227Eh

2221h

H

Extended Device Code*²

BA

H

2200h

Sector

Group

Sector Group Protection

L

H

L

01h*¹

Addresses

Legand: L = V^IL, H = VIH, X= VIL or VIH .

*1 : Sector Group can be protected by "Extended Sector Group Protection", and "New Sector Protection (PPB

Protection)”. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group

addresses.

*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional

codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these

Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.

28

MB84VZ128B/C-70

• Command Definitions (128M Page Flash)

Bus

Fourth Bus

Read/Write

Cycle

First Bus

Second Bus

Write Cycle

Third Bus

Fifth Bus

Sixth Bus

Seventh Bus

Write

Cy-

Command

Sequence

Write Cycle

Write Cycle Write Cycle

cles

Req’d

Addr. Data Addr. Data Addr. Data

Addr.

Data

Addr. Data Addr. Data Addr. Data

Read/Reset

1

3

XXXh F0h

555h AAh 2AAh

RA

RD

55h

—

F0h

—

RA

—

RD

—

555h

(BA)

555h

Autoselect

3

555h AAh 2AAh

55h

90h

—

Program

4

6

555h AAh 2AAh

55h

A0h

80h

PA

555h

PD

AAh

—

2AAh

—

55h

—

555h

SA

—

10h

30h

—

Chip Erase

Sector Erase

Program/Erase

Suspend

Program/Erase

Resume

1

BA

B0h

30h

—

Set to Fast

Mode

Fast Program

Reset from Fast

Mode *¹

3

2

555h AAh 2AAh

55h

PD

555h

—

20h

—

XXXh A0h

BA 90h

PA

4

*

XXXh

—

F0h

Extended

Sector Group

Protection *²

SGA+

WPH

SGA+

WPH

SGA+

WPH

4

XXXh 60h

60h

40h

SD

—

(BA)

98h

55h

Query

1

3

4

—

HiddenROM

Entry

HiddenROM

Program *³

555h AAh 2AAh

55h

555h

88h

A0h

(HRA)

PA

PD

(HR-

BA)

555h

HiddenROM

Exit *³

4

6

555h AAh 2AAh

55h

90h

XXXh

00h

—

HiddenROM

Protect *³

555h AAh 2AAh

55h

555h

60h

OPBP

68h

OPBP

48h XXXh RD(0)

555h AAh 2AAh

55h

555h

38h

XX0h

XX1h

XX2h

XX3h

PD0

PD1

PD2

PD3

Password

Program

4

—

Password

Unlock

Password Verify

PasswordMode

Locking Bit

Program

7

4

555h AAh 2AAh

55h

555h

28h

C8h

XX0h

PWA

PD0

PWD

XX1h

—

PD1 XX2h PD2 XX3h PD3

—

6

555h AAh 2AAh

55h

555h

60h

PL

68h

PL

48h XXXh RD(0)

Persistent

ProtectionMode

Locking Bit

Program

6

555h AAh 2AAh

55h

555h

60h

SPML

68h

SPML

48h XXXh RD(0)

—

PPB Program

6

4

3

555h AAh 2AAh

55h

555h

(BA)

555h

60h

90h

60h

78h

SGA+WP

WP

68h

RD(0)

60h

—

SGA+WP

—

PPB Verify

—

All PPB Erase

PPB Lock Bit

Set

PPB Lock Bit

Verify

SGA+WP

—

40h XXXh RD(0)

555h

—

(BA)

555h

(BA)

555h

4

555h AAh 2AAh

55h

58h

SA

RD(1)

—

DPB Write

DPB Erase

4

555h AAh 2AAh

55h

48h

SA

X1h

X0h

—

DPB Verify

4

555h AAh 2AAh

55h

58h

SA

RD(0)

—

29

MB84VZ128B/C-70

Legend:

RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A²², A21, A20, A19, A18, A17, A16, A15, A14, A13 and

A12 will uniquely select any sector.

BA = Bank Address. Address setted by A22, A21, A20, A19 will select Bank A, Bank B, Bank C and Bank D.

RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

SGA = Sector group address to be protected.

WPH = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0)

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

HRA = Address of the HiddenROM area Word Mode : 000000h to 00007Fh

HRBA = Bank Address of the HiddenROM area (A22 = A21 = A20 = VIL)

RD (0) = Read Data bit. If programmed, DQ0 = 1, if erase, DQ0 = 0

RD (1) = Read Data bit. If programmed, DQ1 = 1, if erase, DQ1 = 0

OPBP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0)

PWA/PWD = Password Address/Password Data

PL =(A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 1, 0, 1, 0)

SPML = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 0, 0, 1, 0)

WP =(A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0)

*1: This command is valid during Fast Mode.

*2: This command is valid while RESET = VID.

*3: This command is valid during HiddenROM mode.

*4: The data “00h” is also acceptable.

Notes : • Address bits A²²to A11 = X = “H” or “L” for all address commands except for

PA, SA, BA, SGA, OPBP, PWA, PL, SPML, WP, WPH.

• Bus operations are defined in this document.

• The system should generate the following address patterns:

Word Mode : 555h or 2AAh to addresses A10 to A0

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

30

MB84VZ128B/C-70

3. AC CHARACTERISTICS

• Read Only Operations Characteristics (Flash) (128M Page Flash)

Symbol

Parameter

Value*

Test Setup

Unit

JEDEC Standard

Min

Max

Read Cycle Time

t^AVAV

tAVQV

—

tRC

tACC

tPRC

tPACC

—

70

ns

CEf = VIL

OE = VIL

Address to Output Delay

Page Read Cycle Time

Page Address to Output Delay

70

—

20

CEf = VIL

OE = VIL

—

20

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

t^ELQV

t^GLQV

t^EHQZ

t^GHQZ

tCE

tOE

tDF

OE = VIL

70

20

ns

—

Output Hold Time From Address,

CEf or OE, Whichever Occurs First

t^AXQX

tOH

—

5

ns

*: Test Conditions– Output Load : 1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to V^CCf

Timing measurement reference level

Input: 0.5×VCCf

Output: 0.5×VCCf

31

MB84VZ128B/C-70

• Write/Erase/Program Operations (Flash) (128M Page Flash)

Symbol

Parameter

Value

Typ

Unit

JEDEC Standard

Min

70

0

Max

Write Cycle Time

t^AVAV

t^AVWL

tWC

tAS

ns

Address Setup Time

Address Setup Time to OE Low During

Toggle Bit Polling

Address Hold Time

Address Hold Time from CEf or OE High

During Toggle Bit Polling

—

tWLAX

—

t^ASO

tAH

15

35

0

ns

t^AHT

Data Setup Time

Data Hold Time

Output Enable Setup Time

t^DVWH

t^WHDX

—

tDS

tDH

30

0

10

0

ns

t^OES

Read

Output Enable

Hold Time

—

t^OEH

Toggle and Data Polling

Read Recover Time Before Write

(OE High to CEf Low)

t^GHWL

t^GHEL

tGHWL

tGHEL

0

ns

CEf Setup Time

WE Setup Time

CEf Hold Time

WE Hold Time

Write Pulse Width

CEf Pulse Width

tELWL

tWLEL

tWHEH

tEHWH

t^WLWH

tELEH

t^WHWL

tEHEL

t^WHWH1

tWHWH2

—

tCS

tWS

0

ns

µs

s

tCH

tWH

0

tWP

40

25

tCP

Write Pulse Width High

CEf Pulse Width High

Programming Operation

Sector Erase Operation *¹

V^CCf Setup Time

Rise Time to V^ID*²

Rise Time to V^ACC*³

Voltage Transition Time *²

Write Pulse Width^*2

Recover Time from RY/BY

RESET Pulse Width

RESET High Level Period Before Read

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Erase Time-out Time

Erase Suspend Transition Time

tWPH

tCPH

tWHWH1

tWHWH2

tVCS

tVIDR

tVACCR

tVLHT

tWPP

tRB

6

5

50

500

4

µs

ns

µs

ns

µs

—

100

0

500

50

tRP

tRH

tBUSY

t^EOE

t^TOW

t^SPD

90

70

50

20

*1 : This does not include the preprogramming time.

*2 : This timing is for Sector Group Protection / Unprotection .

*3 : This timing is for Accelerated Program operation.

32

MB84VZ128B/C-70

• Read Operation Timing Diagram (128M Page Flash)

tRC

Address

Address Stable

tACC

CEf

OE

tOE

tDF

tOEH

WE

tCE

tOH

High-Z

Outputs

Output Valid

CEf : CE0f or CE1f

33

MB84VZ128B/C-70

• Page Read Operation Timing Diagram (128M Page Flash)

Same page Addresses

A

22 to A

2

A

2

to A

0

Aa

Ab

Ac

Ad

t

RC

t

PRC

t

PRC

t

ACC

t

CE

CEf

t

OEH

t

OE

t

DF

t

PACC

OH

t

PACC

OH

t

PACC

OH

WE

t

OH

High-Z

Da

Db

Dc

Dd

Output

CEf : CE0f or CE1f

34

MB84VZ128B/C-70

• Hardware Reset/Read Operation Timing Diagram (128M Page Flash)

tRC

Address

Address Stable

tACC

CEf

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

CEf : CE0f or CE1f

35

MB84VZ128B/C-70

• Alternate WE Controlled Program Operation Timing Diagram (128M Page Flash)

3rd Bus Cycle

555h

Data Polling

PA

Address

CEf

tWC

tRC

tAS

tAH

tCS

tCH

tCE

OE

tOE

tWP

tWPH

tWHWH1

tGHWL

WE

tOH

tDF

tDH

tDS

A0h

PD

DOUT

DQ7

Data

CEf : CE0f or CE1f

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

36

MB84VZ128B/C-70

• Alternate CEf Controlled Program Operation Timing Diagram (128M Page Flash)

3rd Bus Cycle

555h

Data Polling

PA

Address

WE

tWC

tAS

tAH

tWS

tWH

OE

tCPH

tCP

tWHWH1

tGHEL

CEf

tDS

tDH

A0h

PD

DOUT

DQ7

Data

CEf : CE0f or CE1f

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

37

MB84VZ128B/C-70

• Chip/Sector Erase Operation Timing Diagram (128M Page Flash)

555h

tWC

2AAh

555h

2AAh

SA*

Address

CEf

tAS

tAH

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

30h for Sector Erase

10h/

30h

AAh

55h

80h

AAh

55h

Data

VCCf

tVCS

CEf : CE0f or CE1f

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.

38

MB84VZ128B/C-70

• Data Polling during Embedded Algorithm Operation Timing Diagram (128M Page Flash)

CEf

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ0 =

Output Flag

DQ6 to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tEOE

tBUSY

CEf : CE0f or CE1f

* : DQ7 = Valid Data (The device has completed the Embedded operation) .

39

MB84VZ128B/C-70

• AC Waveforms for Toggle Bit I during Embedded Algorithm Operations (128M Page Flash)

Address

tAHT tASO

tAHT tAS

CEf

WE

tCEPH

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

CEf : CE0f or CE1f

* : DQ6 stops toggling (The device has completed the Embedded operation).

40

MB84VZ128B/C-70

• Bank-to-Bank Read/Write Timing Diagram (128M Page Flash)

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

CEf

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDS

tDH

tDF

Valid

Output

Valid

Output

Valid

Output

Status

Intput

(A0h)

(PD)

CEf : CE0f or CE1f

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1 : Address corresponding to Bank 1

BA2 : Address corresponding to Bank 2

41

MB84VZ128B/C-70

• RY/BY Timing Diagram during Program/Erase Operation Timing Diagram (128M Page Flash)

CEf

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

CEf : CE0f or CE1f

• RESET, RY/BY Timing Diagram (128M Page Flash)

WE

RESET

tRP

tRB

RY/BY

tREADY

42

MB84VZ128B/C-70

• Temporary Sector Group Unprotection Timing Diagram (128M Page Flash)

VCCf

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CEf

WE

tVLHT

Program or Erase Command Sequence

Unprotection period

RY/BY

CEf : CE0f or CE1f

43

MB84VZ128B/C-70

• Extended Sector Group Protection Timing Diagram (128M Page Flash)

VCCf

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SGAX

SGAY

A7, A6, A5

A4, A3, A2

A0

A1

CEf

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

CEf : CE0f or CE1f

SGAX : Sector Group Address to be protected

SGAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

44

MB84VZ128B/C-70

• Accelerated Program Timing Diagram (128M Page Flash)

V^CCf

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CEf

WE

tVLHT

Program Sequence

RY/BY

Acceleration period

CEf : CE0f or CE1f

45

MB84VZ128B/C-70

4. Erase and Programming Performance (128M Page Flash)

Value

Parameter

Unit

Comments

Min

Typ

Max

Excludes programming time

prior to erasure

Sector Erase Time

—

0.5

2

s

Excludes system-level

overhead

Word Programming Time

—

6.0

100

µs

Excludes system-level

overhead

Chip Programming Time

Erase/Program Cycle

—

50.3

—

200

—

s

100,000

cycle

—

Note: Typical Erase conditions TA = + 25°C, VCC = 2.9 V

Typical Program conditions T^A= + 25°C, VCC = 2.9 V, Data = checker

46

MB84VZ128B/C-70

■ 64 M FLASH MEMORY for MCP

1. Flexible Sector-erase Architecture on Flash Memory

• Sixteen 4K words, and one hundred twenty-six 32K words.

• Individual-sector, multiple-sector, or bulk-erase capability.

Word Mode

200000h

Word Mode

000000h

SA0 : 8KB (4KW)

001000h

SA71 : 64KB (32KW)

208000h

SA1 : 8KB (4KW)

002000h

SA72 : 64KB (32KW)

210000h

SA2 : 8KB (4KW)

003000h

SA73 : 64KB (32KW)

218000h

SA3 : 8KB (4KW)

004000h

SA74 : 64KB (32KW)

220000h

SA4 : 8KB (4KW)

005000h

SA75 : 64KB (32KW)

228000h

SA5 : 8KB (4KW)

006000h

SA76 : 64KB (32KW)

230000h

SA6 : 8KB (4KW)

007000h

SA77 : 64KB (32KW)

238000h

SA7 : 8KB (4KW)

008000h

SA78 : 64KB (32KW)

240000h

SA8 : 64KB (32KW)

010000h

SA79 : 64KB (32KW)

248000h

SA9 : 64KB (32KW)

018000h

SA80 : 64KB (32KW)

250000h

Bank A

SA10 : 64KB (32KW)

SA11 : 64KB (32KW)

SA12 : 64KB (32KW)

SA13 : 64KB (32KW)

SA14 : 64KB (32KW)

SA15 : 64KB (32KW)

SA16 : 64KB (32KW)

SA17 : 64KB (32KW)

SA18 : 64KB (32KW)

SA19 : 64KB (32KW)

SA20 : 64KB (32KW)

SA21 : 64KB (32KW)

SA22 : 64KB (32KW)

SA23 : 64KB (32KW)

SA24 : 64KB (32KW)

SA25 : 64KB (32KW)

SA26 : 64KB (32KW)

SA27 : 64KB (32KW)

SA28 : 64KB (32KW)

SA29 : 64KB (32KW)

SA30 : 64KB (32KW)

SA31 : 64KB (32KW)

SA32 : 64KB (32KW)

SA33 : 64KB (32KW)

SA34 : 64KB (32KW)

SA35 : 64KB (32KW)

SA36 : 64KB (32KW)

SA37 : 64KB (32KW)

SA38 : 64KB (32KW)

SA39 : 64KB (32KW)

SA40 : 64KB (32KW)

SA41 : 64KB (32KW)

SA42 : 64KB (32KW)

SA43 : 64KB (32KW)

SA44 : 64KB (32KW)

SA45 : 64KB (32KW)

SA46 : 64KB (32KW)

SA47 : 64KB (32KW)

SA48 : 64KB (32KW)

SA49 : 64KB (32KW)

SA50 : 64KB (32KW)

SA51 : 64KB (32KW)

SA52 : 64KB (32KW)

SA53 : 64KB (32KW)

SA54 : 64KB (32KW)

SA55 : 64KB (32KW)

SA56 : 64KB (32KW)

SA57 : 64KB (32KW)

SA58 : 64KB (32KW)

SA59 : 64KB (32KW)

SA60 : 64KB (32KW)

SA61 : 64KB (32KW)

SA62 : 64KB (32KW)

SA63 : 64KB (32KW)

SA64 : 64KB (32KW)

SA65 : 64KB (32KW)

SA66 : 64KB (32KW)

SA67 : 64KB (32KW)

SA68 : 64KB (32KW)

SA69 : 64KB (32KW)

SA70 : 64KB (32KW)

SA81 : 64KB (32KW)

258000h

020000h

028000h

030000h

038000h

040000h

048000h

050000h

058000h

060000h

068000h

070000h

078000h

080000h

088000h

090000h

098000h

0A0000h

0A8000h

0B0000h

0B8000h

0C0000h

0C8000h

0D0000h

0D8000h

0E0000h

0E8000h

0F0000h

0F8000h

100000h

108000h

110000h

118000h

120000h

128000h

130000h

138000h

140000h

148000h

150000h

158000h

160000h

168000h

170000h

178000h

180000h

188000h

190000h

198000h

1A0000h

1A8000h

1B0000h

1B8000h

1C0000h

1C8000h

1D0000h

1D8000h

1E0000h

1E8000h

1F0000h

1F8000h

1FFFFFh

SA82 : 64KB (32KW)

260000h

SA83 : 64KB (32KW)

268000h

SA84 : 64KB (32KW)

270000h

SA85 : 64KB (32KW)

278000h

SA86 : 64KB (32KW)

280000h

SA87 : 64KB (32KW)

288000h

SA88 : 64KB (32KW)

290000h

SA89 : 64KB (32KW)

298000h

SA90 : 64KB (32KW)

2A0000h

SA91 : 64KB (32KW)

2A8000h

SA92 : 64KB (32KW)

2B0000h

SA93 : 64KB (32KW)

2B8000h

SA94 : 64KB (32KW)

2C0000h

SA95 : 64KB (32KW)

2C8000h

SA96 : 64KB (32KW)

2D0000h

SA97 : 64KB (32KW)

2D8000h

SA98 : 64KB (32KW)

2E0000h

Bank C

SA99 : 64KB (32KW)

2E8000h

SA100 : 64KB (32KW)

2F0000h

SA101 : 64KB (32KW)

2F8000h

SA102 : 64KB (32KW)

300000h

SA103 : 64KB (32KW)

308000h

SA104 : 64KB (32KW)

310000h

SA105 : 64KB (32KW)

318000h

SA106 : 64KB (32KW)

320000h

SA107 : 64KB (32KW)

328000h

SA108 : 64KB (32KW)

330000h

SA109 : 64KB (32KW)

338000h

SA110 : 64KB (32KW)

340000h

SA111 : 64KB (32KW)

348000h

SA112 : 64KB (32KW)

350000h

SA113 : 64KB (32KW)

358000h

SA114 : 64KB (32KW)

360000h

SA115 : 64KB (32KW)

368000h

SA116 : 64KB (32KW)

370000h

Bank B

SA117 : 64KB (32KW)

378000h

SA118 : 64KB (32KW)

380000h

SA119 : 64KB (32KW)

388000h

SA120 : 64KB (32KW)

390000h

SA121 : 64KB (32KW)

398000h

SA122 : 64KB (32KW)

3A0000h

SA123 : 64KB (32KW)

3A8000h

SA124 : 64KB (32KW)

3B0000h

SA125 : 64KB (32KW)

3B8000h

SA126 : 64KB (32KW)

3C0000h

SA127 : 64KB (32KW)

3C8000h

Bank D

SA128 : 64KB (32KW)

3D0000h

SA129 : 64KB (32KW)

3D8000h

SA130 : 64KB (32KW)

3E0000h

SA131 : 64KB (32KW)

3E8000h

SA132 : 64KB (32KW)

3F0000h

SA133 : 64KB (32KW)

3F8000h

SA134 : 8KB (4KW)

3F9000h

SA135 : 8KB (4KW)

3FA000h

SA136 : 8KB (4KW)

3FB000h

SA137 : 8KB (4KW)

SA138 : 8KB (4KW)

SA139 : 8KB (4KW)

SA140 : 8KB (4KW)

3FC000h

3FD000h

3FE000h

3FF000h

3FFFFFh

SA141 : 8KB (4KW)

Sector Architecture

47

MB84VZ128B/C-70

FlexBank^TMArchitecture

Bank 1

Bank

Bank 2

Combination

Splits

Volume

Combination

Volume

56M bit

40M bit

56M bit

1

2

3

4

8M bit

Bank A

Bank B

Bank C

Bank D

Remainder (Bank B, C, D)

Remainder (Bank A, C, D)

Remainder (Bank A, B, D)

Remainder (Bank A, B, C)

24M bit

8M bit

Example of Virtual Banks Combination

Bank 1

Volume Combination

Bank 2

Volume Combination

Bank

Splits

Sector Size

Bank B

+

8 × 8K byte/4 Kword

1

2

3

4

8M bit

16M bit

24M bit

32M bit

Bank A

+

56M bit

48M bit

Bank C

+

Bank D

+

15 × 64K byte/32 Kword

111 × 64K byte/32 Kword

Bank A

+

Bank D

16 × 8K byte/4 Kword

Bank B

+

Bank C

+

96 × 64K byte/32 Kword

30 × 64K byte/32 Kword

Bank A

+

Bank C

+

16 × 8K byte/4 Kword

Bank B

48 × 64K byte/32 Kword 40M bit

+

78 × 64K byte/32 Kword

Bank D

Bank A

+

8 × 8K byte/4 Kword

Bank C

+

8 × 8K byte/4 Kword

+

32M bit

+

Bank B

63 × 64K byte/32 Kword

Bank D

63 × 64K byte/32 Kword

Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which

a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B,

neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.)

Meanwhile the system would get to read from either Bank C or Bank D.

Simultaneous Operation

Case

Bank 1 Status

Read mode

Bank 2 Status

Read mode

1

2

3

4

5

6

7

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

Autoselect mode

Program mode

Erase mode *

Read mode

* : By writing erase suspend command on the bank address of sector being erased, the erase operation gets

suspended so that it enables reading from or programming the remaining sectors.

Note: Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank

consists of 4 banks, Bank A, Bank B, BankC and Bank D. Bank Address (BA) meant to specify each of the

Banks.

48

MB84VZ128B/C-70

Sector Address Tables

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

0

A²⁰

0

A¹⁹

0

A¹⁸

0

1

A¹⁷

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

0

A¹³

0

A¹²

0

1

SA0

SA1

000000h to 000FFFh

001000h to 001FFFh

002000h to 002FFFh

003000h to 003FFFh

004000h to 004FFFh

005000h to 005FFFh

006000h to 006FFFh

007000h to 007FFFh

008000h to 00FFFFh

010000h to 017FFFh

018000h to 01FFFFh

020000h to 027FFFh

028000h to 02FFFFh

030000h to 037FFFh

038000h to 03FFFFh

040000h to 047FFFh

048000h to 04FFFFh

050000h to 057FFFh

058000h to 05FFFFh

060000h to 067FFFh

068000h to 06FFFFh

070000h to 077FFFh

078000h to 07FFFFh

SA2

0

1

0

SA3

0

1

SA4

1

0

SA5

1

0

1

SA6

1

0

SA7

1

SA8

X

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

Bank A

(Continued)

49

MB84VZ128B/C-70

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

0

A²⁰

0

1

A¹⁹

1

0

1

A¹⁸

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

A¹³

X

A¹²

X

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

080000h to 087FFFh

088000h to 08FFFFh

090000h to 097FFFh

098000h to 09FFFFh

0A0000h to 0A7FFFh

0A8000h to 0AFFFFh

0B0000h to 0B7FFFh

0B8000h to 0BFFFFh

0C0000h to 0C7FFFh

0C8000h to 0CFFFFh

0D0000h to 0D7FFFh

0D8000h to 0DFFFFh

0E0000h to 0E7FFFh

0E8000h to 0EFFFFh

0F0000h to 0F7FFFh

0F8000h to 0FFFFFh

100000h to 107FFFh

108000h to 10FFFFh

110000h to 117FFFh

118000h to 11FFFFh

120000h to 127FFFh

128000h to 12FFFFh

130000h to 137FFFh

138000h to 13FFFFh

140000h to 147FFFh

148000h to 14FFFFh

150000h to 157FFFh

158000h to 15FFFFh

160000h to 167FFFh

168000h to 16FFFFh

170000h to 177FFFh

178000h to 17FFFFh

180000h to 187FFFh

188000h to 18FFFFh

190000h to 197FFFh

198000h to 19FFFFh

1A0000h to 1A7FFFh

1A8000h to 1AFFFFh

1B0000h to 1B7FFFh

1B8000h to 1BFFFFh

1C0000h to 1C7FFFh

1C8000h to 1CFFFFh

1D0000h to 1D7FFFh

1D8000h to 1DFFFFh

1E0000h to 1E7FFFh

1E8000h to 1EFFFFh

1F0000h to 1F7FFFh

1F8000h to 1FFFFFh

Bank B

(Continued)

50

MB84VZ128B/C-70

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

1

A²⁰

0

1

A¹⁹

0

1

0

A¹⁸

0

1

0

1

0

1

A¹⁷

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

A¹³

X

A¹²

X

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

200000h to 207FFFh

208000h to 20FFFFh

210000h to 217FFFh

218000h to 21FFFFh

220000h to 227FFFh

228000h to 22FFFFh

230000h to 237FFFh

238000h to 23FFFFh

240000h to 247FFFh

248000h to 24FFFFh

250000h to 257FFFh

258000h to 25FFFFh

260000h to 267FFFh

268000h to 26FFFFh

270000h to 277FFFh

278000h to 27FFFFh

280000h to 287FFFh

288000h to 28FFFFh

290000h to 297FFFh

298000h to 29FFFFh

2A0000h to 2A7FFFh

2A8000h to 2AFFFFh

2B0000h to 2B7FFFh

2B8000h to 2BFFFFh

2C0000h to 2C7FFFh

2C8000h to 2CFFFFh

2D0000h to 2D7FFFh

2D8000h to 2DFFFFh

2E0000h to 2E7FFFh

2E8000h to 2EFFFFh

2F0000h to 2F7FFFh

2F8000h to 2FFFFFh

300000h to 307FFFh

308000h to 30FFFFh

310000h to 317FFFh

318000h to 31FFFFh

320000h to 327FFFh

328000h to 32FFFFh

330000h to 337FFFh

338000h to 33FFFFh

340000h to 347FFFh

348000h to 34FFFFh

350000h to 357FFFh

358000h to 35FFFFh

360000h to 367FFFh

368000h to 36FFFFh

370000h to 377FFFh

378000h to 37FFFFh

Bank C

(Continued)

51

MB84VZ128B/C-70

(Continued)

Sector Address

Address Range

Word Mode

Bank

Sector

Bank Address

A²¹

1

A²⁰

1

A¹⁹

1

A¹⁸

0

1

A¹⁷

0

1

0

1

A¹⁶

0

1

0

1

0

1

0

1

A¹⁵

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A¹⁴

X

0

A¹³

X

0

A¹²

X

0

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

380000h to 387FFFh

388000h to 38FFFFh

390000h to 397FFFh

398000h to 39FFFFh

3A0000h to 3A7FFFh

3A8000h to 3AFFFFh

3B0000h to 3B7FFFh

3B8000h to 3BFFFFh

3C0000h to 3C7FFFh

3C8000h to 3CFFFFh

3D0000h to 3D7FFFh

3D8000h to 3DFFFFh

3E0000h to 3E7FFFh

3E8000h to 3EFFFFh

3F0000h to 3F7FFFh

3F8000h to 3F8FFFh

3F9000h to 3F9FFFh

3FA000h to 3FAFFFh

3FB000h to 3FBFFFh

3FC000h to 3FCFFFh

3FD000h to 3FDFFFh

3FE000h to 3FEFFFh

3FF000h to 3FFFFFh

Bank D

0

1

0

1

0

1

0

1

0

1

0

1

52

MB84VZ128B/C-70

Sector Group Addresses

Sector Group

SGA0

A²¹

0

A²⁰

0

A¹⁹

0

A¹⁸

0

A¹⁷

0

A¹⁶

0

1

X

0

1

A¹⁵

0

1

0

1

X

0

1

0

1

A¹⁴

0

1

A¹³

0

1

0

1

A¹²

0

1

0

1

0

1

0

1

Sectors

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SGA1

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

X

SGA8

0

SA8 to SA10

SGA9

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SGA25

SGA26

SGA27

SGA28

SGA29

SGA30

SGA31

SGA32

SGA33

SGA34

SGA35

SGA36

SGA37

SGA38

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

SA11 to SA14

SA15 to SA18

SA19 to SA22

SA23 to SA26

SA27 to SA30

SA31 to SA34

SA35 to SA38

SA39 to SA42

SA43 to SA46

SA47 to SA50

SA51 to SA54

SA55 to SA58

SA59 to SA62

SA63 to SA66

SA67 to SA70

SA71 to SA74

SA75 to SA78

SA79 to SA82

SA83 to SA86

SA87 to SA90

SA91 to SA94

SA95 to SA98

SA99 to SA102

SA103 to SA106

SA107 to SA110

SA111 to SA114

SA115 to SA118

SA119 to SA122

SA123 to SA126

SA127 to SA130

X

SGA39

1

SA131 to SA133

SGA40

SGA41

SGA42

SGA43

SGA44

SGA45

SGA46

SGA47

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

53

MB84VZ128B/C-70

Flash Memory Autoselect Codes

Type

A²¹to A¹²

BA

A⁶

L

A³

L

A²

L

A¹

L

A⁰

L

Code (HEX)

04h

Manufacture’s Code

Device Code

BA

L

H

L

227Eh

2202h

BA

L

H

Extended Device

Code *²

BA

L

H

2201h

Sector Group

Protection

Sector Group

Addresses

L

H

L

01h*¹

Legend: L = V^IL, H = VIH. See DC Characteristics for voltage levels.

*1 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*2 : A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore the system may continue reading out

these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.

54

MB84VZ128B/C-70

Flash Memory Command Definitions

Fourth Bus

First Bus

Second Bus Third Bus

Fifth Bus

Sixth Bus

Bus

Write

Cycles

Req’d

Read/Write

Cycle

Command

Sequence

Write Cycle Write Cycle Write Cycle

Write Cycle Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Read/Reset

1

3

XXXh F0h

—

555h AAh 2AAh 55h 555h F0h

RA

RD

(BA)

Autoselect

Program

3

555h AAh 2AAh 55h

90h

—

555h

555h AAh 2AAh 55h 555h A0h

4

1

PA

—

PD

—

Program

Suspend

BA

B0h

30h

—

Program

Resume

1

—

Chip Erase

6

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h

Sector Erase

555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h

SA

30h

Erase

Suspend

1

BA

B0h

30h

—

Erase

Resume

—

Extended

Sector Group

4

XXXh 60h

SPA

60h

SPA

40h

SPA

SD

—

Protection *²

Set to

3

2

555h AAh 2AAh 55h 555h 20h

—

Fast Mode

Fast

XXXh A0h

PA

90h XXXh

98h

PD

—

Program *¹

4

*

Reset from

2

BA

—

Fast Mode *¹

F0h

—

(BA)

55h

Query

1

3

4

—

HiddenROM

Entry

555h AAh 2AAh 55h 555h 88h

(HRA)

PA

HiddenROM

Program *³

555h AAh 2AAh 55h 555h A0h

PD

(HRBA)

555h

HiddenROM

Exit *³

4

555h AAh 2AAh 55h

90h XXXh 00h

—

(Continued)

55

MB84VZ128B/C-70

(Continued)

*1: This command is valid during Fast Mode.

*2: This command is valid while RESET = VID.

*3: This command is valid during HiddenROM mode.

*4: The data “00h” is also acceptable.

Notes : • Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA),

Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).

• Bus operations are defined in “■ DEVICE BUS OPERATION”.

• RA = Address of the memory location to be read

PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and

A12 will uniquely select any sector.

BA = Bank Address (A21, A20, A19)

• RD = Data read from location RA during read operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.

• SPA =Sector group address to be protected. Set sector group address and

(A⁶, A3, A2, A1, A0) = (0, 0, 0, 1, 0).

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output

00h at unprotected sector group addresses.

• HRA = Address of the HiddenROM area: 000000h to 00007Fh

• HRBA = Bank Address of the HiddenROM area (A21 = A20 = A19 = VIL)

• The system should generate the following address patterns: 555h or 2AAh to addresses A10 to A0

• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

• The command combinations not described in this table are illegal.

56

MB84VZ128B/C-70

2. AC CHARACTERISTICS

• Read Only Operations Characteristics (Flash)

Symbol

Value*

Parameter

Read Cycle Time

Condition

Unit

JEDEC

Standard

Min

Max

t^AVAV

tRC

—

70

—

ns

CEf = VIL

OE = VIL

Address to Output Delay

t^AVQV

tACC

—

70

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High-Z

Output Enable to Output High-Z

tELQV

t^GLQV

t^EHQZ

tGHQZ

tCEf

tOE

tDF

OE = VIL

—

70

30

25

ns

—

Output Hold Time From Addresses,

CEf or OE, Whichever Occurs First

tAXQX

tOH

—

0

—

ns

µs

RESET Pin Low to Read Mode

—

tREADY

—

20

*: Test Conditions– Output Load : 1 TTL gate and 30 pF

Input rise and fall times : 5 ns

Input pulse levels : 0.0 V to V^CCf

Timing measurement reference level

Input : 0.5×VCCf

Output : 0.5×VCCf

57

MB84VZ128B/C-70

• Read Operation Timing Diagram (Flash)

t

RC

Address

Address Stable

t

ACC

CE

OE

t

OE

tDF

t

OEH

WE

t

OH

t

CE

High-Z

Outputs Valid

Outputs

• Hardware Reset/Read Operation Timing Diagram (Flash)

tRC

Address

Address Stable

tACC

CEf

tRH

tRP

tRH

tCE

RESET

Outputs

tOH

High-Z

Outputs Valid

58

MB84VZ128B/C-70

• Write/Erase/Program Operations (Flash)

Symbol

Standard

Value

Unit

Parameter

JEDEC

tAVAV

Min

70

0

Typ

Max

Write Cycle Time

tWC

tAS

ns

Address Setup Time

t^AVWL

Address Setup Time to OE Low During Toggle Bit

Polling

t^ASO

tAH

12

30

0

ns

Address Hold Time

tWLAX

Address Hold Time from CEf or OE High During

Toggle Bit Polling

t^AHT

Data Setup Time

Data Hold Time

t^DVWH

tDS

tDH

25

0

ns

tWHDX

Output

Read

0

Enable Hold

Time

tOEH

Toggle and Data Polling

10

ns

CEf High During Toggle Bit Polling

OE High During Toggle Bit Polling

Read Recover Time Before Write

CEf Setup Time

tCEPH

tOEPH

tGHWL

tGHEL

tCS

20

0

ns

µs

s

tGHWL

tGHEL

0

tELWL

0

WE Setup Time

tWLEL

tWS

0

CEf Hold Time

tWHEH

tEHWH

tWLWH

tELEH

tCH

0

WE Hold Time

tWH

0

Write Pulse Width

tWP

35

20

CEf Pulse Width

tCP

Write Pulse Width High

CEf Pulse Width High

tWHWL

tEHEL

tWPH

tCPH

tWHWH1

tWHWH2

tVCS

tRB

Programming Operation

Sector Erase Operation *

VCCf Setup Time

t^WHWH1

t^WHWH2

6

0.5

50

0

µs

ns

µs

Recover Time from RY/BY

RESET Pulse Width

tRP

500

200

RESET High Level Period Before Read

Program/Erase Valid to RY/BY Delay

Delay Time from Embedded Output Enable

Erase Time-out Time

tRH

tBUSY

t^EOE

tTOW

tSPD

90

70

50

Erase Suspend Transition Time

20

* : This does not include preprogramming time.

59

MB84VZ128B/C-70

• Write Cycle (WE control) (Flash)

3rd Bus Cycle

Data Polling

PA

555h

PA

Address

tWC

tRC

tAS

tAH

CEf

tCS

tCH

tCE

OE

tOE

tWP

tWPH

tWHWH1

tGHWL

WE

tOH

tDF

tDH

tDS

A0h

PD

DOUT

DQ7

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

60

MB84VZ128B/C-70

• Write Cycle (CEf control) (Flash)

3rd Bus Cycle

555h

Data Polling

PA

Address

WE

t

WC

t

AS

tAH

t

WS

t

WH

OE

t

CPH

t

CP

t

WHWH1

t

GHEL

CEf

t

DS

t

DH

A0h

PD

DOUT

DQ7

Data

Notes : • PA is address of the memory location to be programmed.

• PD is data to be programmed at word address.

• DQ7 is the output of the complement of the data written to the device.

• DOUT is the output of the data written to the device.

• Figure indicates last two bus cycles out of four bus cycle sequence.

61

MB84VZ128B/C-70

• AC Waveforms Chip/Sector Erase Operations (Flash)

555h

tWC

2AAh

555h

2AAh

SA*

Address

CEf

tAS

tAH

tCS

tCH

OE

tWP

tWPH

tGHWL

WE

tDS

tDH

30h for Sector Erase

10h/

30h

AAh

55h

80h

AAh

55h

Data

VCCf

tVCS

* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.

62

MB84VZ128B/C-70

• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)

CEf

tCH

tDF

tOE

OE

tOEH

WE

tCE

*

High-Z

DQ7 =

Data

DQ7

Valid Data

tWHWH1 or 2

DQ6 to DQ0 =

Output Flag

DQ6 to DQ0

Valid Data

DQ6 to DQ0

RY/BY

tEOE

tBUSY

* : DQ⁷= Valid Data (the device has completed the Embedded operation) .

63

MB84VZ128B/C-70

• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)

Address

tAHT tASO

tAHT tAS

CEf

WE

tCEPH

tOEPH

tOEH

OE

tOE

tCE

tDH

*

Stop

Output

Valid

Toggle

Data

Toggle

Data

Toggle

Data

DQ 6/DQ2

Data

Toggling

tBUSY

RY/BY

* : DQ6 stops toggling (the device has completed the Embedded operation).

64

MB84VZ128B/C-70

• Bank-to-bank Read/Write Timing Diagram (Flash)

Read

Command

Read

Command

Read

tRC

tWC

tRC

tWC

tRC

BA2

(PA)

BA2

(PA)

Address

CEf

BA1

(555h)

tACC

tCE

tAS

tAH

tAHT

tOE

tCEPH

OE

WE

DQ

tDF

tGHWL

tOEH

tWP

tDS

tDH

tDF

Valid

Output

Valid

Output

Valid

Output

Status

Intput

(A0h)

(PD)

Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.

BA1 : Address corresponding to Bank 1

BA2 : Address corresponding to Bank 2

65

MB84VZ128B/C-70

• RY/BY Timing Diagram during Write/Erase Operations (Flash)

CEf

Rising edge of the last WE signal

WE

Entire programming

or erase operations

RY/BY

tBUSY

• RESET, RY/BY Timing Diagram (Flash)

WE

RESET

tRP

tRB

RY/BY

tREADY

66

MB84VZ128B/C-70

• Temporary Sector Unprotection (Flash)

VCCf

tVIDR

tVCS

tVLHT

VID

VIH

RESET

CEf

WE

tVLHT

Program or Erase Command Sequence

RY/BY

Unprotection period

• Acceleration Mode Timing Diagram (Flash)

V^CCf

tVACCR

tVCS

tVLHT

VACC

VIH

WP/ACC

CEf

WE

tVLHT

Program Sequence

RY/BY

Acceleration period

67

MB84VZ128B/C-70

• Extended Sector Group Protection (Flash)

VCC

tVCS

tVLHT

RESET

tWC

tVIDR

Address

SPAX

SPAY

A6, A3,

A2, A0

A1

CE

OE

TIME-OUT

tWP

WE

60h

40h

01h

60h

Data

tOE

SPAX : Sector Group Address to be protected

SPAY : Next Sector Group Address to be protected

TIME-OUT : Time-Out window = 250 µs (Min)

68

MB84VZ128B/C-70

3. Erase and Programming Performance (Flash)

Value

Parameter

Unit

Remarks

Min

—

Typ

0.5

6

Max

2.0

100

95

Sector Erase Time

s

Excludes programming time prior to erasure

Word Programming Time

Chip Programming Time

Erase/Program Cycle

—

µs Excludes system-level overhead

—

25.2

—

s

Excludes system-level overhead

100,000

—

cycle

Typical Erase conditions TA = + 25°C, VCCf_1 & VCCf_2 = 2.9 V

Typical Program conditions TA = + 25°C, VCCf_1 & VCCf_2 = 2.9 V, Data= Checker

69

MB84VZ128B/C-70

■ 64 M FCRAM for MCP

1. FCRAM Power Down Program Key Table*¹

Basic Key Table

Definition

A¹⁶

A¹⁷

A¹⁹

A²⁰

A²¹

KEY

Mode Select

Area Select

A¹⁹

A²⁰

L

A²¹

AREA

BOTTOM *²

RESERVED

TOP *³

L

X

H

L

H

A¹⁶

A¹⁷

MODE

NAP *⁴

L

H

L

RESERVED

16M Partial

SLEEP *^4,*⁵

H

Available Key Table

A¹⁶

A¹⁷

A¹⁹

A²⁰

A²¹

Data Retention

MODE

NAP

Area

Mode Select

Area Select

L

H

L

X

L

X

L

X

L

None

Bottom 16 M only

Top 16 M only

None

16M Partial

SLEEP

L

H

X

H

X

H

X

H

*1 : The Power Down Program can be performed one time after compliance of Power-up timings and it

should not be re-programmed after regular Read or Write.

Unspecified addresses, A15 to A0, can be either High or Low during the programming.

The RESERVED key should not be used.

*2 : BOTTOM area is from the lowest address location. (i.e., A(20:0) = L)

*3 : TOP area is from the highest address location. (i.e., A(20:0) = H)

*4 : NAP and SLEEP do not retain the data and Area Select is ignored.

*5 : Default state. Power Down Program to this SLEEP mode can be omitted.

70

MB84VZ128B/C-70

2. AC CHARACTERISTICS

• READ OPERATION (FCRAM)

Value

Parameter

Symbol

Unit

Remarks

Min

Max

Read Cycle Time

tRC

t^CE

70

—

5

—

65

40

65

—

ns

Chip Enable Access Time

Output Enable Access Time

Address Access Time

*1,*3

*1

t^OE

t^AA

*1,*4

*1

Output Data Hold Time

t^OH

CE1r Low to Output Low-Z

OE Low to Output Low-Z

CE1r High to Output High-Z

OE High to Output High-Z

Address Setup Time to CE1r Low

tCLZ

5

—

*2

tOLZ

0

—

*2

tCHZ

—

–5

25

10

–5

10

—

70

45

–5

25

45

12

25

12

20

—

*2

tOHZ

tASC

*2

*5

tASO

t^ASO(ABS)

tBSC

—

*3,*6

*7

Address Setup Time to OE

—

LB / UB Setup Time to CE1r Low

LB / UB Setup Time to OE Low

Address Invalid Time

—

*5

tBSO

t^AX

—

5

ns

*4,*8

*4

Address Hold Time from CE1r Low

Address Hold Time from OE Low

Address Hold Time from CE1r High

Address Hold Time from OE High

LB / UB Hold Time from CE1r High

LB / UB Hold Time from OE High

CE1r Low to OE Low Delay Time

OE Low to CE1r High Delay Time

CE1r High Pulse Width

tCLAH

tOLAH

tCHAH

tOHAH

tCHBH

tOHBH

tCLOL

tOLCH

tCP

—

*4,*9

—

1000

—

ns

*3,*6,*9,*10

*9

—

t^OP

1000

—

*6,*9,*10

*7

OE High Pulse Width

t^OP(ABS)

*1 : The output load is 30pF.

*2 : The output load is 5pF.

*3 : The t^CEis applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of

both or either t^ASOor tCLOL is shorter than specified value.

*4 : Applicable only to A⁰and A1 when both CE1r and OE are kept at Low for the address access.

*5 : Applicable if OE is brought to Low before CE1r goes Low.

*6 : The t^ASO, tCLOL(Min) and tOP(Min) are reference values when the access time is determined by tOE.

If actual value of each parameter is shorter than specified minimum value, t^OEbecome longer by the amount

of subtracting actual value from specified minimum value.

For example, if actual t^ASO, tASO(actual), is shorter than specified minimum value, tASO(Min), during OE control

access (ie., CE1r stays Low), the tOE become tOE(Max) + tASO(Min) – tASO(actual).

*7 : The t^ASO(ABS)and tOP(ABS) is the absolute minimum value during OE control access.

*8 : The t^AXis applicable when both A0 and A1 are switched from previous state.

*9 : If actual value of either t^CLOLor tOP is shorter than specified minimum value, both tOLAH and tOLCH become

t^RC(Min) – tCLOL(actual) or tRC(Min) – tOP(actual).

*10 : Maximum value is applicable if CE1r is kept at Low.

71

MB84VZ128B/C-70

• WRITE OPERATION (FCRAM)

Parameter

Value

Symbol

Unit Remarks

Min

Max

Write Cycle Time

t^WC

tAS

70

0

—

ns

*1

*2

Address Setup Time

Address Hold Time

CE1r Write Setup Time

CE1r Write Hold Time

WE Setup Time

tAH

35

0

—

tCS

1000

—

tCH

0

tWS

0

WE Hold Time

tWH

0

—

LB and UB Setup Time

LB and UB Hold Time

OE Setup Time

tBS

–5

0

—

tBH

—

tOES

t^OEH

tOEH(ABS)

tOHCL

tOHAH

tCW

1000

—

*3

*3, *4

*5

25

12

–5

45

10

15

0

OE Hold Time

OE High to CE1r Low Setup Time

OE High to Address Hold Time

CE1r Write Pulse Width

WE Write Pulse Width

CE1r Write Recovery Time

WE Write Recovery Time

Data Setup Time

—

*6

—

*7

—

*1, *8

*1, *9

*1, *3, *9

tWP

—

tWRC

tWR

—

1000

—

t^DS

Data Hold Time

t^DH

—

CE1r High Pulse Width

tCP

12

—

*9

*1 : Minimum value must be equal or greater then the sum of actual t^CW(or tWP) and tWRC (or tWR).

*2 : New write address is valid from either CE1r or WE is bought to High.

*3 : The tOEH is specified from end of tWC(Min). The tOEH(Min) is a reference value when the access time is determined

by tOE.

If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of

subtracting actual value from specified minimum value.

*4 : The t^OEH(Max) is applicable if CE1r is kept at Low and both WE and OE are kept at High.

*5 : The t^OEH(ABS) is the absolute minimum value if write cycle is termnated by WE and CE1r stays Low.

*6 : tOHCL(Min) must be satisfied if read operation is not performed prior to write operation.

In case OE is disabled after tOHCL(Min), WE Low must be asserted after tRC(Min) from CE1r Low.

In other words, read operation is initiated if tOHCL (Min) is not satisfied.

*7 : Applicable if CE1r stays Low after read operation.

*8 : t^CWand tWP is applicable if write operation is initiated by CE1r and WE, respectively.

*9 : tWRC and tWR is applicable if write operation is terminated by CE1r and WE, respectively.

The tWR(Min) can be ignored if CE1r is brought to High together or after WE is brought to High.

In such case, the tCP(Min) must be satisfied.

72

MB84VZ128B/C-70

• POWER DOWN and POWER DOWN PROGRAM PARAMETERS (FCRAM)

Value

Parameter

Symbol

Unit

Remarks

Min

10

Max

—

CE2r Low Setup Time for Power Down Entry

CE2r Low Hold Time after Power Down Entry

t^CSP

ns

tC2LP

70

—

CE1r High Hold Time following CE2r High after

Power Down Exit(SLEEP mode only)

tCHH

tCHHN

tCHS

350

1

—

µs

ns

CE1r High Setup Time following CE2r High after

Power Down Exit(Except for SLEEP mode)

CE1r High Setup Time following CE2r High after

Power Down Exit

10

CE1r High to PE Low Setup Time

PE Power Down Program Pulse Width

PE High to CE1r Low Hold Time

Address Setup Time to PE High

Address Setup Time from PE High

tEPS

tEP

70

15

0

—

ns

*

tEPH

tEAS

tEAH

* : Applicable to Down Program.

• OTHER TIMING PARAMETERS (FCRAM)

Parameter

Value

Symbol

Unit Remarks

Min

Max

CE1r High to OE Invalid Time for Standby Entry

tCHOX

tCHWX

10

—

ns

CE1r High to WE Invalid Time for Standby Entry

CE2r Low Hold Time after Power-up

10

50

—

ns

µs

*1

*2

*3

t^C2LH

CE2r High Hold Time after Power-up

tC2HL

CE1r High Hold Time following CE2r High after

Power-up

tCHH

tT

350

1

—

µs

*2

*4

Input Transition Time

25

ns

*1 : It may write some data into any address location if t^CHWXis not satisfied.

*2 : Must satisfy tCHH(Min) after tC2LH(Min).

*3 : Requires Power Down mode entry and exit after tC2HL.

*4 : The input Trasition Time(tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate

AC specification of some timing parameters.

• AC TEST CONDITIONS (FCRAM)

Symbol

V^IH

Description

Input High Level

Test Setup

Value

VCCr

Unit

V

Remarks

—

V^IL

Input Low Level

—

VSS

V

V^REF

t^T

Input Timing Measurement Level

Input Transition Time

—

VCCr × 0.5

5

V

Between VIL and VIH

ns

73

MB84VZ128B/C-70

• READ Timing #1 (OE Control Access) (FCRAM)

tRC

Address

Address Valid

tOHAH

tCE

tASO

tOHAH

CE1r

tOLCH

tOP

tOE

tCLOL

tOE

OE

tASO

tBSO

tOHBH

tBSO

tOHBH

LB / UB

tOHZ

tOLZ

tOH

tOLZ

tOH

DQ

(Output)

Valid Data Output

Note : CE2r, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

74

MB84VZ128B/C-70

• READ Timing #2 (CE1r Control Access) (FCRAM)

tRC

Address

CE1r

Address Valid

tCHAH

tASC

tCE

tCHAH

tASC

tCE

tCP

OE

tBSC

tCHBH

tBSC

tCHBH

LB / UB

tCHZ

tOH

tCHZ

tOH

tCLZ

DQ

(Output)

Valid Data Output

Note : CE2r, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

75

MB84VZ128B/C-70

• READ Timing #3 (Address Access after OE Control Access) (FCRAM)

tRC

Address

(A²¹to A3)

Address Valid

Address Valid (No change)

Address

(A²to A0)

Address Valid

tOHAH

tASO

tOLAH

tAA

tAX

CE1r

tOE

tOHZ

OE

tBSO

tOHBH

LB / UB

tOLZ

tOH

DQ

(Output)

Valid Data Output

Note : CE2r, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

76

MB84VZ128B/C-70

• READ Timing #4 (Address Access after CE1r Control Access) (FCRAM)

tRC

Address

(A²¹to A3)

Address Valid

Address Valid (No change)

Address

(A²to A0)

Address Valid

tCHAH

tASC

tCLAH

tAA

tAX

CE1r

tCE

tCHZ

OE

tBSC

tCHBH

LB / UB

tOH

tCLZ

DQ

(Output)

Valid Data Output

Note : CE2r, PE and WE must be High for entire read cycle.

Either or both LB and UB must be Low when both CE1r and OE are Low.

77

MB84VZ128B/C-70

• WRITE Timing #1 (CE1r Control) (FCRAM)

tWC

Address

CE1r

Address Valid

tAS

tAH

tAS

tCW

tWRC

tWS

tBS

tWH

tBH

tWS

WE

tBS

UB, LB

tOHCL

OE

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r and PE must be High for write cycle.

78

MB84VZ128B/C-70

• WRITE Timing #2-1 (WE Control,Single Write Operetion) (FCRAM)

tWC

Address

CE1r

WE

Address Valid

tOHAH

tAS

tAH

tAS

tCH

tCP

tOHCL

tCS

tWP

tWR

tOHBH

tBS

tBH

UB, LB

OE

tOES

tOHZ

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r and PE must be High for write cycle.

79

MB84VZ128B/C-70

• WRITE Timing #2-2 (WE Control,Continuous Write Operetion) (FCRAM)

tWC

Address

CE1r

WE

Address Valid

tOHAH

tAS

tAH

tAS

tOHCL

tCS

tWP

tWR

tBH

tBS

tBH

tBS

UB, LB

OE

tOES

tOHZ

tDS

tDH

DQ

(Input)

Valid Data Input

Note : CE2r and PE must be High for write cycle.

80

MB84VZ128B/C-70

• READ / WRITE Timing #1-1 (CE1r Control) (FCRAM)

tWC

Address

CE1r

Write Address

Read Address

tCHAH

tAS

tAH

tASC

tCP

tWRC

tCW

tWH

t^WS

tWH

tBH

tWS

tCLOL

tBSO

WE

tCHBH

tBS

UB, LB

OE

tOHCL

tCHZ

tDH

tOH

tDS

tOLZ

DQ

Read Data Output

Write Data Input

Note : Write address is valid from either CE1r or WE of last falling edge.

81

MB84VZ128B/C-70

• READ / WRITE Timing #1-2 (CE1r Control) (FCRAM)

tRC

Address

CE1r

Read Address

Write Address

tASC

tCHAH

tAS

tWRC

tWRC(Min)

tWH

tCP

tWS

tCE

tWH

tWS

WE

UB, LB

OE

tBH

tBSC

tCHBH

tBS

tOEH

tOHCL

tCHZ

tDH

tCLZ

tOH

DQ

Write Data Input

Read Data Output

Note : The t^OEHis specified from the time satisfied both tWRC and tWR (Min).

82

MB84VZ128B/C-70

• READ(OE Control) / WRITE(WE Control) Timing #2-1 (FCRAM)

tWC

Address

Read Address

Write Address

tOHAH

tAS

tAH

tASO

CE1r

WE

Low

tWP

tWR

tOEH

tBSO

tOHBH

tBS

tBH

UB, LB

OE

tOES

tOHZ

tOH

tDS

tDH

tOLZ

DQ

Read Data Output

Write Data Input

Note : CE1r can be tied to Low for WE and OE controlled operation.

When CE1r is tied to Low, output is exclusively controlled by OE.

83

MB84VZ128B/C-70

• READ(OE Control) / WRITE(WE Control) Timing #2-2

tRC

Address

CE1r

Read Address Valid

Write Address

tOHAH

tAS

tASO

Low

tWR

tOEH

WE

tBSO

tOHBH

tBH

tBS

UB, LB

OE

tOE

tOES

tOHZ

tOH

tDH

tOLZ

DQ

Write Data Input

Read Data Output

Note : CE1r can be tied to Low for WE and OE controlled operation.

When CE1r is tied to Low, output is exclusively controlled by OE.

• POWER DOWN PROGRAM Timing (FCRAM)

CE1r

tEPS

tEP

tEPH

PE

tEAS

tEAH

Address

(A²¹to A16)

KEY

Note : CE2r must be High for Power Down Programming.

Any other inputs not specified above can be either High or Low.

84

MB84VZ128B/C-70

• POWER DOWN Entry and Exit Timing (FCRAM)

CE1r

tCHS

CE2r

tCSP

tC2LP

tCHH (tCHHN)

High-Z

DQ

Power Down Entry

Power Down Mode

Power Down Exit

Note : This Power Down mode can be also used for Power-up #2 below except that t^CHHNcan not be used at

Power-up timing.

• POWER-UP Timing #1 (FCRAM)

CE1r

tCHS

tC2LH

tCHH

CE2r

VCCr

VCCr Min

0V

Note : The tC2LH specifies after VCCr reaches specified minimum level.

• POWER-UP Timing #2 (FCRAM)

CE1r

tCHS

tCSP

tC2HL

tC2LP

tCHH

CE2r

tC2HL

VCCr

VCCr Min

0V

Note : The t^C2HLspecifies from CE2r Low to High transition after VCCr reaches specified minimum level.

CE1r must be brought to High prior to or together with CE2r Low to High transition.

85

MB84VZ128B/C-70

• Standby Entry Timing after Read or Write (FCRAM)

CE1r

tCHOX

tCHWX

OE

WE

Active (Read)

Standby

Active (Write)

Standby

Note : Both t^CHOXand tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it

takes tRC (Min) period from either last address transition of A0 and A1, or CE1r Low to High transition.

86

MB84VZ128B/C-70

3. Data Retention Low V^CCr Characteristics (FCRAM)

Value

Parameter

Symbol

VDR

Test Conditions

Unit

V

Min

Max

CE1r = CE2r ≥ VCCr – 0.2 V or,

CE1r = CE2r = VIH

V^CCr Data Retention Supply Voltage

2.3

3.1

2.3 V ≤ VCCr ≤ 2.7 V,

V^IN= VIH or VIL

CE1r = CE2r = VIH, I^OUT= 0 mA

I^DR

—

1.5

mA

V^CCr Data Retention Supply Current

2.3 V ≤ VCCr ≤ 2.7 V,

V^IN≤ 0.2 V or V^IN≥ VCCr – 0.2 V,

CE1r = CE2r ≥ VCCr – 0.2 V, I^OUT= 0 mA

I^DR1

150

µA

2.7 V ≤ VCCr ≤ 3.1 V

at data retention entry

Data Retention Setup Time

Data Retention Recovery Time

V^CCr Voltage Transition Time

t^DRS

0

—

ns

2.7 V ≤ VCCr ≤ 3.1 V

after data retention

t^DRR

200

0.2

∆V/∆t

—

V/µs

Note : 2.2 ≤ V^IH≤ VCCr+0.3 V

• Data Retention Timing

tDRS

tDRR

3.1 V

VCCr

2.7 V

∆V/∆t

CE2r

2.3 V

>VCCr-0.2 V or VIH Min

CE1r

0.4 V

VSS

Data Retention Mode

Data bus must be in High-Z at data retention entry.

87

MB84VZ128B/C-70

■ 8 M SRAM for MCP

1. AC Characteristics

• Read Cycle (SRAM)

Value

Parameter

Symbol

Unit

Min

70

—

5

Max

—

Read Cycle Time

t^RC

t^AA

ns

Address Access Time

70

35

70

—

Chip Enable (CE1s) Access Time

Chip Enable (CE2s) Access Time

Output Enable Access Time

tCO1

tCO2

t^OE

LB, UB to Output Valid

tBA

Chip Enable (CE1s Low and CE2s High) to Output Active

Output Enable Low to Output Active

LB, UB Enable Low to Output Active

Chip Enable (CE1s High or CE2s Low) to Output High-Z

Output Enable High to Output High-Z

LB, UB Output Enable to Output High-Z

Output Data Hold Time

tCOE

tOEE

tBE

0

—

0

—

tOD

—

10

25

—

tODO

tBD

t^OH

Note: Test Conditions–Output Load:1 TTL gate and 30 pF

Input rise and fall times: 5 ns

Input pulse levels: 0.0 V to 3.0 V

Timing measurement reference level

Input: 0.5 × V^CCs

Output: 0.5 × VCCs

88

MB84VZ128B/C-70

• Read Cycle (SRAM)

t^RC

Address

CE1s

t^AA

t^OH

t^CO1

t^COE

t^OD

t^CO2

CE2s

t^OD

t^OE

OE

t^ODO

t^OEE

LB, UB

t^BA

t^BD

t^BE

t^COE

DQ

Valid Data Output

Note: WE remains HIGH for the read cycle.

89

MB84VZ128B/C-70

• Write Cycle (SRAM)

Parameter

Value

Symbol

Unit

Min

70

50

55

0

Max

—

25

—

Write Cycle Time

t^WC

tWP

t^CW

t^AW

tBW

t^AS

ns

Write Pulse Width

Chip Enable to End of Write

Address valid to End of Write

LB, UB to End of Write

Address Setup Time

Write Recovery Time

WE Low to Output High-Z

WE High to Output Active

Data Setup Time

t^WR

tODW

tOEW

tDS

0

—

0

30

0

Data Hold Time

t^DH

90

MB84VZ128B/C-70

• Write Cycle*¹(WE control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

CE1s

CE2s

t^AW

t^CW

t^BW

LB, UB

t^OEW

t^ODW

D^OUT

*2

*4

*3

t^DS

t^DH

D^IN

Valid Data Input

*4

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the output

will remain at high impedance.

*3 : If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the output

will remain at high impedance.

*4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

91

MB84VZ128B/C-70

• Write Cycle*¹(CE1s control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^AW

t^CW

CE1s

CE2s

t^CW

t^BW

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

*2

Valid Data Input

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

92

MB84VZ128B/C-70

• Write Cycle*¹(CE2s Control) (SRAM)

t^WC

Address

t^AS

t^WP

t^WR

WE

t^CW

CE1s

CE2s

t^AW

t^CW

t^BW

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

D^IN

*2

Valid Data Input

*2

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity

must not be applied.

93

MB84VZ128B/C-70

• Write Cycle*¹(LB, UB Control) (SRAM)

t^WC

Address

WE

t^WP

t^WR

t^CW

CE1s

CE2s

t^CW

t^AW

t^BW

t^AS

LB, UB

t^BE

t^COE

t^ODW

D^OUT

t^DS

t^DH

*2

Valid Data Input

*2

D^IN

*1 : If OE is HIGH during the write cycle, the outputs will remain at high impedance.

*2 : Because I/O signals may be in the output state at this Time, input signals of reverse

polarity must not be applied.

94

MB84VZ128B/C-70

2. Data Retantion Characteristics (SRAM)

Parameter

Value

Unit

Symbol

Min

1.5

—

Typ

—

Max

3.1

15

Data Retention Supply Voltage

V^DH

IDDS2

t^CDR

tR

V

Standby Current

VDH = 3.0 V

—

µA

ns

Chip Deselect to Data Retention Mode Time

Recovery Time

0

—

tRC

—

Note : t^RC: Read cycle time

• CE1s Controlled Data Retention Mode*¹

VCCs

Data Retention Mode

2.7 V

*2

V^IH

VDH

V^CCS– 0.2 V

t^CDR

t^R

CE1s

VSS

*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to VCCs–0.2 V or VSS

to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to

VCCs+0.3 V.

*2 : When CE1s is operating at the VIH Min level, the standby current is given by ISB1s during the transition

of VCCs from Vccs Max to VIH Min level.

• CE2s Controlled Data Retention Mode*³

V^CCs

Data Retention Mode

2.7 V

V^DH

V^IH

t^CDR

t^R

CE2s

V^IL

0.2 V

V^SS

*3 : In CE2s controlled data retention mode, input and input/output pins can be used between

–0.3 V to Vccs+0.3 V.

95

MB84VZ128B/C-70

■ PIN CAPACITANCE

Value

Typ

Parameter

Symbol

Condition

Unit

Min

Max

30.0

35.0

Input Capacitance

C^IN

VIN = 0

pF

Output Capacitance

COUT

C^IN2

VOUT = 0

VIN = 0

Control Pin Capacitance

Note: Test conditions Ta = + 25°C, f = 1.0 MHz

■ HANDLING OF PACKAGE

Please handle this package carefully since the sides of package create acute angles.

■ CAUTION

• The high voltage (VID) cannot apply to address pins and control pins except RESET_1 or RESET_2. Exception

is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to

RESET_1 or RESET_2.

• Without the high voltage (V^ID) , sector group protection can be achieved by using “Extended Sector Group

Protection” command.

96

MB84VZ128B/C-70

■ ORDERING INFORMATION

MB84VZ128B

-70

PBS

Package Type

PBS = 115-ball FBGA

Speed Option

Device Number/Description

128Mega-bit (8M x 16 bit) Page Mode Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

64Mega-bit (4M x 16 bit) Dual Operation Flash Memory

3.0 V-only Read, Program, and Erase

64Mega-bit (2M x 16 bit) FCRAM

8Mega-bit (512K x 16 bit) SRAM

97

MB84VZ128B/C-70

■ PACKAGE DIMENSION

115-ball plastic FBGA

(BGA-115P-M03)

12.00±0.10(.472±.004)

0.20(.008)

S B

B

1.25±0.10

0.40(.016)

REF

0.80(.031)

REF

(Seated height)

(.049±.004)

10

9

8

7

6

5

4

3

2

1

0.80(.031)

REF

A

9.00±0.10

(.354±.004)

0.40(.016)

REF

0.08(.003)

S

0.10±0.05

(.004±.002)

(Stand off)

P

N M L

K

J

H

G

F

E

D

C

B

B A

INDEX-MARK AREA

S

115-ø0.40 ⁺^–0^.0^.0¹⁵⁰

115-ø.016 ⁺^–.^.⁰⁰⁰⁰²⁴

M

ø0.08(.003)

S A

0.20(.008) S A

0.08(.003)

S

C

2003 FUJITSU LIMITED B115003S-c-1-1

Dimensions in mm (inches) .

Note : The values in parentheses are reference values.

98

MB84VZ128B/C-70

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0311

FUJITSU LIMITED Printed in Japan


型号：	MB84VZ128C-70PBS
厂家：	FUJITSU
描述：	Memory Circuit, Flash+PSRAM+SRAM, Hybrid, PBGA115 静态存储器内存集成电路
文件：	总100页 (文件大小：1850K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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