PXN20 [FREESCALE]
PXN20 Microcontroller; PXN20微控制器
| 型号： | PXN20 |
| 厂家： | 
Freescale |
| 描述： | PXN20 Microcontroller |
| 文件： | 总60页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: PXN20
Rev. 1, 09/2011
PXN20 PXN21
MAPBGA–208
17 mm x 17 mm
PXN20 Microcontroller Data
Sheet
•
PXN20 features:
– Internal conversion triggering for ADC
– Triggerable by internal timers or eMIOS200
• 32-bit CPU core complex (e200z650)
– Compliant with Power Architecture embedded category
– 32 KB unified cache with line locking and eight-entry
store buffer16
– Execution speed static to 116 MHz
• 32-bit I/O processor (e200z0)
• Deserial Serial Peripheral Interface (DSPI)
– Four individual DSPI modules
– Full duplex, synchronous transfers
– Master or slave operation
2
• Inter-IC communication (I C) interface
2
– Four individual I C modules
– Execution speed static to 1/2 CPU core speed (58 MHz)
• 2 MB on-chip flash
– Multi-master operation
• Serial Communication Interface (eSCI) module
– Two-channel DMA interface
– Configurable as LIN bus master
• eMIOS200 timed input/output
– 24 channels, 16-bit timers (PXN20)
– 32 channels, 16-bit timers (PXN21)
• Controller Area Network (FlexCAN) module
– Compliant with CAN protocol specification, Version
2.0B active
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 512 KB + 80 KB (592 KB) on-chip ECC SRAM (PXN20)
• 128 KB on-chip ECC SRAM (PXN21)
• 16-entry Memory Protection Unit (PXN21 only)
• Direct memory access controller
– 16-channel on PXN20
– 32-channel on PXN21
• Fast ethernet controller
– 64 mailboxes, each configurable as transmit or receive
• Dual-channel FlexRay controller
– Full implementation of FlexRay Protocol Specification
2.1, RevA
– Supports 10-Mbps and 100-Mbps IEEE 802.3 MII,
10-Mbps 7-wire interface
– IEEE 802.3 MAC (compliant with IEEE 802.3 1998
edition)
– 128 message buffers
• JTAG controller (PXN20 only)
• Media Local Bus (MLB) interface (PXN20 only)
– Supports 16 logical channels, max speed 1024 Fs
• Interrupt controller (INTC) supports 316 external interrupt
vectors (22 are reserved)
– Compliant with the IEEE 1149.1-2001
• Nexus Development Interface (NDI)
– Available in 256 MAPBGA package only
– Compliant with IEEE-ISTO 5001-2003
– Nexus class 3 development support on e200z650
– Nexus class 2+ development support on e200z0
• Internal voltage regulator allows operation from single
3.3 V or 5 V supply
• System clocks
– Frequency-modulated phase-locked loop (FMPLL)
– 4 – 40 MHz crystal oscillator (XTAL)
– 32 kHz crystal oscillator (XTAL)
– Dedicated 16 MHz and 128 kHz internal RC oscillators
• Analog to Digital Converter (ADC) module
– 10-bit A/D resolution
– 32 external channels
– 36 internal channels (PXN20)
– 64 internal channels (PXN21)
• Cross-Triggering Unit (PXN21 only)
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Table of Contents
1
Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
4.6 Operating current specifications
. . . . . . . . . . . . . . 32
1.1 Orderable parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 PXN20 family feature set . . . . . . . . . . . . . . . . . . . . . . . .3
PXN20 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.1 208-ball MAPBGA pin assignments . . . . . . . . . . . . . . . .7
3.2 Pin muxing and reset states . . . . . . . . . . . . . . . . . . . . . .8
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .27
4.3 ESD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.4 VRC electrical specifications. . . . . . . . . . . . . . . . . . . . .30
4.5 DC electrical specifications. . . . . . . . . . . . . . . . . . . . . .30
4.7 I/O pad current specifications . . . . . . . . . . . . . . . . . . . 34
4.8 Low voltage characteristics . . . . . . . . . . . . . . . . . . . . . 36
4.9 Oscillators electrical characteristics. . . . . . . . . . . . . . . 36
4.10 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 38
4.11 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 39
4.12 Flash memory electrical characteristics . . . . . . . . . . . 39
4.13 Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.14 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 58
Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2
3
4
5
6
PXS30 Microcontroller Data Sheet, Rev. 1
2
Freescale Semiconductor
Ordering information
1
Ordering information
1.1
Orderable parts
Table 1 shows the orderable part numbers for the PXN20 family.
M PX
N 20 20 V MG 116 R
Qualification status
Brand
Family
Class
Flash memory size
Temperature range
Package identifier
Operating frequency
Tape and reel indicator
Qualification status
Family
Flash Memory Size
D = Display Graphics
N = Connectivity/Network
R = Performance/Real Time Control
S = Safety
20 = 2 MB
P = Pre-qualification (engineering samples)
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Temperature range
Package identifier
MG = 208 MAPBGA
Operating frequency
Tape and reel status
V = –40 °C to 105 °C
(ambient)
116 = 116 MHz
R = Tape and reel
(blank) = Trays
Note: Not all options are available on all devices. See Table 1 for more information.
Figure 1. PXN20 orderable part number description
Table 1. PXN20 orderable part number summary
Speed
(MHz)
Part number
Flash/SRAM
Package
MPXN2020VMG116
MPXN2120VMG116
2 MB / 592 KB
2 MB / 128 KB
208 MAPBGA (17 mm x 17 mm)
208 MAPBGA (17 mm x 17 mm)
116
116
1.2
PXN20 family feature set
Table 2. PXN20 family feature set
PXN20
Feature
PXN21
Central Processing Unit (CPU)
Cache
e200z650
32K, 4/8way
Yes
e200z650
32K, 4/8way
Yes
Floating Point Unit (FPU)
Signal Processing Engine (SPE)
Memory Management Unit (MMU)
Yes
Yes
32 entry
32 entry
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
3
Ordering information
Table 2. PXN20 family feature set (continued)
PXN20
Feature
PXN21
CPU Execution Speed
Static, 116 MHz
Static, 116 MHz
Input/Output Processor (IOP)
IOP Execution Speed
Flash with ECC
e200z0
e200z0
1/2 CPU execution speed
1/2 CPU execution speed
2 MB
2 MB
Data Flash Block
8x16 KB
8x16 KB
RAM with ECC
592 KB
128 KB
Memory Protection Unit (MPU)
Direct Memory Access Unit (eDMA)
Ethernet (FEC)
No
16 entry
16 Channel
32 Channel
Yes
No
MediaLB (MLB-DIM)
Yes
No
FlexRay Controller
Yes (128 Message Buffers)
36 internal channels, 10-bit
No
Analog-to-Digital Converter (ADC)
64 internal channels, 10-bit
Supports 32 external channels Supports 32 external channels
Total Timer I/O (eMIOS200)
24 channels, 16-bit
32 channels, 16-bit
Cross Trigger Unit (CTU)
No
6
Yes
12
Asynchronous Serial Interfaces (UART)
Synchronous Serial Interfaces (SPI)
Controller Area Network (CAN) Controller
Inter-Integrated Circuit (I2C) Controller
Frequency Modulated PLL (FMPLL)
4 – 40 MHz XTAL Oscillator
4
4
6
5
4
4
Yes
Yes
Yes
Yes
Yes
Yes
8
Yes
Yes
Yes
Yes
Yes
Yes
8
16 MHz IRC Oscillator
32 kHz XTAL Oscillator
128 kHz IRC Oscillator
Real Time Counter/ Autonomous Periodic Interrupts (RTC/API)
Periodic Interrupt Timer (PIT)
System Timer Module (STM)
Software Watchdog Timer (SWT)
General-Purpose I/O (GPIO)
Yes
Yes
155
Yes
Yes
Yes
Yes
155
Yes
Yes
Clock Monitor (FMPLL)
JTAG
Nexus Debug (Only supported on emulation package)
Nexus3 (e200Z6)
Nexus2+ (e200Z0)
Nexus3 (e200Z6)
Nexus2+ (e200Z0)
Production Package
208 MAPBGA
256 MAPBGA
208 MAPBGA
256 MAPBGA
Emulation Package (for development use only)
PXN20 Microcontroller Data Sheet, Rev. 1
4
Freescale Semiconductor
PXN20 block diagrams
2
PXN20 block diagrams
Figure 2 shows a top-level block diagram of the PXN20 device.
PXN20 Block Diagram
Debug
32 kHz
XTAL
4-40 MHz
XTAL
16 MHz
IRC
VREG
Controller
JTAG
Masters
e200z650 Core
VLE
Nexus3 (Z6)
Nexus2+ (Z0)
RTC/API
SWT
STM
INTC
PIT
128 kHz
IRC
FMPLL
MMU (32 TLB)
FPU/SPE
Semaphores
e200z0 Core
16-ch DMA
Mux
32 KB Cache
4/8 Way
Ethernet
MLB-DIM FlexRay™
VLE
BAM
SIU
Crossbar Switch (XBAR)
PBRIDGE A
2 MB
Flash
(ECC)
PBRIDGE B
80 KB
SRAM
(ECC)
512 KB
SRAM
(ECC)
6 x UART/LIN
36 x ADC
2 x I2C
2 x SPI
6 x CAN
2 x SPI
2 x I2C
Standby RAM
ECSM
ECSM
24 x eMIOS
ECSM
ADC
BAM
CAN
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Error correction code
– Error correction status module
– Timed input/output
– Enhanced direct memory access controller
– Fast ethernet controller
MLB-DIM – Media Local Bus device interface module
NDI – Nexus debug interface
PBRIDGE– Peripheral I/O bridge
ECC
PIT
RTC
SIU
SPI
STM
SWT
– Periodic interrupt timer
– Real time clock
– System integration unit
– Serial peripheral interface controller
– System timer module
ECSM
eMIOS
eDMA
FEC
FlexRay™ – FlexRay bus controller
– Software watchdog timer
FMPLL
I2C
INTC
JTAG
– Frequency-modulated phase-locked loop
– Inter-integrated circuit controller
– Interrupt controller
UART/LIN – Universal asynchronous receiver/transmitter/
local interconnect network
VREG
– Voltage regator
– Joint Test Action Group interface
Figure 2. PXN20 block diagram
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
5
PXN20 block diagrams
Figure 3 shows a top level block diagram for the PXN21 device.
PXN21 Block Diagram
Debug
JTAG
32 kHz
XTAL
4–40 MHz
XTAL
16 MHz
IRC
VREG
Controller
Masters
e200z650 Core
VLE
Nexus3 (Z6)
RTC/API
SWT
STM
INTC
PIT
128 kHz
IRC
FMPLL
Nexus2+ (Z0)
MMU (32 TLB)
FPU/SPE
Semaphores
e200z0 Core
32-ch DMA
Mux
32 KB Cache
4/8 Way
VLE
BAM
SIU
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
2 MB
Flash
(ECC)
PBRIDGE B
PBRIDGE A
128 KB
SRAM
(ECC)
2
8 x UART/LIN
64 x ADC
2 x I
C
4 x UART/LIN
2 x SPI
2 x SPI
Standby RAM
ECSM
2
ECSM
32 x eMIOS
5 x CAN
2 x I
C
CTU
MPU
NDI
– Memory protection unit
– Nexus debug interface
ADC
BAM
CAN
CTU
ECC
ECSM
eDMA
eMIOS
FMPLL
I2C
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Cross triggering unit
PBRIDGE – Peripheral I/O bridge
PIT
RTC
SIU
SPI
– Periodic interrupt timer
– Real time clock
– System integration unit
– Serial peripheral interface controller
– System timer module
– Software watchdog timer
– Error correction code
– Error correction status module
– Enhanced direct memory access controller
– Timed input/output
– Frequency-modulated phase-locked loop
– Inter-integrated circuit controller
– Interrupt controller
STM
SWT
UART/LIN – Universal asynchronous receiver/transmitter/
INTC
JTAG
local interconnect network
– Voltage regulator
– Joint Test Action Group interface
VREG
Figure 3. PXN21 block diagram
PXN20 Microcontroller Data Sheet, Rev. 1
6
Freescale Semiconductor
Pin assignments
3
Pin assignments
3.1
208-ball MAPBGA pin assignments
Figure 4 shows the 208-ball MAPBGA pin assignments.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PD0
PC12
PC9
PC7
PC2
PB13
PB10
PB8 RESET VDDSYN XTAL EXTAL VSSSYN
V
V
A
B
C
D
E
F
V
PG1
A
B
C
D
E
F
SS
SS
PD2
PD3
PD5
PD7
PD9
PD11
PD13
PF1
PD1
PD4
PD6
PD8
PD10
PD12
PF0
PC11
PC10
PC13
PC15
PC8
PC5
PC3
PC6
PB14
PC1
PC4
PB11
PB15
PC0
V
PB9
PB4
PB5
PB2
PB3
PB0
PB1
PG0
V
V
DDA
RCCTL
RC
RH
PD14 PC14
PB6
PB12
V
V
RL
SSA
PD15
V
V
V
V
PB7
PA0
PA1
PA14
PA10
PA11
PA13
PA12
PA9
PA8
PA7
PG2
DDE1
SS
DD
DD
PE0
PE3
PE1
PE2
PA15
PA2
208 MAPBGA Ball Map
(as viewed from top through the package)
PA3
PA5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PE4
G
H
J
G
H
J
V
V
PA4
PA6
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
PE5
V
V
PG6
PG7
PG8
PG9
PG10
PH3
PH4
PH6
DD
RCSEL
V
PF2
TDI
PE8
PG3
PG4
PG5
PF13
PF12
PG11
PG12
PG13
PG14
PG15
PH1
DDE3
JCOMP
TMS
TDO
PE10
TCK
V
DD
K
L
PK1
PK0
PK2
PE7
PE6
PF3
PF5
V
K
L
DDEMLB
V
V
DDE2
DD33
PE9
PE11
PE12
PK4
TEST
PF4
PF6
M
N
P
R
T
M
N
P
R
T
PE15
PK10
PK8
PE14
PH8
PJ0
PH9
PH10
PJ2
PH11
PH12
PJ4
V
PH15
PJ10
PJ11
PJ12
V
V
DDE4
DD
SS
PF8
PE13
PK6
PH13
PJ6
PF15
PJ14
PH14
PJ9
PF14
PH5
PF10
PH2
PF7
PF11
PH7
15
V
PJ3
8
PJ7
10
PJ8
11
PJ13
12
PJ15
13
PH0
14
PF9
2
PK3
3
PK5
4
PK7
5
PK9
6
PJ1
7
PJ5
9
V
SS
SS
1
16
Figure 4. PXN20 208-ball MAPBGA (full diagram)
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
7
Pin assignments
3.2
Pin muxing and reset states
Table 3 shows the signals properties for each pin on PXN20. For all port pins that have an associated SIU_PCRn register to
control pin properties, the supported functions column lists the functions associated with the programming of the
SIU_PCRn[PA] bit in the order: general-purpose input/output (GPIO), function 1, function 2, and function 3 (see Figure 5).
When an alternate function is not implemented for a value of SIU_PCRn[PA], a dash is shown in the Description column and
the respective value in the PA bit field is reserved.
GPIO
Supported
(PCR) PA4
Num3
Description
Functions2
PA[0]
AN[0]
0
00
01
10
11
GPIO
Port A GPI
ADC Analog Input
—
—
Function 1
Functions 2 and 3
not implemented
Figure 5. Supported functions example
Table 3. PXN20 signal properties
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
Port A (16)
PA0
PA1
PA2
PA3
PA4
PA5
PA[0]
AN[0]
0
1
2
3
4
5
00 Port A GPI
01 ADC Analog Input
I
I
—
—
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
IHA
IHA
IHA
IHA
IHA
IHA
—
—
—
—
—
—
—
—
—
—
—
—
D15
E15
F16
F15
G16
G15
10
11
—
—
PA[1]
AN[1]
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA[2]
AN[2]
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA[3]
AN[3]
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA[4]
AN[4]
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA[5]
AN[5]
00 Port A GPI
01 ADC Analog Input
I
I
10
11
—
—
—
—
PXN20 Microcontroller Data Sheet, Rev. 1
8
Freescale Semiconductor
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PA6
PA[6]
AN[6]
6
00 Port A GPI
01 ADC Analog Input
I
I
—
—
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
IHA
IHA
IHA
IHA
IHA
IHA
IHA
IHA
IHA
IHA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H16
G14
F14
E14
D13
E13
D14
F13
D16
E16
10
11
—
—
PA7
PA[7]
AN[7]
7
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA8
PA[8]
AN[8]
8
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA9
PA[9]
AN[9]
9
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA10
PA11
PA12
PA13
PA14
PA15
PA[10]
AN[10]
10
11
12
13
14
15
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA[11]
AN[11]
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA[12]
AN[12]
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA[13]
AN[13]
00 Port A GPI
01 ADC Analog Input
I
I
—
—
10
11
—
—
PA[14]
AN[14]
EXTAL32
00 Port A GPI
01 ADC Analog Input
10 External 32 kHz Crystal In
I
I
I
11
—
—
PA[15]
AN[15]
XTAL32
00 Port A GPI
01 ADC Analog Input
10 External 32 kHz Crystal Out
I
I
O
—
11
—
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
9
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
Port B (16)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB[0]
AN[16]/ANW
16
17
18
19
20
21
22
23
24
25
00 Port B GPIO
01 ADC Analog Input/Mux In
I/O VDDE1 SHA
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B14
C14
B13
C13
C12
D12
C11
D11
A10
B12
10
11
—
—
PB[1]
AN[17]/ANX
00 Port B GPIO
01 ADC Analog Input/Mux In
I/O VDDE1 SHA
I
—
—
10
11
—
—
PB[2]
AN[18]/ANY
00 Port B GPIO
01 ADC Analog Input/Mux In
I/O VDDE1 SHA
I
—
—
10
11
—
—
PB[3]
AN[19]/ANZ
00 Port B GPIO
01 ADC Analog Input/Mux In
I/O VDDE1 SHA
I
—
—
10
11
—
—
PB[4]
AN[20]
00 Port B GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
—
—
10
11
—
—
PB[5]
AN[21]
00 Port B GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
—
—
10
11
—
—
PB[6]
AN[22]
00 Port B GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
—
—
10
11
—
—
PB[7]
AN[23]
00 Port B GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
—
—
10
11
—
—
PB[8]
AN[24]
PCS_A[2]
00 Port B GPIO
01 ADC Analog Input
10 DSPI_A Peripheral Chip Select
I/O VDDE1 SHA
I
O
—
11
—
PB[9]
00 Port B GPIO
I/O VDDE1 SHA
AN[25]
PCS_A[3]
01 ADC Analog Input
10 DSPI_A Peripheral Chip Select
I
O
—
11
—
PXN20 Microcontroller Data Sheet, Rev. 1
10
Freescale Semiconductor
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PB10 PB[10]
AN[26]
26
27
28
29
30
31
00 Port B GPIO
01 ADC Analog Input
10 DSPI_B Peripheral Chip Select
11
I/O VDDE1 SHA
I
O
—
—
—
—
—
—
—
—
—
—
—
—
—
A9
PCS_B[4]
—
PB11 PB[11]
AN[27]
00 Port B GPIO
01 ADC Analog Input
10 DSPI_B Peripheral Chip Select
I/O VDDE1 SHA
I
O
—
B9
PCS_B[5]
11
—
PB12 PB[12]
AN[28]
00 Port B GPIO
01 ADC Analog Input
10 DSPI_C Peripheral Chip Select
I/O VDDE1 SHA
I
O
—
C10
A8
PCS_C[1]
11
—
PB13 PB[13]
AN[29]
00 Port B GPIO
01 ADC Analog Input
10 DSPI_C Peripheral Chip Select
I/O VDDE1 SHA
I
O
—
PCS_C[2]
11
—
PB14 PB[14]
AN[30]
00 Port B GPIO
01 ADC Analog Input
10 DSPI_D Peripheral Chip Select
I/O VDDE1 SHA
I
O
—
B8
PCS_D[3]
11
—
PB15 PB[15]
AN[31]
00 Port B GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
C9
PCS_D[4]
10 DSPI_D Peripheral Chip Select
O
—
11
—
Port C (16)
PC0
PC1
PC2
PC3
PC[0]
AN[32]
32
33
34
35
00 Port C GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
—
—
—
—
—
—
—
—
—
—
D9
C8
A7
B7
10
11
—
—
PC[1]
AN[33]
00 Port C GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
—
—
10
11
—
—
PC[2]
AN[34]
EVTI
00 Port C GPIO
01 ADC Analog Input
10 Nexus Event In
I/O VDDE1 SHA
I
I
11
—
—
PC[3]
00 Port C GPIO
I/O VDDE1 SHA
AN[35]
EVTO
01 ADC Analog Input
10 Nexus Event Out
I
O
—
11
—
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
11
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PC4
PC5
PC6
PC7
PC8
PC9
PC[4]
AN[36]
36
37
38
39
40
41
42
43
44
45
46
00 Port C GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D8
C6
C7
A6
B6
A5
B5
B4
A4
C5
C4
10
11
—
—
PC[5]
AN[37]
Z6NMI
00 Port C GPIO
01 ADC Analog Input
10 Z6 Core Non-Maskable Interrupt
I/O VDDE1 SHA
I
I
11
—
—
PC[6]
AN[38]
Z0NMI
00 Port C GPIO
01 ADC Analog Input
10 Z0 Core Non-Maskable Interrupt
I/O VDDE1 SHA
I
I
11
—
—
PC[7]
AN[39]
FR_DBG3
00 Port C GPIO
01 ADC Analog Input
10 FlexRay Debug
I/O VDDE1 SHA
I
O
—
11
—
PC[8]
AN[40]
FR_DBG2
00 Port C GPIO
01 ADC Analog Input
10 FlexRay Debug
I/O VDDE1 SHA
I
O
—
11
—
PC[9]
AN[41]
FR_DBG1
00 Port C GPIO
01 ADC Analog Input
10 FlexRay Debug
I/O VDDE1 SHA
I
O
—
11
—
PC10 PC[10]
AN[42]
00 Port C GPIO
01 ADC Analog Input
10 FlexRay Debug
I/O VDDE1 SHA
I
O
—
FR_DBG0
11
—
PC11 PC[11]
AN[43]
00 Port C GPIO
I/O VDDE1 SHA
I
I/O
—
01 ADC Analog Input
SCL_C
10 I2C_C Serial Clock
11
—
PC12 PC[12]
AN[44]
00 Port C GPIO
I/O VDDE1 SHA
I
I/O
—
01 ADC Analog Input
SDA_C
10 I2C_C Serial Data
11
—
PC13 PC[13]
AN[45]
00 Port C GPIO
01 ADC Analog Input
I/O VDDE1 SHA
I
—
O
—
MA[0]
10
—
11 ADC Ext. Mux Address Select
PC14 PC[14]
AN[46]
00 Port C GPIO
01 ADC Analog Input
10 ADC Ext. Mux Address Select
I/O VDDE1 SHA
I
—
O
MA[1]
11
—
PXN20 Microcontroller Data Sheet, Rev. 1
12
Freescale Semiconductor
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PC15 PC[15]
AN[47]
47
00 Port C GPIO
01 ADC Analog Input
10 ADC Ext. Mux Address Select
11
I/O VDDE1 SHA
I
O
—
—
—
D5
MA[2]
—
Port D (16)
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD[0]
CNTX_A
48
49
50
51
52
53
54
55
56
00 Port D GPIO
01 FlexCAN_A Transmit
I/O VDDE2
SH
SH
SH
SH
SH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A2
B2
B1
C1
C2
D1
D2
E1
E2
O
—
—
10
11
—
—
PD[1]
CNRX_A
00 Port D GPIO
01 FlexCAN_A Receive
I/O VDDE2
I
—
—
10
11
—
—
PD[2]
CNTX_B
00 Port D GPIO
01 FlexCAN_B Transmit
I/O VDDE2
O
—
—
10
11
—
—
PD[3]
CNRX_B
00 Port D GPIO
01 FlexCAN_B Receive
I/O VDDE2
I
—
—
10
11
—
—
PD[4]
CNTX_C
00 Port D GPIO
01 FlexCAN_C Transmit
I/O VDDE2
O
—
—
10
11
—
—
PD[5]
CNRX_C
00 Port D GPIO
01 FlexCAN_C Receive
I/O VDDE2
I
—
—
10
11
—
—
PD[6]
00 Port D GPIO
I/O VDDE2
O
O
CNTX_D
TXD_K
SCL_B
01 FlexCAN_D Transmit
10 SCI_K Transmit
11 I2C_B Serial Clock
I/O
PD[7]
00 Port D GPIO
I/O VDDE2
I
I
CNRX_D
RXD_K
SDA_B
01 FlexCAN_D Receive
10 SCI_K Receive
11 I2C_B Serial Data
I/O
PD[8]
00 Port D GPIO
I/O VDDE2
CNTX_E
TXD_L
SCL_C
01 FlexCAN_E Transmit
10 SCI_L Transmit
11 I2C_C Serial Clock
O
O
I/O
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
13
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PD9
PD[9]
57
58
59
60
61
62
63
00 Port D GPIO
I/O VDDE2
I
I
SH
SH
SH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F1
F2
G1
G2
H1
C3
D3
CNRX_E
RXD_L
SDA_C
01 FlexCAN_E Receive
10 SCI_L Receive
11 I2C_C Serial Data
I/O
PD10
PD11
PD12
PD13
PD14
PD15
PD[10]
00 Port D GPIO
I/O VDDE2
O
O
CNTX_F
TXD_M
SCL_D
01 FlexCAN_F Transmit
10 SCI_M Transmit
11 I2C_D Serial Clock
I/O
PD[11]
00 Port D GPIO
I/O VDDE2
I
I
CNRX_F
RXD_M
SDA_D
01 FlexCAN_F Receive
10 SCI_M Receive
11 I2C_D Serial Data
I/O
PD[12]
TXD_A
00 Port D GPIO
01 eSCI_A Transmit
I/O VDDE2
O
—
—
10
11
—
—
PD[13]
RXD_A
00 Port D GPIO
01 eSCI_A Receive
I/O VDDE2
I
—
—
10
11
—
—
PD[14]
TXD_B
00 Port D GPIO
01 eSCI_B Transmit
I/O VDDE2
O
—
—
10
11
—
—
PD[15]
RXD_B
00 Port D GPIO
01 eSCI_B Receive
I/O VDDE2
I
10
11
—
—
—
—
Port E (16)
PE0
PE1
PE2
PE[0]
TXD_C
eMIOS[31]
64
65
66
00 Port E GPIO
01 eSCI_C Transmit
10 eMIOS Channel
I/O VDDE2
SH
SH
SH
—
—
—
—
—
—
E3
E4
F4
O
I/O
—
11
—
PE[1]
RXD_C
eMIOS[30]
00 Port E GPIO
01 eSCI_C Receive
10 eMIOS Channel
I/O VDDE2
I
I/O
11
—
PE[2]
00 Port E GPIO
I/O VDDE2
TXD_D
eMIOS[29]
01 eSCI_D Transmit
10 eMIOS Channel
O
I/O
11
—
PXN20 Microcontroller Data Sheet, Rev. 1
14
Freescale Semiconductor
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PE3
PE[3]
RXD_D
eMIOS[28]
67
68
69
70
71
72
73
74
75
76
77
00 Port E GPIO
01 eSCI_D Receive
10 eMIOS Channel
11
I/O VDDE2
I
I/O
SH
SH
SH
SH
SH
SH
SH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F3
G3
H3
M2
L2
—
PE4
PE[4]
TXD_E
eMIOS[27]
00 Port E GPIO
01 eSCI_E Transmit
10 eMIOS Channel
I/O VDDE2
O
I/O
11
—
PE5
PE[5]
RXD_E
eMIOS[26]
00 Port E GPIO
01 eSCI_E Receive
10 eMIOS Channel
I/O VDDE2
I
I/O
11
—
PE6
PE[6]
TXD_F
eMIOS[25]
00 Port E GPIO
01 eSCI_F Transmit
10 eMIOS Channel
I/O VDDE2
O
I/O
11
—
PE7
PE[7]
RXD_F
eMIOS[24]
00 Port E GPIO
01 eSCI_F Receive
10 eMIOS Channel
I/O VDDE2
I
I/O
11
—
PE8
PE[8]
TXD_G
PCS_A[1]
00 Port E GPIO
01 eSCI_G Transmit
10 DSPI_A Peripheral Chip Select
I/O VDDE2
O
O
J4
11
—
PE9
PE[9]
RXD_G
PCS_A[4]
00 Port E GPIO
01 eSCI_G Receive
10 DSPI_A Peripheral Chip Select
I/O VDDE2
I
O
M4
N3
N4
P4
P5
11
—
PE10
PE11
PE12
PE13
PE[10]
TXD_H
PCS_B[3]
00 Port E GPIO
01 eSCI_H Transmit
10 DSPI_B Peripheral Chip Select
I/O VDDE2
O
O
11
—
PE[11]
RXD_H
PCS_B[2]
00 Port E GPIO
01 eSCI_H Receive
10 DSPI_B Peripheral Chip Select
I/O VDDE2
I
O
11
—
PE[12]
TXD_J
PCS_C[5]
00 Port E GPIO
01 eSCI_J Transmit
10 DSPI_C Peripheral Chip Select
I/O VDDE2
O
O
11
—
PE[13]
00 Port E GPIO
I/O VDDE2
RXD_J
01 eSCI_J Receive
I
PCS_C[3]
10 DSPI_C Peripheral Chip Select
O
11
—
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
15
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PE14
PE15
PE[14]
SCL_A
PCS_D[2]
78
00 Port E GPIO
01 I2C_A Serial Clock
10 DSPI_D Peripheral Chip Select
11
I/O VDDE2
I/O
O
SH
SH
—
—
N7
—
—
PE[15]
SDA_A
PCS_D[5]
79
00 Port E GPIO
I/O VDDE2
I/O
O
—
—
N6
01 I2C_A Serial Data
10 DSPI_D Peripheral Chip Select
11
—
—
Port F (16)
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF[0]
SCK_A
80
81
82
83
84
85
86
87
00 Port F GPIO
01 DSPI_A Serial Clock
I/O VDDE2
I/O
—
MH
MH
SH
SH
MH
MH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H2
J1
10
11
—
—
—
PF[1]
SOUT_A
00 Port F GPIO
01 DSPI_A Serial Data Out
I/O VDDE2
O
—
—
10
11
—
—
PF[2]
SIN_A
00 Port F GPIO
01 DSPI_A Serial Data In
I/O VDDE2
I
—
—
J2
10
11
—
—
PF[3]
00 Port F GPIO
I/O VDDE2
I/O
O
N2
M1
P2
N1
R2
PCS_A[0]
PCS_B[5]
PCS_C[4]
01 DSPI_A Peripheral Chip Select
10 DSPI_B Peripheral Chip Select
11 DSPI_C Peripheral Chip Select
O
PF[4]
SCK_B
PCS_A[1]
PCS_C[2]
00 Port F GPIO
01 DSPI_B Serial Clock
10 DSPI_A Peripheral Chip Select
11 DSPI_C Peripheral Chip Select
I/O VDDE2
I/O
O
O
PF[5]
00 Port F GPIO
I/O VDDE2
SOUT_B
PCS_A[2]
PCS_C[3]
01 DSPI_B Serial Data Out
10 DSPI_A Peripheral Chip Select
11 DSPI_C Peripheral Chip Select
O
O
O
PF[6]
SIN_B
PCS_A[3]
PCS_C[5]
00 Port F GPIO
I/O VDDE2
I
O
O
01 DSPI_B Serial Data In
10 DSPI_A Peripheral Chip Select
11 DSPI_C Peripheral Chip Select
PF[7]
00 Port F GPIO
I/O VDDE2
PCS_B[0]
PCS_C[5]
PCS_D[4]
01 DSPI_B Peripheral Chip Select
10 DSPI_C Peripheral Chip Select
11 DSPI_D Peripheral Chip Select
I/O
O
O
PXN20 Microcontroller Data Sheet, Rev. 1
16
Freescale Semiconductor
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PF8
PF[8]
SCK_C
88
89
90
91
92
93
94
95
00 Port F GPIO
01 DSPI_C Serial Clock
I/O VDDE2
I/O
—
MH
MH
SH
SH
MH
MH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P1
10
11
—
—
—
PF9
PF[9]
SOUT_C
00 Port F GPIO
01 DSPI_C Serial Data Out
I/O VDDE2
T2
O
—
—
10
11
—
—
PF10
PF11
PF12
PF13
PF14
PF15
PF[10]
SIN_C
00 Port F GPIO
01 DSPI_C Serial Data In
I/O VDDE2
I
—
—
R1
10
11
—
—
PF[11]
00 Port F GPIO
I/O VDDE2
I/O
O
R3
PCS_C[0]
PCS_D[5]
PCS_A[4]
01 DSPI_C Peripheral Chip Select
10 DSPI_D Peripheral Chip Select
11 DSPI_A Peripheral Chip Select
O
PF[12]
SCK_D
00 Port F GPIO
01 DSPI_D Serial Clock
I/O VDDE3
I/O
—
N14
M14
P14
P13
10
11
—
—
—
PF[13]
SOUT_D
00 Port F GPIO
01 DSPI_D Serial Data Out
I/O VDDE3
O
—
—
10
11
—
—
PF[14]
SIN_D
00 Port F GPIO
01 DSPI_D Serial Data In
I/O VDDE3
I
—
—
10
11
—
—
PF[15]
00 Port F GPIO
I/O VDDE3
PCS_D[0]
PCS_A[5]
PCS_B[4]
01 DSPI_D Peripheral Chip Select
10 DSPI_A Peripheral Chip Select
11 DSPI_B Peripheral Chip Select
I/O
O
O
Port G (16)
PG0
PG1
PG[0]
96
97
00 Port G GPIO
I/O VDDE2 SHA
—
—
—
—
B3
A3
PCS_A[4]
PCS_B[3]
AN[48]
01 DSPI_A Peripheral Chip Select
10 DSPI_B Peripheral Chip Select
11 ADC Analog Input
O
O
I
PG[1]
00 Port G GPIO
I/O VDDE2 SHA
PCS_A[5]
PCS_B[4]
AN[49]
01 DSPI_A Peripheral Chip Select
10 DSPI_B Peripheral Chip Select
11 ADC Analog Input
O
O
I
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
17
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG[2]
98
00 Port G GPIO
I/O VDDE3 SHA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H14
J14
K14
L14
H15
J15
K15
L15
M15
J16
K16
PCS_D[1]
SCL_C
AN[50]
01 DSPI_D Peripheral Chip Select
O
I/O
I
10 I2C_C Serial Clock
11 ADC Analog Input
PG[3]
99
00 Port G GPIO
I/O VDDE3 SHA
PCS_D[2]
SDA_C
AN[51]
01 DSPI_D Peripheral Chip Select
10 I2C_C Serial Data
11 ADC Analog Input
O
I/O
I
PG[4]
100
101
102
103
104
105
106
107
108
00 Port G GPIO
I/O VDDE3 SHA
PCS_D[3]
SCL_B
AN[52]
01 DSPI_D Peripheral Chip Select
10 I2C_B Serial Clock
11 ADC Analog Input
O
I/O
I
PG[5]
00 Port G GPIO
I/O VDDE3 SHA
PCS_D[4]
SDA_B
AN[53]
01 DSPI_D Peripheral Chip Select
10 I2C_B Serial Data
11 ADC Analog Input
O
I/O
I
PG[6]
00 Port G GPIO
I/O VDDE3 MHA
PCS_C[1]
FEC_MDC
AN[54]
01 DSPI_C Peripheral Chip Select
10 Ethernet Mgmt. Data Clock
11 ADC Analog Input
O
O
I
PG[7]
00 Port G GPIO
I/O VDDE3 MHA
PCS_C[2]
FEC_MDIO
AN[55]
01 DSPI_C Peripheral Chip Select
10 Ethernet Mgmt. Data I/O
11 ADC Analog Input
O
I/O
I
PG[8]
00 Port G GPIO
I/O VDDE3 SHA
I/O
I
I
eMIOS[7]
FEC_TX_CLK
AN[56]
01 eMIOS Channel
10 Ethernet Transmit Clock
11 ADC Analog Input
PG[9]
00 Port G GPIO
I/O VDDE3 SHA
I/O
I
I
eMIOS[6]
FEC_CRS
AN[57]
01 eMIOS Channel
10 Ethernet Carrier Sense
11 ADC Analog Input
PG[10]
00 Port G GPIO
I/O VDDE3 MHA
eMIOS[5]
FEC_TX_ER
AN[58]
01 eMIOS Channel
10 Ethernet Transmit Error
11 ADC Analog Input
I/O
O
I
PG[11]
00 Port G GPIO
I/O VDDE3 SHA
I/O
I
I
eMIOS[4]
FEC_RX_CLK
AN[59]
01 eMIOS Channel
10 Ethernet Receive Clock
11 ADC Analog Input
PG[12]
00 Port G GPIO
I/O VDDE3 MHA
eMIOS[3]
FEC_TXD[0]
AN[60]
01 eMIOS Channel
10 Ethernet Transmit Data
11 ADC Analog Input
I/O
O
I
PXN20 Microcontroller Data Sheet, Rev. 1
18
Freescale Semiconductor
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PG13
PG14
PG15
PG[13]
109
110
111
00 Port G GPIO
01 eMIOS Channel
10 Ethernet Transmit Data
11 ADC Analog Input
I/O VDDE3 MHA
—
—
—
—
—
—
L16
M16
N16
eMIOS[2]
FEC_TXD[1]
AN[61]
I/O
O
I
PG[14]
00 Port G GPIO
I/O VDDE3 MHA
eMIOS[1]
FEC_TXD[2]
AN[62]
01 eMIOS Channel
10 Ethernet Transmit Data
11 ADC Analog Input
I/O
O
I
PG[15]
00 Port G GPIO
I/O VDDE3 MHA
eMIOS[0]
FEC_TXD[3]
AN[63]
01 eMIOS Channel
10 Ethernet Transmit Data
11 ADC Analog Input
I/O
O
I
Port H (16)
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH[0]
eMIOS[31]
FEC_COL
112
113
114
115
116
117
118
00 Port H GPIO
01 eMIOS Channel
10 Ethernet Collision
I/O VDDE3
I/O
I
SH
SH
MH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T14
P16
R16
N15
P15
R14
R15
11
—
—
PH[1]
eMIOS[30]
FEC_RX_DV
00 Port H GPIO
01 eMIOS Channel
10 Ethernet Receive Data Valid
I/O VDDE3
I/O
I
11
—
—
PH[2]
eMIOS[29]
FEC_TX_EN
00 Port H GPIO
01 eMIOS Channel
10 Ethernet Transmit Enable
I/O VDDE3
I/O
O
11
—
—
PH[3]
eMIOS[28]
FEC_RX_ER
00 Port H GPIO
01 eMIOS Channel
10 Ethernet Receive Error
I/O VDDE3
I/O
I
11
—
—
PH[4]
eMIOS[27]
FEC_RXD[0]
00 Port H GPIO
01 eMIOS Channel
10 Ethernet Receive Data
I/O VDDE3
I/O
I
11
—
—
PH[5]
eMIOS[26]
FEC_RXD[1]
00 Port H GPIO
01 eMIOS Channel
10 Ethernet Receive Data
I/O VDDE3
I/O
I
11
—
—
PH[6]
00 Port H GPIO
I/O VDDE3
eMIOS[25]
FEC_RXD[2]
01 eMIOS Channel
10 Ethernet Receive Data
I/O
I
11
—
—
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
19
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PH7
PH[7]
eMIOS[24]
FEC_RXD[3]
119
120
121
122
123
124
125
126
127
00 Port H GPIO
01 eMIOS Channel
10 Ethernet Receive Data
11
I/O VDDE3
I/O
I
SH
SH
SH
SH
SH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T15
—
—
PH8
PH[8]
eMIOS[23]
00 Port H GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
P7
10
11
—
—
—
PH9
PH[9]
eMIOS[22]
00 Port H GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
N8
10
11
—
—
—
PH10
PH11
PH12
PH13
PH14
PH15
PH[10]
eMIOS[21]
00 Port H GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
P8
10
11
—
—
—
PH[11]
eMIOS[20]
00 Port H GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
N9
10
11
—
—
—
PH[12]
eMIOS[19]
00 Port H GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
P9
10
11
—
—
—
PH[13]
eMIOS[18]
00 Port H GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
P10
P11
N11
10
11
—
—
—
PH[14]
eMIOS[17]
00 Port H GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
10
11
—
—
—
PH[15]
00 Port H GPIO
I/O VDDE4
eMIOS[16]
01 eMIOS Channel
I/O
—
—
10
11
—
—
Port J (16)
PJ0
PJ[0]
128
00 Port J GPIO
I/O VDDE4
SH
—
—
R7
eMIOS[15]
PCS_A[4]
01 eMIOS Channel
I/O
O
—
10 DSPI_A Peripheral Chip Select
11
—
PXN20 Microcontroller Data Sheet, Rev. 1
20
Freescale Semiconductor
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
PJ[1]
eMIOS[14]
PCS_A[5]
129
130
131
132
133
134
135
136
137
138
139
00 Port J GPIO
01 eMIOS Channel
10 DSPI_A Peripheral Chip Select
11
I/O VDDE4
I/O
O
SH
SH
SH
SH
SH
SH
SH
SH
SH
SH
SH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T7
—
—
PJ[2]
eMIOS[13]
PCS_B[1]
00 Port J GPIO
01 eMIOS Channel
10 DSPI_B Peripheral Chip Select
I/O VDDE4
I/O
O
R8
11
—
—
PJ[3]
eMIOS[12]
PCS_B[2]
00 Port J GPIO
01 eMIOS Channel
10 DSPI_B Peripheral Chip Select
I/O VDDE4
I/O
O
T8
11
—
—
PJ[4]
eMIOS[11]
PCS_C[3]
00 Port J GPIO
01 eMIOS Channel
10 DSPI_C Peripheral Chip Select
I/O VDDE4
I/O
O
R9
11
—
—
PJ[5]
eMIOS[10]
PCS_C[4]
00 Port J GPIO
01 eMIOS Channel
10 DSPI_C Peripheral Chip Select
I/O VDDE4
I/O
O
T9
11
—
—
PJ[6]
eMIOS[09]
PCS_D[5]
00 Port J GPIO
01 eMIOS Channel
10 DSPI_D Peripheral Chip Select
I/O VDDE4
I/O
O
R10
T10
T11
R11
N12
P12
11
—
—
PJ[7]
eMIOS[08]
PCS_D[1]
00 Port J GPIO
01 eMIOS Channel
10 DSPI_D Peripheral Chip Select
I/O VDDE4
I/O
O
11
—
—
PJ[8]
eMIOS[07]
00 Port J GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
10
11
—
—
—
PJ[9]
eMIOS[06]
00 Port J GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
10
11
—
—
—
PJ[10]
eMIOS[05]
00 Port J GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
10
11
—
—
—
PJ[11]
00 Port J GPIO
I/O VDDE4
eMIOS[04]
01 eMIOS Channel
I/O
—
—
10
11
—
—
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
21
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PJ12
PJ13
PJ14
PJ15
PJ[12]
eMIOS[03]
140
141
142
143
00 Port J GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
SH
SH
SH
SH
—
—
—
—
—
—
—
—
R12
T12
R13
T13
10
11
—
—
—
PJ[13]
eMIOS[02]
00 Port J GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
10
11
—
—
—
PJ[14]
eMIOS[01]
00 Port J GPIO
01 eMIOS Channel
I/O VDDE4
I/O
—
10
11
—
—
—
PJ[15]
00 Port J GPIO
I/O VDDE4
eMIOS[00]
01 eMIOS Channel
I/O
—
—
10
11
—
—
Port K (11)
PK0
PK1
PK2
PK3
PK4
PK5
PK[0]
144
145
146
147
148
149
00 Port K GPIO
I/O VDDEMLB
I
I/O
O
F
F
—
—
—
—
—
—
—
—
—
—
—
—
L1
K1
K2
T3
R4
T4
MLBCLK
SCK_B
CLKOUT
01 Media Local Bus Clock
10 DSPI_B Serial Clock
11 CLKOUT (Test Only)
PK[1]
00 Port K GPIO
I/O VDDEMLB
I/O
O
MLBSIG
SOUT_B
PCS_D[4]
01 Media Local Bus Signal
10 DSPI_B Serial Data Out
11 DSPI_D Peripheral Chip Select
O
PK[2]
MLBDAT
SIN_B
00 Port K GPIO
I/O VDDEMLB
I/O
I
F
01 Media Local Bus Data
10 DSPI_B Serial Data In
11 DSPI_D Peripheral Chip Select
PCS_D[5]
O
PK[3]
FR_A_RX
MA[0]
00 Port K GPIO
I/O VDDE2
I
O
O
SH
MH
MH
01 FlexRay A Receive Data
10 ADC Ext. Mux Address Select
11 DSPI_C Peripheral Chip Select
PCS_C[1]
PK[4]
FR_A_TX
MA[1]
00 Port K GPIO
I/O VDDE2
01 FlexRay A Transmit Data
10 ADC Ext. Mux Address Select
11 DSPI_C Peripheral Chip Select
O
O
O
PCS_C[2]
PK[5]
00 Port K GPIO
I/O VDDE2
FR_A_TX_EN
MA[2]
PCS_C[3]
01 FlexRay A Transmit Enable
10 ADC Ext. Mux Address Select
11 DSPI_C Peripheral Chip Select
O
O
O
PXN20 Microcontroller Data Sheet, Rev. 1
22
Freescale Semiconductor
Pin assignments
Table 3. PXN20 signal properties (continued)
Package Pin
Locations
Status
GPIO
Pin
Supported
I/O
Volt-
Pad
(PCR) PA4
Num3
Description
Name1 Functions2
Type age Type5
During After
Reset6 Reset7
208
BGA
PK6
PK7
PK8
PK9
PK[6]
150
151
152
153
00 Port K GPIO
01 FlexRay B Receive Data
10 DSPI_B Peripheral Chip Select
11 DSPI_C Peripheral Chip Select
I/O VDDE2
I
O
O
SH
MH
MH
—
—
—
—
—
—
R5
T5
R6
T6
FR_B_RX
PCS_B[1]
PCS_C[4]
PK[7]
00 Port K GPIO
I/O VDDE2
FR_B_TX
PCS_B[2]
PCS_C[5]
01 FlexRay B Transmit Data
10 DSPI_B Peripheral Chip Select
11 DSPI_C Peripheral Chip Select
O
O
O
PK[8]
00 Port K GPIO
I/O VDDE2
FR_B_TX_EN
PCS_B[3]
PCS_A[1]
01 FlexRay B Transmit Enable
10 DSPI_B Peripheral Chip Select
11 DSPI_A Peripheral Chip Select
O
O
O
PK[9]
00 Port K GPIO
I/O VDDE2
MH BOOT GPIO
CLKOUT
PCS_D[1]
PCS_A[2]
BOOTCFG
01 CLKOUT (User mode)
10 DSPI_D Peripheral Chip Select
11 DSPI_A Peripheral Chip Select
Boot Configuration
O
O
O
I
CFG
(Pull-
down)
PK10
PK[10]
154
00 Port K GPIO
I/O VDDE2
SH
—
—
P6
PCS_B[5]
PCS_D[2]
PCS_A[3]
01 DSPI_B Peripheral Chip Select
10 DSPI_D Peripheral Chip Select
11 DSPI_A Peripheral Chip Select
O
O
O
Miscellaneous Pins (9)
EXTAL EXTAL
EXTCLK
—
—
Main Crystal Oscillator Input
I
VDDSYN
A
EXTAL
XTAL
A14
External Clock Input
Main Crystal Oscillator Output
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Mode Select Input
JTAG Test Clock Input
JTAG Compliancy
I
O
I
XTAL
TDI
XTAL
TDI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDSYN
VDDE2
VDDE2
VDDE2
VDDE2
VDDE2
VDDE3
A
A13
J3
SH
MH
MH
TDI (Pull Up)
TDO (Pull Up8)
TMS (Pull Up)
TDO
TMS
TCK
TDO
TMS
TCK
O
I
M3
L3
I
SH TCK (Pull Down)
P3
JCOMP (Pull Down)
TEST9
JCOMP JCOMP
TEST TEST
RESET RESET
I
SH
IH
K3
Test Mode Select
I
M13
A11
External Reset
I/O VDDE1
MH RESET (Pull Up)
1
2
The primary signal name is used as the pin label on the BGA map for identification purposes.
Each line in the Signal Name column corresponds to a separate signal function on the pin. For all device I/O pins, the primary,
alternate, or GPIO signal functions are designated in the PA field of the System Integration Unit (SIU) PCR registers except
where explicitly noted.
3
4
The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number.
The PA bitfield in the SIU_PCRn register selects the signal function for the pin. A dash in the Description field of this table
indicates that this value for PC is reserved on this pin, and should not be used.
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
23
Pin assignments
5
The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed, H–high voltage, I—input-only,
M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad.
6
The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high
impedance. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown
enabled, Low – output driven low, High – output driven high. A dash on the left side of the slash denotes that both the input and
output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on
the pin. The signal name to the left or right of the slash indicates the pin is enabled.
7
The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the
input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down
enabled on the pin.
8
Pullup is enabled only when JCOMP is negated.
9
Tie to VSS for normal operation.
PXN20 Microcontroller Data Sheet, Rev. 1
24
Freescale Semiconductor
Pin assignments
3.2.1
Power and ground supply summary
Table 4. PXN20 power/ground
Package Pin Locations
Pin
Name
Function Description
Voltage1
208
VDD
VDDE1
VDDE2
VDDE3
VDDE4
VDDA
Internal Logic Power
External I/O Power
1.2 V
D4, D10, H4, G13, K13, N5
3.3–5.0 V
D6
L4
J13
N10
B15
L13
K4
Analog Power
3.3 V I/O Power
3.3–5.0 V
3.3 V
VDD33
VDDEMLB
VRCSEL
VRC
Media Local Bus Power
Voltage Regulator Select
Voltage Regulator Control Voltage
Voltage Regulator Control Output
Clock Synthesizer Power
Analog High Voltage Reference
Analog Low Voltage Reference
Ground
2.5 or 3.3 V
VSSA / VDDA
3.3–5.0 V
H13
B10
B11
A12
B16
C16
2
VRCCTL
VDDSYN
VRH
—
3.3 V
3.3–5.0 V
0 V
VRL
VSS
0 V
A1, A16, D7, G4, G[7:10], H[7:10],
J[7:10], K[7:10], N13, T1, T16
VSSA
Analog Ground
0 V
0 V
C15
A15
VSSSYN
Clock Synthesizer Ground
1
2
Nominal voltages.
Base current to external NPN power transistor. Voltage may vary.
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
25
Electrical characteristics
4
Electrical characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the PXN20.
4.1
Maximum ratings
1
Table 5. Absolute maximum ratings
Spec
Characteristic
1.2 V Core Supply Voltage2
Symbol
Min
Max
Unit
1
2
3
4
5
6
VDD
VDDSYN
VDD33
VRC
–0.3
–0.3
–0.3
–0.3
–0.3
1.323
3.6
V
V
V
V
V
V
3.3 V Clock Synthesizer Voltage2, 4
3.3 V I/O Buffer Voltage 2, 4
3.6
3.3–5.0 V Voltage Regulator Control Voltage 2, 5, 6
3.3–5.0 V Analog Supply Voltage (reference to VSSA
3.3–5.0 V External I/O Supply Voltage 2, 5, 7
5.5
2, 5
)
VDDA
5.5
8
VDDE1
VDDE2
VDDE3
VDDE4
–0.3
–0.3
–0.3
–0.3
5.5
5.5
5.5
5.5
8
8
8
8
7
9
2.5–3.3 V External I/O Supply Voltage (MLB) 2, 4
VDDEMLB
–0.3
3.6
V
V
DC Input Voltage9
VDDE1, VDDE2, VDDE3, VDDE4
VDDEMLB, VDDENEX
VIN
–1.010
–1.09
V
V
+
+
0.3 V11
10
DDEx
0.3
V
DDEx
10 Analog Reference High Voltage
VRH
–0.3
Minimum of
5.5
V
or
VDDA + 0.3
11 Analog Reference Low Voltage
VRL
–0.3
–100
–100
–2
5.5
100
100
2
V
12
V
SS to VSSA Differential Voltage
VSS – VSSA
VSS – VSSSYN
IMAXD
mV
mV
mA
13 VSS to VSSSYN Differential Voltage
14 Maximum DC Digital Input Current12 (per pin, applies to all
digital F, MH, SH, and IH pins)
15 Maximum DC Analog Input Current13 (per pin, applies to all
analog AE and A pins)
IMAXA
–3
3
mA
16 Storage Temperature Range
17 Maximum Solder Temperature14
18 Moisture Sensitivity Level15
TSTG
TSDR
MSL
–55.0
—
150.0
235.0
3
oC
oC
—
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause permanent damage to the device.
2
3
4
5
6
7
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.
5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.
6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.
VRC cannot be 100mV higher than VDDA. VDDSYN and VDD33 cannot be 100 mV higher than VRC.
All functional non-supply I/O pins are clamped to VSS and VDDEx
.
PXN20 Microcontroller Data Sheet, Rev. 1
26
Freescale Semiconductor
Electrical characteristics
8
9
VDDEx are separate power segments and may be powered independently with no differential voltage constraints between the
power segments.
AC signal over and undershoot of the input voltages of up to ±2.0 V is permitted for a cumulative duration of 60 hours over the
complete lifetime of the device (injection current does not need to be limited for this duration).
10 Internal structures will hold the input voltage above –1.0 V if the injection current limit of 2 mA is met.
11 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum
injection current specification is met (25 mA for all pins) and VDDE is within Operating Voltage specifications.
12 Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
13 Total injection current for all analog input pins must not exceed 15 mA.
14 Solder profile per CDF-AEC-Q100.
15 Moisture sensitivity per JEDEC test method A112.
4.2
Thermal characteristics
Table 6. Thermal characteristics
Value
Spec
Characteristic
Junction to Ambient1, 2
Symbol
Unit
208 MAPBGA
256 MAPBGA
1
2
RJA
°C/W
39
39
Natural Convection
(Single layer board)
Junction to Ambient1, 3
Natural Convection
RJA
°C/W
24
24
(Four layer board 2s2p)
3
4
Junction to Ambient1, 3
RJMA
RJMA
°C/W
°C/W
31
20
31
20
(@200 ft./min., Single layer board)
Junction to Ambient1, 3
(@200 ft./min., Four layer board 2s2p)
5
6
7
Junction to Board4
Junction to Case5
RJB
RJC
JT
°C/W
°C/W
°C/W
13
6
13
6
Junction to Package Top6
Natural Convection
2
2
1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
6
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
4.2.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
P )
Eqn. 1
J
A
JA
D
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
27
Electrical characteristics
where:
o
T = ambient temperature for the package ( C)
A
o
R
= junction to ambient thermal resistance ( C/W)
JA
P = power dissipation in the package (W)
D
The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined on the single-layer (1s) board and on the four-layer
board with two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of
the component is not a constant. It depends on the construction of the application board (number of planes), the effective size
of the board which cools the component, how well the component is thermally and electrically connected to the planes, and the
power being dissipated by adjacent components.
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between through vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value
obtained on the board with the internal planes is usually appropriate if the application board has one oz. (35 micron nominal
thickness) internal planes, the components are well separated, and the overall power dissipation on the board is less than 0.02
2
W/cm .
The thermal performance of any component depends strongly on the power dissipation of surrounding components. In addition,
the ambient temperature varies widely within the application. For many natural convection and especially closed box
applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature
near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description
of the local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
T = T + (R
P )
Eqn. 2
J
B
JB
D
where:
T = junction temperature ( C)
o
J
o
T = board temperature at the package perimeter ( C/W)
B
o
R
= junction to board thermal resistance ( C/W) per JESD51-8
JB
P = power dissipation in the package (W)
D
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
The application board should be similar to the thermal test condition, with the component soldered to a board with internal
planes.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case
to ambient thermal resistance:
R
= R
+ R
CA
Eqn. 3
JA
JC
where:
o
R
R
R
= junction to ambient thermal resistance ( C/W)
JA
JC
CA
o
= junction to case thermal resistance ( C/W)
o
= case to ambient thermal resistance ( C/W)
R
is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
JC
ambient thermal resistance, R
. For instance, the user can change the air flow around the device, add a heat sink, change the
CA
PXN20 Microcontroller Data Sheet, Rev. 1
28
Freescale Semiconductor
Electrical characteristics
mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the
device. This description is most useful for packages with heat sinks where some 90% of the heat flow is through the case to the
heat sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction to board thermal resistance and the junction
to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount
of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance
when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a
computational fluid dynamics (CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the Thermal
Characterization Parameter ( ) can be used to determine the junction temperature with a measurement of the temperature at
JT
the top center of the package case using the following equation:
T = T + ( P )
Eqn. 4
J
T
JT
D
where:
o
T = thermocouple temperature on top of the package ( C)
T
o
= thermal characterization parameter ( C/W)
JT
P = power dissipation in the package (W)
D
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
29
Electrical characteristics
4.3
ESD characteristics
1, 2
Table 7. ESD ratings
Characteristic
Symbol
Value
Unit
ESD for Human Body Model (HBM)
HBM Circuit Description
2000
1500
V
R1
C
Ohm
pF
100
ESD for Field Induced Charge Model (FDCM)
750 (corner pins)
250 (all other pins)
V
Number of Pulses per pin:
Positive Pulses (HBM)
Negative Pulses (HBM)
—
—
1
1
—
—
Interval of Pulses
—
1
second
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification.
4.4
VRC electrical specifications
Table 8. VRC electrical specifications
Spec
Characteristic
Symbol
Min
Max
Units
Current which can be sourced by VRCCTL
I_VRCCTL
1
6.25 µA
20 mA
—
Minimum Required Gain from external circuit:
IDD / I_VRCCTL (@VDD = 1.32 V)1
2
–40C
25C
150C
BETA
50
50
50
500
1
Assumes “typical usage” currents which will vary with application.
4.5
DC electrical specifications
Table 9. DC electrical specifications
Spec
Characteristic
Symbol
Min
Max
Unit
1
2
3
4
Maximum Operating Temperature Range — Die Junction Temperature
3.3 V Clock Synthesizer Voltage1
TJ
–40.0
3.0
150.0
3.6
oC
V
VDDSYN
VDD33
VVRC
3.3 V I/O Buffer Voltage1
3.0
3.6
V
3.3–5.0 V Voltage Regulator Reference Voltage1
VRCSEL = VSSA
V
3.0
4.5
3.6
5.5
VRCSEL = VDDA
5
3.3–5.0 V Analog Supply Voltage
VDDA
maximum of
3.0 V or
5.5
V
VVRC – 0.1
PXN20 Microcontroller Data Sheet, Rev. 1
30
Freescale Semiconductor
Electrical characteristics
Table 9. DC electrical specifications
Spec
Characteristic
Symbol
Min
Max
Unit
6
3.3–5.0 V External I/O Supply Voltage2
V
VDDE1
VDDE2
VDDE3
VDDE4
3.0
3.0
3.0
3.0
5.5
5.5
5.5
5.5
3
7
9
2.5 V – 3.3 V External I/O Supply Voltage (MLB)
VDDEMLB
VIH
2.375
3.6
V
V
Pad Input High Voltage
VDDE + 0.3
Hysteresis enabled
0.65 VDDE
0.55 VDDE
0.55 VDDE
Hysteresis disabled (IHA/SH/SHA/MH/MHA)4, 5
Hysteresis disabled (F)
10 Pad Input Low Voltage
Hysteresis enabled
VIL
VSS – 0.3
V
0.35 VDDE
0.40 VDDE
0.40 VDDE
Hysteresis disabled (IHA/SH/SHA/MH/MHA)4, 5
Hysteresis disabled (F)
11 Pad Input Hysteresis
VHYS
VINDC
VOH
0.1 VDDE
VSSA – 0.3 VDDA + 0.3
V
V
12 Analog (IHA) Input Voltage
13 Pad Output High Voltage6, 7, 8
0.8 VDDE
—
V
14 Pad Output Low Voltage8
VOL
—
—
—
—
0.2 VDDE
V
15 Input Capacitance (Digital Pins: Pad type F, MH, SH)4
16 Input Capacitance (Analog Pins: Pad type IHA)4, 5
17 Input Capacitance (Shared digital/analog pins: MHA, SHA)4
CIN
7
pF
pF
pF
A
CIN_A
CIN_M
IACT
10
12
18 I/O Weak Pull Up/Down Absolute Current4, 9
Pad F: 2.375 V – 3.6 V
25
10
35
180
95
200
Pad SH/MH/IHA: 3.0 V – 3.6 V
Pad SH/MH/IHA: 4.5 V – 5.5 V
19 I/O Input Leakage Current10
IINACT_D
IIC
IINACT_A
VRH
–2.5
–1.0
2.5
1.0
A
mA
nA
20 DC Injection Current (per pin)
21 Analog Input Current, Channel Off11 (Analog pins IHA)4, 5
22 Analog Reference High Voltage
23 Analog Reference Low Voltage
–150
150
VDDA
VDDA – 500
VSSA
mV
VRL
VSSA + 500 mV
24 VSS to VSSA Differential Voltage
25 VSSSYN to VSS Differential Voltage
VSS – VSSA
VSSSYN – VSS
VRamp
–100
100
100
100
mV
mV
–100
26 Slew rate on VDDA, VDDEx, VDDSYN, VDD33, and VRC power supply
pins
—
V/ms
27 Capacitive Supply Load (VDD
)
VLoad
VLoad
8
1
—
—
µF
µF
28 Capacitive Supply Load (VDD33, VDDSYN
)
1
When VRCSEL = VSSA (low), VDDSYN and VDD33 are externally supplied. When VRCSEL = VDDA (high), VDDSYN and VDD33 are
generated by internal voltage regulators. When VRCSEL = VSSA (low), VDDSYN and VDD33 cannot be 100 mV higher than VRC
.
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
31
Electrical characteristics
2
VDDE1 – VDDE4 are separate power segments and may be powered independently with no differential voltage constraints
between the power segments. VDDE1 – VDDE3 pad power segments contain ADC analog input channels and thus the input
analog signal level may be clamped to the VDDE level, resulting in inaccurate ADC results if the VDDE voltage level is less than
VDDA
.
3
4
When VRCSEL = VDDA (high), the internally generated VDD33 voltage may be used to power VDDEMLB as long as the PK[0:2]
pads remain in the disabled default state with their output buffers, input buffers, and pull devices disabled.
The pad type is indicated by one or more of the following abbreviations: A–analog, F—fast speed, H–high voltage, I—input-only,
M–medium speed, S–slow speed. For example, pad type SH designates a slow high-voltage pad.
5
6
The IHA pads are related to VDDA
.
Characterization Based Capability:
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE = 3.0 V;
IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE = 2.25 V;
IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE = 1.62 V.
7
Characterization Based Capability:
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH = 4.5 V;
IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH = 3.0 V
8
9
All VOL/VOH values 100% tested with ±2 mA load.
Absolute value of current, measured at VIL and VIH.
10 Weak pull up/down inactive. Measured at VDDE = 5.25 V. Applies to pad types: SH and MH. Leakage specification guaranteed
only when power supplies are within specified operating conditions.
11 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
4.6
Operating current specifications
Table 10. Operating currents
Typ1
25 C
Max1
–40–150 C
Junction
Spec
Characteristic
Symbol
Unit
Ambient
Equations ITOTAL = IDDE + IDDA + IRH + IDD33 + IDDSYN + IRC + IDD
IDDE = IDDE1 + IDDE2 + IDDE3 + IDDE4 + IDDEMLB
—
—
—
—
1
2
VDDE Current
IDDE
VDDE(1,2,3,4) @ 3.0 V – 5.5 V
VDDEMLB @ 2.375 V – 3.6 V
Static2
0
30
25
A
mA
Dynamic3
Note 3
VDDA Current
IDDA
VDDA @ 3.0 V – 5.5 V
Run mode
Sleep mode
1
20
+5
30
50
+15
mA
A
A
– Optional 32 kHz osc enabled
3
4
VRH Current
IRH
VRH @ 3.0 V – 5.5 V
Run mode
Sleep mode
300
1
700
30
A
A
VDD33 Current
VDD33 @ 3.0 V – 3.6 V
Run mode
IDD33
10
10
20
20
mA
A
Sleep mode
PXN20 Microcontroller Data Sheet, Rev. 1
32
Freescale Semiconductor
Electrical characteristics
Max1
Table 10. Operating currents (continued)
Typ1
25 C
Spec
Characteristic
Symbol
–40–150 C
Unit
Ambient
Junction
5
V
DDSYN Current
VDD33 @ 3.0 V – 3.6 V
Run mode
IDDSYN
5
1
10
20
+350
+400
mA
A
A
A
Sleep mode
– Optional4 4–40 MHz osc enabled w/ no clock
– Optional4 4–40 MHz osc enabled w/ clock
+150
+300
5
6
7
VRC Current (excluding IDD, IDD33, IDDSYN
VRC @ 3.135 V – 5.5 V
Run mode
)
IRC
1
0
+40
10
10
+60
mA
A
A
Sleep mode
– Optional4 16MIRC enabled
VDD Current
IDD
VDD @ 1.08 V – 1.32 V
Run mode (Maximum @ 116 MHz)6
Sleep mode
200
100
+5
+200
+5
340
900
+10
+220
+20
+20
+200
+150
+300
+600
mA
A
A
A
A
A
A
A
A
A
– Optional4 128KIRC enabled
– Optional4 16MIRC enabled
– Optional4 32 kHz osc enabled
– Optional4 4–40 MHz osc enabled w/ no clock
– Optional4 4–40 MHz osc enabled w/ clock
– Optional4 32 KB RAM
+5
+150
+10
+20
+40
– Optional4 64 KB RAM
– Optional4 128 KB RAM
1
2
Typ – Nominal voltage levels and functional activity. Max – Maximum voltage levels and functional activity.
Static state of pins is when input pins are disabled or not being toggled and driven to a valid input level, output pins are not
toggling or driving against any current loads, and internal pull devices are disabled or not pulling against any current loads.
3
4
Dynamic current from pins is application-specific and depends on active pull devices, switching outputs, output capacitive and
current loads, and switching inputs. Refer to Table 11 for more information.
Optional currents are values that should be added to their respective current specifications to obtain the actual value for that
specification when the optional function is active. The plus sign (+) in the Typ and Max columns indicates these optional
currents. For example, VDDSYN in Sleep mode draws 1 .A (typ). With the optional 4–40 MHz osc enabled w/ no clock, add
150 .A for a total of 151 .A (typ).
5
6
VRC Current excluding the current supply to VDD33, VDDSYN and VDD from VRC
.
Maximum supply current transition: 50mA per 20S observation window.
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
33
Electrical characteristics
4.7
I/O pad current specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 11 based on
the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load
parameters that fall outside the values given in Table 11.
1
Table 11. I/O pad average I
specifications
DDE
Pad
Period
(ns)
Load3
(pF)
VDDE
(V)
Drive/Slew
Rate Select
IDDE Avg
(mA)
IDDE RMS
(mA)
Spec
Symbol
Type2
1
2
37
130
650
840
24
50
50
50
200
50
50
50
200
50
30
20
10
50
30
20
10
0.5
5.5
5.5
11
01
00
00
11
01
00
00
11
10
01
00
11
10
01
00
N/A
14
5.3
1.1
3
Slow
IDRV_SSR_HV
3
5.5
4
5.5
6
5.5
9
7
62
5.5
2.5
0.5
1.5
50.4
14.2
16.4
9.8
22.9
6.7
4.5
3
Medium IDRV_MSR_HV
8
317
425
10
5.5
9
5.5
11
12
13
14
15
16
17
18
19
3.6
101.6
57.3
43.6
15.9
45.3
25.3
17.3
9.6
10
3.6
10
3.6
10
3.6
Fast
IDRV_FC
10
2.75
2.75
2.75
2.75
5.5
10
10
10
Input
IDRV_I_HV
7
N/A
N/A
1
2
3
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3.
All loads are lumped.
PXN20 Microcontroller Data Sheet, Rev. 1
34
Freescale Semiconductor
Electrical characteristics
4.7.1
I/O pad VDD33 current specifications
The power consumption of the V
supply is dependent on the usage of the pins on all I/O segments. The power consumption
DD33
is the sum of all input and output pin V
currents for all I/O segments. The output pin V
current can be calculated from
DD33
DD33
Table 12 based on the voltage, frequency, and load on all Pad F pins. The input pin V
current can be calculated from
DD33
Table 12 based on the voltage, frequency, and load on all Pad MH pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 12.
1
Table 12. I/O pad average I
specifications
DD33
Pad
Period
(ns)
Load3
(pF)
Drive
Select
IDD33 Avg
(µA)
IDD33 RMS
(µA)
Spec
Symbol
Type2
1
2
3
4
5
6
7
8
9
100
200
800
800
40
50
50
11
01
00
00
11
01
00
00
N/A
0.8
0.04
0.06
0.009
235.7
87.4
47.4
47
Slow
IDRV_SSR_HV
50
200
50
100
500
500
7
50
0.11
0.02
0.01
76.5
56.2
56.2
Medium
Input
IDRV_MSR_HV
50
200
0.5
IDRV_I_HV
1
2
3
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3.
All loads are lumped.
1
Table 13. I
pad average DC current
DD33
Pad
Period
(ns)
Load3
(pF)
VDD33
(V)
VDDE
(V)
Drive
Select
IDD33 Avg
(µA)
IDD33 RMS
(µA)
Spec
Symbol
Type2
1
2
3
4
5
6
7
8
10
10
10
10
10
10
10
10
50
30
20
10
50
30
20
10
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
11
10
01
00
11
10
01
00
3.32
2.28
1.73
1.39
2.3
11.77
7.07
5.75
4.77
7.81
4.96
4.31
4.09
3.6
3.6
Fast
IDRV_FC
2.75
2.75
2.75
2.75
1.64
1.37
1.06
1
2
3
These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3.
All loads are lumped.
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
35
Electrical characteristics
4.8
Low voltage characteristics
Table 14. Low voltage monitors
Spec
Characteristic
Symbol
Min
Typical
Max
Unit
1
2
Power-on-Reset Assert Level1
VPOR
1.5
—
2.8
V
V
Low Voltage Monitor 3.3 V2
Assert Level
VLVI33A
VLVI33D
3.00
3.04
3.05
3.12
3.10
3.19
De-assert Level
3
4
Low Voltage Monitor Synthesizer3
Assert Level
V
V
VLVISYNA
VLVISYND
3.00
3.04
3.05
3.12
3.10
3.19
De-assert Level
Low Voltage Monitor 3.0 V Low Threshold1
VRCSEL = VSSA
Assert Level
De-assert Level
VLVI_VDDA_LOA
VLVI_VDDA_LOD
3.00
3.04
3.05
3.12
3.10
3.19
VRCSEL = VDDA
Assert Level
De-assert Level
VLVI_VDDA_LOA
VLVI_VDDA_LOD
3.25
3.35
3.35
3.45
3.48
3.55
5
Low Voltage Monitor 5.0 V1, 4
Assert Level
V
V
VLVI_VDDA_A
VLVI_VDDA_D
4.35
4.45
4.475
4.575
4.55
4.65
De-assert Level
6
Low Voltage Monitor 5.0 V High Threshold1, 5
Assert Level
VLVI_VDDA_HA
VLVI_VDDA_HD
4.50
4.50
4.675
4.675
4.80
4.80
De-assert Level
1
Monitors VDDA.
2
3
4
Monitors VDD33.
Monitors VDDSYN.
Disabled when VRCSEL = VSSA
.
4.9
Oscillators electrical characteristics
Table 15. 3.3 V high frequency external oscillator
Spec
Characteristic
Frequency Range
Symbol
Min
Max
Unit
1
2
3
fref
tDC
41
40
60
MHz
%
Duty Cycle of reference
40
EXTAL Input High Voltage
External crystal mode2
External clock mode
VIHEXT
V
VXTAL + 0.4
0.65 VDDSYN
VDDSYN + 0.3
VDDSYN + 0.3
4
EXTAL Input Low Voltage
External crystal mode3
External clock mode
VILEXT
V
VDDSYN – 0.3
VXTAL – 0.4
0.35 VDDSYN
VDDSYN – 0.3
5
6
7
XTAL Current4
IXTAL
1
3
3
3
mA
pF
pF
Total On-chip stray capacitance on XTAL
Total On-chip stray capacitance on EXTAL
CS_XTAL
CS_EXTAL
—
—
PXN20 Microcontroller Data Sheet, Rev. 1
36
Freescale Semiconductor
Electrical characteristics
Table 15. 3.3 V high frequency external oscillator (continued)
Spec
Characteristic
Symbol
Min
Max
Unit
8
Crystal manufacturer’s recommended
capacitive load
CL
See crystal
specification
See crystal
specification
pF
9
Discrete load capacitance to be connected
to EXTAL
CL_EXTAL
CL_XTAL
tstartup
—
—
—
2CL – CS_EXTAL
–
pF
pF
ms
5
CPCB_EXTAL
10
11
Discrete load capacitance to be connected
to XTAL
2CL – CS_XTAL – C
5
PCB_XTAL
Startup Time
10
1
2
3
When PLL frequency modulation is active, reference frequencies less than 8 MHz will distort the modulated waveform and the
effects of this on emissions is not characterized.
This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal
mode. In that case, Vextal – Vxtal 400 mV criteria has to be met for oscillator’s comparator to produce output clock.
This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal
mode. In that case, Vxtal – Vextal 400 mV criteria has to be met for oscillator’s comparator to produce output clock.
Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
4
5
CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
Table 16. 5 V low frequency (32 kHz) external oscillator
Spec
Characteristic
Frequency Range
Symbol
Min
Max
Unit
1
2
3
4
fref32
tdc32
IXTAL32
CL32
32
40
—
40
60
3
kHz
%
Duty Cycle of reference
XTAL32 Current1
A
pF
Crystal manufacturer’s recommended
capacitive load
See crystal
specification
See crystal
specification
5
Startup Time
tStartup
—
2
s
1
Ixtal32 is the oscillator bias current out of the XTAL32 pin with both EXTAL32 and XTAL32 pins grounded.
Table 17. 5 V High Frequency (16 MHz) internal RC oscillator
Spec
Characteristic
Frequency before trim1
Symbol Range
Min
Typ
Max
Unit
1
2
3
4
5
fut
35%
7%
—
10.4
14.9
—
16
16
21.6
17.1
05
—
MHz
MHz
%
Frequency after loading factory trim2
Application trim resolution3
Application frequency trim step3
Startup Time
ft
ts
—
fs
—
—
300
—
kHz
ns
tStartup
—
—
500
1
2
3
Across process, voltage, and temperature.
Across voltage and temperature.
Fixed voltage and temperature.
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
37
Electrical characteristics
Table 18. 5V low frequency (128 kHz) internal RC oscillator
Spec
Characteristic
Symbol Range
Min
Typ
Max
Unit
1
2
3
4
5
Frequency before trim1
Fut128
Ft128
Ts128
Fs128
St128
35%
7%
—
83.2
119.0
—
128
128
—
172.8
137.0
2
kHz
kHz
%
Frequency after loading factory trim2
Application trim resolution3
Application frequency trim step3
Startup Time
—
—
4
—
kHz
s
—
—
—
100
1
2
3
Across process, voltage, and temperature.
Across voltage and temperature.
Fixed voltage and temperature.
4.10 FMPLL electrical characteristics
1
Table 19. FMPLL electrical specifications
Spec
Characteristic
Symbol
Min
Max
Unit
1
2
3
System Frequency2
fSYS
fREF
fPLL
—
4
116
40
MHz
MHz
MHz
PLL Reference Frequency Range
PLL Frequency
fvcomin
------------------------------
ERFD + 1
4
5
6
Loss of Reference Frequency 3
Self Clocked Mode Frequency
fLOR
fSCM
tLPLL
100
16
2000
64
kHz
MHz
s
PLL Lock Time4
—
400
tDC
fUL
7
8
9
40
60
4.0
2.0
%
Duty Cycle of Reference
Frequency un-LOCK Range
Frequency LOCK Range
% fSYS
% fSYS
–4.0
–2.0
fLCK
CLKOUT Period Jitter,5 Measured at fSYS Max
Cycle-to-cycle Jitter
%
fSYS
10
CJitter
CJitter
–5
5
ns
11
12
CLKOUT Jitter at 50 µs period
–250
250
6,7
Peak-to-Peak Frequency Modulation Range Limit
(fSYSMax must not be exceeded)
Cmod
%fSYS
0
4
13
14
15
FM Depth Tolerance8
VCO Frequency9
Cmod_err
fVCO
–0.50
192
0.50
600
1
%fSYS
MHz
Modulation Rate Limits10
fMOD
0.400
MHz
1
VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH.
PXN20 Microcontroller Data Sheet, Rev. 1
38
Freescale Semiconductor
Electrical characteristics
2
The maximum frequency value is with frequency modulation disabled. If frequency modulation is enabled, the maximum
frequency value should be de-rated by the percentage of modulation enabled so that the maximum frequency is not exceeded.
3
4
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal
startup time.
5
6
7
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter + Cmod
.
Modulation depth selected must not result in fPLL value greater than the fPLL maximum specified value.
Maximum and minimum variations from programmed modulation depth are 2%, 3%, and 4% peak-to-peak. Use only these
settings.
8
9
Depth tolerance is the programmed modulation depth ±0.25% of fSYS
.
See the Block Guide for VCO frequency synthesis equations.
10 Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than
1 MHz will result in reduced calibration accuracy.
4.11 ADC electrical characteristics
Table 20. ADC conversion specifications (operating)
Spec
Characteristic
Analog High Reference Voltage
Symbol
Min
Max
Unit
1
2
3
4
5
6
VRH
VRL
AVIN
FS
VDDA – 0.5
VDDA
0.5
V
V
Analog Low Reference Voltage
Analog Input Voltage
0
VRL
—
VRH
1.53
60
V
Sampling Frequency
MHz
MHz
ns
Maximum ADC Clock Frequency
FMAX
tS
—
Sampling Time
—
VDDA = 3.0 V – 3.6 V
VDDA > 3.6 V – 5.5 V
250
125
7
8
9
Differential Non Linearity
Integral Non Linearity
Offset Error
DNL
INL
–1.0
–1.5
–1.0
–2.0
–2.0
1.0
1.5
1.0
2.0
2.0
LSB
LSB
LSB
LSB
LSB
OFS
GNE
TUE
10 Gain Error
11 Total Unadjusted Error 1
1
TUE assumes no pin activity on pins adjacent to analog channel or output driver activity on corresponding VDDE segment.
4.12 Flash memory electrical characteristics
1
Table 21. Flash program and erase specifications
Initial
Max2
Spec
Characteristic
Double Word (64 bits) Program Time4
Symbol Min
Max3 Unit
1
2
3
4
5
tdwprogram
tpprogram
—
—
—
—
—
—
500
500
s
s
Page (128 bits and 256 bits) Program Time4
16 KB Block Pre-program and Erase Time
64 KB Block Pre-program and Erase Time
128 KB Block Pre-program and Erase Time
160
t16kpperase
t64kpperase
t128kpperase
1000
1800
2600
5000
5000
7500
ms
ms
ms
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
39
Electrical characteristics
Table 21. Flash program and erase specifications (continued)
Characteristic Symbol Min
1
Initial
Max2
Spec
Max3 Unit
6
7
256 KB Block Pre-program and Erase Time
t256kpperase
trwsc
—
5200 15,000 ms
MHz
Wait States Relative to System Frequency5
PFCRPn[RWSC] = PFCRPn[APC] = 0b000; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b001; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b010; PFCRPn[WWSC] = 0b01
PFCRPn[RWSC] = PFCRPn[APC] = 0b011 – 0b111; PFCRPn[WWSC] = 0b01
—
—
—
—
—
—
—
—
30
60
90
fSYS max
8
Recovery Time
tRecover
—
—
45
s
1
2
3
Typical program and erase times assume nominal supply values and operation at 25 oC.
Initial factory condition: 100program/erase cycles, nominal supply values and operation at 25 oC.
The maximum time is at worst case conditions after the specified number of program/erase cycles. This maximum value is
characterized but not guaranteed.
4
5
Actual hardware programming time. This does not include software overhead.
Wait state timing is based on the system clock frequency and thus is same for all masters.
Table 22. Flash EEPROM Module Life (Full Temperature Range)
Spec
Characteristic
Symbol
Min
Typical1 Unit
cycles
1
Number of Program/Erase cycles per block for 16 KB and 64 KB blocks
over the operating temperature range (TJ)
P/E
100,000
—
2
3
Number of Program/Erase cycles per block for 128 KB blocks over the
operating temperature range (TJ)
Minimum Data Retention at 85 °C ambient temperature2
Blocks with 0–1,000 P/E cycles
P/E
1,000
100,000 cycles
years
Retention
—
20
10
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
1 – 5
1
2
Typical endurance is evaluated at 25 oC. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance
for Nonvolatile Memory.
Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
4.13 Pad AC specifications
1
Table 23. Pad AC specifications (5.0 V, 2.5 V)
Rise/Fall5,6
(ns)
Load Drive
(pF)
Spec
Pad Type2
SRC/DSC3
Output Delay4,4 (ns)
318/343
408/431
61/67
155/173
188/204
30/34
50
200
50
00
01
11
Slow7
1
80/90
38/44
200
50
18/18
10/11
27/28
15/17
200
PXN20 Microcontroller Data Sheet, Rev. 1
40
Freescale Semiconductor
Electrical characteristics
1
Table 23. Pad AC specifications (5.0 V, 2.5 V) (continued)
Rise/Fall5,6
Load Drive
(pF)
Spec
Pad Type2
SRC/DSC3
Output Delay4,4 (ns)
(ns)
142/186
195/253
20/35
65/89
91/122
8.7/16.6
24/35
50
200
50
00
01
11
2
Medium
41/64
200
50
12/11
5.3/5.9
21/23
32/34
200
10
00
01
20
Fast8
Input
3
4
2.7
1.5
10
30
11
50
N/A
1.9/1.9
1.5/1.5
0.5
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 116 MHz, VDD = 1.08 – 1.32 V, VDDE = 1.62 – 1.98 V, VDDEH = 4.5 – 5.5 V, VRC33 and VDDPLL = 3.0 – 3.6 V, TA = TL to
TH.
2
3
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3.
SRC/DSC are bit fields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only),
DSC—Drive Strength Control (fast pad type only).
4
5
6
7
8
This parameter is supplied for reference and is not guaranteed by design and not tested.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
Add a maximum of one system clock to the output delay for delay with respect to system clock.
Output delay is shown in. Add a maximum of one system clock to the output delay for delay with respect to system clock.
1
Table 24. De-rated pad AC specifications (3.3 V, 3.3 V)
Out Delay4,5
(ns)
Rise/Fall6,
(ns)
Load Drive
(pF)
Spec
Pad Type2
SRC/DSC3
408/431
533/592
80/90
188/204
250/288
38/44
50
200
50
00
Slow7
1
01
11
00
01
11
146/167
27/28
82/96
200
50
15/17
81/92
57/67
200
50
184/240
253/330
28/47
79/107
114/153
11.8/21.8
34/49
200
50
2
Medium
58/88
200
50
18/17
7.6/8.9
30/35
46/51
200
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
41
Electrical characteristics
Table 24. De-rated pad AC specifications (3.3 V, 3.3 V) (continued)
1
Out Delay4,5
(ns)
Rise/Fall6,
(ns)
Load Drive
(pF)
Spec
Pad Type2
SRC/DSC3
00
01
1.2
1.2
10
20
30
50
0.5
Fast8
Input
3
4
2.5
3/3
10
1.2
11
1.2
N/A
1.5/1.5
1
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 116 MHz, VDD = 1.08 – 1.32 V, VDDE = 3.0 – 3.6 V, VDDEH = 3.0 – 3.6 V, VRC33 and VDDPLL = 3.0 – 3.6 V, TA = TL to
TH.
2
3
Slow = SH or SHA; Medium = MH or MHA; Fast = F; Input = IHA. See Table 3.
SRC/DSC are bit fields in the Pad Configuration Registers. SRC—Slew Rate Control (slow and medium pad types only),
DSC—Drive Strength Control (fast pad type only).
4
5
6
7
8
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Add a maximum of one system clock to the output delay for delay with respect to system clock.
Output delay is shown in Figure 6. Add a maximum of one system clock to the output delay for delay with respect to system
clock.
VDD/2
Pad
Internal Data Input Signal
Rising
Edge
Out
Falling
Edge
Out
Delay
Delay
VOH
Pad
Output
VOL
Figure 6. Pad output delay
PXN20 Microcontroller Data Sheet, Rev. 1
42
Freescale Semiconductor
Electrical characteristics
4.14 AC timing
4.14.1 Reset and boot configuration pins
Table 25. Reset and boot configuration timing
Spec
Characteristic Symbol
Min
Max
Unit
1
2
3
RESET Pulse Width
tRPW
tRCSU
tRCH
150
—
0
—
100
—
ns
s
s
BOOTCFG Setup Time after RESET Valid
BOOTCFG Hold Time from RESET Valid
RESET
1
2
BOOTCFG
3
Figure 7. Reset and boot configuration timing
4.14.2 External interrupt (IRQ) and non-maskable interrupt (NMI) pins
Table 26. IRQ/NMI timing
Spec
Characteristic
IRQ/NMI Pulse Width Low
Symbol
Min
Max
Unit
1
2
3
tIPWL
TIPWH
tICYC
3
3
6
—
—
—
tSYS
tSYS
tSYS
IRQ/NMI Pulse Width High
IRQ/NMI Edge to Edge Time1
1
Applies when IRQ/NMI pins are configured for rising edge or falling edge events, but not both.
IRQ/NMI
1,2
1,2
3
Figure 8. IRQ and NMI timing
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
43
Electrical characteristics
4.14.3 JTAG (IEEE 1149.1) interface
1
Table 27. JTAG interface timing
Spec
Characteristic
Symbol
Min
Max
Unit
1
2
TCK Cycle Time
tJCYC
tJDC
100
40
—
5
—
60
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK Clock Pulse Width (Measured at VDDE/2)
TCK Rise and Fall Times (40% – 70%)
TMS, TDI Data Setup Time
3
tTCKRISE
4
tTMSS, TDIS
TMSH, tTDIH
tTDOV
tTDOI
t
—
—
25
—
20
—
—
50
50
50
—
—
5
TMS, TDI Data Hold Time
t
25
—
0
6
TCK Low to TDO Data Valid
7
TCK Low to TDO Data Invalid
8
TCK Low to TDO High Impedance
JCOMP Assertion Time
tTDOHZ
tJCMPPW
tJCMPS
tBSDV
—
100
40
—
—
—
50
50
9
10
11
12
13
14
15
JCOMP Setup Time to TCK Low
TCK Falling Edge to Output Valid
TCK Falling Edge to Output Valid out of High Impedance
TCK Falling Edge to Output High Impedance
Boundary Scan Input Valid to TCK Rising Edge
TCK Rising Edge to Boundary Scan Input Invalid
tBSDVZ
tBSDHZ
tBSDST
tBSDHT
1
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and
CL = 30 pF with SRC = 0b11.
TCK
2
3
2
1
3
Figure 9. JTAG test clock input timing
PXN20 Microcontroller Data Sheet, Rev. 1
44
Freescale Semiconductor
Electrical characteristics
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 10. JTAG Test Access Port (TAP) timing
TCK
10
JCOMP
9
Figure 11. JTAG JCOMP timing
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
45
Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 12. JTAG boundary scan timing
PXN20 Microcontroller Data Sheet, Rev. 1
46
Freescale Semiconductor
Electrical characteristics
4.14.4 Enhanced Modular I/O Subsystem (eMIOS)
1
Table 28. eMIOS timing
Spec
Characteristic
Symbol
Min
Max
Unit
1
2
eMIOS Input Pulse Width
eMIOS Output Pulse Width
tMIPW
4
12
—
—
tCYC
tCYC
tMOPW
1
2
eMIOS timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and CL = 30 pF with SRC = 0b11.
This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise
and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).
Figure 13. eMIOS timing
D_CLKOUT
2
eMIOS output
eMIOS input
1
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
47
Electrical characteristics
4.14.5 Deserial Serial Peripheral Interface (DSPI)
Table 29. DSPI timing
116 MHz1
Spec
Characteristic
Symbol
Unit
Min. Value
Max. Value
1
DSPI Cycle Time
Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
tSCK
100
100
50
—
—
—
—
ns
ns
ns
ns
50
2
3
4
5
PCS to SCK Delay2
After SCK Delay3
SCK Duty Cycle
tCSC
tASC
tSDC
tA
7
14
—
—
ns
ns
ns
ns
0.4 tSCK
—
0.6 tSCK
25
Slave Access Time
(SS active to SOUT valid)
6
Slave SOUT Disable Time
tDIS
—
25
ns
(SS inactive to SOUT High-Z or invalid)
7
8
9
PCSx to PCSS time
PCSS to PCSx time
tPCSC
tPASC
tSUI
0
0
—
—
ns
ns
Data Setup Time for Inputs
Master (MTFE = 0)
25
5
10
25
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)4
Master (MTFE = 1, CPHA = 1)
10
11
12
Data Hold Time for Inputs
Master (MTFE = 0)
tHI
tSUO
tHO
–4
7
12
–4
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)4
Master (MTFE = 1, CPHA = 1)
Data Valid (after SCK edge)
Master (MTFE = 0)
—
—
—
—
8
28
15
8
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Data Hold Time for Outputs
Master (MTFE = 0)
–7
2
1
—
—
—
—
ns
ns
ns
ns
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
–7
1
2
3
4
116 MHz timing specified at CL = 50 pF with SRC = 0b11.
The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
PXN20 Microcontroller Data Sheet, Rev. 1
48
Freescale Semiconductor
Electrical characteristics
2
3
PCSx
1
4
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
10
9
Last Data
SIN
First Data
Data
Data
12
11
First Data
Last Data
SOUT
Figure 14. DSPI classic SPI timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
10
SCK Output
(CPOL = 1)
9
SIN
Data
Data
First Data
Last Data
12
11
SOUT
Last Data
First Data
Figure 15. DSPI classic SPI timing — Master, CPHA = 1
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
49
Electrical characteristics
3
2
SS
1
4
SCK Input
(CPOL = 0)
4
SCK Input
(CPOL = 1)
5
11
12
Data
6
First Data
Last Data
SOUT
SIN
9
10
First Data
Data
Last Data
Figure 16. DSPI classic SPI timing — Slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
Data
Data
SOUT
SIN
First Data
10
9
Last Data
First Data
Figure 17. DSPI classic SPI timing — Slave, CPHA = 1
PXN20 Microcontroller Data Sheet, Rev. 1
50
Freescale Semiconductor
Electrical characteristics
3
PCSx
4
1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)
9
10
SIN
First Data
Last Data
Last Data
Data
12
11
SOUT
First Data
Data
Figure 18. DSPI modified transfer format timing — Master, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
10
9
SIN
Last Data
First Data
Data
12
Data
11
First Data
Last Data
SOUT
Figure 19. DSPI modified transfer format timing — Master, CPHA = 1
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
51
Electrical characteristics
3
2
SS
1
SCK Input
(CPOL = 0)
4
4
SCK Input
(CPOL = 1)
12
11
6
5
First Data
9
Data
Data
Last Data
10
SOUT
SIN
Last Data
First Data
Figure 20. DSPI modified transfer format timing — Slave, CPHA = 0
SS
SCK Input
(CPOL = 0)
SCK Input
(CPOL = 1)
11
5
6
12
Last Data
First Data
10
Data
Data
SOUT
SIN
9
First Data
Last Data
Figure 21. DSPI modified transfer format timing — Slave, CPHA = 1
8
7
PCSS
PCSx
Figure 22. DSPI PCS strobe (PCSS) timing
PXN20 Microcontroller Data Sheet, Rev. 1
52
Freescale Semiconductor
Electrical characteristics
4.14.6 MLB Interface
4.14.6.1 Media Local Bus DC Electrical Characteristics
Table 30 provides the DC electrical characteristics for the Media Local Bus interface.
Table 30. Media Local Bus DC Electrical Characteristics
Parameter
Maximum Input Voltage
Symbol
Min
Typ
Max
Unit
Comments
—
VIL
VIH
VOL
VOH
IL
—
—
—
—
—
—
—
—
3.6
0.7
—
V
V
—
—
Low Level Input Threshold
High Level Input Threshold
Low Level Output Threshold
High Level Output Threshold
Input Leakage Current
1.81
V
—
—
0.4
—
V
IOL = 6 mA
IOH = –6 mA
0 < Vin < VDDE4
2.0
—
V
±1
µA
1
Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated and
assumed by the customer.
4.14.6.2 Media Local Bus (MLB) AC electrical characteristics
Table 31 and Table 32 provide the AC electrical characteristics for the Media Local Bus interface.
Table 31. MLB timing for MLB speed 256 Fs or 512 Fs
Spec
Parameter
Symbol
Min
Typ
Max
Unit
Comments
1
MLBCLK Operating Frequency1
fmck
11.264
—
—
—
12.288
24.576
—
—
—
—
256 Fs at 44.0 kHz
256 Fs at 48.0 kHz
MHz 512 Fs at 48.0 kHz
512 Fs at 48.1 kHz
—
24.6272
25.600
—
512 Fs PLL unlocked
2
3
4
MLBCLK rise time
MLBCLK fall time
MLBCLK cycle time
tmckr
tmckf
tmckc
—
—
—
—
—
3
3
ns VIL to VIH
ns VIH to VIL
81
40
—
ns 256 Fs
512 Fs
5
MLBCLK low time
tmckl
31.5
30
37
35.5
—
—
—
—
ns 256 Fs
256 Fs PLL unlocked
14.5
14
17
16.5
ns 512 Fs
512 Fs PLL unlocked
6
MLBCLK high time
tmckh
31.5
30
38
36.5
ns 256 Fs
256 Fs PLL unlocked
14.5
14
17
16.5
ns 512 Fs
512 Fs PLL unlocked
7
8
MLBCLK pulse width variation2
tmpwv
tdsmcf
—
1
—
—
2
ns p-p
ns
—
—
MLBSIG/MLBDAT input valid to
MLBCLK falling
—
9
MLBSIG/MLBDAT input hold from
MLBCLK low
tdhmcf
0
—
—
ns
—
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
53
Electrical characteristics
Table 31. MLB timing for MLB speed 256 Fs or 512 Fs (continued)
Spec
Parameter
Symbol
Min
Typ
Max
Unit
Comments
10
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0
—
tmckl
ns
—
11
12
Bus Hold time3
tmdzh
4
—
—
—
8
ns
ns
—
—
MLBSIG/MLBDAT output valid from tmcrdv
MLBCLK rising
—
• Ground = 0.0V
• Load Capacitance = 60 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b11.
• MLB speed of 256 Fs or 512 Fs (Fs = 48 kHz)
Unless otherwise noted, all timing parameters are specified from the valid voltage threshold in Table 30.
1
2
The Controller can shut off MLBCLK to place MLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
3
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 32. MLB timing for MLB speed 1024 Fs
Spec
Parameter
Symbol
Min
Typ
Max
Unit
Comments
1
MLBCLK Operating Frequency1
fmck
45.056
—
—
—
49.152
—
—
—
49.2544
51.200
1024 Fs at 44.0 kHz
1024 Fs at 48.0 kHz
MHz 1024 Fs at 48.1 kHz
1024 Fs PLL unlocked
—
—
2
3
4
5
MLBCLK rise time
MLBCLK fall time
MLBCLK cycle time
MLBCLK low time
tmckr
tmckf
tmckc
tmckl
—
—
—
—
—
1
1
ns VIL to VIH
ns VIH to VIL
ns VIL to VIH
20.3
—
—
6.5
6.1
7.7
7.3
ns 1024 Fs
PLL unlocked
6
MLBCLK high time
tmckh
9.7
9.3
10.6
10.2
—
ns 1024 Fs
PLL unclocked
7
8
MLBCLK pulse width variation2
tmpwv
tdsmcf
—
1
—
—
0.7
—
ns p-p
ns
MLBSIG/MLBDAT input valid to
MLBCLK falling
9
MLBSIG/MLBDAT input hold from
MLBCLK low
tdhmcf
tmcfdz
tmdzh
0
0
—
—
—
ns
ns
10
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmckl
11
12
Bus Hold time3
2
—
—
—
7
ns
ns
MLBSIG/MLBDAT output valid from tmcrdv
MLBCLK rising
—
• Ground = 0.0V
• Load Capacitance = 40 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b00.
• MLB speed = 1024Fs (Fs = 48 kHz)
• Unless otherwise noted, timing parameters are specified from the valid voltage threshold in Table 30.
PXN20 Microcontroller Data Sheet, Rev. 1
54
Freescale Semiconductor
Electrical characteristics
1
2
The Controller can shut off MLBCLK to place MLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
3
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
MLBSIG/
MLBDAT
valid data
(input)
9
8
3
6
2
5
MLBCLK
4
10
12
11
MLBSIG/
MLBDAT
(output)
valid data
Figure 23. Media Local Bus (MLB) timing
4.14.7
Fast Ethernet Controller (FEC) interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.
They follow the CMOS electrical characteristics.
4.14.7.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.
Table 33. MII receive signal timing
Spec
Characteristic
Min
Max
Unit
M1
M2
M3
M4
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
RX_CLK pulse width high
5
—
—
ns
5
ns
35%
35%
65%
65%
RX_CLK period
RX_CLK period
RX_CLK pulse width low
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
55
Electrical characteristics
M3
M4
RX_CLK (input)
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
Figure 24. MII receive signal timing diagram
4.14.7.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
1
Table 34. MII transmit signal timing
Spec
Characteristic
Min
Max
Unit
M5
M6
M7
M8
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
TX_CLK pulse width high
5
—
ns
—
25
ns
35%
35%
65%
65%
TX_CLK period
TX_CLK period
TX_CLK pulse width low
1
Output pads configured with SRC = 0b11.
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
Figure 25. MII transmit signal timing diagram
4.14.7.3 MII async inputs signal timing (CRS and COL)
1
Table 35. MII Async Inputs Signal Timing
Spec
Characteristic
CRS, COL minimum pulse width
Min
Max
Unit
M9
1.5
—
TX_CLK period
1
Output pads configured with SRC = 0b11.
PXN20 Microcontroller Data Sheet, Rev. 1
56
Freescale Semiconductor
Electrical characteristics
CRS, COL
M9
Figure 26. MII async inputs timing diagram
4.14.7.4 MII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
1
Table 36. MII serial management channel timing
Spec
Characteristic
Min
Max
Unit
M10
M11
M12
M13
M14
M15
MDC falling edge to MDIO output invalid (minimum propagation delay)
MDC falling edge to MDIO output valid (max prop delay)
MDIO (input) to MDC rising edge setup
MDIO (input) to MDC rising edge hold
MDC pulse width high
0
—
—
25
ns
ns
ns
10
—
0
—
ns
40%
40%
60%
60%
MDC period
MDC period
MDC pulse width low
1
Output pads configured with SRC = 0b11.
M14
M15
MDC (output)
MDIO (output)
M10
M11
MDIO (input)
M12
Figure 27. MII serial management channel timing diagram
M13
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
57
Package characteristics
5
Package characteristics
5.1
Package mechanical data
Figure 28. 208 MAPBGA package mechanical drawing
PXN20 Microcontroller Data Sheet, Rev. 1
58
Freescale Semiconductor
Package characteristics
Figure 29. 208 MAPBGA package detail
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
59
6
Revision history
Figure 37 describes the changes made to this document between revisions.
Table 37. Revision history
Revision
Date
Description of Changes
1
September 2011 Initial release: Technical Data
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Document Number: PXN20
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2011
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