MCIMX536AVV8C [FREESCALE]
Automotive and Infotainment Applications Processors; 汽车和信息娱乐应用处理器型号: | MCIMX536AVV8C |
厂家: | Freescale |
描述: | Automotive and Infotainment Applications Processors |
文件: | 总178页 (文件大小:2649K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: IMX53AEC
Rev. 2, 5/2011
Freescale Semiconductor
Data Sheet: Advance Information
MCIMX53xA
i.MX53xA Automotive and
InfotainmentApplications
Processors
Package Information
Plastic Package
Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 3
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17
4.2. Power Supplies Requirements and Restrictions . 24
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 27
4.4. Output Buffer Impedance Characteristics . . . . . . 34
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38
4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 45
4.7. External Peripheral Interfaces Parameters . . . . . . 67
4.8. XTAL Electrical Specifications . . . . . . . . . . . . . . 148
5. Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 149
5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 149
5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 150
5.3. Power setup during Boot . . . . . . . . . . . . . . . . . . 151
6. Package Information and Contact Assignments . . . . . 152
6.1. 19x19 mm Package Information . . . . . . . . . . . . . 152
6.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 171
7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
1 Introduction
The MCIMX53xA (i.MX53xA) automotive
infotainment processor is Freescale Semiconductor’s
latest addition to a growing family of
multimedia-focused products offering high performance
processing with a high degree of functional integration
aimed at the growing automotive infotainment,
telematics, HMI, and display-based cluster markets. This
device includes 3D and 2D graphics processors, 1080i/p
video processing, and dual display, and provides a
variety of interfaces.
The i.MX53xA processor features Freescale’s advanced
implementation of the ARM™ core, which operates at
clock speeds as high as 800 MHz and interfaces with
DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800
DRAM memories. This device is well suited for
graphics rendering for HMI, navigation, high
performance speech processing with large databases,
video processing and display, audio playback, and many
other applications.
The flexibility of the i.MX53xA architecture allows for
its use in a wide variety of applications. As the heart of
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© 2011 Freescale Semiconductor, Inc. All rights reserved.
Introduction
the application chipset, the i.MX53xA processor provides all the interfaces for connecting peripherals,
such as WLAN, Bluetooth™, GPS, hard drive, camera sensors, and dual displays.
Features of the i.MX53xA processor include the following:
•
Multilevel memory system—The multilevel memory system of the i.MX53xA is based on the L1
instruction and data caches, L2 cache, internal and external memory. The i.MX53xA supports
many types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3,
NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed
NAND including eMMC up to rev 4.4.
•
•
Smart speed technology—The i.MX53xA device has power management throughout the IC that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product requiring levels of power far lower than industry expectations.
Multimedia powerhouse—The multimedia performance of the i.MX53xA processor ARM core is
boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision
floating point support) and vector floating point coprocessors. The system is further enhanced by
a multistandard hardware video codec, autonomous image processing unit (IPU), and a
programmable smart DMA (SDMA) controller.
•
•
Powerful graphics acceleration— The i.MX53xA processors provide two independent, integrated
graphics processing units: an OpenGL ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s,
and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator
(200 Mpix/s).
®
Interface flexibility—The i.MX53xA processor supports connection to a variety of interfaces,
including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go
with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed
MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces
2
2
(PATA, UART, I C, and I S serial audio, among others).
•
•
Automotive environment support—Includes interfaces such as two CAN ports, an MLB port, an
ESAI audio interface, and an asynchronous sample rate converter for multichannel/multisource
audio.
Advanced security—The i.MX53xA processors deliver hardware-enabled security features that
enable secure e-commerce, digital rights management (DRM), information encryption, secure
boot, and secure software downloads. For detailed information about the i.MX53xA security
features contact a Freescale representative.
The i.MX53xA application processor is a follow-on to the i.MX51xA, with improved performance, power
efficiency, and multimedia capabilities.
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Introduction
1.1
Ordering Information
Table 1 provides ordering information.
Table 1. Ordering Information
Part Number1
Mask Set
Features
Notes
Package2
MCIMX536AVV8C
N78C
800 MHz, full feature set
—
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
PCIMX536AVV8C
MCIMX534AVV8C
N78C
N78C
800 MHz, full feature set
—
—
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
800 MHz, no hardware video
codecs
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
1
2
Part numbers with a PC prefix indicate non production engineering parts.
Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.
1.2
Features
The i.MX53xA multimedia applications processor (AP) is based on the ARM Platform, which has the
following features:
•
•
•
•
MMU, L1 instruction and L1 data cache
Unified L2 cache
Target frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz
Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)
coprocessor supporting VFPv3
•
TrustZone
The memory system consists of the following components:
•
Level 1 cache:
— Instruction (32 Kbyte)
— Data (32 Kbyte)
•
•
Level 2 cache:
— Unified instruction and data (256 Kbyte)
Level 2 (internal) memory:
— Boot ROM, including HAB (64 Kbyte)
— Internal multimedia/shared, fast access RAM (128 Kbyte)
— Secure/non-secure RAM (16 Kbyte)
External memory interfaces:
•
— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
— 32-bit LPDDR2
— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
— 8/16-bit NOR Flash, PSRAM, and cellular RAM.
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3
Introduction
— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.
— 8-bit Asynchronous (DTACK mode) EIM interface.
— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects EIM
port, as primary muxing at system boot.
— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O
mode)
The i.MX53xA system is built around the following system on chip interfaces:
•
64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,
GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.
•
•
32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.
32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral
devices operating at 66 MHz.
The i.MX53xA makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia
performance. The use of hardware accelerators provides both high performance and low power
consumption while freeing up the CPU core for other tasks.
The i.MX53xA incorporates the following hardware accelerators:
•
•
VPU, version 3—video processing unit
GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and
800 Mpix/s z-plane performance, 256 Kbyte RAM memory
•
•
•
GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,
IPU, version 3M—image processing unit
ASRC—asynchronous sample rate converter
The i.MX53xA includes the following interfaces to external devices:
NOTE
Not all interfaces are available simultaneously, depending on I/O
multiplexer configuration.
•
•
Hard disk drives:
— PATA, up to U-DMA mode 5, 100 MByte/s
— SATA I, 1.5 Gbps
Displays:
— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two
interfaces may be active at once.
— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,
UXGA at 60 Hz).
— LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel
ports up to 85 MP/s (for example, WXGA at 60 Hz) each.
— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).
Camera sensors:
•
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Freescale Semiconductor
Introduction
— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up
to 120-MHz peak clock frequency.
•
•
Expansion cards:
— Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port
supporting 832 Mbps (8-bit, eMMC 4.4).
USB
— High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY
— Three USB 2.0 (480 Mbps) hosts:
– High-speed host with integrated on-chip high-speed PHY
– Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB
Automotive environment interfaces:
•
•
— Two controller area network (FlexCAN) interfaces, 1 Mbps each
— Media local bus or MediaLB (MLB) provides interface to most networks (50 Mbps)
— Enhanced serial audio interface (ESAI), up to 1.4 Mbps each channel
Miscellaneous interfaces:
— One-wire (OWIRE) port
— Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio multiplexer
(AUDMUX) providing four external ports.
— Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support
4-wire.
— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port
2
— Three I C ports, supporting 400 kbps
— Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps
— Sony Phillips Digital Interface (SPDIF), Rx and Tx
— Key pad port (KPP)
— Two pulse-width modulators (PWM)
— GPIO with interrupt capabilities
The system supports efficient and smart power control and clocking:
•
•
•
•
•
•
Power gating SRPG (State Retention Power Gating) for ARM core and Neon
Support for various levels of system power modes
Flexible clock gating control scheme
On-chip temperature monitor
On-chip oscillator amplifier supporting 32.768 kHz external crystal
On-chip LDO voltage regulators for PLLs
Security functions are enabled and accelerated by the following hardware:
•
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so
on)
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Introduction
•
•
Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features
Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and
mechanism to detect voltage and clock glitches
•
•
Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine
SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator
(TRNG)
•
•
Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure
RAM and support for multiple keys as well as TZ/non-TZ separation
Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is
configured during boot by e-fuses, and determines the security level operation mode as well as the
TrustZone (TZ) policy
•
Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization
NOTE
The actual feature set depends on the part number as described in Table 1.
Functions such as video hardware acceleration with 2D and 3D hardware
graphics acceleration may not be enabled for specific part numbers.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Architectural Overview
2 Architectural Overview
The following subsections provide an architectural overview of the i.MX53xA processor system.
2.1
Block Diagram
Figure 1 shows the functional modules in the i.MX53xA processor system.
Composite CVBS/ S-Video
Component RGB, YCC
(HD TV-Out / VGA)
DDR2/DDR3/
LPDDR2
NOR/NAND Battery Ctrl
Flash Device
Camera
LVDS
LCD
(WSXGA+)
Display (2)
(2)
Application Processor
Domain (AP)
Temperature
Sensor
External
Memory I/F
(EXTMC)
Digital
Audio
LDB
TV-Encoder
Internal
RAM
144 KB
Clock and Reset
Image Processing
Subsystem
(IPU)
PLL (4)
SATA /
P-ATA
HDD
CCM
GPC
SRC
Smart DMA
(SDMA)
Boot
ROM
64 KB
ARM Cortex A8
Platform
XTALOSC (2)
CAMP (2)
Debug
DAP
CAN i/f
GPS
ARM Cortex A8
Neon, VFPv3
L1 I/D cache
SPBA
AP Peripherals
TPIU
CTI (2)
SJC
ECSPI
L2 cache 256 KB
ETM, CTI0,1
CSPI
Shared Peripherals
UART (4)
AUDMUX
eSDHCv2 (3)
eSDHCv3
UART
SSI
ECSPI
ESAI
2
Security
I C (3)
Video
Proc. Unit
(VPU)
SAHARAv4
Lite
RF/IF
OWIRE
PWM (2)
IIM
SPDIF Rx/Tx
ASRC
P-ATA
RTICv3
SCCv2
SRTC
SATA
3D Graphics
Proc. Unit
(GPU3D)
+ Temp Mon
IOMUXC
KPP
RF / IF
IC’s
CSU
G-Memory
256 KB
GPIOx32 (7)
SSI (2)
TZIC
Audio,
Power
Mngmnt.
Fuse Box
FIRI
2D Graphics
Proc. Unit
FlexCAN (2)
FEC(IEEE1588)
MLB
(
GPU2D)
Timers
WDOG (2)
Ethernet
10/100
Mbps
USB PHY1
USB PHY2
GPT
USB OTG +
3 HS Ports
EPIT (2)
IrDA
XVR
JTAG
MMC/SD
USB OTG
(dev/host)
Access.
Conn.
Keypad
Bluetooth
WLAN
(IEEE1149.1) eMMC/eSD
Figure 1. i.MX53xA System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (2) indicates two separate PWM peripherals.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Modules List
3 Modules List
The i.MX53xA processor contains a variety of digital and analog modules. Table 2 describes these
modules in alphabetical order.
Table 2. i.MX53xA Digital and Analog Blocks
Block
Mnemonic
Block Name
Subsystem
ARM
Brief Description
ARM
ARM Platform
The ARM Cortex A8TM Platform consists of the ARM processor version
r2p5 (with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte
L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and
a 256 Kbyte L2 cache. The platform also contains an event monitor and
debug modules. It also has a NEON coprocessor with SIMD media
processing architecture, a register file with 32/64-bit general-purpose
registers, an integer execute pipeline (ALU, Shift, MAC), dual
single-precision floating point execute pipelines (FADD, FMUL), a
load/store and permute pipeline and a non-pipelined vector floating point
(VFP Lite) coprocessor supporting VFPv3.
ASRC
Asynchronous
Sample Rate
Converter
Multimedia
Peripherals
The asynchronous sample rate converter (ASRC) converts the sampling
rate of a signal associated to an input clock into a signal associated to a
different output clock. The ASRC supports concurrent sample rate
conversion of up to 10 channels of about –120 dB THD+N. The sample rate
conversion of each channel is associated to a pair of incoming and outgoing
sampling rates. The ASRC supports up to three sampling rate pairs.
AUDMUX
Digital Audio
Multiplexer
Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example,
SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice
codecs). The AUDMUX has seven ports (three internal and four external)
with identical functionality and programming models. A desired connectivity
is achieved by configuring two or more AUDMUX ports.
CAMP-1
CAMP-2
Clock Amplifier
Clocks,
Resets, and
Power Control
Clock amplifier
CCM
GPC
SRC
Clock Control
Module
Global Power
Controller
System Reset
Controller
Clocks,
Resets, and
Power Control The system includes four PLLs.
These modules are responsible for clock and reset distribution in the
system, as well as for system power management.
CSPI
ECSPI-1
ECSPI-2
Configurable
SPI, Enhanced
CSPI
Connectivity
Peripherals
Full-duplex enhanced synchronous serial interface, with data rates
16-60 Mbit/s. It is configurable to support master/slave modes. In Master
mode it supports four slave selects for multiple peripherals.
CSU
Central Security Security
Unit
The central security unit (CSU) is responsible for setting comprehensive
security policy within the i.MX53xA platform, and for sharing security
information between the various security modules. The security control
registers (SCR) of the CSU are set during boot time by the high assurance
boot (HAB) code and are locked to prevent further writing.
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Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
DEBUG
Debug System
System
Control
The debug system provides real-time trace debug capability of both
instructions and data. It supports a trace protocol that is an integral part of
the ARM Real Time Debug solution (RealView).
Real-time tracing is controlled by specifying a set of triggering and filtering
resources, which include address and data comparators, three
cross-system triggers (CTI), counters, and sequencers.
debug access port (DAP) —The DAP provides real-time access for the
debugger without halting the core to system memory, peripheral register,
debug configuration registers and JTAG scan chains.
EXTMC
External Memory Connectivity
Controller Peripherals
The EXTMC is an external and internal memory interface. It performs
arbitration between multi-AXI masters to multi-memory controllers, divided
into four major channels, fast memories (DDR2/DDR3/LPDDR2) channel,
slow memories (NOR-FLASH / PSRAM / NAND-FLASH etc.) channel,
internal memory (RAM, ROM) channel and graphical memory (GMEM)
channel.
In order to increase the bandwidth performance, the EXTMC separates the
buffering and the arbitration between different channels so parallel
accesses can occur. By separating the channels, slow accesses do not
interfere with fast accesses.
EXTMC Features:
• 64-bit and 32-bit AXI ports
• Enhanced arbitration scheme for fast channel, including dynamic master
priority, and taking into account which pages are open or closed and
what type (read or write) was the last access
• Flexible bank interleaving
• Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2.
• Support up to 2 GByte DDR memories.
• Support NFC, EIM signal muxing scheme.
• Support 8/16/32-bit Nor-Flash/PSRAM memories (sync and async
operating modes), at slow frequency. (8-bit is not supported on
D[23]-D[16]).
• Support 4/8/14/16-bit ECC, page sizes of 512-B, 2-KB and 4-KB
Nand-Flash (including MLC)
• Multiple chip selects (up to 4).
• Enhanced DDR memory controller, supporting access latency hiding
• Support watermark for security (internal and external memories)
EPIT-1
EPIT-2
Enhanced
Periodic Interrupt Peripherals
Timer
Timer
Each EPIT is a 32-bit “set and forget” timer that starts counting after the
EPIT is enabled by software. It is capable of providing precise interrupts at
regular intervals with minimal processor intervention. It has a 12-bit
prescaler for division of input clock frequency to get the required time
setting for the interrupts to occur, and counter values can be programmed
on the fly.
ESAI
Enhanced Serial Connectivity
The enhanced serial audio interface (ESAI) provides a full-duplex serial port
for serial communication with a variety of serial devices, including
industry-standard codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and receiver sections, each
section with its own clock generator.
Audio Interface
Peripherals
The ESAI has 12 pins for data and clocking connection to external devices.
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Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
ESDHCV3-3 Ultra-High-
Speed eMMC /
Connectivity
Peripherals
Ultra high-speed eMMC / SD host controller, enhanced to support eMMC
4.4 standard specification, for 832 MBps.
SD Host
Controller
• Port 3 is specifically enhanced to support eMMC 4.4 specification, for
double data rate (832 Mbps, 8-bit port).
ESDHCV3 is backward compatible to ESDHCV2 and supports all the
features of ESDHCV2 as described below.
ESDHCV2-1 Enhanced
ESDHCV2-2 Multi-Media Card
Enhanced multimedia card / secure digital host controller
• Ports 1, 2, and 4 are compatible with the “MMC System Specification”
version 4.3, full support and supporting 1, 4 or 8-bit data.
The generic features of the eSDHCv2 module, when serving as SD / MMC
host, include the following:
ESDHCv2-4
/
Secure Digital
Host Controller
• Can be configured either as SD / MMC controller
• Supports eSD and eMMC standard, for SD/MMC embedded type cards
• Conforms to SD Host Controller Standard Specification, version 2.0, full
support.
• Compatible with the SD Memory Card Specification, version 1.1
• Compatible with the SDIO Card Specification, version 1.2
• Designed to work with SD memory, miniSD memory, SDIO, miniSDIO,
SD Combo, MMC and MMC RS cards
• Configurable to work in one of the following modes:
- SD/SDIO 1-bit, 4-bit
- MMC 1-bit, 4-bit, 8-bit
• Full/high speed mode.
• Host clock frequency variable between 32 kHz to 52 MHz
• Up to 200 Mbps data transfer for SD/SDIO cards using 4 parallel data
lines
• Up to 416 Mbps data transfer for MMC cards using 8 parallel data lines
FEC
FIRI
Fast Ethernet
Controller
Connectivity
Peripherals
The Ethernet media access controller (MAC) is designed to support both
10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media.
The i.MX53xA also consists of HW assist for IEEE1588™ standard. See,
TSU and CE_RTC (IEEE1588) section for more details.
Fast Infrared
Interface
Connectivity
Peripherals
Fast infrared interface
FLEXCAN-1 Flexible
FLEXCAN-2 Controller Area
Network
Connectivity
Peripherals
The controller area network (CAN) protocol was primarily, but not
exclusively, designed to be used as a vehicle serial data bus. Meets the
following specific requirements of this application: real-time processing,
reliable operation in the EXTMC environment of a vehicle,
cost-effectiveness and required bandwidth. The FLEXCAN is a full
implementation of the CAN protocol specification, Version 2.0 B (ISO
11898), which supports both standard and extended message frames at
1 Mbps.
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Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block Name Subsystem Brief Description
General Purpose System
Block
Mnemonic
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPIO-5
GPIO-6
GPIO-7
These modules are used for general purpose input/output to external ICs.
Each GPIO module supports up to 32 bits of I/O.
I/O Modules
Control
Peripherals
GPT
General Purpose Timer
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a
programmable prescaler and compare and capture register. A timer counter
value can be captured using an external event, and can be configured to
trigger a capture event on either the leading or trailing edges of an input
pulse. When the timer is configured to operate in “set and forget” mode, it is
capable of providing precise interrupts at regular intervals with minimal
processor intervention. The counter has output compare logic to provide the
status and interrupt at comparison. This timer can be configured to run
either on an external clock or on an internal clock.
Timer
Peripherals
GPU3D
GPU2D
Graphics
Processing Unit Peripherals
Multimedia
The GPU, version 3, provides hardware acceleration for 2D and 3D
graphics algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD1080 resolution. It
supports color representation up to 32 bits per pixel. GPU enables
high-performance mobile 3D and 2D vector graphics at rates up to 33
Mtriangles/s, 200 Mpix/s, 800 Mpix/s (z).
Graphics
Processing
Unit-2D
Multimedia
Peripherals
The GPU2D version 1, provides hardware acceleration for 2D graphic
algorithms with sufficient processor power to run desk-top quality
interactive graphics applications on displays up to HD1080 resolution.
I2C-1
I2C-2
I2C-3
I2C Controller
Connectivity
Peripherals
I2C provides serial interface for controlling peripheral devices. Data rates of
up to 400 kbps are supported.
IIM
IC Identification Security
Module
The IC identification module (IIM) provides an interface for reading,
programming, and/or overriding identification and control information stored
in on-chip fuse elements. The module supports electrically programmable
poly fuses (e-Fuses). The IIM also provides a set of volatile
software-accessible signals that can be used for software control of
hardware elements not requiring non-volatility. The IIM provides the primary
user-visible mechanism for interfacing with on-chip fuse elements. Among
the uses for the fuses are unique chip identifiers, mask revision numbers,
cryptographic keys, JTAG secure mode, boot characteristics, and various
control signals requiring permanent non-volatility. The IIM also provides up
to 28 volatile control signals. The IIM consists of a master controller, a
software fuse value shadow cache, and a set of registers to hold the values
of signals visible outside the module.
IIM interfaces to the electrical fuse array (split to banks). Enabled to set up
boot modes, security levels, security keys and many other system
parameters.
i.MX53A consists of 4 x 256-bit + 1x 128-bit fuse-banks (total 1152 bits)
through IIM interface.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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11
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
IOMUXC
IPU
IOMUX Control
System
Control
Peripherals
This module enables flexible I/O multiplexing. Each I/O pad has default as
well as several alternate functions. The alternate functions are software
configurable.
Image
Multimedia
Version 3M IPU enables connectivity to displays, relevant processing and
synchronization. It supports two display ports and two camera ports,
through the following interfaces:
Processing Unit Peripherals
• Legacy parallel interfaces
• Single/dual channel LVDS display interface
• Analog TV or VGA interfaces
The processing includes:
• Image enhancement—color adjustment and gamut mapping, gamma
correction and contrast enhancement
• Video/graphics combining
• Support for display backlight reduction
• Image conversion—resizing, rotation, inversion and color space
conversion
• Hardware de-interlacing support
• Synchronization and control capabilities, allowing autonomous
operation.
KPP
LDB
MLB
Keypad Port
Connectivity
Peripherals
The KPP supports an 8 × 8 external keypad matrix. The KPP features are
as follows:
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
LVDS Display
Bridge
Connectivity
Peripherals
LVDS display bridge is used to connect the IPU (image processing unit) to
external LVDS display interface. LDB supports two channels; each channel
has following signals:
• 1 clock pair
• 4 data pairs
On-chip differential drivers are provided for each pair.
Media local
Connectivity/ The MLB interface module provides a link to a MOST® data network, using
bus—MediaLB
Multimedia
Peripherals
the standardize MediaLB protocol (up to 50 Mbps).
OWIRE
PATA
One-Wire
Interface
Connectivity
Peripherals
One-wire support provided for interfacing with an on-board EEPROM, and
smart battery interfaces, for example, Dallas DS2502.
Parallel ATA
Connectivity
Peripherals
The PATA block is a AT attachment host interface. Its main use is to interface
with hard disk drives and optical disc drives. It interfaces with the ATA-6
compliant device over a number of ATA signals. It is possible to connect a
bus buffer between the host side and the device side.
PWM-1
PWM-2
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate
tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate
sound.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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12
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
Internal RAM, shared with VPU.
The on-chip memory controller (OCRAM) module, is an interface between
the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is
used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.
INTRAM
Internal RAM
Internal
Memory
BOOTROM Boot ROM
Internal
Memory
Supports secure and regular boot modes.
The ROM controller supports ROM patching.
RTIC
Run-Time
Integrity Checker
Security
Protecting read only data from modification is one of the basic elements in
trusted platforms. The run-time integrity checker, version 3 (RTIC) block is
a data-monitoring device responsible for ensuring that the memory content
is not corrupted during program execution. The RTIC mechanism
periodically checks the integrity of code or data sections during normal OS
run-time execution without interfering with normal operation. The purpose
of the RTIC is to ensure the integrity of the peripheral memory contents,
protect against unauthorized external memory elements replacement and
assist with boot authentication.
SAHARA
SAHARA
Security
Accelerator
Security
SAHARA (symmetric/asymmetric hashing and random accelerator),
version 4, is a security coprocessor. It implements symmetric encryption
algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA
and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and
a hardware true random number generator. It has a slave IP Bus interface
for the host to write configuration and command information, and to read
status information. It also has a DMA controller, with an AHB bus interface,
to reduce the burden on the host to move the required data to and from
memory.
SATA
Serial ATA
Connectivity
Peripherals
SATA HDD interface, includes the SATA controller and the PHY. It is a
complete mixed-signal IP solution for SATA HDD connectivity.
SCCv2
Security
Controller, ver. 2
Security
The security controller is a security assurance hardware module designed
to safely hold sensitive data, such as encryption keys, digital right
management (DRM) keys, passwords and biometrics reference data. The
SCCv2 monitors the system’s alert signal to determine if the data paths to
and from it are secure, that is, it cannot be accessed from outside of the
defined security perimeter. If not, it erases all sensitive data on its internal
RAM. The SCCv2 also features a key encryption module (KEM) that allows
non-volatile (external memory) storage of any sensitive data that is
temporarily not in use. The KEM utilizes a device-specific hidden secret key
and a symmetric cryptographic algorithm to transform the sensitive data
into encrypted data.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
SDMA
Smart Direct
Memory Access Control
Peripherals
System
The SDMA is multi-channel flexible DMA engine. It helps in maximizing
system performance by off loading various cores in dynamic data routing.
The SDMA features list is as follows:
• Powered by a 16-bit instruction-set micro-RISC engine
• Multi-channel DMA supports up to 32 time-division multiplexed DMA
channels
• 48 events with total flexibility to trigger any combination of channels
• Memory accesses including linear, FIFO, and 2D addressing
• Shared peripherals between ARM and SDMA
• Very fast context-switching with two-level priority-based preemptive
multi-tasking
• DMA units with auto-flush and prefetch capability
• Flexible address management for DMA transfers (increment, decrement,
and no address changes on source and destination address)
• DMA ports can handle unidirectional and bidirectional flows (copy mode)
• Up to 8-word buffer for configurable burst transfers to / from the EXTMC
• Support of byte swapping and CRC calculations
• A library of scripts and API is available
SECRAM
SJC
Secure /
Non-secure RAM Memory
Internal
Secure / non-secure Internal RAM, controlled by SCC.
Secure JTAG
Interface
System
Control
Peripherals
JTAG manipulation is a known hacker’s method of executing unauthorized
program code, getting control over secure applications, and running code in
privileged modes. The JTAG port provides a debug access to several
hardware blocks including the ARM processor and the system bus.
The JTAG port must be accessible during platform initial laboratory
bring-up, manufacturing tests and troubleshooting, as well as for software
debugging by authorized entities. However, in order to properly secure the
system, unauthorized JTAG usage should be strictly forbidden.
In order to prevent JTAG manipulation while allowing access for
manufacturing tests and software debugging, the i.MX53xA processor
incorporates a mechanism for regulating JTAG access. SJC provides four
different JTAG security modes that can be selected through an e-fuse
configuration.
SPBA
Shared
Peripheral Bus
Arbiter
System
Control
Peripherals
SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP
bus) arbiter.
SPDIF
Sony Philips
Digital Interface Peripherals
Multimedia
A standard digital audio transmission protocol developed jointly by the Sony
and Philips corporations. Both transmitter and receiver functionalists are
supported.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
SRTC
Secure Real
Time Clock
Security
The SRTC incorporates a special system state retention register (SSRR)
that stores system parameters during system shutdown modes. This
register and all SRTC counters are powered by dedicated supply rail
NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized
separately even if all other supply rails are shut down. The power for this
block comes from NVCC_SRTC_POW supply. When this supply is driven
by the MC13892 power management controller, this block can be power
backed up through the coin-cell feature of the MC13892. This register is
helpful for storing warm boot parameters. The SSRR also stores the system
security state. In case of a security violation, the SSRR mark the event
(security violation indication).
SSI-1
SSI-2
SSI-3
I2S/SSI/AC97
Interface
Connectivity
Peripherals
The SSI is a full-duplex synchronous interface used on the i.MX53A
processor to provide connectivity with off-chip audio peripherals. The SSI
interfaces connect internally to the AUDMUX for mapping to external ports.
The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S,
and AC-97), bit depths (up to 24 bits per word), and clock/frame sync
options.
Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an
external DMA controller in order to minimize its impact on system
performance. The second pair of FIFOs provides hardware interleaving of
a second audio stream, which reduces CPU overhead in use cases where
two time slots are being used simultaneously.
IPTP
IEEE1588
Precision Time
Protocol
Connectivity
Peripherals
The IEEE 1588-2002 (version 1) standard defines a precision time protocol
(PTP) - which is a time-transfer protocol that enables synchronization of
networks (for example, Ethernet), to a high degree of accuracy and
precision.
The IEEE1588 hardware assist is composed of the two blocks: time stamp
unit and real time clock, which provide the timestamping protocol’s
functionality, generating and reading the needed timestamps.
The hardware-assisted implementation delivers more precise clock
synchronization at significantly lower CPU load compared to purely
software implementations.
Temperature
Monitor
(Part of SATA
Block)
System
Control
Peripherals
The temperature sensor is an internal module to the i.MX53xA that monitors
the die temperature. The monitor is capable in generating SW interrupt, or
trigger the CCM, to reduce the core operating frequency.
TVE
TV Encoder
Multimedia
The TV encoder, version 2.1 is implemented in conjunction with the image
processing unit (IPU) allowing handheld devices to display captured still
images and video directly on a TV or LCD projector. It supports composite
PAL/NTSC, VGA, S-video, and component up to HD1080p analog video
outputs.
TZIC
TrustZone Aware ARM/Control The TrustZone interrupt controller (TZIC) collects interrupt requests from all
Interrupt
Controller
i.MX53xA sources and routes them to the ARM core. Each interrupt can be
configured as a normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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15
Modules List
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
UART-1
UART-2
UART-3
UART-4
UART-5
UART Interface
Connectivity
Peripherals
Each of the UART blocks supports the following serial data transmit/receive
protocols and configurations:
• 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd,
or none)
• Programmable bit-rates up to 4 Mbps. This is a higher max baud rate
relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F
standard.
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
USB
USB Controller
Connectivity
Peripherals
USB supports USB2.0 480 MHz, and contains:
• One high-speed OTG sub-block with integrated HS USB PHY
• One high-speed host sub-block with integrated HS USB PHY
• Two identical high-speed Host modules
The high-speed OTG module, which is internally connected to the HS USB
PHY, is equipped with transceiver-less logic to enable on-board USB
connectivity without USB transceivers
All the USB ports are equipped with standard digital interfaces (ULPI, HS
IC-USB) and transceiver-less logic to enable onboard USB connectivity
without USB transceivers.
VPU
VideoProcessing Multimedia
A high-performing video processing unit (VPU) version 3, which covers
many SD-level video decoders and SD-level encoders as a multi-standard
video codec engine as well as several important video processing such as
rotation and mirroring.
Unit
Peripherals
VPU Features:
• MPEG-2 decode, Mail-High profile, up to 1080i/p resolution, 40 Mbps bit
rate
• MPEG4/XviD decode, SP/ASP profile, up to 1080 i/p resolution, 40 Mbps
bit rate
• H.263 decode, P0/P3 profile, up to 16CIF resolution, 20 Mbps bit rate
• Sorenson H.263 decode, 4CIF resolution, 8 Mbps bit rate
• H.264 decode, BP/MP/HP profile, up to 1080 i/p resolution, 40 Mbps bit
rate
• VC1 decode, SP/MP/AP profile, up to 1080 i/p resolution, 40 Mbps bit
rate
• RV10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 Mbps bit rate
• DivX decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 Mbps bit rate
• MJPEG decode, Baseline profile, up to 8192 x 8192 resolution,
40 Mpixel/s bit rate for 4:4:4 format
• MPEG21 encode, Main-Main profile, up to D1 resolution, 15 Mbps bit
rate
• MPEG4 encode, Simple profile, up to 720p resolution, 12 Mbps bit rate2
• H.263 encode, P0/P3 profile, up to 4CIF resolution, 8 Mbps bit rate2
• H.264 encode, Baseline profile, up to 720p resolution, 14 Mbps bit rate2
• MJPEG encode, Baseline profile, up to 8192 x 8192 resolution,
80 Mpixel/s bit rate for 4:2:2 format
WDOG-1
Watch Dog
Timer
Peripherals
The watch dog timer supports two comparison points during each counting
period. Each of the comparison points is configurable to evoke an interrupt
to the ARM core, and a second point evokes an external event on the
WDOG line.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Electrical Characteristics
Table 2. i.MX53xA Digital and Analog Blocks (continued)
Block
Mnemonic
Block Name
Subsystem
Brief Description
WDOG-2
(TZ)
Watch Dog
(TrustZone)
Timer
Peripherals
The TrustZone watchdog (TZ WDOG) timer module protects against
TrustZone starvation by providing a method of escaping normal mode and
forcing a switch to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. This situation should be
avoided, as it can compromise the system’s security. Once the TZ WDOG
module is activated, it must be serviced by TZ software on a periodic basis.
If servicing does not take place, the timer times out. Upon a time-out, the
TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ
mode. If it is still not served, the TZ WDOG asserts a security violation
signal to the CSU. The TZ WDOG module cannot be programmed or
deactivated by a normal mode SW.
XTALOSC
24 MHz Crystal
Oscillator
Clocking
Clocking
Provides a crystal oscillator amplifier that supports a 24-MHz external
crystal
XTALOSC_ 32.768 KHz
32K Crystal Oscillator
I/F
Provides a crystal oscillator amplifier that supports a 32.768-kHz external
crystal.
1
2
Video partially performed in hardware accelerator (70%) and partially in software.
VPU can generate higher bit rate than the maximum specified by the corresponding standard.
3.1
Special Signal Considerations
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are defined in the i.MX53 Reference Manual. Special signal
considerations information is contained in Chapter 1 of i.MX53 System Development User's Guide.
Document number is MX53UG.
4 Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX53xA processor.
NOTE
This electrical specification is preliminary. These specifications are not fully
tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after thorough characterization and device
qualifications have been completed.
4.1
Chip-Level Conditions
This section provides the device-level electrical characteristics for the IC. See Table 3 for a quick reference
to the individual tables and sections.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Electrical Characteristics
Table 3. i.MX53xA Chip-Level Conditions
For these characteristics, …
Absolute Maximum Ratings
Topic appears …
Table 4 on page 18
Table 5 on page 19
Table 6 on page 20
Table 7 on page 22
Table 8 on page 22
Table 9 on page 24
TEPBGA-2 Package Thermal Resistance Data
i.MX53xA Operating Ranges
External Clock Sources
Maximal Supply Currents
USB Interface Current Consumption
4.1.1
Absolute Maximum Ratings
CAUTION
Stresses beyond those listed under Table 4 may cause permanent damage to
the device. These are stress ratings only. Functional operation of the device
at these or any other conditions beyond those indicated under Table 6 is not
implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
Table 4. Absolute Maximum Ratings
Parameter Description
Symbol
Min
Max
Unit
Peripheral Core Supply Voltage
ARM Core Supply Voltage
Supply Voltage UHVIO
Supply Voltage for non UHVIO
USB VBUS
VCC
VDDGP
–0.3
–0.3
–0.5
–0.5
—
1.35
1.35
3.6
V
V
V
V
V
V
Supplies denoted as I/O Supply
Supplies denoted as I/O Supply
VBUS
3.3
5.25
3.631
Input voltage on USB_OTG_DP, USB_OTG_DN,
USB_H1_DP, USB_H1_DN pins
USB_DP/USB_DN
–0.3
Input/Output Voltage Range
ESD Damage Immunity:
Vin/Vout
Vesd
–0.5
OVDD +0.32
V
V
• Human Body Model (HBM)
• Charge Device Model (CDM)
—
—
2000
500
Storage Temperature Range
TSTORAGE
–40
150
oC
1
USB_DN and USB_DP can tolerate 5 V for up to 24 hours.
2
The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in
Table 113 on page 156. The maximum range can be superseded by the DC tables.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
18
Freescale Semiconductor
Electrical Characteristics
4.1.2
Thermal Resistance
4.1.2.1
TEPBGA-2 Package Thermal Resistance
Table 5 provides the TEPBGA-2 package thermal resistance data.
Table 5. TEPBGA-2 Package Thermal Resistance Data
Rating
Board
Symbol
Value
Unit
Junction to Ambient (natural convection)1, 2
Single layer board
(1s)
RθJA
28
°C/W
Junction to Ambient (natural convection)1, 2, 3
Junction to Ambient (at 200 ft/min)1, 3
Junction to Ambient (at 200 ft/min)1, 3
Four layer board
(2s2p)
RθJA
RθJMA
RθJMA
16
21
13
°C/W
°C/W
°C/W
Single layer board
(1s)
Four layer board
(2s2p)
Junction to Board4
—
—
—
RθJB
RθJC
ΨJT
6
4
4
°C/W
°C/W
°C/W
Junction to Case5
Junction to Package Top (natural convection)6
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2
3
4
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5
6
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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19
Electrical Characteristics
4.1.3
Operating Ranges
Table 6 provides the operating ranges of i.MX53xA processor.
Table 6. i.MX53xA Operating Ranges
Symbol
Parameter
ARM core supply voltage
fARM ≤ 800 MHz
Minimum1 Nominal2 Maximum1 Unit
1.05
0.8
1.1
1.15
1.15
V
V
VDDGP
ARM core supply voltage
Stop mode
0.85
Peripheral supply voltage
1.25
0.9
1.3
1.35
1.35
V
V
Peripheral supply voltage—Stop mode
0.95
VCC
Memory arrays voltage
1.25
0.9
1.30
0.95
1.30
0.95
1.3
1.35
1.35
1.35
1.35
1.35
1.95
1.95
V
V
V
V
V
V
V
VDDA3
Memory arrays voltage—Stop mode
L1 Cache Memory arrays voltage
1.25
0.9
VDDAL13
L1 Cache Memory arrays voltage—Stop mode
PLL Digital supplies—external regulator option
PLL Analog supplies—external regulator option
VDD_DIG_PLL4
VDD_ANA_PLL5
1.25
1.75
1.65
1.8
ESD protection of the CKIH pins, FUSE read Supply
and 1.8V bias for the UHVIO pads
1.8
NVCC_CKIH
NVCC_LCD
NVCC_JTAG
GPIO digital power supplies
1.65
1.8 or
2.775
3.1
V
NVCC_LVDS
LVDS interface Supply
2.25
2.25
1.7
2.5
2.5
1.8
1.2
1.55
1.5
1.5
—
2.75
2.75
1.9
V
V
NVCC_LVDS_BG
LVDS Band Gap Supply
DDR Supply DDR2 range
DDR Supply LPDDR2 range
1.14
1.47
1.42
1.42
3.0
1.3
NVCC_EMI_DRAM
VDD_FUSE6
1.63
1.58
1.58
3.3
V
V
DDR Supply LV-DDR2 range
DDR Supply DDR3 range
Fusebox Program Supply (Write Only)
Ultra High voltage I/O (UHVIO) supplies:
• UHVIO_L
NVCC_NANDF
NVCC_SD1
NVCC_SD2
1.65
2.5
1.8
1.95
3.1
NVCC_PATA
• UHVIO_H
2.775
NVCC_KEYPAD
NVCC_GPIO
NVCC_FEC
V
• UHVIO_UH
3.0
3.3
3.6
NVCC_EIM_MAIN
NVCC_EIM_SEC
NVCC_CSI
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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20
Electrical Characteristics
Table 6. i.MX53xA Operating Ranges (continued)
Symbol
Parameter
Minimum1 Nominal2 Maximum1 Unit
TVE digital and analog power supply, TVE-to-DAC
level shifter supply, cable detector supply, analog
power supply to RGB channel
2.69
1.65
2.75
2.91
V
TVDAC_DHVDD7
TVDAC_AHVDDRGB7
For GPIO use only, when TVE is not in use
1.8 or
2.775
3.1
V
NVCC_SRTC_POW
NVCC_RESET
SRTC Core and slow I/O Supply (GPIO)8
LVIO
1.25
1.65
1.3
1.35
3.1
V
V
1.8 or
2.775
USB_H1_VDDA25
USB_OTG_VDDA25
NVCC_XTAL
USB_PHY analog supply, oscillator amplifier analog
supply9
2.25
3.0
2.5
2.75
3.6
V
V
USB_H1_VDDA33
USB PHY I/O analog supply
3.3
USB_OTG_VDDA33
See Table 4 on page 18 and Table 106 on page 148
for details. Note that this is not a power supply.
VBUS
—
—
—
—
V
VDD_REG10
Power supply input for the integrated linear
regulators
2.37
2.5
2.63
VP
VPH
TJ
SATA PHY core power supply
SATA PHY I/O supply voltage
Junction Temperature
1.25
2.25
–40
1.3
2.5
1.35
2.75
125
V
V
10511
oC
1
2
3
Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design
must allow for supply tolerances and system voltage drops.
The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than 50 mV. Use of supplies with a
tighter tolerance allows reduction of the setpoint with commensurate power savings.
VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this
configuration, the regulator is still operating at the default 1.2 V, as bootup start. During bootup initialization, software should
increase this regulator voltage to match VCC (1.3 V nominal) in order to reduce internal leakage current.
4
By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this
supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass
capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use
of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.
5
6
7
By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving
this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is
driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.
After fuses are programmed, Freescale strongly recommends the best practice of reading the fuses to verify that they are
written correctly. In Read mode, VDD_FUSE should be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V–3.3
V) increases the possibility of inadvertently blowing fuses and is not recommended in read mode.
If not using TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and TVDAC_AHVDDRGB
can remain floating.
8
9
GPIO pad operational at low frequency
The analog supplies should be isolated in the application design. Use of series inductors is recommended.
10 VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are
configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and
VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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21
Electrical Characteristics
11 Lifetime of 43,800 hours based on 105 C junction temperature at nominal supply voltages.
4.1.4
External Clock Sources
The i.MX53xA device has four external input system clocks, a low frequency (CKIL), a high frequency
(XTAL), and two general purpose CKIH1 and CKIH2 clocks.
The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real
time clock operation, and slow system and watch-dog counters. The clock input can be connected to either
external oscillator or a crystal using internal oscillator amplifier.
The system clock input XTAL is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either external oscillator or a crystal using internal
oscillator amplifier.
CKIH1 and CKIH2 provide additional clock source option for peripherals that require specific and
accurate frequencies.
Table 7 shows the interface frequency requirements. Refer to Chapter 1 of the i.MX53 System
Development User's Guide for additional clock and oscillator information. Document number is
MX53UG.
Table 7. External Input Clock Frequency
Parameter Description
CKIL Oscillator1
Symbol
Min
Typ
Max
Unit
fckil
—
32.7682/32.0
—
kHz
CKIH1, CKIH2 Operating
Frequency
fckih1
fckih2
,
See Table 32, "CAMP Electrical Parameters (CKIH1,
CKIH2)," on page 46
MHz
XTAL Oscillator
fxtal
22
24
27
MHz
1
External oscillator or a crystal with internal oscillator amplifier.
Recommended nominal frequency 32.768 kHz.
2
4.1.5
Maximal Supply Currents
Table 8 represents the maximal momentary current transients on power lines, and should be used for power
supply selection. Maximal currents higher by far than the average power consumption of typical use cases.
For typical power consumption information, refer to i.MX53xA power consumption application note.
Table 8. Maximal Supply Currents
Power Line
Conditions
Max Current
Unit
VDDGP
VCC
800 MHz ARM clock.
1450
800
100
10
mA
mA
mA
mA
mA
mA
VDDA+VDDAL1
VDD_DIG_PLL
VP
20
VDD_ANA_PLL
10
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22
Freescale Semiconductor
Electrical Characteristics
Unit
Table 8. Maximal Supply Currents (continued)
Power Line
Conditions
Max Current
MVCC_XTAL
VDD_REG
25
mA
mA
mA
325
120
VDD_FUSE
Fuse Write Mode
operation
1.8v (DDR2)
1.5v (DDR3)
1.2v (LPDDR2)
800
650
250
200
<1
mA
mA
mA
mA
mA
mA
NVCC_EMI_DRAM
TVDAC_DHVDD + TVDAC_AHVDDRGB
NVCC_SRTC_POW
USB_H1_VDDA25 +
USB_OTG_VDDA25
50
USB_H1_VDDA33 +
USB_OTG_VDDA33
20
mA
mA
VPH
60
NVCC_CKIH
Use maximal IO Eq1, N=4
NVCC_CSI
Use maximal IO Eq1, N=20
Use maximal IO Eq1, N=39
Use maximal IO Eq1, N=16
Use maximal IO Eq1, N=78
Use maximal IO Eq1, N=11
Use maximal IO Eq1, N=13
Use maximal IO Eq1, N=6
Use maximal IO Eq1, N=11
Use maximal IO Eq1, N=29
Use maximal IO Eq1, N=20
Use maximal IO Eq1, N=1
Use maximal IO Eq1, N=8
Use maximal IO Eq1, N=29
Use maximal IO Eq1, N=5
Use maximal IO Eq1, N=6
NVCC_EIM_MAIN
NVCC_EIM_SEC
NVCC_EMI_DRAM
NVCC_FEC
NVCC_GPIO
NVCC_JTAG
NVCC_KPAD
NVCC_LCD
NVCC_LVDS
NVCC_LVDS_BG
NVCC_NANDF
NVCC_PATA
NVCC_REST
NVCC_SD1
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Electrical Characteristics
Table 8. Maximal Supply Currents (continued)
Conditions Max Current
Power Line
Unit
NVCC_SD2
NVCC_XTAL
Use maximal IO Eq1, N=6
Use maximal IO Eq1, N=2
1
General Equation for estimated, maximal power consumption of an IO power supply:
Imax = N * C * V * (0.5 * F)
Where:
N - Number of IO pins supplies by the power line
C - Equivalent external capacitive load
V - IO voltage
(0.5 * F) - Data change rate. Up to 0.5 of the clock rate (F).
4.1.6
USB-OH-3 (OTG + 3 Host ports) Module and the Two USB PHY (OTG
and H1) Current Consumption
Table 9 shows the USB interface current consumption.
Table 9. USB Interface Current Consumption
Parameter
Conditions
Typical at 25 °C
Max
Unit
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
5.5
7
6
8
Full Speed
Analog Supply 3.3 V
USB_H1_VDDA33
USB_OTG_VDDA33
mA
5
6
High Speed
Full Speed
High Speed
Full Speed
High Speed
5
6
6.5
6.5
12
21
8
7
Analog Supply 2.5 V
USB_H1_VDDA25
USB_OTG_VDDA25
7
mA
mA
13
22
—
—
—
—
8
Digital Supply
VCC (1.2 V)
8
8
4.2
Power Supplies Requirements and Restrictions
The system design must comply with power-up sequence, power-down sequence and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from
these sequences may result in the following situations:
•
•
Excessive current during power-up phase
Prevention of the device from booting
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
24
Electrical Characteristics
•
Irreversible damage to the i.MX53xA processor (worst-case scenario)
4.2.1
Power-Up Sequence
The following observations should be considered:
•The consequent steps in power up sequence should not start before the previous step supplies have
been stabilized within 90-110% of their nominal voltage, unless stated otherwise.
•NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time
clock status. Otherwise, it has to be powered ON together with VCC, or preceding VCC.
•The VCC should be powered ON together, or any time after NVCC_SRTC_POW.
•NVCC_CKIH should be powered ON after VCC is stable and before other IO supplies
(NVCC_xxx) are powered ON.
•IO Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede
NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is
stabilized. Within this group, the supplies can be powered-up in any order.
•IO Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after
NVCC_CKIH is stable.
•In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator
(default case for i.MX53), there are no related restrictions on VDD_REG, as it is used as their
internal regulators power source.
If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage
during the power-up, it is recommended to activate the VDD_REG before or at the same time
with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that
the 2.5 V VDD_REG supply shut-off output impedance is higher than 1 kΩ when it is inactive.
•VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered
on after VCC and before NVCC_EMI_DRAM. The sequence should be:
VCC →VDD_REG →NVCC_EMI_DRAM
•VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless of any other power
signal.
•VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.
•VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come
before POR.
•TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This
is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is
powered ON before the other.
NOTE
The POR_B input must be immediately asserted at power-up and remain
asserted until after the last power rail reaches its working voltage.
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Electrical Characteristics
Figure 2 shows the power-up sequence diagram.
NVCC_SRTC_POW
90%
(may remain ON)
VCC
90%
Δt > 0
NVCC_CKIH
90%
Δt > 0
IO Supplies below or equal to
2.8 V nom./3.1 V max.
90%
90%
(in any order, after NVCC_CKIH
ramp up start, if needed)
Δt > 0
IO Supplies above 2.8 V nom./3.1 V max
(in any order, if needed)
Δt > 0
Δt > 0
90%
VDD_REG
Δt > 0
90%
NVCC_EMI_DRAM
Δt > 0
VP, VPH
(in any order)
90%
Δt > 0
Δt > 0
VDDA,VDDAL1,VDDGP
(in any order)
90%
POR_B
1
Figure 2. Power Up Detailed Sequence
NOTE
Need to ensure that there is no back voltage (leakage) from any supply on
the board towards the 3.3 V supply (for example, from the parts that use
both 1.8 V and the 3.3 V supply).
1. If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable.
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26
Freescale Semiconductor
Electrical Characteristics
4.2.2
Power-Down Sequence
Power-down sequence should follow one of the following two options:
Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few
microseconds of actual power-down of the different power rails is acceptable.
Option 2: Switch down supplies, in any order, keeping the following rules:
•
NVCC_CKIH must be powered down at the same time or after the UHVIO IO cell supplies (for
full supply list, refer to Table 6, Ultra High voltage I/O (UHVIO) supplies). A deviation of few
microseconds of actual power-down of the different power rails is acceptable.
•
•
VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A
deviation of few microseconds of actual power-down of the different power rails is acceptable.
If all of the following conditions are met:
— 1. VDD_REG is powered down to 0V (Not Hi-Z)
— 2. VDD_DIG_PLL and VDD_ANA_PLL are provided externally,
— 3. VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL
Then the following rule should be kept: VDD_REG output impedance must be higher than 1 kΩ,
when inactive.
4.2.3
Power Supplies Usage
•
All IO pins should not be externally driven while the IO power supply for the pin (NVCC_xxx) is
off. This can cause internal latch-up and malfunctions due to reverse current flows. For information
about IO power supply of each pin refer to “Power Rail” columns in pin list tables of Section 6,
“Package Information and Contact Assignments.”
•
If not using SATA interface and the embedded thermal sensor, the VP and VPH should be
grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not
recommended and might lead to excessive power consumption.
•
•
When internal clock source is used for SATA temperature monitor the USB_PHY supplies and
PLL need to be active because they are providing the clock.
If not using TVE the module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can remain
floating. If only the GPIO pads in TVDAC_AHVDDRGB domain are in use, the supplies can be
set to GPIO pad voltage range (1.65 V to 3.1 V).
4.3
I/O DC Parameters
This section includes the DC parameters of the following I/O types:
•
•
•
•
•
General Purpose I/O (GPIO)
Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes
Low Voltage I/O (LVIO)
Ultra High Voltage I/O (UHVIO)
LVDS I/O
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27
Electrical Characteristics
NOTE
The term ‘OVDD’ in this section refers to the associated supply rail of an
input or output. The association is shown in Table 113.
Figure 3. Circuit for Parameters Voh and Vol for IO Cells
4.3.1
General Purpose I/O (GPIO) DC Parameters
The parameters in Table 10 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 10 shows DC parameters for GPIO pads, operating at two supply ranges:
•
•
1.1 V to 1.3 V
1.65 V to 3.1 V
Table 10. GPIO I/O DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage1
Voh
Iout = –1 mA
Iout= specified Ioh Drive
OVDD – 0.15
0.8*OVDD
—
—
V
Low-level output voltage1
Vol
Ioh
Iout = 1 mA
Iout= specified Iol Drive
—
—
—
0.15
0.2 × OVDD
V
High-level output current
(1.1-1.3V OVDD)
Vout = 0.8×OVDD
Low drive
–0.85
–1.7
–2.5
–3.4
Medium drive
High drive
Max drive
—
—
—
mA
Low-level output current
(1.1-1.3V OVDD)
Iol
Vout = 0.2×OVDD
Low drive
0.9
1.9
2.9
3.8
Medium drive
High drive
Max drive
—
—
mA
mA
High-level output current
(1.65-3.1V OVDD)
Ioh
Vout = 0.8×OVDD
Low drive
–2.1
–4.2
–6.3
–8.4
Medium drive
High drive
Max drive
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Electrical Characteristics
Table 10. GPIO I/O DC Electrical Characteristics (continued)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Low-level output current
(1.65-3.1V OVDD)
Iol
Vout = 0.2×OVDD
Low drive
2.1
4.2
6.3
8.4
Medium drive
High drive
Max drive
—
—
mA
High-Level DC input voltage1, 2
Low-Level DC input voltage1, 2
Input Hysteresis
VIH
VIL
—
—
0.7 × OVDD
—
—
OVDD
0.3 × OVDD
—
V
V
V
0
VHYS
OVDD = 1.875 V
OVDD = 2.775 V
0.25
0.34
0.45
Schmitt trigger VT+2, 3
VT+
VT–
Iin
—
—
0.5 × OVDD
—
—
—
—
—
V
V
Schmitt trigger VT–2, 3
—
—
—
0.5 × OVDD
Input current (no pull-up/down)
Input current (22 kΩ Pull-up)
Vin = OVDD or 0
2
μA
Iin
Vin = 0 V
Vin = OVDD
161
2
μA
μA
μA
Input current (47 kΩ Pull-up)
Input current (100 kΩ Pull-up)
Input current (100 kΩ Pull-down)
Keeper Circuit Resistance
Iin
Iin
Iin
Vin = 0 V
Vin = OVDD
—
—
—
—
—
—
76
2
Vin = 0 V
Vin= OVDD
36
2
Vin = 0 V
Vin = OVDD
—
2
36
μA
kΩ
1304
—
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.
3
4
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.2
LPDDR2 I/O DC Parameters
The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.
4.3.2.1 DDR2 Mode I/O DC Parameters
The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The
parameters in Table 11 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
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Electrical Characteristics
Parameters
1
Table 11. DDR2 I/O DC Electrical Parameters
Symbol Test Conditions
Min
Typ
Max
Unit
High-level output voltage2
Low-level output voltage
Voh
Vol
Ioh
—
—
0.9*OVDD
—
—
—
—
—
0.1*OVDD
—
V
V
Output minimum Source Current3
OVDD=1.7 V,
Vout=1.42 V
–13.4
mA
Output min Sink Current4
Iol
OVDD=1.7 V,
Vout=280 mV
13.4
—
—
mA
V
Input Reference Voltage
Vref
0.49*OVDD
Vref+0.125V
0.5*OVDD
—
0.51*OVDD
OVDD+0.3
DC input High Voltage (data pins)
Vihd
(dc)
—
DC input Low Voltage (data pins)
Vild (dc)
Vin (dc)
—
—
–0.3
–0.3
—
—
Vref-0.125V
OVDD+0.3
V
V
DC Input voltage range of each
differential input5
DC Differential input voltage required for Vid (dc)
switching 6
—
0.25
—
OVDD+0.6
V
Termination Voltage
Vtt
Iin
Vtt
Vref – 0.04
Vref
Vref + 0.04
V
Input current (no pull-up/down)
Vin = 0 V
Vin=OVDD
—
—
—
—
1
1
μA
Keeper Circuit Resistance
—
—
—
1307
—
kΩ
1
Note that the JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any
specification in this document.
2
3
4
5
6
OVDD is the I/O power supply (1.7 V–1.9 V for DDR2)
(Vout - OVDD) / Ioh must be less than 21 Ω for values of Vout between OVDD and OVDD-0.28 V.
Vout / Iol must be less than 21 Ω for values of Vout between 0 V and 280 mV.
Vin(dc) specifies the allowable DC voltage exertion of each differential input.
Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input level and Vcp is the
“complementary” input level. The minimum value is equal to Vih(dc) -Vil(dc).
7
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.2.2
LPDDR2 Mode I/O DC Parameters
The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009.
1
Table 12. LPDDR2 I/O DC Electrical Parameters
Parameters
Symbol Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Low-level output voltage
Input Reference Voltage
DC input High Voltage
DC input Low Voltage
Voh
—
—
0.9*OVDD
—
—
—
V
V
Vol
—
0.5*OVDD
—
0.1*OVDD
0.51*OVDD
OVDD
Vref
0.49*OVDD
Vref+0.13V
OVSS
Vih(dc)
Vil(dc)
—
—
V
V
—
Vref-0.13V
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Electrical Characteristics
1
Table 12. LPDDR2 I/O DC Electrical Parameters (continued)
Differential Input Logic High
Vih(diff)
0.26
See Note2
-0.26
Differential Input Logic Low
Vil(diff)
Iin
See Note2
Input current (no pull-up/down)
Vin = 0 V
Vin=OVDD
—
—
—
—
1
1
μA
Pull-up/Pull-down impedance Mismatch
-15
+15
%
240 Ohm unit calibration resolution
Keeper Circuit Resistance
10
—
Ohm
—
—
—
1403
kΩ
1
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
2
3
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.2.3
DDR3 Mode I/O DC Parameters
The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The
parameters in Table 13 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 13. DDR3 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Low-level output voltage
DC input Logic High
Voh
Vol
—
—
—
—
—
—
—
—
0.8*OVDD1
—
—
—
—
—
—
—
—
—
—
0.2*OVDD
OVDD
Vref-0.1
See Note3
-0.2
V
V
V
V
V
V
V
VIH(dc)
VIL(dc)
VIH(diff)
VIL(diff)
Vpeak
Varea
Vref2+0.1
OVSS
0.2
DC input Logic Low
Differential input Logic High
Differential input Logic Low
Over/undershoot peak
See Note3
—
0.4
Over/undershoot area
(above OVDD or below OVSS)
—
0.67
V x
nS
Termination Voltage
Vtt
Iin
Vtt tracking OVDD/2
0.49*OVDD
Vref
0.51*OVDD
V
Input current (no pull-up/down)
VI = 0 V
VI=OVDD
—
—
—
—
1
1
μA
Pull-up/Pull-down impedance mismatch
—
Minimum impedance
configuration
—
—
3
Ω
240 Ω unit calibration resolution
—
—
—
—
—
—
—
10
—
Ω
Keeper Circuit Resistance
1304
kΩ
1
OVDD – I/O power supply (1.425 V–1.575 V for DDR3)
2
Vref – DDR3 external reference voltage
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31
Electrical Characteristics
3
The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
4
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.3
Low Voltage I/O (LVIO) DC Parameters
The parameters in Table 14 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
The LVIO pads operate only as inputs.
Table 14. LVIO DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
High-Level DC input voltage1, 2
Low-Level DC input voltage1, 2
Input Hysteresis
Vih
Vil
—
—
0.7 × OVDD
—
—
OVDD
0.3 × OVDD
—
V
V
V
0
Vhys
OVDD = 1.875 V
OVDD = 2.775 V
0.35
0.62
1.27
Schmitt trigger VT+2, 3
VT+
VT–
Iin
—
—
0.5 × OVDD
—
—
—
—
—
0.5 × OVDD
1
V
V
Schmitt trigger VT–2, 3
—
—
—
Input current (no pull-up/down)
Input current (22 kΩ Pull-up)
Vin = OVDD or 0 V
μA
Iin
Vin = 0 V
Vin = OVDD
161
1
μA
μA
μA
Input current (47 kΩ Pull-up)
Input current (100 kΩ Pull-up)
Input current (100 kΩ Pull-down)
Keeper Circuit Resistance
Iin
Iin
Iin
—
Vin = 0 V
Vin = OVDD
—
—
—
—
—
—
76
1
Vin = 0 V
Vin = OVDD
36
1
Vin = 0 V
Vin = OVDD
—
1
36
μA
kΩ
1304
—
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply
when hysteresis is enabled.
3
4
Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled.
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
32
Freescale Semiconductor
Electrical Characteristics
4.3.4
Ultra-High Voltage I/O (UHVIO) DC Parameters
The parameters in Table 15 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 15. UHVIO DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage1
Voh
Iout = –1mA
Iout= specified Ioh
Drive
OVDD–0.15
0.8 * OVDD
—
—
V
Low-level output voltage1
Vol
Iout = 1mA
Iout= specified Ioh
Drive
—
—
0.15
0.2 * OVDD
V
High-level output current, low voltage mode
Vout = 0.8 × OVDD
Low Drive
–2.2
–4.4
–6.6
Ioh_lv
Ioh_hv
Iol_lv
—
—
—
—
—
—
—
—
mA
mA
mA
mA
Medium Drive
High Drive
High-level output current, high voltage
mode
Vout = 0.8 × OVDD
Low Drive
–5.1
–10.2
–15.3
Medium Drive
High Drive
Low-level output current, low voltage mode
Low-level output current, high voltage mode
Vout = 0.2 × OVDD
Low Drive
2.2
4.4
6.6
Medium Drive
High Drive
Vout = 0.2 × OVDD
Low Drive
5.1
10.2
15.3
Iol_hv
Medium Drive
High Drive
High-Level DC input voltage1, 2
Low-Level DC input voltage1, 2
Input Hysteresis
VIH
VIL
—
—
0.7 × OVDD
—
—
—
OVDD
V
V
0
0.3 × OVDD
VHYS
low voltage mode
high voltage mode
0.38
0.95
0.43
1.33
V
Schmitt trigger VT+2, 3
VT+
VT–
Iin
—
—
0.5 × OVDD
—
—
—
—
—
0.5 × OVDD
1
V
V
Schmitt trigger VT–2, 3
—
—
—
Input current (no pull-up/down)
Input current (22 kΩ Pull-up)
Vin = OVDD or 0 V
μA
Iin
Vin = 0
Vin = OVDD
202
1
μA
μA
μA
Input current (75 kΩ Pull-up)
Input current (100 kΩ Pull-up)
Input current (360 kΩ Pull-down)
Keeper Circuit Resistance
Iin
Iin
Iin
—
Vin = 0
Vin = OVDD
—
—
—
—
—
—
61
1
Vin = 0
Vin = OVDD
47
1
Vin = 0
Vin = OVDD
—
1
5.7
μA
kΩ
—
1304
—
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
33
Electrical Characteristics
1
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2
To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current
DC level to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply
when hysteresis is enabled.
3
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
4.3.5
LVDS I/O DC Parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 16 shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics.
Table 16. LVDS DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Differential Voltage
Output High Voltage
Output Low Voltage
Offset Voltage
VOD
VOH
VOL
VOS
Rload=100Ω
padP, –padN
250
1.25
0.9
350
1.375
1.025
1.2
450
1.6
mV
1.25
1.375
V
1.125
4.4
Output Buffer Impedance Characteristics
This section defines the I/O Impedance parameters of the i.MX53xA processor for the following I/O
types:
•
•
•
•
General Purpose I/O (GPIO)
Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes
Ultra High Voltage I/O (UHVIO)
LVDS I/O
NOTE
Output driver impedance is measured with “long” transmission line of
impedance Ztl attached to I/O pad and incident wave launched into
transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 4).
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
34
Freescale Semiconductor
Electrical Characteristics
OVDD
PMOS (Rpu)
Ztl Ω, L = 20 inches
ipp_d
pad
predriver
Cload = 1p
NMOS (Rpd)
OVSS
U,(V)
VDD
(do)
Vin
t,(ns)
0
U,(V)
Vout (pad)
OVDD
Vref2
Vref1
Vref
t,(ns)
0
Vovdd – Vref1
Vref1
Rpu =
Rpd =
× Ztl
× Ztl
Vref2
Vovdd – Vref2
Figure 4. Impedance Matching Load for Measurement
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
35
Electrical Characteristics
4.4.1
GPIO Output Buffer Impedance
Table 17 shows the GPIO output buffer impedance.
Table 17. GPIO Output Buffer Impedance
Typ
Parameter
Symbol
Test Conditions
Min
Max
Unit
OVDD 2.775 V OVDD 1.875 V
Output Driver
Impedance
Rpu
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
Max Drive Strength, Ztl = 37.5 Ω
80
40
27
20
104
52
35
150
75
51
250
125
83
Ω
26
38
62
Output Driver
Impedance
Rpd
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
Max Drive Strength, Ztl = 37.5 Ω
64
32
21
16
88
44
30
22
134
66
44
243
122
81
Ω
34
61
4.4.2
DDR Output Driver Average Impedance
The DDR2/LVDDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April,
2008. The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
36
Freescale Semiconductor
Electrical Characteristics
Table 18 shows DDR output driver average impedance of the i.MX53xA processor.
1
Table 18. DDR Output Driver Average Impedance
Drive strength (DSE)
Parameter Symbol
Test Conditions
Unit
000
001
010
011
100
101
110
111
LPDDR1/DDR2 mode
NVCC_DRAM = 1.8 V
DDR_SEL = 00
Hi-Z
300
150
100
75
60
50
43
Calibration resistance = 300 Ω3
DDR2 mode
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
180
200
140
160
240
160
240
90
100
70
60
66
46
53
80
53
80
45
50
35
40
60
40
60
36
40
28
32
48
32
48
30
33
23
27
40
27
48
26
28
20
23
34
23
34
NVCC_DRAM = 1.8 V
DDR_SEL = 01
Calibration resistance = 180 Ω3
DDR2 mode
NVCC_DRAM = 1.8 V
DDR_SEL = 10
Calibration resistance = 200 Ω3
DDR2 mode
NVCC_DRAM= 1.8 V
DDR_SEL = 11
Calibration resistance = 140 Ω3
Output
Driver
Ω
Rdrv2
LPDDR2 mode
80
Impedance
NVCC_DRAM= 1.2 V
DDR_SEL = 014
Calibration resistance = 160 Ω3
LPDDR2 mode
120
80
NVCC_DRAM = 1.2 V
DDR_SEL = 10
Calibration resistance = 240 Ω3
LPDDR2 mode
NVCC_DRAM = 1.2 V
DDR_SEL = 114
Calibration resistance = 160 Ω3
DDR3 mode
120
NVCC_DRAM = 1.5 V
DDR_SEL = 00
Calibration resistance = 200 Ω3
1
Output driver impedance is controlled across PVTs (process, voltages, and temperatures) using calibration procedure and
pu_*cal, pd_*cal input pins.
2
3
Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.
Calibration is done against external reference resistor. Value of the resistor should be varied depending on DDR mode and
DDR_SEL setting.
4
If DDR_SEL = ‘01’ or DDR_SEL = ‘11’ are selected with NVCC_DRAM = 1.2 V for LPDDR2 operation, the external reference
resistor value must be 160 Ω for a correct ZQ calibration. In any case, reference resistors attached to the DDR memory devices
should be kept to 240 Ω per the JEDEC standard.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
37
Electrical Characteristics
4.4.3
UHVIO Output Buffer Impedance
Table 19 shows the UHVIO output buffer impedance.
Table 19. UHVIO Output Buffer Impedance
Min
OVDD OVDD OVDD
Typ
Max
Parameter Symbol
Test Conditions
Unit
OVDD OVDD OVDD
1.95 V 3.0 V 1.875 V 3.3 V
1.65 V 3.6 V
Output Driver
Impedance
Rpu
Rpd
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
98
49
32
114
57
38
124
62
41
135
67
45
198
99
66
206
103
69
Ω
Ω
Output Driver
Impedance
Low Drive Strength, Ztl = 150 Ω
Medium Drive Strength, Ztl = 75 Ω
High Drive Strength, Ztl = 50 Ω
97
49
32
118
59
40
126
63
42
154
77
51
179
89
60
217
109
72
4.4.4
LVDS I/O Output Buffer Impedance
The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
4.5
I/O AC Parameters
This section includes the AC parameters of the following I/O types:
•
•
•
•
•
General Purpose I/O (GPIO)
Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes
Low Voltage I/O (LVIO)
Ultra High Voltage I/O (UHVIO)
LVDS I/O
The load circuit and output transition time waveforms are shown in Figure 5 and Figure 6.
From Output
Under Test
Test Point
CL
CL includes package, probe and fixture capacitance
Figure 5. Load Circuit for Output
OVDD
0 V
80%
20%
80%
20%
Output (at pad)
tf
tr
Figure 6. Output Transition Time Waveform
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
38
Electrical Characteristics
4.5.1
GPIO I/O AC Electrical Characteristics
AC electrical characteristics for GPIO I/O in slow and fast modes are presented in the Table 20 and
Table 21, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit
in the IOMUXC control registers.
Table 20. GPIO I/O AC Parameters Slow Mode
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times (Max Drive)
tr, tf
tr, tf
tr, tf
tr, tf
tps
15 pF
35 pF
1.91/1.52
3.07/2.65
ns
—
—
Output Pad Transition Times (High Drive)
Output Pad Transition Times (Medium Drive)
Output Pad Transition Times (Low Drive)
Output Pad Slew Rate (Max Drive)1
Output Pad Slew Rate (High Drive)1
Output Pad Slew Rate (Medium Drive)1
Output Pad Slew Rate (Low Drive)1
15 pF
35 pF
2.22/1.81
3.81/3.42
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
15 pF
35 pF
2.88/2.42
5.43/5.02
15 pF
35 pF
4.94/4.50
10.55/9.70
15 pF
35 pF
0.5/0.65
0.32/0.37
—
—
—
—
tps
15 pF
35 pF
0.43/0.54
0.26/0.41
V/ns
tps
15 pF
35 pF
0.34/0.41
0.18/0.2
tps
15 pF
35 pF
0.20/0.22
0.09/0.1
Output Pad di/dt (Max Drive)
Output Pad di/dt (High Drive)
Output Pad di/dt (Medium drive)
Output Pad di/dt (Low drive)
Input Transition Times2
tdit
tdit
tdit
tdit
trm
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30
23
15
7
mA/ns
ns
25
1
tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
2
Table 21. GPIO I/O AC Parameters Fast Mode
Test
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Output Pad Transition Times (Max Drive)
Output Pad Transition Times (High Drive)
tr, tf
15 pF
35 pF
—
—
1.45/1.24
2.76/2.54
ns
tr, tf
tr, tf
15 pF
35 pF
—
—
—
—
1.81/1.59
3.57/3.33
ns
ns
Output Pad Transition Times (Medium
Drive)
15 pF
35 pF
2.54/2.29
5.25/5.01
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
39
Electrical Characteristics
Table 21. GPIO I/O AC Parameters Fast Mode (continued)
Test
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Output Pad Transition Times (Low Drive)
tr, tf
15 pF
35 pF
4.82/4.5
10.54/9.95
ns
—
—
—
—
—
—
Output Pad Slew Rate (Max Drive)1
Output Pad Slew Rate (High Drive)1
Output Pad Slew Rate (Medium Drive)1
Output Pad Slew Rate (Low Drive)1
tps
tps
tps
tps
15 pF
35 pF
0.69/0.78
0.36/0.39
V/ns
V/ns
V/ns
V/ns
—
—
—
—
15 pF
35 pF
0.55/0.62
0.28/0.30
15 pF
35 pF
0.39/0.44
0.19/0.20
15 pF
35 pF
0.21/0.22
0.09/0.1
Output Pad di/dt (Max Drive)
Output Pad di/dt (High Drive)
Output Pad di/dt (Medium drive)
Output Pad di/dt (Low drive)
tdit
tdit
tdit
tdit
trm
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
70
53
35
18
25
mA/ns
mA/ns
mA/ns
mA/ns
ns
Input Transition Times2
1
tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
Hysteresis mode is recommended for inputs with transition time greater than 25 ns.
2
4.5.2
LPDDR2 I/O AC Electrical Characteristics
The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release
April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release
April, 2008.
Table 22 shows the AC parameters for LPDDR2 I/O operating in DDR2 mode.
1
Table 22. LPDDR2 I/O DDR2 mode AC Characteristics
Parameter
AC input logic high
Symbol Test Condition
Min
Typ
Max
Unit
Vih(ac)
Vil(ac)
Vid(ac)
Vix(ac)
Vox(ac)
tsr
—
Vref+0.25
—
—
—
—
—
—
—
—
V
V
AC input logic low
—
—
Vref-0.25
OVDD
AC differential input voltage2
Input AC differential cross point voltage3
Output AC differential cross point voltage4
Single output slew rate
—
0.5
Vref – 0.175
Vref – 0.125
0.4
V
—
—
Vref + 0.175
Vref + 0.125
2
V
V
At 25 Ω to Vref
V/ns
ns
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD
clk=266Mhz
clk=400Mhz
—
0.2
0.1
1
Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this
document.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
40
Freescale Semiconductor
Electrical Characteristics
2
3
4
Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
The typical value of Vox(ac) is expected to be about 0.5 * OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
indicates the voltage at which differential output signal must cross.
Table 23 shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode.
1
Table 23. LPDDR2 I/O LPDDR2 mode AC Characteristics
Parameter
AC input logic high
Symbol
Test Condition
Min
Typ
Max
Unit
Vih(ac)
Vil(ac)
—
Vref + 0.22
—
—
—
—
—
—
—
OVDD
Vref – 0.22
—
V
V
AC input logic low
—
0
0.44
—
AC differential input high voltage2
AC differential input low voltage
Input AC differential cross point voltage3
Over/undershoot peak
Vidh(ac)
Vidl(ac)
Vix(ac)
Vpeak
—
V
—
Relative to OVDD/2
—
0.44
V
-0.12
—
0.12
V
0.35
V
Over/undershoot area (above OVDD
or below OVSS)
Varea
266MHz
—
0.6
V*ns
Single output slew rate
tsr
50Ohm to Vref.
5pF load.
Drive impedance=
40Ohm +-30%
1.5
1
—
—
—
3.5
2.5
V/ns
50Ohm to Vref.
5pF load.Drive
impedance= 60Ohm
+-30%
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD
clk=266MHz
clk=400MHz
ns
—
0.2
0.1
1
2
Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
3
The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Table 24 shows the AC parameters for LPDDR2 I/O operating in DDR3 mode.
1
Table 24. LPDDR2 I/O DDR3 mode AC Characteristics
Parameter
AC input logic high
Symbol Test Condition
Min
Typ
Max
Unit
Vih(ac)
Vil(ac)
Vid(ac)
Vix(ac)
—
—
—
—
Vref + 0.175
0
—
—
—
—
OVDD
Vref – 0.175
—
V
V
V
V
AC input logic low
AC differential input voltage2
Input AC differential cross point voltage3
0.35
Vref – 0.15
Vref + 0.15
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
41
Electrical Characteristics
Table 24. LPDDR2 I/O DDR3 mode AC Characteristics (continued)
1
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Output AC differential cross point voltage4
Single output slew rate
Vox(ac)
tsr
—
Vref – 0.15
—
—
—
Vref + 0.15
5
V
V/ns
ns
At 25 Ω to Vref
2.5
—
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD
clk=266MHz
clk=400MHz
0.2
0.1
1
Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
2
3
4
Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
The typical value of Vox(ac) is expected to be about 0.5 * OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
indicates the voltage at which differential output signal must cross.
4.5.3
LVIO I/O AC Electrical Characteristics
AC electrical characteristics for LVIO I/O in slow and fast modes are presented in the Table 25 and
Table 26, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit
in the IOMUXC control registers.
Table 25. LVIO I/O AC Parameters in Slow Mode
Parameter
Input Transition Times1
Symbol Test Condition
trm
Min
Typ
Max
Unit
—
—
—
25
ns
1
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
42
Electrical Characteristics
4.5.4
UHVIO I/O AC Electrical Characteristics
Table 26. LVIO I/O AC Parameters in Fast Mode
Test
Condition
Parameter
Input Transition Times1
Symbol
Min
Typ
Max
Unit
trm
—
—
—
25
ns
1
Hysteresis mode is recommended for inputs with transition time greater than 25 ns.
Table 27 shows the AC parameters for UHVIO I/O operating in low output voltage mode. Table 28
shows the AC parameters for UHVIO I/O operating in high output voltage mode.
Table 27. AC Electrical Characteristics of UHVIO Pad (Low Output Voltage Mode)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times (High Drive)
tr, tf
tr, tf
tr, tf
tps
15 pF
35 pF
—
—
1.59/1.69
3.05/3.30
Output Pad Transition Times (Medium Drive)
Output Pad Transition Times (Low Drive)
Output Pad Slew Rate (High Drive)1
Output Pad Slew Rate (Medium Drive)1
Output Pad Slew Rate (Low Drive)1
15 pF
35 pF
—
—
—
—
—
—
—
2.16/2.35
4.45/4.84
ns
15 pF
35 pF
4.06/4.42
8.79/9.55
15 pF
35 pF
0.63/0.59
0.33/0.30
—
—
—
tps
15 pF
35 pF
0.46/0.42
0.22/0.21
V/ns
tps
15 pF
35 pF
0.25/0.23
0.11/0.11
Output Pad di/dt (High Drive)
Output Pad di/dt (Medium drive)
Output Pad di/dt (Low drive)
Input Transition Times2
tdit
tdit
tdit
trm
—
—
—
—
—
—
—
—
—
—
—
—
43.6
32.3
18.24
25
mA/ns
ns
1
tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
2
Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Output Pad Transition Times (High Drive)
Output Pad Transition Times (Medium Drive)
Output Pad Transition Times (Low Drive)
tr, tf
tr, tf
tr, tf
15 pF
35 pF
—
—
1.72/1.92
3.46/3.70
15 pF
35 pF
—
—
—
—
2.38/2.56
5.07/5.25
ns
15 pF
35 pF
4.55/4.58
10.04/9.94
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Electrical Characteristics
Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode) (continued)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Output Pad Slew Rate (High Drive)1
tps
tps
tps
15 pF
35 pF
1.05/0.94
0.52/0.49
—
—
Output Pad Slew Rate (Medium Drive)1
Output Pad Slew Rate (Low Drive)1
15 pF
35 pF
0.76/0.71
0.36/0.34
—
—
—
—
V/ns
15 pF
35 pF
0.40/0.93
0.18/0.18
Output Pad di/dt (High Drive)
Output Pad di/dt (Medium drive)
Output Pad di/dt (Low drive)
Input Transition Times2
tdit
tdit
tdit
trm
—
—
—
—
—
—
—
—
—
—
—
—
82.8
65.6
43.1
25
mA/ns
ns
1
tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
2
4.5.5
LVDS I/O AC Electrical Characteristics
The differential output transition time waveform is shown in Figure 7.
Figure 7. Differential LVDS Driver Transition Time Waveform
Table 29 shows the AC parameters for LVDS I/O.
Table 29. AC Electrical Characteristics of LVDS Pad
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Transition Low to High Time1
Transition High to Low Time1
Operating Frequency
tTLH
0.26
0.26
—
—
—
0.5
0.5
—
Rload = 100 Ω,
Cload = 2 pF
ns
tTHL
f
—
—
300
—
MHz
mV
Offset voltage imbalance
Vos
—
150
1
Measurement levels are 20-80% from output voltage.
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Electrical Characteristics
4.6
System Modules Timing
This section contains the timing and electrical parameters for the modules in the i.MX53xA processor.
4.6.1
Reset Timings Parameters
Figure 8 shows the reset timing and Table 30 lists the timing parameters.
RESET_IN
(Input)
CC1
Figure 8. Reset Timing Diagram
Table 30. Reset Timing Parameters
ID
Parameter
Min
Max
Unit
CC1
Duration of RESET_IN to be qualified as valid (input slope = 5 ns)
50
—
ns
4.6.2
WDOG Reset Timing Parameters
Figure 9 shows the WDOG reset timing and Table 31 lists the timing parameters.
WATCHDOG_RST
(Input)
CC5
Figure 9. WATCHDOG_RST Timing Diagram
Table 31. WATCHDOG_RST Timing Parameters
ID
Parameter
Min
Max
Unit
TCKIL
CC5
Duration of WATCHDOG_RESET Assertion
1
—
NOTE
is one period or approximately 30 μs.
CKIL is approximately 32 kHz. T
CKIL
4.6.3
Clock Amplifier Parameters (CKIH1, CKIH2)
The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave
or sinusoidal frequency source. No external series capacitors are required.
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Electrical Characteristics
Table 32 shows the electrical parameters of CAMP.
Table 32. CAMP Electrical Parameters (CKIH1, CKIH2)
Parameter
Min
Typ
Max
Unit
Input frequency
8.0
—
—
—
—
50
40.0
0.3
MHz
V
VIL (for square wave input)
VIH (for square wave input)1
Sinusoidal input amplitude
Output duty cycle
0
NVCC_CKIH – 0.25
NVCC_CKIH
VDD
V
0.4
45
Vp-p
%
55
1
NVCC_CKIH is the supply voltage of CAMP.
4.6.4
DPLL Electrical Parameters
Table 33 shows the electrical parameters of digital phase-locked loop (DPLL).
Table 33. DPLL Electrical Parameters
Parameter
Test Conditions/Remarks
Min
Typ
Max
Unit
Reference clock frequency range1
—
—
10
10
—
—
100
40
MHz
MHz
Reference clock frequency range after
pre-divider
Output clock frequency range (dpdck_2)
Pre-division factor2
—
300
—
—
—
—
—
50
—
1025
16
MHz
—
—
1
Multiplication factor integer part
Multiplication factor numerator3
Multiplication factor denominator2
Output Duty Cycle
—
5
15
—
Should be less than denominator
–67108862
67108862
67108863
51.5
—
—
—
—
1
—
48.5
—
%
Frequency lock time4
(FOL mode or non-integer MF)
398
Td
pdref
Phase lock time
—
—
—
—
—
—
0.02
2.0
—
100
0.04
3.5
µs
Tdck
ns
Frequency jitter5 (peak value)
Phase jitter (peak value)
Power dissipation
—
FPL mode, integer and fractional MF
fdck = 300 MHz at avdd = 1.8 V,
0.65 (avdd)
0.92 (dvdd)
1.98 (avdd)
1.8 (dvdd)
mW
dvdd = 1.2 V
f
dvdd = 1.2 V
dck = 650 MHz at avdd = 1.8 V,
1
Device input range cannot exceed the electrical specifications of the CAMP, see Table 32.
2
The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user. Therefore,
the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.
3
The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must
be zero.
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Electrical Characteristics
4
5
Tdpdref is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL
mode is 398 cycles of divided reference clock when DPLL starts after full reset.
Tdck is the time period of the output clock, dpdck_2.
4.6.5
NAND Flash Controller (NFC) Parameters
This section provides the relative timing requirements among various signals of NFC at the module level,
in each operational mode.
Timing parameters in Figure 10, Figure 11, Figure 12, Figure 13, Figure 15, and Table 35 show the default
NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B.
Timing parameters in Figure 10, Figure 11, Figure 12, Figure 14, Figure 15, and Table 35 show symmetric
NFC mode using one Flash clock cycle per one access of RE_B and WE_B.
With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%
of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is
20 pF (except for NF16 - 40 pF) and there is maximum drive strength on all contacts.
All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system
level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The
clock is derived from emi_slow_clk after single divider.
Figure 34 demonstrates several examples of clock frequency settings.
Table 34. NFC Clock Settings Examples
emi_slow_clk (MHz)
nfc_podf (Division Factor)
enfc_clk (MHz)
T-Clock Period (ns)
100 (Boot mode)
71
32
4
14.29
33.33
33.33
44.333
663
70
30
133
30
3
22.5
15
2
1
2
3
Boot value NFC_FREQ_SEL Fuse High (burned)
Boot value NFC_FREQ_SEL Fuse Low
For RBB_MODE=1, using NANDF_RB0 signal for ready/busy indication. This mode require setting the delay line. See the
Reference Manual for details.
NOTE
A potential limitation for minimum clock frequency may exist for some
devices. When the clock frequency is too low, the data bus capturing might
occur after the specified t
(RE_B high to output hold) period. Setting the
rhoh
clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper
operation for devices having t > 15 ns. It is also recommended that the
rhoh
NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with
33.33 MHz clock.
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Electrical Characteristics
Lower frequency operation can be supported for most available devices in
the market, relying on data lines Bus-Keeper logic. This depends on device
behavior on the data bus in the time interval between data output valid to
data output high-Z state. In NAND device parameters this period is marked
between t
and t (RE_B high to output high-Z). In most devices, the
rhoh
rhz
data transition from valid value to high-Z occurs without going through
other states. Setting the data bus pads to Bus-Keeper mode in the IOMUXC
registers, keeps the data bus valid internally after the specified hold time,
allowing proper capturing with slower clock.
NFCLE
NF2
NF1
NF3
NF4
NFCE_B
NF5
NFWE_B
NFIO[7:0]
NF8
NF9
command
Figure 10. Command Latch Cycle Timing
NF4
NF3
NFCE_B
NF10
NF11
NF5
NFWE_B
NFALE
NF7
NF6
NF8
NF9
NFIO[7:0]
Address
Figure 11. Address Latch Cycle Timing
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Electrical Characteristics
NF3
NFCE_B
NF10
NF11
NF5
NFWE_B
NF8
NF9
NFIO[15:0]
Data to NF
Figure 12. Write Data Latch Timing
NFCE_B
NF14
NF15
NF13
NFRE_B
NFRB_B
NF17
NF16
NF12
NFIO[15:0]
NFCE_B
Data from NF
Figure 13. Read Data Latch Timing, Asymmetric Mode
NF14
NF15
NF13
NFRE_B
NFRB_B
NF18
NF16
NF12
NFIO[15:0]
Data from NF
Figure 14. Read Data Latch Timing, Symmetric Mode
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Electrical Characteristics
NF19
NFCLE
NF20
NFCE_B
NFWE_B
NF21
NF22
NFRE_B
NFRB_B
Figure 15. Other Timing Parameters
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Electrical Characteristics
Table 35. NFC—Timing Characteristics
Symmetric Mode
ID
Parameter
Symbol
Asymmetric Mode Min
Max
Min
NF1
NF2
NFCLE setup Time
NFCLE Hold Time
NFCE_B Setup Time
NFCE_B Hold Time
NFWE_B Pulse Width
NFALE Setup Time
NFALE Hold Time
Data Setup Time
tCLS
tCLH
tCS
2T + 0.1
T – 4.45
3T + 0.95
2T–5.55
T – 1.4
2T + 0.1
T – 4.45
T – 0.9
T – 5.55
2T
2T + 0.1
T – 4.45
3T+0.95
1.5T–5.55
0.5T – 1.4
2T + 0.1
T – 4.45
0.5T – 0.9
0.5T – 5.55
T–0.5
—
—
NF31
NF4
—
tCH
—
NF5
tWP
tALS
tALH
tDS
—
NF6
—
NF7
—
NF8
—
NF9
Data Hold Time
tDH
—
NF10
NF11
NF12
NF13
NF14
NF15
NF162
NF174
NF185
NF19
NF20
NF21
NF22
Write Cycle Time
tWC
tWH
tRR
—
NFWE_B Hold Time
Ready to NFRE_B Low
NFRE_B Pulse Width
READ Cycle Time
NFRE_B High Hold Time
Data Setup on READ
Data Hold on READ
Data Hold on READ
CLE to RE delay
T – 1.15
9T + 8.9
1.5T
0.5T – 1.15
9T + 8.9
0.5T–1
—
—
tRP
—
—
tRC
2T
T
tREH
tDSR
tDHR
tDHR
tCLR
tCRE
tWHR
tWB
0.5T – 1.15
11.2 + 0.5T – Tdl3
0
0.5T – 1.15
11.2 – Tdl2
—
—
—
2Taclk + T
2Taclk + T
—
—
Tdl2 – 11.2
9T
9T
CE to RE delay
T – 3.45
10.5T
T – 3.45
10.5T
T + 0.3
—
WE high to RE low
WE high to busy
—
—
6T
1
2
In case of NUM_OF_DEVICES is greater than 0 (for example, interleaved mode), then only during the data phase of
symmetric mode the setup time will equal 1.5T + 0.95.
tDSR is calculated by the following formula:
2
1
Asymmetric mode: tDSR = tREpd + tDpd + / T – Tdl
2
Symmetric mode:
tREpd + tDpd = 11.2 ns (including clock skew)
tDSR = tREpd + tDpd – Tdl2
where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to
EXTMC including I/O pad delay.
tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T – tDSR.
3
Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (Taclk). Default
is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. Taclk is
“emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).
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Electrical Characteristics
4
NF17 is defined only in asymmetric operation mode.
NF17 max value is equivalent to max tRHZ value that can be used with NFC.
Taclk is “emi_slow_clk” of the system.
5
NF18 is defined only in Symmetric operation mode.
tDHR (MIN) is calculated by the following formula:
Tdl2 – (tREpd + tDpd)
where tREpd is RE propogation delay in the chip including I/O pad delay, and tDpd is Data propogation delay from I/O pad to
EXTMC including I/O pad delay.
NF18 max value is equivalent to max tRHZ value that can be used with NFC.
Taclk is “emi_slow_clk” of the system.
4.6.6
External Interface Module (EIM)
The following subsections provide information on the EIM.
4.6.6.1
EIM Signal Cross Reference
Table 36 is a guide intended to help the user identify signals in the External Interface Module Chapter of
the Reference Manual which are identical to those mentioned in this data sheet.
Table 36. EIM Signal Cross Reference
Data Sheet Nomenclature,
Reference Manual
Reference Manual External Signals and Pin Multiplexing Chapter,
EIM Chapter Nomenclature
and IOMUXC Controller Chapter Nomenclature
BCLK
CSx
EIM_BCLK
EIM_CSx
WE_B
EIM_RW
OE_B
EIM_OE
BEy_B
ADV
EIM_EBx
EIM_LBA
ADDR
EIM_A[25:16], EIM_DA[15:0]
EIM_DAx (Addr/Data muxed mode)
ADDR/M_DATA
DATA
EIM_NFC_D (Data bus shared with NAND Flash)
EIM_Dx (dedicated data bus)
WAIT_B
EIM_WAIT
4.6.6.2
EIM Interface Pads Allocation
EIM supports16-bit and 8-bit devices operating in address/data separate or multiplexed modes. In some
of the modes the EIM and the NAND FLASH have shared data bus. Table 37 provides EIM interface
pads allocation in different modes.
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Table 37. EIM Internal Module Multiplexing
Non Multiplexed Address/Data Mode
Multiplexed
Address/Data mode
Setup
8 Bit
MUM = 0,
16 Bit
MUM = 0, MUM = 0,
32 Bit
MUM = 0,
16 Bit
32 Bit
MUM = 0,
MUM = 0,
MUM = 1,
MUM = 1,
DSZ = 111 DSZ = 111 DSZ = 111 DSZ = 001 DSZ = 010 DSZ = 011 DSZ = 001 DSZ = 011
A[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
EIM_DA
[15:0]
A[25:16]
EIM_A
[25:16]
EIM_A
[25:16]
EIM_A
[25:16]
EIM_A
[25:16]
EIM_A
[25:16]
EIM_A
EIM_A
[25:16]
NANDF_D
[8:0]1
[24:16]1
D[7:0],
EIM_EB
0
NANDF_D
[7:0]2
—
—
—
—
NANDF_D
[7:0]2
—
NANDF_D
[7:0]
EIM_DA
[7:0]
EIM_DA
[7:0]
D[15:8],
EIM_EB
1
—
—
NANDF_D
[15:8]3
NANDF_D
[15:8]3
—
NANDF_D
[15:8]
EIM_DA
[15:8]
EIM_DA
[15:8]
D[23:16]
—
—
EIM_D
[23:16]
EIM_D
[23:16]
—
NANDF_D
[7:0]
,
EIM_EB
2
D[31:24]
—
—
EIM_D
[31:24]
—
EIM_D
[31:24]
EIM_D
[31:24]
—
NANDF_D
[15:8]
,
EIM_EB
3
1
2
3
For 32-bit mode, the address range is A[24:0], due to address space allocation in memory map.
NANDF_D[7:0] multiplexed on ALT3 mode of PATA_DATA[7:0]
NANDF_D[15:8] multiplexed on ALT3 mode of PATA_DATA[15:8]
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Electrical Characteristics
4.6.6.3
General EIM Timing-Synchronous Mode
Figure 16, Figure 17, and Table 38 specify the timings related to the EIM module. All EIM output control
signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge
according to corresponding assertion/negation control fields.
,
...
WE3
BCLK
WE1
WE4
WE6
WE5
WE7
WE9
Address
CSx_B
WE8
WE10
WE12
WE_B
OE_B
BEy_B
WE11
WE13
WE15
WE17
WE14
WE16
ADV_B
Output Data
Figure 16. EIM Outputs Timing Diagram
BCLK
WE18
Input Data
WE19
WE20
WAIT_B
WE21
Figure 17. EIM Inputs Timing Diagram
1
Table 38. EIM Bus Timing Parameters
BCD = 0
Max
BCD = 1
Min Max
BCD = 2
Max
BCD = 3
Min Max
ID
Parameter
Min
Min
WE1 BCLK Cycle time2
t
2*t
3*t
4*t
1.6*t
WE2 BCLK Low Level
Width
0.4*t
0.8*t
1.2*t
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Electrical Characteristics
BCD = 3
1
Table 38. EIM Bus Timing Parameters (continued)
BCD = 0 BCD = 1 BCD = 2
Max Min Max
ID
Parameter
Min
Min
1.2*t
Max
Min
Max
WE3 BCLK High Level
Width
0.4*t
0.8*t
-t-1.25
t-1.25
-t-1.25
t-1.25
-t-1.25
t-1.25
-t-1.25
t-1.25
-t-1.25
t-1.25
-t-1.25
t-1.25
-t-1.25
t-1.25
1.6*t
WE4 Clock rise to
address valid3
-0.5*t-1.25 -0.5*t+1.75
-t+1.75 -1.5*t-1.2
5
-1.5*t
+1.75
-2*t-1.25 -2*t+1.75
WE5 Clock rise to
address invalid
0.5*t-1.25
0.5*t+1.75
t+1.75 1.5*t-1.2 1.5*t +1.75 2*t-1.25
5
2*t+1.75
WE6 Clock rise to
CSx_B valid
-0.5*t-1.25 -0.5*t+1.75
-t+1.75 -1.5*t-1.2
5
-1.5*t
+1.75
-2*t-1.25 -2*t+1.75
WE7 Clock rise to
CSx_B invalid
0.5*t-1.25
0.5*t+1.75
t+1.75 1.5*t-1.2 1.5*t +1.75 2*t-1.25
5
2*t+1.75
WE8 Clock rise to
WE_B Valid
-0.5*t-1.25 -0.5*t+1.75
-t+1.75 -1.5*t-1.2
5
-1.5*t
+1.75
-2*t-1.25 -2*t+1.75
WE9 Clock rise to
WE_B Invalid
0.5*t-1.25
0.5*t+1.75
t+1.75 1.5*t-1.2 1.5*t +1.75 2*t-1.25
5
2*t+1.75
WE10 Clock rise to OE_B -0.5*t-1.25 -0.5*t+1.75
Valid
-t+1.75 -1.5*t-1.2
5
-1.5*t
+1.75
-2*t-1.25 -2*t+1.75
WE11 Clock rise to OE_B 0.5*t-1.25
Invalid
0.5*t+1.75
t+1.75 1.5*t-1.2 1.5*t +1.75 2*t-1.25
5
2*t+1.75
WE12 Clock rise to
BEy_B Valid
-0.5*t-1.25 -0.5*t+1.75
-t+1.75 -1.5*t-1.2
5
-1.5*t
+1.75
-2*t-1.25 -2*t+1.75
WE13 Clock rise to
BEy_B Invalid
0.5*t-1.25
0.5*t+1.75
t+1.75 1.5*t-1.2 1.5*t +1.75 2*t-1.25
5
2*t+1.75
WE14 Clock rise to
ADV_B Valid
-0.5*t-1.25 -0.5*t+1.75
-t+1.75 -1.5*t-1.2
5
-1.5*t
+1.75
-2*t-1.25 -2*t+1.75
WE15 Clock rise to
ADV_B Invalid
0.5*t-1.25
0.5*t+1.75
t+1.75 1.5*t-1.2 1.5*t +1.75 2*t-1.25
5
2*t+1.75
WE16 Clock rise to
Output Data Valid
-0.5*t-1.25 -0.5*t+1.75
-t+1.75 -1.5*t-1.2
5
-1.5*t
+1.75
-2*t-1.25 -2*t+1.75
WE17 Clock rise to
Output Data
Invalid
0.5*t-1.25
0.5*t+1.75
t+1.75 1.5*t-1.2 1.5*t +1.75 2*t-1.25
5
2*t+1.75
WE18 Input Data setup
time to Clock rise
2
2
—
—
4
2
—
—
—
—
—
—
—
—
—
—
WE19 Input Data hold
time from Clock
rise
WE20 WAIT_B setup
time to Clock rise
2
2
—
—
4
2
—
—
—
—
—
—
—
—
—
—
WE21 WAIT_B hold time
from Clock rise
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Electrical Characteristics
1
t is the maximal EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum
allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be ≤ 104 MHz. If BCD = 1, then 133 MHz is
allowed for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 104 MHz, other busses
are impacted which are clocked from this source. See the CCM chapter of the i.MX53 Reference Manual for a detailed clock
tree description.
2
BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined
as 50% as signal value.
3
For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.
4.6.6.4
Examples of EIM Synchronous Accesses
Figure 18 to Figure 21 provide few examples of basic EIM accesses to external memory devices with the
timing parameters mentioned previously for specific control parameters settings.
BCLK
WE4
WE6
WE5
WE7
ADDR
CSx_B
WE_B
ADV_B
OE_B
Address v1
Last Valid Address
WE14
WE10
WE12
WE15
WE18
WE11
WE13
BEy_B
DATA
D(v1)
WE19
Figure 18. Synchronous Memory Read Access, WSC=1
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Electrical Characteristics
BCLK
ADDR
WE5
WE4
Last Valid Address
Address V1
WE7
WE6
WE8
CSx_B
WE_B
ADV_B
OE_B
WE9
WE14
WE15
WE13
WE12
WE16
BEy_B
DATA
WE17
D(V1)
Figure 19. Synchronous Memory, Write Access, WSC=1, WBEA=0, and WADVN=0
BCLK
WE16
WE17
WE5
WE4
ADDR/
M_DATA
Write Data
Address V1
Valid Addr
Last
WE6
WE7
WE9
CSx_B
WE_B
WE8
WE14
WE15
ADV_B
OE_B
WE10
WE11
BEy_B
Figure 20. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and
ADH=1
NOTE
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the
data bus.
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Electrical Characteristics
BCLK
WE4
Valid Addr
WE6
WE5
Address V1
WE19
WE18
ADDR/
M_DATA
Last
Data
CSx_B
WE_B
WE7
WE15
WE10
WE14
WE12
ADV_B
OE_B
WE11
WE13
BEy_B
Figure 21. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, and OEA=0
4.6.6.5
General EIM Timing-Asynchronous Mode
Figure 22 through Figure 27, and Table 39 help to determine timing parameters relative to the chip select
(CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing
parameters mentioned above.
Asynchronous read and write access length in cycles may vary from what is shown in Figure 22 through
Figure 25 as RWSC, OEN, and CSN is configured differently. Refer to i.MX53xA RM for the EIM
programming model.
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Freescale Semiconductor
Electrical Characteristics
end of
access
start of
access
INT_CLK
CSx_B
MAXCSO
WE31
WE32
ADDR/
M_DATA
Next Address
Last Valid Address
Address V1
WE_B
WE39
WE40
WE36
WE38
ADV_B
WE35
WE37
OE_B
BEy_B
WE44
MAXCO
DATA[7:0]
D(V1)
WE43
MAXDI
Figure 22. Asynchronous Memory Read Access (RWSC = 5)
end of
access
start of
access
INT_CLK
CSx_B
MAXCSO
MAXDI
WE31
D(V1)
Addr. V1
WE32A
ADDR/
M_DATA
WE44
WE_B
WE40A
WE39
WE35A
WE37
ADV_B
WE36
WE38
OE_B
BEy_B
MAXCO
Figure 23. Asynchronous A/D Muxed Read Access (RWSC = 5)
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59
Electrical Characteristics
CSx_B
ADDR
WE31
Last Valid Address
WE32
WE34
WE40
Next Address
Address V1
WE33
WE_B
ADV_B
OE_B
WE39
WE45
WE41
WE46
BEy_B
DATA
WE42
D(V1)
Figure 24. Asynchronous Memory Write Access
CSx_B
WE41
WE31
D(V1)
Addr. V1
WE32A
ADDR/
M_DATA
WE42
WE33
WE39
WE34
WE_B
WE40A
ADV_B
OE_B
WE45
WE46
WE42
BEy_B
Figure 25. Asynchronous A/D Muxed Write Access
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60
Electrical Characteristics
CSx_B
ADDR
WE31
WE32
Next Address
Last Valid Address
Address V1
WE_B
ADV_B
OE_B
WE39
WE35
WE37
WE40
WE36
WE38
BEy_B
WE44
DATA[7:0]
D(V1)
WE43
WE48
DTACK
WE47
Figure 26. DTACK Read Access (DAP=0)
CSx_B
ADDR
WE31
WE32
WE34
WE40
Next Address
Last Valid Address
Address V1
WE33
WE_B
ADV_B
OE_B
WE39
WE45
WE41
WE46
BEy_B
DATA
WE42
D(V1)
WE48
DTACK
WE47
Figure 27. DTACK Write Access (DAP=0)
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Electrical Characteristics
Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select
Max
Determination by
Synchronous measured
parameters 12
Ref
No.
(If 133 Mhz is
supported by
SOC)
Parameter
Min
Unit
WE31
WE32
CSx_B valid to Address Valid
WE4 - WE6 - CSA3
WE7 - WE5 - CSN4
—
—
3 - CSA
3 - CSN
ns
ns
Address Invalid to CSx_B
invalid
WE32
A(mux
ed A/D
CSx_B valid to Address
Invalid
t5 + WE4 - WE7 + (ADVN +
ADVA + 1 - CSA3)
-3 + (ADVN +
ADVA + 1 - CSA)
—
ns
WE33
WE34
CSx_B Valid to WE_B Valid
WE8 - WE6 + (WEA - CSA)
WE7 - WE9 + (WEN - CSN)
—
—
3 + (WEA - CSA)
3 - (WEN_CSN)
ns
ns
WE_B Invalid to CSx_B
Invalid
WE35
CSx_B Valid to OE_B Valid
CSx_B Valid to OE_B Valid
WE10 - WE6 + (OEA - CSA)
—
3 + (OEA - CSA)
ns
ns
WE35
A
(muxe
d A/D)
WE10 - WE6 + (OEA +
RADVN + RADVA + ADH + 1
- CSA)
-3 + (OEA +
RADVN+RADVA
+ADH+1-CSA)
3 + (OEA +
RADVN+RADVA+A
DH+1-CSA)
WE36
WE37
WE38
OE_B Invalid to CSx_B
Invalid
WE7 - WE11 + (OEN - CSN)
WE12 - WE6 + (RBEA - CSA)
WE7 - WE13 + (RBEN - CSN)
—
—
—
3 - (OEN - CSN)
3 + (RBEA6 - CSA)
3 - (RBEN7- CSN)
ns
ns
ns
CSx_B Valid to BEy_B Valid
(Read access)
BEy_B Invalid to CSx_B
Invalid (Read access)
WE39
WE40
CSx_B Valid to ADV_B Valid
WE14 - WE6 + (ADVA - CSA)
WE7 - WE15 - CSN
—
—
3 + (ADVA - CSA)
3 - CSN
ns
ns
ADV_B Invalid to CSx_B
Invalid (ADVL is asserted)
WE40
A
CSx_B Valid to ADV_B Invalid
WE14 - WE6 + (ADVN +
ADVA + 1 - CSA)
-3 + (ADVN +
ADVA + 1 - CSA)
3 + (ADVN + ADVA
+ 1 - CSA)
ns
(muxe
d A/D)
WE41
CSx_B Valid to Output Data
Valid
WE16 - WE6 - WCSA
—
—
3 - WCSA
ns
ns
WE41
A
(muxe
d A/D)
CSx_B Valid to Output Data
Valid
WE16 - WE6 + (WADVN +
WADVA + ADH + 1 - WCSA)
3 + (WADVN +
WADVA + ADH + 1 -
WCSA)
WE42
Output Data Invalid to CSx_B
Invalid
WE17 - WE7 - CSN
—
3 - CSN
ns
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Electrical Characteristics
Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select
Max
Determination by
Synchronous measured
parameters 12
Ref
No.
(If 133 Mhz is
supported by
SOC)
Parameter
Min
Unit
MAXC
O
Output max. delay from
internal driving ADDR/control
FFs to chip outputs.
10
—
—
—
—
—
ns
MAXC
SO
Output max. delay from CSx
internal driving FFs to CSx
out.
10
—
—
MAXDI
WE43
DATA MAXIMUM delay from
chip input data to its internal
FF
5
Input Data Valid to CSx_B
Invalid
MAXCO - MAXCSO + MAXDI
MAXCO -
MAXCSO +
MAXDI
ns
WE44
WE45
WE46
CSx_B Invalid to Input Data
invalid
0
0
—
ns
ns
ns
—
CSx_B Valid to BEy_B Valid
(Write access)
WE12 - WE6 + (WBEA - CSA)
—
—
—
3 + (WBEA - CSA)
-3 + (WBEN - CSN)
—
BEy_B Invalid to CSx_B
Invalid (Write access)
WE7 - WE13 + (WBEN -
CSN)
MAXD
TI
DTACKMAXIMUMdelayfrom
chip dtack input to its internal
FF + 2 cycles for
synchronization
WE47
WE48
Dtack Active to CSx_B Invalid
MAXCO - MAXCSO +
MAXDTI
MAXCO -
MAXCSO +
MAXDTI
—
—
ns
ns
CSx_B Invalid to Dtack
invalid
0
0
1
2
3
4
5
6
7
Parameters WE4... WE21 value see column BCD = 0 in Table 38
All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.
CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.
CS Negation. This bit field determines when CS signal is negated during read/write cycles.
t is axi_clk cycle time.
BE Assertion. This bit field determines when BE signal is asserted during read cycles.
BE Negation. This bit field determines when BE signal is negated during read cycles.
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Electrical Characteristics
4.6.7
DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2, and
DDR3)
The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008,
supporting DDR2-800 and LVDDR2-800.
The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting
DDR3-800.
The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800.
Figure 28 and Table 40 show the address and control timing parameters for DDR2 and DDR3.
DDR1
SDCLK
SDCLK
DDR2
DDR4
CS
DDR5
RAS
DDR5
DDR4
CAS
DDR4
DDR5
DDR5
WE
ODT/CKE
DDR4
DDR6
DDR7
ADDR
ROW/BA
COL/BA
Figure 28. DDR SDRAM Address and Control Parameters for DDR2 and DDR3
1 2
Table 40. DDR SDRAM Timing Parameter Table
SDCLK = 400 MHz
ID
Parameter
Symbol
Units
Min
Max
DDR1 SDRAM clock high-level width
DDR2 SDRAM clock low-level width
tCH
tCL
0.48
0.48
0.52
0.52
tCK
tCK
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Electrical Characteristics
1 2
Table 40. DDR SDRAM Timing Parameter Table (continued)
SDCLK = 400 MHz
ID
Parameter
Symbol
Units
Min
Max
DDR4 CS, RAS, CAS, CKE, WE, ODT setup time
DDR5 CS, RAS, CAS, CKE, WE, ODT hold time
DDR6 Address output setup time
tIS
tIH
tIS
tIH
0.6
0.6
0.6
0.6
—
ns
ns
ns
ns
—
—
—
DDR7 Address output hold time
1
2
All timings are refer to Vref level cross point.
Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.
Figure 29 and Table 41 show the address and control timing parameters for LPDDR2.
CK
LP1
LP4
LP2
CS
LP3
LP3
CKE
LP3
LP4
CA
LP4
LP3
Figure 29. DDR SDRAM Address and Control Timing Parameters for LPDDR2
1 2
Table 41. DDR SDRAM Timing Parameter Table for LPDDR2
SDCLK = 400 MHz
ID
Parameter
Symbol
Units
Min
Max
LP1
LP2
LP3
LP4
LP3
LP4
SDRAM clock high-level width
SDRAM clock low-level width
CS, CKE setup time
CS, CKE hold time
tCH
tCL
tIS
0.45
0.45
0.3
0.55
0.55
—
tCK
tCK
ns
ns
ns
ns
tIH
tIS
0.3
—
CA setup time
0.3
—
CA hold time
tIH
0.3
—
1
2
All timings are refer to Vref level cross point.
Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.
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Electrical Characteristics
Figure 30 and Table 42 show the data write timing parameters.
SDCLK
SDCLK_B
DDR21
DDR17
DDR22
DDR23
DQS (output)
DQ (output)
DDR18
Data
DDR17
DDR18
Data
DM
Data
Data
DM
Data
Data
DM
Data
DM
Data
DM
DM
DM
DM
DQM (output)
DDR17
DDR17
DDR18
DDR18
Figure 30. DDR SDRAM Data Write Cycle
1 2 3
Table 42. DDR SDRAM Write Cycle
SDCLK = 400 MHz
ID
Parameter
Symbol
Unit
Min
Max
DDR17 DQ and DQM setup time to DQS (differential strobe)
DDR18 DQ and DQM hold time to DQS (differential strobe)
DDR21 DQS latching rising transitions to associated clock edges
DDR22 DQS high level width
tDS
tDH
0.285
0.285
-0.25
0.45
—
—
ns
ns
tDQSS
tDQSH
tDQSL
+0.25
0.55
0.55
tCK
tCK
tCK
DDR23 DQS low level width
0.45
1
2
3
All timings are refer to Vref level cross point.
Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.
To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle
of DQ window.
Figure 31 and Table 43 show the data read timing parameters.
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Electrical Characteristics
SDCLK
SDCLK_B
DQS (input)
DDR27
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DQ (input)
DDR26
Figure 31. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle
1
Table 43. DDR SDRAM Read Cycle
SDCLK = 400 MHz
ID
Parameter
Symbol
Unit
Min
Max
DDR26
Minimum required DQ valid window width
except from LPDDR2
—
—
—
0.6
—
ns
ns
ns
DDR26(LP Minimum required DQ valid window width
DDR2)
0.425
—
for LPDDR2
DDR27
DQS to DQ valid data
0.275
0.475
1
To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle
of DQ window.
4.7
External Peripheral Interfaces Parameters
The following subsections provide information on external peripheral interfaces.
4.7.1
AUDMUX Timing Parameters
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI
electrical specifications found within this document.
4.7.2
CSPI and ECSPI Timing Parameters
This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have
separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI
modules and the respective routing of these signals is shown in Table 44.
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Electrical Characteristics
Block Instance
Table 44. CSPI Nomenclature and Routing
I/O Access
ECSPI-1
ECSPI-2
CSPI
GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC
DISP0_DAT, CSI0_DAT and EIM through IOMUXC
DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC
4.7.2.1
CSPI Master Mode Timing
Figure 32 depicts the timing of CSPI in master mode. Table 45 lists the CSPI master mode timing
characteristics.
RDY
CS10
SSx
CS5
CS6
CS2
CS1
CS3
CS4
SCLK
MOSI
MISO
CS2
CS7
CS3
CS9
CS8
Figure 32. CSPI/ECSPI Master Mode Timing Diagram
Table 45. CSPI Master Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
CS2
CS3
CS4
CS5
SCLK Cycle Time
SCLK High or Low Time
SCLK Rise or Fall1
SSx pulse width
tclk
tSW
60
26
—
26
26
—
—
—
—
—
ns
ns
ns
ns
ns
tRISE/FALL
tCSLH
tSCS
SSx Lead Time (Slave Select setup
time)
CS6
CS7
SSx Lag Time (SS hold time)
tHCS
26
–1
—
ns
ns
MOSI Propagation Delay
(CLOAD = 20 pF)
tPDmosi
21
CS8
MISO Setup Time
tSmiso
5
—
ns
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Electrical Characteristics
Unit
Table 45. CSPI Master Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
CS9
MISO Hold Time
RDY to SSx Time2
tHmiso
tSDRY
5
5
—
—
ns
ns
CS10
1
2
See specific I/O AC parameters Section 4.5, “I/O AC Parameters”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
4.7.2.2
CSPI Slave Mode Timing
Figure 33 depicts the timing of CSPI in slave mode. Timing characteristics were not available at the time
of publication.
SSx
CS1
CS5
CS6
CS2
CS4
SCLK
MISO
CS2
CS9
CS8
CS7
MOSI
Figure 33. CSPI/ECSPI Slave Mode Timing Diagram
4.7.2.3
ECSPI Master Mode Timing
Figure 32 depicts the timing of ECSPI in master mode. Table 46 lists the ECSPI master mode timing
characteristics.
Table 46. ECSPI Master Mode Timing Parameters
ID
Parameter
SCLK Cycle Time–Read
Symbol
Min
Max
Unit
CS1
tclk
30
15
—
ns
SCLK Cycle Time–Write
CS2
SCLK High or Low Time–Read
SCLK High or Low Time–Write
tSW
14
7
—
ns
CS3
CS4
CS5
CS6
CS7
CS8
SCLK Rise or Fall1
tRISE/FALL
tCSLH
—
—
—
—
—
2.5
—
ns
ns
ns
ns
ns
ns
SSx pulse width
Half SCLK period
SSx Lead Time (CS setup time)
SSx Lag Time (CS hold time)
MOSI Propagation Delay (CLOAD = 20 pF)
MISO Setup Time
tSCS
5
5
tHCS
tPDmosi
tSmiso
-0.5
8.5
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Electrical Characteristics
Table 46. ECSPI Master Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
CS9
MISO Hold Time
tHmiso
tSDRY
0
5
—
—
ns
ns
CS10
RDY to SSx Time2
1
2
See specific I/O AC parameters Section 4.5, “I/O AC Parameters”
SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
4.7.2.4
ECSPI Slave Mode Timing
Figure 33 depicts the timing of ECSPI in slave mode. Table 47 lists the ECSPI slave mode timing
characteristics.
Table 47. ECSPI Slave Mode Timing Parameters
ID
Parameter
SCLK Cycle Time–Read
Symbol
Min
Max
Unit
CS1
tclk
15
40
—
ns
SCLK Cycle Time–Write
CS2
SCLK High or Low Time–Read
SCLK High or Low Time–Write
tSW
7
20
—
ns
CS4
CS5
CS6
CS7
CS8
CS9
SSx pulse width
tCSLH
tSCS
Half SCLK period
—
—
—
—
—
17
ns
ns
ns
ns
ns
ns
SSx Lead Time (CS setup time)
SSx Lag Time (CS hold time)
MOSI Setup Time
5
5
4
4
4
tHCS
tSmosi
tHmosi
tPDmiso
MOSI Hold Time
MISO Propagation Delay (CLOAD = 20 pF)
4.7.3
Enhanced Serial Audio Interface (ESAI) Timing Parameters
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 48 shows the interface timing values. The number field in the table refers to timing signals
found in Figure 34 and Figure 35.
Table 48. Enhanced Serial Audio Interface (ESAI) Timing
Characteristics1’2,3
No.
Symbol Expression3 Min
Max Condition4 Unit
62 Clock cycle5
tSSICC
4 × T
4 × T
30.0
30.0
—
—
i ck
i ck
ns
ns
c
c
63 Clock high period
• For internal clock
—
—
2 × T − 9.0
6
—
—
—
—
c
• For external clock
2 × T
15
c
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Electrical Characteristics
Table 48. Enhanced Serial Audio Interface (ESAI) Timing (continued)
Characteristics1’2,3
No.
Symbol Expression3 Min
Max Condition4 Unit
64 Clock low period
ns
—
—
2 × T − 9.0
6
—
—
—
—
• For internal clock
c
• For external clock
2 × T
15
c
65 SCKR rising edge to FSR out (bl) high
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
66 SCKR rising edge to FSR out (bl) low
67 SCKR rising edge to FSR out (wr) high6
68 SCKR rising edge to FSR out (wr) low6
69 SCKR rising edge to FSR out (wl) high
70 SCKR rising edge to FSR out (wl) low
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
—
—
—
—
—
—
19.0
9.0
x ck
i ck a
—
—
—
—
—
—
16.0
6.0
x ck
i ck a
—
—
—
—
—
—
17.0
7.0
x ck
i ck a
71 Data in setup time before SCKR (SCK in synchronous
mode) falling edge
—
—
—
—
12.0
19.0
—
—
x ck
i ck
72 Data in hold time after SCKR falling edge
73 FSR input (bl, wr) high before SCKR falling edge6
74 FSR input (wl) high before SCKR falling edge
75 FSR input hold time after SCKR falling edge
78 SCKT rising edge to FST out (bl) high
79 SCKT rising edge to FST out (bl) low
80 SCKT rising edge to FST out (wr) high6
81 SCKT rising edge to FST out (wr) low6
82 SCKT rising edge to FST out (wl) high
83 SCKT rising edge to FST out (wl) low
—
—
—
—
3.5
9.0
—
—
x ck
i ck
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
—
—
—
—
2.0
12.0
—
—
x ck
i ck a
—
—
—
—
2.5
8.5
—
—
x ck
i ck a
—
—
—
—
—
—
18.0
8.0
x ck
i ck
—
—
—
—
—
—
20.0
10.0
x ck
i ck
—
—
—
—
—
—
20.0
10.0
x ck
i ck
—
—
—
—
—
—
22.0
12.0
x ck
i ck
—
—
—
—
—
—
19.0
9.0
x ck
i ck
—
—
—
—
—
—
20.0
10.0
x ck
i ck
84 SCKT rising edge to data out enable from high
impedance
—
—
—
—
—
—
22.0
17.0
x ck
i ck
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Electrical Characteristics
Table 48. Enhanced Serial Audio Interface (ESAI) Timing (continued)
Characteristics1’2,3
No.
Symbol Expression3 Min
Max Condition4 Unit
86 SCKT rising edge to data out valid
—
—
—
—
—
—
18.0
13.0
x ck
i ck
ns
ns
ns
ns
ns
87 SCKT rising edge to data out high impedance 77
89 FST input (bl, wr) setup time before SCKT falling edge6
90 FST input (wl) setup time before SCKT falling edge
91 FST input hold time after SCKT falling edge
—
—
—
—
—
—
21.0
16.0
x ck
i ck
—
—
—
—
2.0
18.0
—
—
x ck
i ck
—
—
—
—
2.0
18.0
—
—
x ck
i ck
—
—
—
—
4.0
5.0
—
—
x ck
i ck
95 HCKR/HCKT clock cycle
—
—
—
2 x TC
—
15
—
—
—
—
—
—
ns
ns
ns
96 HCKT input rising edge to SCKT output
97 HCKR input rising edge to SCKR output
18.0
18.0
—
1
2
VCORE_VDD= 1.00 +- 0.10V
Tj = -40C to 125C
CL=50pF
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
3
4
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
5
6
For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
7
Periodically sampled and not 100% tested.
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Electrical Characteristics
62
63
64
SCKT
(Input/Output)
78
79
FST (Bit)
Out
82
83
FST (Word)
Out
86
84
86
87
First Bit
Last Bit
Data Out
89
91
FST (Bit) In
91
90
FST (Word) In
Figure 34. ESAI Transmitter Timing
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Electrical Characteristics
62
63
64
SCKR
(Input/Output)
65
66
FSR (Bit)
Out
69
70
FSR (Word)
Out
72
71
Data In
Last Bit
First Bit
75
73
FSR (Bit)
In
74
75
FSR (Word)
In
Figure 35. ESAI Receiver Timing
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Freescale Semiconductor
Electrical Characteristics
4.7.4
Enhanced Secured Digital Host Controller(eSDHCv2/v3) AC timing
This section describes the electrical information of the eSDHCv2/v3, which includes SD/eMMC4.3
(Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing.
4.7.4.1
SD/eMMC4.3 (Single Data Rate) AC Timing
Figure 36 depicts the timing of SD/eMMC4.3, and Table 49 lists the SD/eMMC4.3 timing characteristics.
SD4
SD2
SD1
SD5
SCK
SD3
CMD
SD6
DAT0
DAT1
output from eSDHCv2 to card
......
DAT7
SD7
SD8
CMD
DAT0
DAT1
......
input from card to eSDHCv2
DAT7
Figure 36. SD/eMMC4.3 Timing
Table 49. SD/eMMC4.3 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
1
SD1 Clock Frequency (Low Speed)
fPP
0
0
400
25/50
20/52
400
—
kHz
MHz
MHz
kHz
ns
2
Clock Frequency (SD/SDIO Full Speed/High Speed)
Clock Frequency (MMC Full Speed/High Speed)
Clock Frequency (Identification Mode)
fPP
3
fPP
0
fOD
tWL
100
7
SD2 Clock Low Time
SD3 Clock High Time
SD4 Clock Rise Time
SD5 Clock Fall Time
tWH
tTLH
tTHL
7
—
ns
—
—
3
ns
3
ns
eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)
SD6 eSDHC Output Delay
tOD
–5
5
ns
eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)
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Electrical Characteristics
Table 49. SD/eMMC4.3 Interface Timing Specification (continued)
ID
Parameter
Symbols
Min
Max
Unit
eSDHC Input Setup Time
eSDHC Input Hold Time4
tISU
2.5
—
ns
SD7
SD8
tIH
2.5
—
ns
1
2
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,
clock frequency can be any value between 0–50 MHz.
In normal (full) speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In high-speed mode, clock
frequency can be any value between 0–52 MHz.
3
4To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
4.7.4.2
eMMC4.4 (Dual Data Rate) eSDHCv3 AC Timing
Figure 37 depicts the timing of eMMC4.4. Table 50 lists the eMMC4.4 timing characteristics. Be aware
that only DATA is sampled on both edges of the clock (not applicable to CMD).
SD1
SCK
SD2
SD2
DAT0
DAT1
......
output from eSDHCv3 to card
......
......
DAT7
SD3
SD4
DAT0
DAT1
......
DAT7
input from card to eSDHCv3
Figure 37. eMMC4.4 Timing
Table 50. eMMC4.4 Interface Timing Specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
Clock Frequency (MMC Full Speed/High Speed)
SD1
SD2
fPP
0
52
5
MHz
ns
eSDHC Output / Card Inputs CMD, DAT (Reference to CLK)
eSDHC Output Delay tOD –5
eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)
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Electrical Characteristics
Table 50. eMMC4.4 Interface Timing Specification (continued)
ID
Parameter
eSDHC Input Setup Time
Symbols
Min
Max
Unit
SD3
SD4
tISU
tIH
2.5
2.5
—
—
ns
ns
eSDHC Input Hold Time
4.7.5
FEC AC Timing Parameters
This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC
is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver
interface and transceiver function are required to complete the interface to the media. The FEC supports
the 10/100 Mbps MII (18 pins in total) and the 10 Mbps (only 7-wire interface, which uses 7 of the MII
pins), for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see the i.MX53
Reference Manual.
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.7.5.1
MII Receive Signal Timing
The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and
FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of
25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must
exceed twice the FEC_RX_CLK frequency. Table 51 lists the MII receive channel signal timing
parameters and Figure 38 shows MII receive signal timings.
.
Table 51. MII Receive Signal Timing
No.
Characteristics1 2
Min
Max
Unit
M1
M2
M3
M4
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
FEC_RX_CLK pulse width high
5
—
—
ns
5
ns
35%
35%
65%
65%
FEC_RX_CLK period
FEC_RX_CLK period
FEC_RX_CLK pulse width low
1
2
FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.
Test conditions: 25pF on each output signal.
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Electrical Characteristics
M3
FEC_RX_CLK (input)
M4
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M1
M2
Figure 38. MII Receive Signal Timing Diagram
4.7.5.2
MII Transmit Signal Timing
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
Table 52 lists MII transmit channel timing parameters. Figure 39 shows MII transmit signal timing
diagram for the values listed in Table 52.
Table 52. MII Transmit Signal Timing
Num
Characteristic1 2
Min
Max
Unit
M5
M6
M7
M8
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
FEC_TX_CLK pulse width high
5
—
ns
—
20
ns
35%
35%
65%
65%
FEC_TX_CLK period
FEC_TX_CLK period
FEC_TX_CLK pulse width low
1
2
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
Test conditions: 25pF on each output signal.
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Electrical Characteristics
.
M7
FEC_TX_CLK (input)
M5
M8
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M6
Figure 39. MII Transmit Signal Timing Diagram
4.7.5.3
MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 53 lists MII asynchronous inputs signal timing information. Figure 40 shows MII asynchronous
input timings listed in Table 53.
Table 53. MII Async Inputs Signal Timing
Num
Characteristic 1
Min
Max
Unit
M92
FEC_CRS to FEC_COL minimum pulse width
1.5
—
FEC_TX_CLK period
1
2
Test conditions: 25pF on each output signal.
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
.
FEC_CRS, FEC_COL
M9
Figure 40. MII Async Inputs Timing Diagram
4.7.5.4
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Table 54 lists MII serial management channel timings. Figure 41 shows MII serial management channel
timings listed in Table 54. The MDC frequency should be equal to or less than 2.5 MHz to be compliant
with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC
frequency of 15 MHz.
Table 54. MII Transmit Signal Timing
ID
Characteristics1
Min Max
Unit
M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)
M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)
M12 FEC_MDIO (input) to FEC_MDC rising edge setup
0
—
5
ns
ns
ns
—
18
—
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Electrical Characteristics
Table 54. MII Transmit Signal Timing (continued)
Characteristics1
ID
Min Max
Unit
M13 FEC_MDIO (input) to FEC_MDC rising edge hold
M14 FEC_MDC pulse width high
0
—
ns
40 60% FEC_MDC period
%
M15 FEC_MDC pulse width low
40 60% FEC_MDC period
%
1
Test conditions: 25pF on each output signal.
M14
M15
FEC_MDC (output)
FEC_MDIO (output)
M10
M11
FEC_MDIO (input)
M12
M13
Figure 41. MII Serial Management Channel Timing Diagram
4.7.5.5
RMII Mode Timing
In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz 50 ppm continuous reference
clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode include
FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER.
The RMII mode timings are shown in Table 55 and Figure 42.
Table 55. RMII Signal Timing
No.
Characteristics1
Min
Max
Unit
M16
M17
M18
M19
REF_CLK(FEC_TX_CLK) pulse width high
REF_CLK(FEC_TX_CLK) pulse width low
REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid
REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid
35%
35%
2
65%
65%
—
REF_CLK period
REF_CLK period
ns
ns
—
16
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Electrical Characteristics
Table 55. RMII Signal Timing (continued)
No.
Characteristics1
Min
Max
Unit
M20
FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to
REF_CLK setup
4
—
ns
M21
REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER
hold
2
—
ns
1
Test conditions: 25pF on each output signal.
M16
M17
REF_CLK (input)
M18
FEC_TXD[1:0] (output)
FEC_TX_EN
M19
CRS_DV (input)
FEC_RXD[1:0]
FEC_RX_ER
M20
M21
Figure 42. RMII Mode Signal Timing Diagram
4.7.6
Flexible Controller Area Network (FLEXCAN) AC Electrical
Specifications
The electrical characteristics are related to the CAN transceiver external to i.MX53xA such as MC33902
from Freescale.The i.MX53xA has two CAN modules available for systems design. Tx and Rx ports for
both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the i.MX53 Reference
Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN,
respectively.
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Electrical Characteristics
4.7.7
I2C Module Timing Parameters
2
2
This section describes the timing parameters of the I C module. Figure 43 depicts the timing of I C
module, and Table 56 lists the I C module timing characteristics.
2
IC11
IC9
IC10
I2DAT
I2CLK
IC7
IC4
IC2
IC3
IC8
IC10
IC6
IC11
STOP
START
START
START
IC5
IC1
2
Figure 43. I C Bus Timing
2
Table 56. I C Module Timing Parameters
Standard Mode
Supply Voltage =
1.65 V–1.95 V, 2.7 V–3.3 V
Fast Mode
Supply Voltage =
2.7 V–3.3 V
ID
Parameter
Unit
Min
Max
Min
Max
IC1
IC2
I2CLK cycle time
10
4.0
4.0
01
—
—
2.5
0.6
0.6
01
—
—
—
µs
µs
µs
Hold time (repeated) START condition
Set-up time for STOP condition
IC3
—
IC4
Data hold time
3.452
—
0.92 µs
IC5
HIGH Period of I2CLK Clock
4.0
4.7
4.7
250
4.7
—
0.6
1.3
0.6
1003
1.3
—
—
—
—
—
µs
µs
µs
ns
µs
IC6
LOW Period of the I2CLK Clock
Set-up time for a repeated START condition
Data set-up time
—
IC7
—
IC8
—
IC9
Bus free time between a STOP and START condition
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
Capacitive load for each bus line (Cb)
—
4
IC10
IC11
IC12
1000
300
400
20 + 0.1Cb 300 ns
4
—
20 + 0.1Cb 300 ns
—
—
400 pF
1
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
2
3
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
4
Cb = total capacitance of one bus line in pF.
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Electrical Characteristics
4.7.8
Image Processing Unit (IPU) Module Parameters
The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor
and/or to a display device. This support covers all aspects of these activities:
•
•
Connectivity to relevant devices—cameras, displays, graphics accelerators, and TV encoders.
Related image processing and manipulation: sensor image signal processing, display processing,
image conversions, and other related functions.
•
Synchronization and control capabilities, such as avoidance of tearing artifacts.
4.7.8.1
IPU Sensor Interface Signal Mapping
The IPU supports a number of sensor input formats. Table 57 defines the mapping of the Sensor Interface
Pins used for various supported interface formats.
Table 57. Camera Input Signal Cross Reference, Format and Bits per Cycle
RGB565
8 bits
2 cycles
RGB5652
8 bits
3 cycles
RGB6663 RGB888
YCbCr RGB5654 YCbCr5
YCbCr6
16 bits
1 cycle
YCbCr7
20 bits
1 cycle
Signal
Name1
8 bits
8 bits
8 bits
16 bits
16 bits
1 cycle
3 cycles
3 cycles
2 cycles 2 cycles
CSIx_DAT0
CSIx_DAT1
CSIx_DAT2
CSIx_DAT3
CSIx_DAT4
CSIx_DAT5
CSIx_DAT6
CSIx_DAT7
CSIx_DAT8
CSIx_DAT9
CSIx_DAT10
CSIx_DAT11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
C[8]
C[9]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y[8]
Y[9]
—
—
0
—
—
—
—
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
0
—
—
—
—
—
—
B[0]
B[1]
B[2]
B[3]
B[4]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
R[0]
R[1]
R[2]
R[3]
R[4]
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
CSIx_DAT12 B[0], G[3] R[2],G[4],B[2] R/G/B[4]
CSIx_DAT13 B[1], G[4] R[3],G[5],B[3] R/G/B[5]
CSIx_DAT14 B[2], G[5] R[4],G[0],B[4] R/G/B[0]
CSIx_DAT15 B[3], R[0] R[0],G[1],B[0] R/G/B[1]
CSIx_DAT16 B[4], R[1] R[1],G[2],B[1] R/G/B[2]
CSIx_DAT17 G[0], R[2] R[2],G[3],B[2] R/G/B[3]
CSIx_DAT18 G[1], R[3] R[3],G[4],B[3] R/G/B[4]
CSIx_DAT19 G[2], R[4] R[4],G[5],B[4] R/G/B[5]
R/G/B[0]
R/G/B[1]
R/G/B[2]
R/G/B[3]
R/G/B[4]
R/G/B[5]
R/G/B[6]
R/G/B[7]
Y/C[0]
Y/C[1]
Y/C[2]
Y/C[3]
Y/C[4]
Y/C[5]
Y/C[6]
Y/C[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
1
CSIx stands for CSI1 or CSI2
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Electrical Characteristics
2
The MSB bits are duplicated on LSB bits implementing color extension
3
The two MSB bits are duplicated on LSB bits implementing color extension
4
RGB 16 bits – supported in two ways: (1) As a “generic data” input – with no on-the-fly processing; (2) With on-the-fly
processing, but only under some restrictions on the control protocol.
5
YCbCr 16 bits - supported as a “generic-data” input – with no on-the-fly processing.
6
YCbCr 16 bits - supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).
7
YCbCr, 20 bits, supported only within the BT.1120 protocol (syncs embedded within the data stream).
4.7.8.2
Sensor Interface Timings
There are three camera timing modes supported by the IPU.
4.7.8.2.1
BT.656 and BT.1120 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use
an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing
syntax is defined by the BT.656/BT.1120 standards.
This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only
control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data
stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking
is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one
component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are
received over the SENSB_DATA bus.
4.7.8.2.2
Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure 44.
Active Line
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_HSYNC
SENSB_PIX_CLK
invalid
invalid
SENSB_DATA[19:0]
1st byte
1st byte
Figure 44. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid
as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
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SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.7.8.2.3
Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.7.8.2.2, “Gated Clock Mode,”)
except for the SENSB_HSYNC signal, which is not used (see Figure 45). All incoming pixel clocks are
valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK
invalid
invalid
SENSB_DATA[19:0]
1st byte
1st byte
Figure 45. Non-Gated Clock Mode Timing Diagram
The timing described in Figure 45 is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.7.8.3
Electrical Characteristics
Figure 46 depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by
the IPU. Table 58 lists the sensor interface timing characteristics.
SENSB_PIX_CLK
(Sensor Output)
1/IP1
IP2
IP3
SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC
Figure 46. Sensor Interface Timing Diagram
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Table 58. Sensor Interface Timing Characteristics
ID
Parameter
Symbol
Fpck
Min
Max
Unit
MHz
IP1
IP2
IP3
Sensor output (pixel) clock frequency
Data and control setup time
0.01
2
180
—
Tsu
Thd
ns
ns
Data and control holdup time
1
—
4.7.8.4
IPU Display Interface Signal Mapping
The IPU supports a number of display output video formats. Table 59 defines the mapping of the Display
Interface Pins used during various supported video interface formats.
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Table 59. Video Signal Cross-Reference
LCD
i.MX53xA
RGB/TV Signal Allocation (Example)
16-bit 18-bit 24 Bit 8-bit 16-bit 20-bit
Smart
Comment1
RGB,
Signal
Name
Port Name
(x=0, 1)
Signal
Name
(General) RGB RGB RGB YCrCb2 YCrCb YCrCb
DISPx_DAT0
DISPx_DAT1
DISPx_DAT2
DISPx_DAT3
DISPx_DAT4
DISPx_DAT5
DISPx_DAT6
DISPx_DAT7
DISPx_DAT8
DISPx_DAT9
DAT[0]
DAT[1]
DAT[2]
DAT[3]
DAT[4]
DAT[5]
DAT[6]
DAT[7]
DAT[8]
DAT[9]
B[0]
B[1]
B[2]
B[3]
B[4]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
R[0]
R[1]
R[2]
R[3]
R[4]
—
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
—
B[0]
B[1]
B[2]
B[3]
B[4]
B[5]
B[6]
B[7]
G[0]
G[1]
G[2]
G[3]
G[4]
G[5]
G[6]
G[7]
R[0]
R[1]
R[2]
R[3]
R[4]
R[5]
Y/C[0]
Y/C[1]
Y/C[2]
Y/C[3]
Y/C[4]
Y/C[5]
Y/C[6]
Y/C[7]
—
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
—
C[0]
C[1]
C[2]
C[3]
C[4]
C[5]
C[6]
C[7]
C[8]
C[9]
Y[0]
Y[1]
Y[2]
Y[3]
Y[4]
Y[5]
Y[6]
Y[7]
Y[8]
Y[9]
—
DAT[0]
DAT[1]
DAT[2]
DAT[3]
DAT[4]
DAT[5]
DAT[6]
DAT[7]
DAT[8]
DAT[9]
DAT[10]
DAT[11]
DAT[12]
DAT[13]
DAT[14]
DAT[15]
—
The restrictions are as follows:
a) There are maximal three
continuous groups of bits that
could be independently mapped to
the external bus.
Groups should not be overlapped.
b) The bit order is expressed in
each of the bit groups, for example
B[0] = least significant blue pixel
bit
—
DISPx_DAT10 DAT[10]
DISPx_DAT11 DAT[11]
DISPx_DAT12 DAT[12]
DISPx_DAT13 DAT[13]
DISPx_DAT14 DAT[14]
DISPx_DAT15 DAT[15]
DISPx_DAT16 DAT[16]
DISPx_DAT17 DAT[17]
DISPx_DAT18 DAT[18]
DISPx_DAT19 DAT[19]
DISPx_DAT20 DAT[20]
DISPx_DAT21 DAT[21]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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Table 59. Video Signal Cross-Reference (continued)
LCD
i.MX53xA
RGB/TV Signal Allocation (Example)
16-bit 18-bit 24 Bit 8-bit 16-bit 20-bit
Smart
Comment1
RGB,
Signal
Name
Port Name
(x=0, 1)
Signal
Name
(General) RGB RGB RGB YCrCb2 YCrCb YCrCb
DISPx_DAT22 DAT[22]
DISPx_DAT23 DAT[23]
DIx_DISP_CLK
—
—
—
—
R[6]
R[7]
—
—
—
—
—
—
—
—
—
—
—
—
PixCLK
—
DIx_PIN1
VSYNC_IN May be required for anti-tearing
DIx_PIN2
DIx_PIN3
DIx_PIN4
DIx_PIN5
DIx_PIN6
DIx_PIN7
DIx_PIN8
DIx_D0_CS
DIx_D1_CS
HSYNC
—
—
—
VSYNC
—
VSYNC out
—
Additional frame/row synchronous
signals with programmable timing
—
—
—
—
—
—
—
—
—
CS0
CS1
—
—
Alternate mode of PWM output for
contrast or brightness control
DIx_PIN11
DIx_PIN12
DIx_PIN13
DIx_PIN14
DIx_PIN15
DIx_PIN16
DIx_PIN17
—
WR
RD
—
—
—
—
RS1
RS2
DRDY
—
Register select signal
Optional RS2
—
DRDY/DV
Data validation/blank, data enable
—
Q
Additional data synchronous
signals with programmable
features/timing
—
1
Signal mapping (both data and control/synchronization) is flexible. The table provides examples.
2
This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line
start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data
during blanking intervals is not supported.
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Electrical Characteristics
NOTE
Table 59 provides information for both the Disp0 and Disp1 ports. However,
Disp1 port has reduced pinout depending on IOMUXC configuration and
therefore may not support all the above configurations. See the IOMUXC
table for details.
4.7.8.5
IPU Display Interface Timing
The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There
are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.
4.7.8.5.1
Synchronous Controls
The synchronous control changes its value as a function of a system or of an external clock. This control
has a permanent period and a permanent wave form.
There are special physical outputs to provide synchronous controls:
•
The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display
(component, pixel) clock for a display.
•
The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide
HSYNC, VSYNC, DRDY or any else independent signal to a display.
The IPU has a system of internal binding counters for internal events (such as HSYNC/VSYCN and so on)
calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control
starts from the local start point with predefined UP and DOWN values to calculate control’s changing
points with half DI_CLK resolution. A full description of the counters system can be found in the IPU
chapter of the i.MX53 Reference Manual.
4.7.8.5.2
Asynchronous Controls
The asynchronous control is a data-oriented signal that changes its value with an output data according to
additional internal flags coming with the data.
There are special physical outputs to provide asynchronous controls, as follows:
•
•
The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.
The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide
WR. RD, RS or any other data oriented signal to display.
NOTE
The IPU has independent signal generators for asynchronous signals
toggling. When a DI decides to put a new asynchronous data in the bus, a
new internal start (local start point) is generated. The signals generators
calculate predefined UP and DOWN values to change pins states with half
DI_CLK resolution.
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Electrical Characteristics
4.7.8.6
Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
IPU Display Operating Signals
4.7.8.6.1
The IPU uses four control signals and data to operate a standard synchronous interface:
•
•
•
•
IPP_DISP_CLK—Clock to display
HSYNC—Horizontal synchronization
VSYNC—Vertical synchronization
DRDY—Active data
All synchronous display controls are generated on the base of an internally generated “local start point”.
The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.
The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved
relative to the local start point. The data bus of the synchronous interface is output direction only.
4.7.8.6.2
LCD Interface Functional Description
Figure 47 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
•
•
DI_CLK internal DI clock, used for calculation of other controls.
IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, IPP_DISP_CLK runs continuously.
•
•
HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPP_PIN_3 is used as VSYNC.)
•
DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
VSYNC
HSYNC
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1 LINE n
HSYNC
DRDY
1
2
3
m–1
m
IPP_DISP_CLK
IPP_DATA
Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels
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Electrical Characteristics
4.7.8.6.3
TFT Panel Sync Pulse Timing Diagrams
Figure 48 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All the parameters shown in the figure are programmable. All controls are started by
corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of
the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.
IP13o
IP7
IP5
IP5o
IP8o
IP8
DI clock
IPP_DISP_CLK
VSYNC
HSYNC
DRDY
IPP_DATA
Dn
D0
D1
IP9o
IP10
IP9
IP6
Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 49 depicts the vertical timing (timing of one frame). All parameters shown in the figure are
programmable.
End of frame
Start of frame
IP13
VSYNC
HSYNC
DRDY
IP11
IP15
IP14
IP12
Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse
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Electrical Characteristics
Table 60 shows timing characteristics of signals presented in Figure 48 and Figure 49.
Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level)
ID
Parameter
Symbol
Value
Description
Unit
IP5
IP6
Display interface clock period Tdicp
Display pixel clock period
(1)
Display interface clock. IPP_DISP_CLK
ns
ns
Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display,
× Tdicp
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXELis receivedby
DC/DI one access division to n
components.
IP7
Screen width time
Tsw
(SCREEN_WIDTH)
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
ns
× Tdicp
The SCREEN_WIDTH should be built by
suitable DI’s counter2.
IP8
IP9
HSYNC width time
Thsw
Thbi1
(HSYNC_WIDTH)
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
ns
ns
Horizontal blank interval 1
BGXP × Tdicp
BGXP—width of a horizontal blanking
before a first active data in a line (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
IP10 Horizontal blank interval 2
IP12 Screen height
Thbi2
Tsh
(SCREEN_WIDTH –
BGXP – FW) × Tdicp
Width a horizontal blanking after a last
active data in a line (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
ns
(SCREEN_HEIGHT)
SCREEN_HEIGHT—screenheight in lines ns
with blanking.
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
× Tsw
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
IP13 VSYNC width
Tvsw
Tvbi1
Tvbi2
VSYNC_WIDTH
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
ns
ns
ns
IP14 Vertical blank interval 1
IP15 Vertical blank interval 2
BGYP × Tsw
BGYP—width of first Vertical
blanking interval in line.The BGYP should
be built by suitable DI’s counter.
(SCREEN_HEIGHT – Width of second Vertical
BGYP – FH) × Tsw blanking interval in line.The FH should be
built by suitable DI’s counter.
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Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
ID
Parameter
Symbol
Value
Description
Unit
IP5o Offset of IPP_DISP_CLK
Todicp
DISP_CLK_OFFSET—offset of
IPP_DISP_CLK edges from local start
point, in DI_CLK×2
ns
DISP_×CLTKd_icOlkFFSET
(0.5 DI_CLK Resolution)
Defined by DISP_CLK counter
IP13o Offset of VSYNC
Tovs
Tohs
VSYNC_OFFSET
VSYNC_OFFSET—offset of Vsync edges
from a local start point, when a Vsync
should be active, in DI_CLK×2
(0.5 DI_CLK Resolution).The
VSYNC_OFFSET should be built by
suitable DI’s counter.
ns
ns
ns
× Tdiclk
IP8o Offset of HSYNC
HSYNC_OFFSET
HSYNC_OFFSET—offset of Hsync edges
from a local start point, when a Hsync
should be active, in DI_CLK×2
(0.5 DI_CLK Resolution).The
HSYNC_OFFSET should be built by
suitable DI’s counter.
× Tdiclk
IP9o Offset of DRDY
Todrdy
DRDY_OFFSET
DRDY_OFFSET—offset of DRDY edges
from a suitable local start point, when a
corresponding data has been set on the
bus, in DI_CLK×2
× Tdiclk
(0.5 DI_CLK Resolution)
The DRDY_OFFSET should be built by
suitable DI’s counter.
1
Display interface clock period immediate value.
⎧
⎪
⎪
⎨
⎪
DISP_CLK_PERIOD
----------------------------------------------------
DISP_CLK_PERIOD
DI_CLK_PERIOD
T
×
,
for integer ----------------------------------------------------
diclk
DI_CLK_PERIOD
Tdicp =
DISP_CLK_PERIOD
----------------------------------------------------
+ 0.5 ± 0.5 , for fractional ----------------------------------------------------
DISP_CLK_PERIOD
DI_CLK_PERIOD
⎛
⎞
T
floor
⎪ diclk⎝
⎠
DI_CLK_PERIOD
⎩
DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.
DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency
Display interface clock period average value.
DISP_CLK_PERIOD
----------------------------------------------------
Tdicp = T
×
diclk
DI_CLK_PERIOD
2
DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the
counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by
corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance
between HSYNCs is a SCREEN_WIDTH.
The maximal accuracy of UP/DOWN edge of controls is:
Accuracy = (0.5 × T
)±0.62ns
diclk
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Electrical Characteristics
The maximal accuracy of UP/DOWN edge of IPP_DATA is:
Accuracy = T
±0.62ns
diclk
The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed through the registers.
Figure 50 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and
DISP_CLK_UP parameters are set through the Register. Table 61 lists the synchronous display interface
timing characteristics.
IP20o IP20
VSYNC
HSYNC
DRDY
other controls
IPP_DISP_CLK
Tdicd
Tdicu
IP18
IPP_DATA
IP16
IP17
IP19
local start point
Figure 50. Synchronous Display Interface Timing Diagram—Access Level
Table 61. Synchronous Display Interface Timing Characteristics (Access Level)
ID
Parameter
Symbol
Min
Typ1
Max
Unit
IP16
Display interface clock Tckl
low time
Tdicd-Tdicu–1.24
Tdicd2–Tdicu3
Tdicd–Tdicu+1.24
ns
IP17
Display interface clock Tckh
high time
Tdicp–Tdicd+Tdicu–1.24 Tdicp–Tdicd+Tdicu Tdicp–Tdicd+Tdicu+1.2 ns
IP18
IP19
IP20o
Data setup time
Data holdup time
Tdsu
Tdhd
Tdicd–1.24
Tdicu
—
—
ns
ns
ns
Tdicp–Tdicd–1.24
Tocsu–1.24
Tdicp–Tdicu
Tocsu
Control signals offset Tocsu
times (defines for each
pin)
Tocsu+1.24
IP20
Control signals setup Tcsu
time to display
Tdicd–1.24–Tocsu%Tdicp Tdicu
—
ns
interface clock
(defines for each pin)
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
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2
3
Display interface clock down time
2 × DISP_CLK_DOWN
1
2
⎛
⎞
⎠
-----------------------------------------------------------
× ceil
Tdicd = -- T
⎝ diclk
DI_CLK_PERIOD
Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
2 × DISP_CLK_UP
1
2
⎛
⎞
⎠
------------------------------------------------
× ceil
Tdicu = -- T
⎝ diclk
DI_CLK_PERIOD
4.7.8.7
Interface to a TV Encoder (TVDAC)
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of
the interface is described in Figure 51.
NOTE
•
•
•
•
The frequency of the clock DISP_CLK is 27 MHz (within 10%)
The HSYNC, VSYNC signals are active low.
The DRDY signal is shown as active high.
The transition to the next row is marked by the negative edge of the
HSYNC signal. It remains low for a single clock cycle.
•
The transition to the next field/frame is marked by the negative edge of
the VSYNC signal. It remains low for at least one clock cycles.
— At a transition to an odd field (of the next frame), the negative edges
of VSYNC and HSYNC coincide.
— At a transition is to an even field (of the same frame), they do not
coincide.
•
The active intervals—during which data is transferred—are marked by
the HSYNC signal being high.
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Electrical Characteristics
DISP_CLK
HSYNC
VSYNC
DRDY
Cb
Y
Cr
Y
3
Cb
Y
Cr
IPP_DATA
Pixel Data Timing
523
524
525
1
2
4
5
6
10
HSYNC
DRDY
VSYNC
Even Field
262 263
Odd Field
268 269
261
264
265
266
267
273
HSYNC
DRDY
VSYNC
Even Field
Odd Field
Line and Field Timing - NTSC
621
622
623
624
625
1
2
3
4
23
HSYNC
DRDY
VSYNC
Even Field
Odd Field
308
309
310
311
312
313
314
315
316
336
HSYNC
DRDY
VSYNC
Even Field
Odd Field
Line and Field Timing - PAL
Figure 51. TV Encoder Interface Timing Diagram
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4.7.8.7.1
TVEv2 TV Encoder Performance Specifications
The TV encoder output specifications are shown in Table 62. All the parameters in the table are defined
under the following conditions:
•
•
R
= 1.05 kΩ 1%, resistor on TVDAC_VREF pin to GND
set
R
= 37.5 Ω 1%, output load to the GND
load
Table 62. TV Encoder Video Performance Specifications
Parameter
Conditions
Min
Typ
Max
Unit
DAC STATIC PERFORMANCE
Resolution1
—
—
—
—
—
—
10
1
—
2
Bits
LSBs
LSBs
%
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL) 2
Channel-to-channel gain matching2
Full scale output voltage2
—
0.6
2
1
—
—
Rset = 1.05 kΩ ±1%
1.24
1.306
1.37
V
Rload = 37.5 Ω ±1%
DAC DYNAMIC PERFORMANCE
Spurious Free Dynamic Range (SFDR)
Fout = 3.38 MHz
Fsamp = 216 MHz
—
—
59
54
—
—
dBc
dBc
Spurious Free Dynamic Range (SFDR)
Fout = 9.28 MHz
Fsamp = 297 MHz
VIDEO PERFORMANCE IN SD MODE2
Short Term Jitter (Line to Line)
Long Term Jitter (Field to Field)
Frequency Response
—
—
—
2.5
3.5
—
—
—
0.1
0
ns
—
ns
0-4.0 MHz
–0.1
–0.7
—
dB
5.75 MHz
—
dB
Luminance Nonlinearity
Differential Gain
—
0.5
0.35
0.6
75
—
—
—
—
—
—
—
—
—
—
—
—
%
—
—
%
Degrees
dB
Differential Phase
—
—
Signal-to-Noise Ratio (SNR)
Hue Accuracy
Flat field full bandwidth
—
—
—
—
—
—
—
—
—
—
0.8
1.5
–70
–47
0.5
2.5
0.1
1.0
Degrees
%
Color Saturation Accuracy
Chroma AM Noise
—
—
dB
Chroma PM Noise
—
dB
Chroma Nonlinear Phase
Chroma Nonlinear Gain
Chroma/Luma Intermodulation
Chroma/Luma Gain Inequality
—
Degrees
%
—
—
%
—
%
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Table 62. TV Encoder Video Performance Specifications (continued)
Parameter
Conditions
Min
Typ
Max
Unit
Chroma/Luma Delay Inequality
VIDEO PERFORMANCE IN HD MODE2
Luma Frequency Response
—
—
1.0
—
ns
0-30 MHz
0-15 MHz,
–0.2
–0.2
—
—
0.2
0.2
dB
dB
Chroma Frequency Response
YCbCr 422 mode
Luma Nonlinearity
—
—
—
—
—
3.2
3.4
62
—
—
—
—
%
%
Chroma Nonlinearity
—
Luma Signal-to-Noise Ratio
Chroma Signal-to-Noise Ratio
0-30 MHz
0-15 MHz
dB
dB
72
1
Guaranteed by design.
2
Guaranteed by characterization.
4.7.8.8
Asynchronous Interfaces
The following sections describes the types of asynchronous interfaces.
4.7.8.8.1 Standard Parallel Interfaces
The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s
internal control levels (0 or 1) by UP and DOWN that are defined in registers. Each asynchronous pin has
a dynamic connection with one of the signal generators. This connection is redefined again with a new
display access (pixel/component). The IPU can generate control signals according to system 80/68
requirements. The burst length is received as a result from predefined behavior of the internal signal
generator machines.
The access to a display is realized by the following:
•
•
•
•
CS (IPP_CS) chip select
WR (IPP_PIN_11) write strobe
RD (IPP_PIN_12) read strobe
RS (IPP_PIN_13) Register select (A0)
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 52,
Figure 53, Figure 54, and Figure 55. The timing images correspond to active-low IPP_CS, WR and RD
signals.
Each asynchronous access is defined by an access size parameter. This parameter can be different between
different kinds of accesses. This parameter defines a length of windows, when suitable controls of the
current access are valid. A pause between two different display accesses can be guaranteed by programing
suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control
signal can be switched at any time during access size.
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IPP_CS
RS
WR
RD
IPP_DATA
Burst access mode with sampling by CS signal
IPP_CS
RS
WR
RD
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
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IPP_CS
RS
WR
RD
IPP_DATA
Burst access mode with sampling by WR/RD signals
IPP_CS
RS
WR
RD
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
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IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Burst access mode with sampling by CS signal
IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
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IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Burst access mode with sampling by ENABLE signal
IPP_CS
RS
WR
(READ/WRITE)
RD
(ENABLE)
IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 55. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram
Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT
signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until
IPP_WAIT release. Figure 56 shows timing of the parallel interface with IPP_WAIT control.
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DI clock
IPP_CS
IPP_DATA
WR
RD
IPP_WAIT
IPP_DATA_IN
waiting
IP39
waiting
Figure 56. Parallel Interface Timing Diagram—Read Wait States
4.7.8.8.2
Asynchronous Parallel Interface Timing Parameters
Figure 57 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k
interfaces. Table 64 shows timing characteristics at display access level. All timing diagrams are based
on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register).
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IP29 IP32
IP35
IP33
IP30
IP36
IP47
IP31
IP34
DI clock
IPP_CS
RS
WR
RD
IPP_DATA
A0
D0
D1
D2
D3
PP_DATA_IN
IP28a
IP27
IP28d
IP37
IP38
Figure 57. Asynchronous Parallel Interface Timing Diagram
Table 63. Asynchronous Display Interface Timing Parameters (Pixel Level)
ID
Parameter
Symbol
Value
Description
Unit
IP28a Address Write system cycle time Tcycwa
ACCESS_SIZE_#
ACCESS_SIZE_#
UP#
predefined value in DI REGISTER
predefined value in DI REGISTER
ns
ns
ns
IP28d Data Write system cycle time
Tcycwd
Tdcsrr
IP29
IP30
IP31
IP32
RS start
CS start
CS hold
RS hold
RS strobe switch, predefined value
in DI REGISTER
Tdcsc
Tdchc
Tdchrr
UP#
CS strobe switch, predefined value
in DI REGISTER
ns
—
—
DOWN#
DOWN#
CS strobe release, predefined
value in DI REGISTER
RS strobe release, predefined
value in DI REGISTER
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Table 63. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued)
ID
Parameter
Symbol
Value
Description
Unit
IP35
Write start
Tdcsw
UP#
write strobe switch, predefined
value in DI REGISTER
ns
IP36
Controls hold time for write
Tdchw
DOWN#
write strobe release, predefined
value in DI REGISTER
ns
Table 64. Asynchronous Parallel Interface Timing Parameters (Access Level)
ID
Parameter
Symbol
Min
Typ1
Tdicpw2
Max
Tdicpw+1.24
Unit
IP28 Write system cycle time Tcycw
Tdicpw – 1.24
Tdicurs – 1.24
Tdicucs – 1.24
ns
ns
ns
ns
IP29 RS start
IP30 CS start
IP31 CS hold
Tdcsrr
Tdcsc
Tdchc
Tdicurs
Tdicur
Tdicurs+1.24
Tdicucs+1.24
Tdicdcs – Tdicucs – 1.2 Tdicdcs3–Tdicucs4 Tdicdcs – Tdicucs+1.24
4
IP32 RS hold
Tdchrr Tdicdrs – Tdicurs – 1.24 Tdicdrs5–Tdicurs6 Tdicdrs – Tdicurs+1.24
ns
ns
IP35 Controls setup time for
write
Tdcsw Tdicuw – 1.24
Tdicuw
Tdicuw+1.24
IP36 Controls hold time for
write
Tdchw Tdicdw – Tdicuw – 1.24 Tdicpw7–Tdicuw8
Tdicdw–Tdicuw+1.24
Tdicpr – Tdicdr – 1.24
ns
ns
IP38 Slave device data hold
time8
Troh
Tdrp – Tlbd – Tdicdr+1.
24
—
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
2Display period value for write
DI_ACCESS_SIZE_#
-----------------------------------------------------
DI_CLK_PERIOD
Tdicpw = T
DI_CLK × ceil
ACCESS_SIZE is predefined in REGISTER.
3Display control down for CS
2 × DISP_DOWN_#
1
2
⎛
⎞
⎠
--------------------------------------------------
DI_CLK_PERIOD
Tdicdcs = -- T
× ceil
× ceil
× ceil
DI_CLK
⎝
DISP_DOWN is predefined in REGISTER.
4Display control up for CS
2 × DISP_UP_#
1
2
⎛
⎞
⎠
---------------------------------------------
Tdicucs = -- T
⎝ DI_CLK
DI_CLK_PERIOD
DISP_UP is predefined in REGISTER.
5Display control down for RS
2 × DISP_DOWN_#
1
2
⎛
⎞
⎠
--------------------------------------------------
Tdicdrs = -- T
⎝ DI_CLK
DI_CLK_PERIOD
DISP_DOWN is predefined in REGISTER.
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6Display control up for RS
2 × DISP_UP_#
1
2
⎛
⎞
⎠
---------------------------------------------
Tdicurs = -- T
⎝ DI_CLK
× ceil
× ceil
× ceil
DI_CLK_PERIOD
DISP_UP is predefined in REGISTER.
7Display control down for read
2 × DISP_DOWN_#
1
2
⎛
⎞
⎠
--------------------------------------------------
Tdicdrw = -- T
⎝ DI_CLK
DI_CLK_PERIOD
DISP_DOWN is predefined in REGISTER.
8Display control up for write
2 × DISP_UP_#
1
2
⎛
⎞
---------------------------------------------
Tdicuw = -- T
⎝ DI_CLK
⎠
DI_CLK_PERIOD
DISP_UP is predefined in REGISTER.
4.7.9
LVDS Display Bridge (LDB) Module Parameters
The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD
644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.
4.7.10 MediaLB (MLB) Controller AC Timing Electrical Specifications
This section describes the timing electrical information of the MediaLB Controller module.
Figure 58 and Figure 59 show the timing of MediaLB Controller, and Table 65 and Table 66 lists the
MediaLB controller timing characteristics.
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Figure 58. MediaLB Timing
Figure 59. MediaLB Pulse Width Variation Timing
Ground = 0.0 V; Load Capacitance = 60 pF; MediaLB speed = 256/512 Fs; Fs = 48 kHz; all timing
parameters specified from the valid voltage threshold as listed below; unless otherwise noted.
Table 65. MLB 256/512 Fs Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLBCLK operating frequency1
fmck
11.264
MHz
Min: 256*fs at 44.0 kHz
Typ: 256*fs at 48.0 kHz
Typ: 512*fs at 48.0 kHz
Max: 512*fs at 48.1 kHz
Max: 512*fs PLL unlocked
12.288
24.576
24.6272
25.600
MLBCLK rise time
MLB fall time
tmckr
tmckf
tmckc
—
—
—
—
3
3
ns
ns
ns
VIL TO VIH
VIH TO VIL
MLBCLK cycle time
—
—
81
40
—
—
256*Fs
512*Fs
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Table 65. MLB 256/512 Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLBCLK low time
tmckl
31.5
30
37
35.5
—
—
ns
256*Fs
256*Fs PLL unlocked
14.5
14
17
16.5
—
—
ns
ns
ns
512*Fs
512*Fs PLL unlocked
MLBCLK high time
tmckh
31.5
30
38
36.5
—
—
256*Fs
256*Fs PLL unlocked
14.5
14
17
16.5
—
—
512*Fs
512*Fs PLL unlocked
MLBCLK pulse width variation
tmpwv
tdsmcf
—
1
—
—
2
ns pp
ns
Note2
—
MLBSIG/MLBDAT input valid to
MLBCLK falling
—
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
tmcfdz
tmdzh
0
0
4
—
—
—
—
tmckl
—
ns
ns
ns
—
—
MLBSIG/MLBDAT output high
impedance from MLBCLK low
Bus Hold Time
Note3
1
The MLB controller can shut off MLBCLK to place MediaLB in a low-power state.
2
3
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp)
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Ground = 0.0 V; load capacitance = 40 pF; MediaLB speed = 1024 Fs; Fs = 48 kHz; all timing parameters
specified from the valid voltage threshold as listed in Table 66; unless otherwise noted.
Table 66. MLB Device 1024 Fs Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLBCLK Operating
Frequency1
fmck
45.056
MHz
Min: 1024*fs at 44.0 kHz
Typ: 1024*fs at 48.0 kHz
Max: 1024fs*fs at 48.1 kHz
Max: 1024*fs PLL unlocked
49.152
49.2544
51.200
MLBCLK rise time
MLB fall time
tmckr
tmckf
tmckc
tmckl
—
—
—
—
—
1
1
ns
ns
ns
ns
VIL TO VIH
VIH TO VIL
—
MLBCLK cycle time
MLBCLK low time
20.3
—
—
6.5
6.1
7.7
7.3
PLL unlocked
MLBCLK high time
tmckh
9.7
9.3
10.6
10.2
—
—
ns
PLL unlocked
Note2
MLBCLK pulse width variation
tmpwv
—
—
0.7
ns pp
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Table 66. MLB Device 1024 Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
Max
Units
Comment
MLBSIG/MLBDAT input valid
to MLBCLK falling
tdsmcf
1
—
—
ns
—
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
tmcfdz
tmdzh
0
0
2
—
—
—
—
tmckl
—
ns
ns
ns
—
—
MLBSIG/MLBDAT output high
impedance from MLBCLK low
Bus Hold Time
Note3
1
2
The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (pp).
3
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
4.7.11 One-Wire (OWIRE) Timing Parameters
Figure 60 depicts the RPP timing, and Table 67 lists the RPP timing parameters.
One-WIRE Tx
“Reset Pulse”
One Wire Device Tx
“Presence Pulse”
OW2
OW3
One-Wire bus
(BATT_LINE)
OW1
OW4
tR
Figure 60. Reset and Presence Pulses (RPP) Timing Diagram
Table 67. RPP Sequence Delay Comparisons Timing Parameters
ID
Parameters
Reset Time Low
Symbol
Min
Typ
Max
Unit
1
OW1
tRSTL
tPDH
tPDL
480
15
511
—
—
µs
µs
µs
µs
OW2
OW3
OW4
Presence Detect High
Presence Detect Low
60
240
—
60
—
Reset Time High
tRSTH
480
512
(includes recovery time)
1
In order not to mask signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 µs.
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Figure 61 depicts Write 0 Sequence timing, and Table 68 lists the timing parameters.
OW6
tREC
One-Wire bus
(BATT_LINE)
OW5
Figure 61. Write 0 Sequence Timing Diagram
Table 68. WR0 Sequence Timing Parameters
ID
Parameter
Write 0 Low Time
Symbol
Min
Typ
Max
Unit
OW5
OW6
tLOW0
tSLOT
tREC
60
OW5
1
100
117
—
120
120
—
µs
µs
µs
Transmission Time Slot
Recovery time
Figure 62 depicts Write 1 Sequence timing, Figure 63 depicts the Read Sequence timing, and Table 69
lists the timing parameters.
OW8
One-Wire bus
(BATT_LINE)
OW7
Figure 62. Write 1 Sequence Timing Diagram
OW8
One-Wire bus
(BATT_LINE)
tSU
OW11
OW9
OW10
Figure 63. Read Sequence Timing Diagram
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Table 69. WR1 /RD Timing Parameters
ID
Parameter
Write 1 Low Time
Symbol
Min
Typ
Max
Unit
OW7
OW8
tLOW1
tSLOT
1
60
—
1
5
117
—
5
15
120
1
µs
µs
µs
µs
µs
µs
Transmission Time Slot
Read Data Setup
Read Low Time
Read Data Valid
Release Time
tSU
OW9
OW10
OW11
tLOWR
tRDV
15
—
—
0
15
—
tRELEASE
45
4.7.12 Pulse Width Modulator (PWM) Timing Parameters
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 64 depicts the timing of the PWM, and Table 70 lists the PWM timing parameters.
1
2a
3b
System Clock
2b
4b
3a
4a
PWM Output
Figure 64. PWM Timing
Table 70. PWM Output Timing Parameter
Ref. No.
Parameter
System CLK frequency1
Min
Max
Unit
1
0
12.29
9.91
—
ipg_clk
—
MHz
ns
2a
2b
3a
3b
4a
4b
Clock high time
Clock low time
Clock fall time
—
ns
0.5
ns
Clock rise time
Output delay time
Output setup time
—
0.5
ns
—
9.37
—
ns
8.71
ns
1
CL of PWMO = 30 pF
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4.7.13 PATA Timing Parameters
This section describes the timing parameters of the Parallel ATA module which are compliant with
ATA/ATAPI-6 specification.
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA
module interface consist of a total of 29 pins. Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.
Table 71 and Figure 65 define the AC characteristics of all the PATA interface signals in all data transfer
modes.
ATA Interface Signals
SI2
SI1
Figure 65. PATA Interface Signals Timing Diagram
Table 71. AC Characteristics of All Interface Signals
ID
Parameter
Symbol
Min
Max
Unit
SI1
SI2
SI3
Rising edge slew rate for any signal on ATA interface1
Falling edge slew rate for any signal on ATA interface1
Host interface signal capacitance at the host connector
Srise
Sfall
—
—
—
1.25
1.25
20
V/ns
V/ns
pF
Chost
1
SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal
amplitude with all capacitive loads from 15–40 pF where all signals have the same capacitive load value.
The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53xA PATA
interface is 3.3 V compatible.
The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it
difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode
operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
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In the timing equations, some timing parameters are used. These parameters depend on the
implementation of the i.MX53xA PATA interface on silicon, the bus buffer used, the cable delay and
cable skew. Table 72 shows ATA timing parameters.
Table 72. PATA Timing Parameters
Value/
Name
Description
Bus clock period (AHB_CLK_ROOT)
Contributing Factor1
T
Peripheral clock frequency
(7.5 ns for 133 MHz clock)
ti_ds
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
15 ns
10 ns
7 ns
5 ns
UDMA5
4 ns
ti_dh
tco
Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
Propagation delay bus clock L-to-H to
12.0 ns
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
tsu
tsui
Set-up time ata_data to bus clock L-to-H
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
8.5 ns
8.5 ns
2.5 ns
7 ns
thi
tskew1
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
tskew2
tskew3
Max difference in buffer propagation delay for any of following signals:
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
Transceiver
Transceiver
Max difference in buffer propagation delay for any of following signals ata_iordy,
ata_data (read)
tbuf
Max buffer propagation delay
Transceiver
Cable
tcable1
tcable2
Cable propagation delay for ata_data
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,
ata_dmack
Cable
tskew4
tskew5
Max difference in cable propagation delay between ata_iordy and ata_data (read)
Cable
Cable
Max difference in cable propagation delay between (ata_dior, ata_diow,
ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
tskew6
Max difference in cable propagation delay without accounting for ground bounce
Cable
1
Values provided where applicable.
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4.7.13.1 PIO Mode Read Timing
Figure 66 shows timing for PIO read. Table 73 lists the timing parameters for PIO read.
Figure 66. PIO Read Timing Diagram
Table 73. PIO Read Timing Parameters
ATA
Parameter
Controlling
Variable
Value
Parameter from Figure 66
t1
t2 (read)
t9
t1
t2r
t9
t1(min) = time_1 * T – (tskew1 + tskew2 + tskew5)
t2(min) = time_2r * T – (tskew1 + tskew2 + tskew5)
t9(min) = time_9 * T – (tskew1 + tskew2 + tskew6)
t5(min) = tco + tsu + tbuf + tbuf+ tcable1 + tcable2
time_1
time_2r
time_9
t5
t5
time_2 (affects tsu and
tco)
t6
tA
trd
t6
tA
0
—
tA(min) = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)
time_ax
trd1
trd1(max) = (–trd)+ (tskew3 + tskew4)
time_pio_rdx
trd1(min) = (time_pio_rdx – 0.5)*T – (tsu + thi)
(time_pio_rdx – 0.5) * T > tsu + thi + tskew3 + tskew4
t0
—
t0(min) = (time_1 + time_2r+ time_9) * T
time_1, time_2r, time_9
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Figure 67 shows timing for PIO write. Table 74 lists the timing parameters for PIO write.
Figure 67. Multi-word DMA (MDMA) Timing
Table 74. PIO Write Timing Parameters
ATA
Paramete
r
Parameter
from Figure 67
Controlling
Variable
Value
t1
t2 (write)
t9
t1
t2w
t9
t1(min) = time_1 * T – (tskew1 + tskew2 + tskew5)
t2(min) = time_2w * T – (tskew1 + tskew2 + tskew5)
t9(min) = time_9 * T – (tskew1 + tskew2 + tskew6)
t3(min) = (time_2w – time_on)* T – (tskew1 + tskew2 +tskew5)
time_1
time_2w
time_9
t3
—
If not met, increase
time_2w
t4
tA
t0
t4
tA
—
t4(min) = time_4 * T – tskew1
time_4
tA = (1.5 + time_ax) * T – (tco + tsui + tcable2 + tcable2 + 2*tbuf)
t0(min) = (time_1 + time_2 + time_9) * T
time_ax
time_1, time_2r,
time_9
—
—
—
—
Avoid bus contention when switching buffer on by making ton long enough
Avoid bus contention when switching buffer off by making toff long enough
—
—
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Figure 68 shows timing for MDMA read, Figure 69 shows timing for MDMA write, and Table 75 lists
the timing parameters for MDMA read and write.
Figure 68. MDMA Read Timing Diagram
Figure 69. MDMA Write Timing Diagram
Table 75. MDMA Read and Write Timing Parameters
Parameter from
ATA
Parameter
Controlling
Variable
Figure 68 (Read),
Figure 69 (Write)
Value
tm, ti
tm
td, td1
tk1
tm(min) = ti(min) = time_m * T – (tskew1 + tskew2 + tskew5)
td1(min) = td(min) = time_d * T – (tskew1 + tskew2 + tskew6)
tk(min) = time_k * T – (tskew1 + tskew2 + tskew6)
t0(min) = (time_d + time_k) * T
time_m
time_d
td
tk
time_k
t0
—
time_d, time_k
time_d
tg(read)
tgr
tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2
tgr(min-drive) = td – te(drive)
tf(read)
tg(write)
tf(write)
tL
tfr
—
—
—
tfr(min) = 5 ns
—
tg(min-write) = time_d * T – (tskew1 + tskew2 + tskew5)
tf(min-write) = time_k * T – (tskew1 + tskew2 + tskew6)
tL (max) = (time_d + time_k – 2)×T – (tsu + tco + 2×tbuf + 2×tcable2)
time_d
time_k
time_d,
time_k2
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Table 75. MDMA Read and Write Timing Parameters (continued)
Parameter from
Figure 68 (Read),
Figure 69 (Write)
ATA
Parameter
Controlling
Variable
Value
tn, tj
—
tkjn
tn= tj= tkjn = time_jn * T – (tskew1 + tskew2 + tskew6)
time_jn
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
1
2
tk1 in the MDMA figures (Figure 68 and Figure 69) equals (tk – 2*T).
tk1 in the MDMA figures equals (tk – 2*T).
4.7.13.2 Ultra DMA (UDMA) Input Timing
Figure 70 shows timing when the UDMA in transfer starts, Figure 71 shows timing when the UDMA in
host terminates transfer, Figure 72 shows timing when the UDMA in device terminates transfer, and
Table 76 lists the timing parameters for UDMA in burst.
Figure 70. UDMA in Transfer Starts Timing Diagram
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Figure 71. UDMA in Host Terminates Transfer Timing Diagram
Figure 72. UDMA in Device Terminates Transfer Timing Diagram
Table 76. UDMA in Burst Timing Parameters
Parameter
from
ATA
Parameter
Figure 70,
Figure 71,
Figure 72
Description
Controlling Variable
tack
tenv
tack
tenv
tack (min) = (time_ack × T) – (tskew1 + tskew2)
time_ack
time_env
tenv (min) = (time_env × T) – (tskew1 + tskew2)
tenv (max) = (time_env × T) + (tskew1 + tskew2)
tds
tdh
tds1
tdh1
tds – (tskew3) – ti_ds > 0
tskew3, ti_ds, ti_dh
should be low enough
tdh – (tskew3) – ti_dh > 0
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Controlling Variable
Table 76. UDMA in Burst Timing Parameters (continued)
Parameter
from
ATA
Parameter
Figure 70,
Figure 71,
Figure 72
Description
tcyc
trp
tc1
trp
(tcyc – tskew) > T
T big enough
time_rp
trp (min) = time_rp × T – (tskew1 + tskew2 + tskew6)
(time_rp × T) – (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive)
tmli1 (min) = (time_mlix + 0.4) × T
—
tx11
tmli1
tzah
tdzfs
tcvh
time_rp
tmli
tzah
tdzfs
tcvh
—
time_mlix
time_zah
time_dzfs
time_cvh
—
tzah (min) = (time_zah + 0.4) × T
tdzfs = (time_dzfs × T) – (tskew1 + tskew2)
tcvh = (time_cvh ×T) – (tskew1 + tskew2)
ton
ton = time_on × T – tskew1
toff = time_off × T – tskew1
toff2
1
2
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
Make ton and toff big enough to avoid bus contention.
4.7.13.3 UDMA Output Timing
Figure 73 shows timing when the UDMA out transfer starts, Figure 74 shows timing when the UDMA out
host terminates transfer, Figure 75 shows timing when the UDMA out device terminates transfer, and
Table 77 lists the timing parameters for UDMA out burst.
Figure 73. UDMA Out Transfer Starts Timing Diagram
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Figure 74. UDMA Out Host Terminates Transfer Timing Diagram
Figure 75. UDMA Out Device Terminates Transfer Timing Diagram
Table 77. UDMA Out Burst Timing Parameters
Parameter
from
Figure 73,
Figure 74,
Figure 75
ATA
Parameter
Controlling
Variable
Value
tack
tenv
tack
tenv
tack (min) = (time_ack × T) – (tskew1 + tskew2)
time_ack
time_env
tenv (min) = (time_env × T) – (tskew1 + tskew2)
tenv (max) = (time_env × T) + (tskew1 + tskew2)
tdvs
tdvh
tcyc
tdvs
tdvh
tcyc
—
tdvs = (time_dvs × T) – (tskew1 + tskew2)
tdvs = (time_dvh × T) – (tskew1 + tskew2)
tcyc = time_cyc × T – (tskew1 + tskew2)
t2cyc = time_cyc × 2 × T
time_dvs
time_dvh
time_cyc
time_cyc
t2cyc
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Table 77. UDMA Out Burst Timing Parameters (continued)
Parameter
from
ATA
Parameter
Controlling
Variable
Figure 73,
Figure 74,
Figure 75
Value
trfs1
—
trfs
tdzfs
tss
trfs = 1.6 × T + tsui + tco + tbuf + tbuf
—
time_dzfs
time_ss
—
tdzfs = time_dzfs × T – (tskew1)
tss
tmli
tli
tss = time_ss × T – (tskew1 + tskew2)
tdzfs_mli
tli1
tdzfs_mli =max (time_dzfs, time_mli) × T – (tskew1 + tskew2)
tli1 > 0
—
tli
tli2
tli2 > 0
—
tli
tli3
tli3 > 0
—
tcvh
—
tcvh
tcvh = (time_cvh ×T) – (tskew1 + tskew2)
time_cvh
—
ton
toff
ton = time_on × T – tskew1
toff = time_off × T – tskew1
4.7.14 SATA PHY Parameters
This section describes SATA PHY electrical specifications.
4.7.14.1 Reference Clock Electrical and Jitter Specifications
The refclk signal is differential and supports frequencies of 25 MHz or 50-156.25 MHz (100 MHz and
125 MHz are common frequencies). The frequency is pin-selectable (for more information about the
signal, see “Per-Transceiver Control and Status Signals” in the SATA PHY chapter in the Reference
Manual).
Table 78 provides the SATA PHY reference clock specifications.
Table 78. Reference Clock Specifications
Parameters
Test Conditions
Min
Max
Unit
mV
Differential peak voltage (typically 0.71 V)
—
—
350
850
Common mode voltage
(refclk_p + refclk_m) / 2
175
2,000
mV
Total phase jitter
For information about total
phase jitter, see following
section
—
3
ps RMS
Minimum/maximum duty cycle
Frequency range
—
—
40
25
60
% UI
MHz
156.25
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4.7.14.1.1 Reference Clock Jitter Measurement
The total phase jitter on the reference clock is specified at 3 ps RMS. There are numerous ways to measure
the reference clock jitter, one of which is as follows.
Using a high-speed sampling scope (20 GSamples/s), 1 million samples of the differential reference clock
are taken, and the zero-crossing times of each rising edge are calculated. From the zero-crossing data, an
average reference clock period is calculated. This average reference clock period is subtracted from each
sequential, instantaneous period to find the difference between each reference clock rising edge and the
ideal placement to produce the phase jitter sequence. The power spectral density (PSD) of the phase jitter
is calculated and integrated after being weighted with the transfer function shown in Figure 76. The square
root of the resultant integral is the RMS total phase jitter.
Figure 76. Weighting Function for RMS Phase Jitter Calculation
4.7.14.2 Transmitter and Receiver Characteristics
The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA
specification. The following subsections provide values obtained from a combination of simulations and
silicon characterization.
NOTE
The tables in the following sections indicate any exceptions to the SATA
specification or aspects of the SATA PHY that exceed the standard, as well
as provide information about parameters not defined in the standard.
4.7.14.2.1 SATA PHY Transmitter Characteristics
Table 79 provides specifications for SATA PHY transmitter characteristics.
Table 79. SATA2 PHY Transmitter Characteristics
Parameters
Symbol
Min
Typ
Max
Unit
V
Transmit common mode voltage
VCTM
—
0.4
—
0.6
Transmitter pre-emphasis accuracy (measured
change in de-emphasized bit)
–0.5
—
0.5
dB
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4.7.14.2.2 SATA PHY Receiver Characteristics
Table 80 provides specifications for SATA PHY receiver characteristics.
Table 80. SATA PHY Receiver Characteristics
Parameters
Symbol
Min
Typ
Max
Unit
Minimum Rx eye height (differential peak-to-peak) VMIN_RX_EYE_HEIGHT
Tolerance PPM
—
—
—
175
400
mV
–400
ppm
4.7.14.3 SATA_REXT Reference Resistor Connection
The impedance calibration process requires connection of reference resistor 191 Ω. 1% precision resistor
on SATA_REXT pad to ground.
Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an
internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT
pin. The calibration register value is then supplied to all Tx and Rx termination resistors.
During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the
external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor.
4.7.14.4 SATA Connectivity When Not in Use
NOTE
The Temperature Sensor is part of the SATA module. If SATA IP is disabled,
the Temperature Sensor will not work as well. Temperature Sensor
functionality is important in supporting high performance applications
without overheating the device (at high ambient temp).
When both SATA and thermal sensor are not required, connect VP and VPH supplies to ground. The rest
of the ports, both inputs and outputs (SATA_REFCLKM, SATA_REFCLKP, SATA_REXT, SATA_RXM,
SATA_RXP, SATA_TXM) can be left floating. It is not recommended to turn off the VPH while the VP is
active.
When SATA is not in use but thermal sensor is still required, both VP and VPH supplies must be powered
on according to their nominal voltage levels. The reference clock input frequency must fall within the
specified range of 25 MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the
termination impedance is not of consequence.
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4.7.15 SCAN JTAG Controller (SJC) Timing Parameters
Figure 77 depicts the SJC test clock input timing. Figure 78 depicts the SJC boundary scan timing.
Figure 79 depicts the SJC test access port. Signal parameters are listed in Table 81.
SJ1
SJ2
VM
SJ2
VM
TCK
(Input)
VIH
VIL
SJ3
SJ3
Figure 77. Test Clock Input Timing Diagram
TCK
(Input)
VIH
SJ5
Input Data Valid
VIL
SJ4
Data
Inputs
SJ6
Data
Outputs
Output Data Valid
SJ7
SJ6
Data
Outputs
Data
Outputs
Output Data Valid
Figure 78. Boundary Scan (JTAG) Timing Diagram
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TCK
(Input)
VIH
VIL
SJ8
Input Data Valid
SJ9
TDI
TMS
(Input)
SJ10
SJ11
SJ10
TDO
Output Data Valid
(Output)
TDO
(Output)
TDO
(Output)
Output Data Valid
Figure 79. Test Access Port Timing Diagram
TCK
(Input)
SJ13
TRST
(Input)
SJ12
Figure 80. TRST Timing Diagram
Table 81. JTAG Timing
All Frequencies
ID
Parameter1,2
Unit
Min
Max
1
SJ0
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
SJ8
TCK frequency of operation 1/(3•TDC
)
0.001
45
22.5
—
22
—
—
3
MHz
ns
TCK cycle time in crystal mode
2
TCK clock pulse width measured at VM
TCK rise and fall times
ns
ns
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
5
—
—
40
40
—
ns
24
—
ns
ns
TCK low to output high impedance
TMS, TDI data set-up time
—
ns
5
ns
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Table 81. JTAG Timing (continued)
Parameter1,2
All Frequencies
ID
Unit
Min
Max
SJ9
TMS, TDI data hold time
25
—
—
44
44
—
—
ns
ns
ns
ns
ns
SJ10 TCK low to TDO data valid
SJ11 TCK low to TDO high impedance
SJ12 TRST assert time
—
100
40
SJ13 TRST set-up time to TCK low
1
2
T
= target frequency of SJC
DC
VM = mid-point voltage
4.7.16 SPDIF Timing Parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 82 and Figures , show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format
(SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing
of the modulating Tx clock (STCLK) for SPDIF in Tx mode.
Table 82. SPDIF Timing Parameters
Timing Parameter Range
Characteristics
Symbol
Units
Min
Max
SPDIFIN Skew: asynchronous inputs, no specs apply
SPDIFOUT output (Load = 50pf)
—
—
0.7
ns
ns
—
—
—
—
—
—
1.5
24.2
31.3
• Skew
• Transition rising
• Transition falling
SPDIFOUT1 output (Load = 30pf)
—
—
—
ns
• Skew
• Transition rising
• Transition falling
—
—
—
1.5
13.6
18.0
Modulating Rx clock (SRCK) period
SRCK high period
srckp
srckph
srckpl
stclkp
stclkph
stclkpl
40.0
16.0
16.0
40.0
16.0
16.0
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
SRCK low period
Modulating Tx clock (STCLK) period
STCLK high period
STCLK low period
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srckp
srckpl
VM
srckph
VM
SRCK
(Output)
Figure 81. SPDIF Timing Diagram
stclkp
stclkpl
VM
stclkph
VM
STCLK
(Input)
Figure 82. STCLK Timing
4.7.17 SSI Timing Parameters
This section describes the timing parameters of the SSI module. The connectivity of the serial
synchronous interfaces are summarized in Table 83.
Table 83. AUDMUX Port Allocation
Port
Signal Nomenclature
Type and Access
AUDMUX port 1
AUDMUX port 2
AUDMUX port 3
AUDMUX port 4
AUDMUX port 5
AUDMUX port 6
AUDMUX port 7
SSI 1
SSI 2
AUD3
AUD4
AUD5
AUD6
SSI 3
Internal
Internal
External – AUD3 I/O
External – EIM or CSPI1 I/O through IOMUXC
External – EIM or SD1 I/O through IOMUXC
External – EIM or DISP2 through IOMUXC
Internal
NOTE
•
•
The terms WL and BL used in the timing diagrams and tables refer to
Word Length (WL) and Bit Length (BL).
The SSI timing diagrams use generic signal names wherein the names
used in the i.MX53 Reference Manual are channel specific signal
names. For example, a channel clock referenced in the IOMUXC
chapter as AUD3_TXC appears in the timing diagram as TXC.
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4.7.17.1 SSI Transmitter Timing with Internal Clock
Figure 83 depicts the SSI transmitter internal clock timing and Table 84 lists the timing parameters for the
SSI transmitter internal clock.
.
SS1
SS5
SS4
SS3
SS2
TXC
SS8
SS6
TXFS (bl)
(Output)
SS10
SS12
SS14
SS17
TXFS (wl)
(Output)
SS15
SS16
SS18
TXD
(Output)
SS43
SS42
SS19
RXD
(Input)
Note: SRXD input in synchronous mode only
: SRXD input in synchronous mode only
Figure 83. SSI Transmitter Internal Clock Timing Diagram
Table 84. SSI Transmitter Timing with Internal Clock
ID
Parameter
Internal Clock Operation
Min
Max
Unit
SS1
SS2
(Tx/Rx) CK clock period
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Tx) CK high to FS (bl) high
(Tx) CK high to FS (bl) low
(Tx) CK high to FS (wl) high
(Tx) CK high to FS (wl) low
(Tx/Rx) Internal FS rise time
(Tx/Rx) Internal FS fall time
SS3
6.0
SS4
36.0
—
—
SS5
6.0
SS6
—
15.0
15.0
15.0
15.0
6.0
SS8
—
SS10
SS12
SS14
SS15
SS16
—
—
—
—
6.0
(Tx) CK high to STXD valid from high impedance
—
15.0
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Table 84. SSI Transmitter Timing with Internal Clock (continued)
ID
Parameter
(Tx) CK high to STXD high/low
Min
Max
Unit
SS17
SS18
SS19
—
—
—
15.0
15.0
6.0
ns
ns
ns
(Tx) CK high to STXD high impedance
STXD rise/fall time
Synchronous Internal Clock Operation
SS42
SS43
SS52
SRXD setup before (Tx) CK falling
SRXD hold after (Tx) CK falling
Loading
10.0
0.0
—
—
—
ns
ns
pF
25.0
NOTE
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
•
All timings are on Audiomux Pads when SSI is being used for data
transfer.
•
•
•
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
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Electrical Characteristics
4.7.17.2 SSI Receiver Timing with Internal Clock
Figure 84 depicts the SSI receiver internal clock timing and Table 85 lists the timing parameters for the
receiver timing with the internal clock
SS1
SS3
SS5
SS4
SS2
TXC
(Output)
SS9
SS7
TXFS (bl)
(Output)
SS11
SS13
TXFS (wl)
(Output)
SS20
SS21
RXD
(Input)
SS51
SS50
SS47
SS49
SS48
RXC
(Output)
Figure 84. SSI Receiver Internal Clock Timing Diagram
Table 85. SSI Receiver Timing with Internal Clock
ID
Parameter
Internal Clock Operation
Min
Max
Unit
SS1
SS2
(Tx/Rx) CK clock period
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
SS3
6.0
—
SS4
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
36.0
—
SS5
6.0
15.0
15.0
15.0
15.0
—
SS7
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
—
SS9
—
SS11
SS13
SS20
SS21
—
—
10.0
0.0
—
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Table 85. SSI Receiver Timing with Internal Clock (continued)
ID
Parameter
Min
Max
Unit
Oversampling Clock Operation
SS47
SS48
SS49
SS50
SS51
Oversampling clock period
15.04
6.0
—
—
—
ns
ns
ns
ns
ns
Oversampling clock high period
Oversampling clock rise time
Oversampling clock low period
Oversampling clock fall time
3.0
—
6.0
—
3.0
NOTE
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
•
All timings are on Audiomux Pads when SSI is being used for data
transfer.
•
•
•
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
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Electrical Characteristics
4.7.17.3 SSI Transmitter Timing with External Clock
Figure 85 depicts the SSI transmitter external clock timing and Table 86 lists the timing parameters for
the transmitter timing with the external clock
SS22
SS23
SS25
SS26
SS24
TXC
(Input)
SS27
SS29
TXFS (bl)
SS33
(Input)
SS31
TXFS (wl)
(Input)
SS39
SS37
SS38
TXD
(Output)
SS45
SS44
RXD
(Input)
SS46
Note: SRXD Input in Synchronous mode only
Figure 85. SSI Transmitter External Clock Timing Diagram
Table 86. SSI Transmitter Timing with External Clock
ID
Parameter
External Clock Operation
Min
Max
Unit
SS22
SS23
SS24
SS25
SS26
SS27
SS29
SS31
SS33
SS37
SS38
(Tx/Rx) CK clock period
81.4
36.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Tx) CK high to FS (bl) high
(Tx) CK high to FS (bl) low
(Tx) CK high to FS (wl) high
(Tx) CK high to FS (wl) low
6.0
—
36.0
—
6.0
15.0
—
–10.0
10.0
–10.0
10.0
—
15.0
—
(Tx) CK high to STXD valid from high impedance
(Tx) CK high to STXD high/low
15.0
15.0
—
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Electrical Characteristics
Table 86. SSI Transmitter Timing with External Clock (continued)
ID
Parameter
Min
Max
Unit
SS39
(Tx) CK high to STXD high impedance
—
15.0
ns
Synchronous External Clock Operation
SS44
SS45
SS46
SRXD setup before (Tx) CK falling
SRXD hold after (Tx) CK falling
SRXD rise/fall time
10.0
2.0
—
—
—
ns
ns
ns
6.0
NOTE
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
•
All timings are on Audiomux Pads when SSI is being used for data
transfer.
•
•
•
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
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Electrical Characteristics
4.7.17.4 SSI Receiver Timing with External Clock
Figure 86 depicts the SSI receiver external clock timing and Table 87 lists the timing parameters for the
receiver timing with the external clock.
SS22
SS26
SS25
SS24
SS23
TXC
SS30
SS28
TXFS (bl)
TXFS (wl)
SS32
SS35
SS34
SS41
SS36
SS40
RXD
(Input)
Figure 86. SSI Receiver External Clock Timing Diagram
Table 87. SSI Receiver Timing with External Clock
ID
Parameter
External Clock Operation
Min
Max
Unit
SS22
SS23
SS24
SS25
SS26
SS28
SS30
SS32
SS34
SS35
SS36
SS40
SS41
(Tx/Rx) CK clock period
81.4
36
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
6.0
—
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
36
—
6.0
15.0
—
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
(Tx/Rx) External FS rise time
(Tx/Rx) External FS fall time
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
–10
10
–10
10
—
15.0
—
6.0
6.0
—
—
10
2
—
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Electrical Characteristics
NOTE
•
•
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
•
•
•
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms WL and BL refer to Word Length (WL) and Bit Length (BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
4.7.18 UART I/O Configuration and Timing Parameters
4.7.18.1 UART RS-232 I/O Configuration in Different Modes
The i.MX53xA UART interfaces can serve both as DTE or DCE device. This can be configured by the
DCEDTE control bit (default 0 – DCE mode). Table 88 shows the UART I/O configuration based on the
enabled mode.
Table 88. UART I/O Configuration vs. Mode
DTE Mode
Description
DCE Mode
Description
Port
Direction
Direction
RTS
CTS
Output
Input
RTS from DTE to DCE
CTS from DCE to DTE
DTR from DTE to DCE
DSR from DCE to DTE
DCD from DCE to DTE
RING from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
Input
Output
Input
RTS from DTE to DCE
CTS from DCE to DTE
DTR from DTE to DCE
DSR from DCE to DTE
DCD from DCE to DTE
RING from DCE to DTE
Serial data from DCE to DTE
Serial data from DTE to DCE
DTR
Output
Input
DSR
Output
Output
Output
Output
Input
DCD
Input
RI
Input
TXD_MUX
RXD_MUX
Input
Output
4.7.18.2 UART RS-232 Serial Mode Timing
The following sections describe the electrical information of the UART module in the RS-232 mode.
4.7.18.2.1
UART Transmitter
Figure 87 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format.
Table 89 lists the UART RS-232 serial mode transmit timing characteristics.
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Electrical Characteristics
Possible
Parity
Bit
UA1
UA1
Bit 3
Next
Start
Bit
Start
TXD
STOP
BIT
Bit 7
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Par Bit
Bit
(output)
UA1
UA1
Figure 87. UART RS-232 Serial Mode Transmit Timing Diagram
Table 89. RS-232 Serial Mode Transmit Timing Parameters
ID
Parameter
Transmit Bit Time
Symbol
Min
Max
Units
1
UA1
tTbit
1/Fbaud_rate
–
1/Fbaud_rate
Tref_clk
+
—
2
Tref_clk
1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
ref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
T
4.7.18.2.2
UART Receiver
Figure 88 depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 90 lists
serial mode receive timing characteristics.
Possible
UA2
Parity
Bit
UA2
Bit 3
Next
Start
Bit
Start
Bit
RXD
(input)
STOP
BIT
Bit 7
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Bit 6
Par Bit
UA2
UA2
Figure 88. UART RS-232 Serial Mode Receive Timing Diagram
Table 90. RS-232 Serial Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Units
Receive Bit Time1
tRbit
1/Fbaud_rate
–
1/Fbaud_rate +
—
2
UA2
1/(16*Fbaud_rate
)
1/(16*Fbaud_rate)
1
2
The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16*Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
4.7.18.3 UART IrDA Mode Timing
The following subsections give the UART transmit and receive timings in IrDA mode.
4.7.18.3.3
UART IrDA Mode Transmitter
Figure 89 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 91 lists
the transmit timing characteristics.
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Electrical Characteristics
UA4
Bit 5
UA3
UA3
UA3
UA3
TXD
(output)
Start
Bit
STOP
BIT
Bit 0
Bit 1
Possible
Parity
Bit
Bit 2
Bit 3
Bit 4
Bit 6
Bit 7
Figure 89. UART IrDA Mode Transmit Timing Diagram
Table 91. IrDA Mode Transmit Timing Parameters
ID
Parameter
Symbol
Min
Max
1/Fbaud_rate + T
Units
1
UA3
Transmit Bit Time in IrDA mode
tTIRbit
1/Fbaud_rate
–
—
ref_clk
2
T
ref_clk
UA4
Transmit IR Pulse Duration
tTIRpulse
(3/16)*(1/Fbaud_rate
– T
)
(3/16)*(1/Fbaud_rate)+
—
T
ref_clk
ref_clk
1
2
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
ref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).
T
4.7.18.3.4
UART IrDA Mode Receiver
Figure 90 depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 92 lists the
receive timing characteristics.
UA6
UA5
UA5
UA5
UA5
RXD
(input)
Start
Bit
STOP
BIT
Bit 0
Bit 1
Possible
Parity
Bit
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 90. UART IrDA Mode Receive Timing Diagram
Table 92. IrDA Mode Receive Timing Parameters
ID
Parameter
Symbol
Min
Max
Units
Receive Bit Time1 in IrDA mode
tRIRbit
1/Fbaud_rate
–
1/Fbaud_rate
1/(16*Fbaud_rate)
+
—
2
UA5
1/(16*Fbaud_rate
)
UA6
Receive IR Pulse Duration
tRIRpulse
1.41 us
(5/16)*(1/Fbaud_rate
)
—
1
2
The UART receiver can tolerate 1/(16*Fbaud_rate) tolerance in each bit. But accumulation tolerance in one frame must not
exceed 3/(16*Fbaud_rate).
Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.
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Electrical Characteristics
4.7.19 USB-OH-3 Parameters
This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip
USB PHY parameters see Section 4.7.20, “USB PHY Parameters.”
4.7.19.1 Serial Interface
In order to support four serial different interfaces, the USB serial transceiver can be configured to operate
in one of four modes:
•
•
•
•
DAT_SE0 bidirectional, 3-wire mode
DAT_SE0 unidirectional, 6-wire mode
VP_VM bidirectional, 4-wire mode
VP_VM unidirectional, 6-wire mode
4.7.19.1.1 DAT_SE0 Bidirectional Mode
Table 93. Signal Definitions - DAT_SE0 Bidirectional Mode
Direction Signal Description
Transmit enable, active low
Name
USB_TXOE_B
USB_DAT_VP
Out
Out
In
TX data when USB_TXOE_B is low
Differential RX data when USB_TXOE_B is high
USB_SE0_VM
Out
In
SE0 drive when USB_TXOE_B is low
SE0 RX indicator when USB_TXOE_B is high
Transmit
US3
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US1
US4
US2
Figure 91. USB Transmit Waveform in DAT_SE0 Bidirectional Mode
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Electrical Characteristics
Receive
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US7
US8
USB_SE0_VM
Figure 92. USB Receive Waveform in DAT_SE0 Bidirectional Mode
Table 94. Definitions of USB Waveform in DAT_SE0 Bi-Directional Mode
Conditions /
Reference Signal
No.
US1
Parameter
Signal Name
Direction
Min
Max
Unit
TX Rise/Fall Time
TX Rise/Fall Time
TX Rise/Fall Time
TX Duty Cycle
USB_DAT_VP
USB_SE0_VM
USB_TXOE_B
USB_DAT_VP
USB_DAT_VP
USB_SE0_VM
Out
Out
Out
Out
In
-—
—
5.0
5.0
ns
ns
ns
%
50 pF
50 pF
50 pF
—
US2
US3
US4
US7
US8
—
5.0
49.0
—
51.0
3.0
RX Rise/Fall Time
RX Rise/Fall Time
ns
ns
35 pF
35 pF
In
—
3.0
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Electrical Characteristics
4.7.19.1.2 DAT_SE0 Unidirectional Mode
Table 95. Signal Definitions - DAT_SE0 Unidirectional Mode
Name
USB_TXOE_B
Direction
Signal Description
Transmit enable, active low
Out
Out
Out
In
USB_DAT_VP
USB_SE0_VM
USB_VP1
TX data when USB_TXOE_B is low
SE0 drive when USB_TXOE_B is low
Buffered data on DP when USB_TXOE_B is high
Buffered data on DM when USB_TXOE_B is high
USB_VM1
In
Transmit
US11
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US9
US10
US12
Figure 93. USB Transmit Waveform in DAT_SE0 Unidirectional Mode
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Electrical Characteristics
Receive
USB_TXOE_B
USB_DAT_VP
US15
US16
USB_SE0_VM
Figure 94. USB Receive Waveform in DAT_SE0 Unidirectional Mode
Table 96. USB Port Timing Specification in DAT_SE0 Unidirectional Mode
Signal
Source
Condition /
Reference Signal
No.
US9
Parameter
Signal Name
Min
Max
Unit
TX Rise/Fall Time
TX Rise/Fall Time
TX Rise/Fall Time
TX Duty Cycle
USB_DAT_VP
USB_SE0_VM
USB_TXOE_B
USB_DAT_VP
USB_VP1
Out
Out
Out
Out
In
—
—
5.0
5.0
5.0
51.0
3.0
3.0
ns
ns
ns
%
50 pF
50 pF
50 pF
—
US10
US11
US12
US15
US16
—
49.0
—
RX Rise/Fall Time
RX Rise/Fall Time
ns
ns
35 pF
35 pF
USB_VM1
In
—
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Electrical Characteristics
4.7.19.1.3 VP_VM Bidirectional Mode
Table 97. Signal Definitions - VP_VM Bidirectional mode
Direction Signal Description
Out Transmit enable, active low
Name
USB_TXOE_B
USB_DAT_VP
Out (Tx)
In (Rx)
TX VP data when USB_TXOE_B is low
RX VP data when USB_TXOE_B is high
USB_SE0_VM
Out (Tx)
In (Rx)
TX VM data when USB_TXOE_B low
RX VM data when USB_TXOE_B high
Transmit
US20
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US18
US21
US19
US22
US22
Figure 95. USB Transmit Waveform in VP_VM Bidirectional Mode
Receive
US26
USB_DAT_VP
USB_SE0_VM
US27
US28
Figure 96. USB Receive Waveform in VP_VM Bidirectional Mode
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Electrical Characteristics
Table 98. USB Port Timing Specification in VP_VM Bidirectional Mode
Condition /
Reference Signal
No.
Parameter
TX Rise/Fall Time
TX Rise/Fall Time
TX Rise/Fall Time
TX Duty Cycle
TX Overlap
Signal Name Direction
Min
—
Max
5.0
Unit
ns
ns
ns
%
USB_DAT_V
US18
US19
US20
US21
US22
US26
US27
US28
Out
Out
Out
Out
Out
In
In
In
50 pF
50 pF
P
USB_SE0_V
—
5.0
M
USB_TXOE
—
5.0
50 pF
_B
USB_DAT_V
49.0
-3.0
—
51.0
+3.0
3.0
—
P
USB_SE0_V
ns
ns
ns
ns
USB_DAT_VP
35 pF
M
USB_DAT_V
RX Rise/Fall Time
RX Rise/Fall Time
RX Skew
P
USB_SE0_V
—
3.0
35 pF
M
USB_DAT_V
-4.0
+4.0
USB_SE0_VM
P
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Electrical Characteristics
4.7.19.1.4 VP_VM Unidirectional Mode
Table 99. Signal Definitions - VP_VM Unidirectional mode
Name
USB_TXOE_B
Direction
Signal Description
Transmit enable, active low
Out
Out
Out
In
USB_DAT_VP
USB_SE0_VM
USB_VP1
TX VP data when USB_TXOE_B is low
TX VM data when USB_TXOE_B is low
RX VP data when USB_TXOE_B is high
RX VM data when USB_TXOE_B is high
USB_VM1
In
Transmit
US32
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US30
US33
US31
US34
Figure 97. USB Transmit Waveform in VP_VM Unidirectional Mode
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Electrical Characteristics
Receive
USB_TXOE_B
USB_VP1
US38
US39
USB_VM1
US40
Figure 98. USB Receive Waveform in VP_VM Unidirectional Mode
Table 100. USB Timing Specification in VP_VM Unidirectional Mode
Conditions /
Reference Signal
No.
Parameter
Signal
Direction
Min
Max
Unit
US30
US31
TX Rise/Fall Time
TX Rise/Fall Time
USB_DAT_VP
Out
Out
—
—
5.0
5.0
ns
ns
50 pF
50 pF
USB_SE0_V
M
US32
TX Rise/Fall Time
USB_TXOE_
B
Out
—
5.0
ns
50 pF
US33
US34
TX Duty Cycle
TX Overlap
USB_DAT_VP
Out
Out
49.0
-3.0
51.0
3.0
%
—
USB_SE0_V
M
ns
USB_DAT_VP
US38
US39
US40
RX Rise/Fall Time
RX Rise/Fall Time
RX Skew
USB_VP1
USB_VM1
USB_VP1
In
In
In
—
—
3.0
3.0
ns
ns
ns
35 pF
35 pF
-4.0
+4.0
USB_VM1
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Electrical Characteristics
4.7.19.2 Parallel Interface (Normal ULPI) Timing
Electrical and timing specifications of Parallel Interface (Normal ULPI) for Host Port2 and Port3 are
presented in the subsequent sections.
Table 101. Signal Definitions - Parallel Interface (Normal ULPI)
Name
Direction
Signal Description
USB_Clk
Interface clock. All interface signals are synchronous to Clock.
In
USB_Data[7:0]
Bi-directional data bus, driven low by the link during idle. Bus
ownership is determined by Dir.
I/O
In
USB_Dir
USB_Stp
Direction. Control the direction of the Data bus.
Stop. The link asserts this signal for 1 clock cycle to stop the
data stream currently on the bus.
Out
In
USB_Nxt
Next. The PHY asserts this signal to throttle the data.
USB_Clk
US15
US16
USB_Dir/Nxt
US15
US16
USB_Data
USB_Stp
US17
US17
Figure 99. USB Transmit/Receive Waveform in Parallel Mode
Table 102. USB Timing Specification for Normal ULPI Mode
Conditions /
Reference Signal
ID
Parameter
Min
Max
Unit
US15
US16
US17
Setup Time (Dir&Nxt in, Data in)
Hold Time (Dir&Nxt in, Data in)
6.0
0.0
—
—
—
ns
ns
ns
10 pF
10 pF
10 pF
Output Delay Time (Stp out, Data out
9.0
4.7.20 USB PHY Parameters
This section describes the USB-OTG PHY and the USB Host port PHY parameters.
4.7.20.1 USB PHY AC Parameters
Table 103 lists the AC timing parameters for USB PHY.
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Table 103. USB PHY AC Timing Parameters
Parameter
Conditions
Min
Typ
Max
Unit
trise
1.5 Mbps
12 Mbps
480 Mbps
75
4
0.5
—
300
20
ns
tfall
1.5 Mbps
12 Mbps
480 Mbps
75
4
0.5
—
—
300
20
ns
ns
Jitter
1.5 Mbps
12 Mbps
480 Mbps
—
10
1
0.2
4.7.20.2 USB PHY Additional Electrical Parameters
Table 104 lists the parameters for additional electrical characteristics for USB PHY.
Table 104. Additional Electrical Characteristics for USB PHY
Parameter
Conditions
HS Mode
Min
Typ
Max
Unit
Vcm DC
–0.05
0.8
—
0.5
2.5
V
(dc level measured at receiver connector)
LS/FS Mode
Crossover Voltage
LS Mode
FS Mode
1.3
1.3
—
0
2
2
V
Power supply ripple noise
(analog 3.3 V)
< 160 MHz
–50
50
mV
mV
mV
Power supply ripple noise
(analog 2.5 V)
< 1.2 MHz
> 1.2 MHz
–10
–50
0
0
10
50
Power supply ripple noise
(Digital 1.2 V)
All conditions
–50
0
50
4.7.20.3 USB PHY System Clocking (SYSCLK)
Table 105 lists the USB PHY system clocking parameters.
Table 105. USB PHY System Clocking Parameters
Parameter
Conditions
Min
Typ
Max
Unit
Clock deviation
Reference Clock
–150
—
150
ppm
frequency 24 MHz
Rise/fall time
—
—
0
—
—
—
—
200
50
ps
ps
ps
%
Jitter (peak-peak)
Jitter (peak-peak)
Duty-cycle
< 1.2 MHz
> 1.2 MHz
0
100
60
Reference Clock
40
frequency 24 MHz
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Electrical Characteristics
4.7.20.4 USB PHY Voltage Thresholds
Table 106 lists the USB PHY voltage thresholds.
Table 106. VBUS Comparators Thresholds
Parameter
Conditions
Min
Typ
Max
Unit
A-Device Session Valid
—
—
—
—
0.8
0.8
0.2
4.4
1.4
1.4
2.0
4.0
V
V
V
V
B-Device Session Valid
B-Device Session End
0.45
4.6
0.8
VBUS Valid Comparator Threshold1
4.75
1
For VBUS maximum rating, see Table 4 on page 18
4.7.20.5 USB PHY Termination
USB driver impedance in FS and HS modes is 45 Ω 10% (steady state). No external resistors required.
4.8
XTAL Electrical Specifications
Table 107 shows the XTALOSC electrical specifications.
Table 108 shows the XTALOSC_32K electrical specifications.
Table 107. XTALOSC Electrical Specifications
Parameter
Frequency
Min
Typ
Max
Units
22
24
27
MHz
Table 108. XTALOSC_32K Electrical Specifications
Parameter
Frequency
Min
Typ
Max
Units
--
32.768/32.01
--
kHz
1
Recommended nominal frequency 32.768 kHz.
4.9
Integrated LDO Voltage Regulators Parameters
The PLL supplies VDD_DIG_PLL and VDD_ANA_PLL can be powered ON from internal LDO voltage
regulator (default case). In this case VDD_REG is used as internal regulator’s power source. The
regulator’s output can be used as a supply for other domains such as VDDA and VDDAL1.
Table 109 shows the VDD_DIG_PLL and VDD_ANA_PLL Integrated Voltage Regulators Parameters.
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Table 109. LDO Voltage Regulators Electrical Specifications
Parameter
Symbol
Min
Typ
Max
Units
VDD_DIG_PLL functional Voltage
Range1
VVID_DIG_PLL
1.15
1.2
1.3
V
VDD_ANA_PLL functional Voltage
Range1
VVDD_ANA_PLL
1.7
—
—
—
—
1.8
—
1.95
+/–3
—
V
%
VDD_DIG_PLL and VDD_ANA_PLL
accuracy
—
—
—
VDD_DIG_PLL power-supply rejection
ratio2
–18
–15
—
dB
dB
mA
VDD_ANA_PLL power-supply rejection
ratio2
—
Output current3
IVID_DIG_PLL
+
125
IVDD_ANA_PLL
1
VDD_DIG_PLL and VDD_ANA_PLL voltages are programmable, but should not be set outside the target functional range
for proper PLL operation.
2
3
The gain or attenuation from the input supply variation to the output of the LDO (by design).
The limitation is for sum of the VDD_DIG_PLL and VDD_ANA_PLL current.
5 Boot Mode Configuration
This section provides information on boot mode configuration pins allocation and boot devices interfaces
allocation.
5.1
Boot Mode Configuration Pins
Table 110 provides boot options, functionality, fuse values, and associated pins. Several input pins are also
sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.
The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an
unblown fuse). For detailed boot mode options configured by the boot mode pins, please refer to the
i.MX53 Fuse Map document and Boot chapter in i.MX53 Reference Manual.
Table 110. Fuses and Associated Pins Used for Boot
Direction at
Pin
E-Fuse Name
Details
Reset
BOOT_MODE[1]
BOOT_MODE[0]
Input
Input
N/A
Boot Mode selection
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Table 110. Fuses and Associated Pins Used for Boot (continued)
Direction at
Reset
Pin
E-Fuse Name
Details
EIM_A22
EIM_A21
EIM_A20
EIM_A19
EIM_A18
EIM_A17
EIM_A16
EIM_LBA
EIM_EB0
EIM_EB1
EIM_DA0
EIM_DA1
EIM_DA2
EIM_DA3
EIM_DA4
EIM_DA5
EIM_DA6
EIM_DA7
EIM_DA8
EIM_DA9
EIM_DA10
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
BOOT_CFG1[7]/Test Mode Selection
BOOT_CFG1[6]/Test Mode Selection
BOOT_CFG1[5]/Test Mode Selection
BOOT_CFG1[4]
Boot Options, Pin value overrides fuse
settings for BT_FUSE_SEL = ‘0’.
Signal Configuration as Fuse Override
Input at Power Up. These are special I/O
lines that control the boot up configuration
during product development. In production,
the boot configuration can be controlled by
fuses.
BOOT_CFG1[3]
BOOT_CFG1[2]
BOOT_CFG1[1]
BOOT_CFG1[0]
BOOT_CFG2[7]
BOOT_CFG2[6]
BOOT_CFG2[5]
BOOT_CFG2[4]
BOOT_CFG2[3]
BOOT_CFG2[2]
BOOT_CFG3[7]
BOOT_CFG3[6]
BOOT_CFG3[5]
BOOT_CFG3[4]
BOOT_CFG3[3]
BOOT_CFG3[2]
BOOT_CFG3[1]
5.2
Boot Devices Interfaces Allocation
Table 111 lists the interfaces that can be used by the boot process in accordance with the specific boot
mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,
which are configured during boot when appropriate.
Table 111. Interfaces Allocation During Boot
Interface
IP Instance
Allocated Pads During Boot
Comment
SPI
SPI
SPI
CSPI
EIM_A25, EIM_D21, EIM_D22, EIM_D28
EIM_D[19:16]
Only SS1 is supported
Only SS1 is supported
Only SS1 is supported
ECSPI-1
ECSPI-2
CSI_DAT[10:8], EIM_LBA
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Comment
Table 111. Interfaces Allocation During Boot (continued)
Allocated Pads During Boot
Interface
IP Instance
EIM
EIM
EIM
• Lower 16 bit data bus A/D
multiplexed or upper 16 bit data bus
non multiplexed
• Only CS0 is supported.
NAND Flash
EXTMC
NAND
• 8/16 bit
• NAND data can be muxed either over
EIM data or PATA data
• Only CS0 is supported
SD/MMC
SD/MMC
SD/MMC
SD/MMC
eSDHCv2-1 PATA_DATA[11:8], SD1_DATA[3:0], SD1_CMD,
SD1_CLK
1, 4 or 8 bit
1, 4 or 8 bit
1, 4 or 8 bit
1, 4 or 8 bit
eSDHCv2-2 PATA_DATA[15:12], SD2_CLK, SD2_CMD,
SD2_DATA[3:0]
eSDHCv3-3 PATA_RESET_B, PATA_IORDY, PATA_DA_0,
PATA_DATA[3:0], PATA_DATA[11:8]
eSDHCv2-4 PATA_DA1, PATA_DA_2, PATA_DATA[7:4],
PATA_DATA[15:12]
I2C
I2C
I2C-1
I2C-2
I2C-3
PATA
EIM_D21, EIM_D28
EIM_D16, EIM_EB2
EIM_D[18:17]
—
—
—
—
I2C
PATA
PATA_DIOW, PATA_DMACK, PATA_DMARQ,
PATA_BUFFER_EN, PATA_INTRQ, PATA_DIOR,
PATA_RESET_B, PATA_IORDY, PATA_DA_[2:0],
PATA_CS_[1:0], PATA_DATA[15:0]
SATA
SATA_PHY SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM,
SATA_REXT, SATA_REFCLKM, SATA_REFCLKP
—
UART
UART
UART
UART
UART
USB
UARTv2-1 CSI0_DAT[11:10]
RXD/TXD only
RXD/TXD only
RXD/TXD only
RXD/TXD only
RXD/TXD only
—
UARTv2-2 PATA_DMARQ, PATA_BUFFER_EN
UARTv2-3 EIM_D24, EIM_D25
UARTv2-4 CSI0_DAT[13:12]
UARTv2-5 CSI0_DAT[15:14]
USB-OTG USB_H1_GPANAIO
PHY
USB_H1_RREFEXT
USB_H1_DP
USB_H1_DN
USB_H1_VBUS
5.3
Power setup during Boot
By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to
achieve the standard operating mode (see VDD_DIG_PLL on Table 6), LDO output to VDD_DIG_PLL
should be configured by software by boot code after power-up to 1.3 V output. This is done by
programming the PLL1P2_VREG bits.
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Package Information and Contact Assignments
6 Package Information and Contact Assignments
This section includes the contact assignment information and mechanical package drawing.
6.1
19x19 mm Package Information
This section contains the outline drawing, signal assignment map, ground/power reference ID (by ball grid
location) for the 19 × 19 mm, 0.8 mm pitch package.
6.1.1
Case TEPBGA-2, 19 x 19 mm, 0.8 mm Pitch, 23 x 23 Ball Matrix
Figure 100 shows the top view of the 19×19 mm package, Figure 101 shows the bottom view and the ball
location (529 solder balls) of the 19×19 mm package, and Figure 102 shows the side view of the 19×19
mm package.
Figure 100. 19 x 19 mm Package Top View
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Package Information and Contact Assignments
Figure 101. 19 x 19 mm Package, 529 Solder Balls, Bottom View
Figure 102. 19 x 19 mm Package Side View
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Package Information and Contact Assignments
The following notes apply to Figure 100, Figure 101, and Figure 102.
1. All dimensions are in millimeters.
2. Dimensions and tolerancing per ASME Y14.5M1–994.
6.1.2
19 x 19 mm Signal Assignments, Power Rails, and I/O
Table 112 shows the device connection list for ground, power, sense, and reference contact signals.
Table 113 displays an alpha-sorted list of the signal assignments including associated power supplies. The
table also includes out of reset pad state. Table 114 shows the package ball map.
6.1.2.1
19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments
Table 112 shows the device connection list for ground, power, sense, and reference contact signals
alpha-sorted by name.
Table 112. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments
Contact Name
DDR_VREF
Package Contact Assignment(s)
L17
GND
A1, A11, A13, A18, A2, A22, A23, AA11, AA15, AA20, AA21, AB1, AB18, AB2, AB22, AB23,
AC1, AC18, AC2, AC22, AC23, B1, B11, B13, B18, B23, C12, C20, C21, D19, E19, F19, F20,
F21, F22, G19, G7, H10, H12, H8, J11, J13, J15, J17, J20, J9, K10, K12, K14, K16, K21, K8,
L11, L13, L15, L7, L9, M10, M12, M14, M16, M8, N11, N13, N15, N9, P10, P12, P14, P16,
P21, P7, P8, R11, R13, R15, R17, R20, R9, T10, T14, T16, T8, U15, U19, V15, V18, V19,
V20, V21, V22, W19, Y14, Y15, Y19
NVCC_CKIH
G17
NVCC_CSI
R7
NVCC_EIM_MAIN
NVCC_EIM_SEC
NVCC_EMI_DRAM
NVCC_FEC
U10, U9
U7
H18, K17, N17, P17, T18
F11
F8
NVCC_GPIO
NVCC_JTAG
G9
NVCC_KEYPAD
NVCC_LCD
F7
J6, J7
U13
U14
T12
N7
NVCC_LVDS
NVCC_LVDS_BG
NVCC_NANDF
NVCC_PATA
NVCC_RESET
NVCC_SD1
H16
H15
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Package Information and Contact Assignments
Table 112. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)
Contact Name
NVCC_SD2
Package Contact Assignment(s)
H14
V11
NVCC_SRTC_POW
NVCC_XTAL
V12
SVCC
B22
SVDDGP
B2
TVDAC_AHVDDRGB
TVDAC_DHVDD
USB_H1_VDDA25
USB_H1_VDDA33
USB_OTG_VDDA25
USB_OTG_VDDA33
VCC
U17, V16
U16
F13
G13
F14
G14
H13, J14, J16, K13, K15, L14, L16, M11, M13, M15, M9, N10, N12, N14, N16, N8, P11, P13,
P15, P9, R10, R12, R14, R16, R8, T11, T13, T15, T17, T7, T9, U18, U8
VDDA
G12, M17, M7, U12
VDDAL1
VDD_ANA_PLL
VDD_DIG_PLL
VDD_FUSE
VDDGP
F9
G16
H17
G15
G10, G11, G8, H11, H7, H9, J10, J12, J8, K11, K7, K9, L10, L12, L8
VDD_REG
VP
G18
A15, B15
A9, B9
VPH
Table 113 displays an alpha-sorted list of the signal assignments including power rails. The table also
includes out of reset pad state.
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Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
BOOT_MODE C18
0
NVCC_RESET
NVCC_RESET
NVCC_CKIH
NVCC_CKIH
LVIO
ALT0 SRC
ALT0 SRC
src_BOOT_MOD
E[0]
Input
Input
Input
Input
100 KΩ PD
100 KΩ PD
Analog
BOOT_MODE B20
1
LVIO
src_BOOT_MOD
E[1]
CKIH1
B21
ANALOG
ANALOG
ALT0 CAMP- camp1_CKIH
1
CKIH2
D18
ALT0 CAMP- camp2_CKIH
2
Analog
CKIL
AB10
R5
T2
NVCC_SRTC_POW ANALOG
—
SRCT
CKIL
—
—
CSI0_DAT10
CSI0_DAT11
CSI0_DAT12
CSI0_DAT13
CSI0_DAT14
CSI0_DAT15
CSI0_DAT16
CSI0_DAT17
CSI0_DAT18
CSI0_DAT19
CSI0_DAT4
CSI0_DAT5
CSI0_DAT6
CSI0_DAT7
CSI0_DAT8
CSI0_DAT9
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
ALT1 GPIO-5 gpio5_GPIO[28]
ALT1 GPIO-5 gpio5_GPIO[29]
ALT1 GPIO-5 gpio5_GPIO[30]
ALT1 GPIO-5 gpio5_GPIO[31]
ALT1 GPIO-6 gpio6_GPIO[0]
ALT1 GPIO-6 gpio6_GPIO[1]
ALT1 GPIO-6 gpio6_GPIO[2]
ALT1 GPIO-6 gpio6_GPIO[3]
ALT1 GPIO-6 gpio6_GPIO[4]
ALT1 GPIO-6 gpio6_GPIO[5]
ALT1 GPIO-5 gpio5_GPIO[22]
ALT1 GPIO-5 gpio5_GPIO[23]
ALT1 GPIO-5 gpio5_GPIO[24]
ALT1 GPIO-5 gpio5_GPIO[25]
ALT1 GPIO-5 gpio5_GPIO[26]
ALT1 GPIO-5 gpio5_GPIO[27]
ALT1 GPIO-5 gpio5_GPIO[20]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
100 KΩ PU
100 KΩ PU
360 KΩ PD
360 KΩ PD
360 KΩ PD
360 KΩ PD
360 KΩ PD
360 KΩ PD
360 KΩ PD
360 KΩ PD
100 KΩ PU
360 KΩ PD
100 KΩ PU
100 KΩ PU
100 KΩ PU
360 KΩ PD
100 KΩ PU
T3
T6
U1
U2
T4
T5
U3
U4
R1
R2
R6
R3
T1
R4
CSI0_DATA_E P3
N
CSI0_MCLK
P2
NVCC_CSI
NVCC_CSI
NVCC_CSI
UHVIO
UHVIO
UHVIO
ALT1 GPIO-5 gpio5_GPIO[19]
ALT1 GPIO-5 gpio5_GPIO[18]
ALT1 GPIO-5 gpio5_GPIO[21]
Input
Input
Input
100 KΩ PU
100 KΩ PU
100 KΩ PU
CSI0_PIXCLK P1
CSI0_VSYNC P4
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Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
DI0_DISP_CL H4
K
NVCC_LCD
GPIO
ALT1 GPIO-4 gpio4_GPIO[16]
Input
100 KΩ PU
DI0_PIN15
DI0_PIN2
E4
D3
C2
D2
J5
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
NVCC_LCD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT1 GPIO-4 gpio4_GPIO[17]
ALT1 GPIO-4 gpio4_GPIO[18]
ALT1 GPIO-4 gpio4_GPIO[19]
ALT1 GPIO-4 gpio4_GPIO[20]
ALT1 GPIO-4 gpio4_GPIO[21]
ALT1 GPIO-4 gpio4_GPIO[22]
ALT1 GPIO-4 gpio4_GPIO[31]
ALT1 GPIO-5 gpio5_GPIO[5]
ALT1 GPIO-5 gpio5_GPIO[6]
ALT1 GPIO-5 gpio5_GPIO[7]
ALT1 GPIO-5 gpio5_GPIO[8]
ALT1 GPIO-5 gpio5_GPIO[9]
ALT1 GPIO-5 gpio5_GPIO[10]
ALT1 GPIO-5 gpio5_GPIO[11]
ALT1 GPIO-5 gpio5_GPIO[12]
ALT1 GPIO-5 gpio5_GPIO[13]
ALT1 GPIO-4 gpio4_GPIO[23]
ALT1 GPIO-5 gpio5_GPIO[14]
ALT1 GPIO-5 gpio5_GPIO[15]
ALT1 GPIO-5 gpio5_GPIO[16]
ALT1 GPIO-5 gpio5_GPIO[17]
ALT1 GPIO-4 gpio4_GPIO[24]
ALT1 GPIO-4 gpio4_GPIO[25]
ALT1 GPIO-4 gpio4_GPIO[26]
ALT1 GPIO-4 gpio4_GPIO[27]
ALT1 GPIO-4 gpio4_GPIO[28]
ALT1 GPIO-4 gpio4_GPIO[29]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PD
100 KΩ PD
100 KΩ PU
100 KΩ PD
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PD
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PD
100 KΩ PD
100 KΩ PD
100 KΩ PD
100 KΩ PD
100 KΩ PU
DI0_PIN3
DI0_PIN4
DISP0_DAT0
DISP0_DAT1
J4
DISP0_DAT10 G3
DISP0_DAT11 H5
DISP0_DAT12 H1
DISP0_DAT13 E1
DISP0_DAT14 F2
DISP0_DAT15 F3
DISP0_DAT16 D1
DISP0_DAT17 F5
DISP0_DAT18 G4
DISP0_DAT19 G5
DISP0_DAT2
H2
DISP0_DAT20 F4
DISP0_DAT21 C1
DISP0_DAT22 E3
DISP0_DAT23 C3
DISP0_DAT3
DISP0_DAT4
DISP0_DAT5
DISP0_DAT6
DISP0_DAT7
DISP0_DAT8
F1
G2
H3
G1
H6
G6
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Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
DISP0_DAT9
DRAM_A0
DRAM_A1
DRAM_A10
E2
NVCC_LCD
GPIO
ALT1 GPIO-4 gpio4_GPIO[30]
ALT0 EXTMC emi_DRAM_A[0]
ALT0 EXTMC emi_DRAM_A[1]
Input
100 KΩ PU
Low
M19
L21
K19
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
Output
Output
Output
Low
ALT0 EXTMC emi_DRAM_A[10
]
Low
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
L22
L20
L23
N18
M18
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_A[11
]
Output
Output
Output
Output
Output
Low
Low
Low
Low
Low
ALT0 EXTMC emi_DRAM_A[12
]
ALT0 EXTMC emi_DRAM_A[13
]
ALT0 EXTMC emi_DRAM_A[14
]
ALT0 EXTMC emi_DRAM_A[15
]
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
M20
N20
K20
N21
M22
N22
N23
M21
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM special
ALT0 EXTMC emi_DRAM_A[2]
ALT0 EXTMC emi_DRAM_A[3]
ALT0 EXTMC emi_DRAM_A[4]
ALT0 EXTMC emi_DRAM_A[5]
ALT0 EXTMC emi_DRAM_A[6]
ALT0 EXTMC emi_DRAM_A[7]
ALT0 EXTMC emi_DRAM_A[8]
ALT0 EXTMC emi_DRAM_A[9]
Output
Output
Output
Output
Output
Output
Output
Output
Input
Low
Low
Low
Low
Low
Low
Low
Low
—
DRAM_CALIB M23
RATION
—
—
(used in DRAM
driver calibration.
See Special
Signal
Considerations
{add xref} above)
DRAM_CAS
DRAM_CS0
L18
K18
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_CAS
Output
Output
High
High
ALT0 EXTMC emi_DRAM_CS[
0]
DRAM_CS1
P19
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_CS[
1]
Output
High
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
158
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
DRAM_D0
DRAM_D1
DRAM_D10
H20
G21
E22
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_D[0]
ALT0 EXTMC emi_DRAM_D[1]
Output
Output
High
High
High
ALT0 EXTMC emi_DRAM_D[10 Output
]
DRAM_D11
DRAM_D12
DRAM_D13
DRAM_D14
DRAM_D15
DRAM_D16
DRAM_D17
DRAM_D18
DRAM_D19
D20
E23
C23
F23
C22
U20
T21
U21
R21
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_D[11 Output
]
High
High
High
High
High
High
High
High
High
ALT0 EXTMC emi_DRAM_D[12 Output
]
ALT0 EXTMC emi_DRAM_D[13 Output
]
ALT0 EXTMC emi_DRAM_D[14 Output
]
ALT0 EXTMC emi_DRAM_D[15 Output
]
ALT0 EXTMC emi_DRAM_D[16 Output
]
ALT0 EXTMC emi_DRAM_D[17 Output
]
ALT0 EXTMC emi_DRAM_D[18 Output
]
ALT0 EXTMC emi_DRAM_D[19 Output
]
DRAM_D2
J21
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_D[2]
Output
High
High
DRAM_D20
U23
ALT0 EXTMC emi_DRAM_D[20 Output
]
DRAM_D21
DRAM_D22
DRAM_D23
DRAM_D24
DRAM_D25
R22
U22
R23
Y20
W21
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_D[21 Output
]
High
High
High
High
High
ALT0 EXTMC emi_DRAM_D[22 Output
]
ALT0 EXTMC emi_DRAM_D[23 Output
]
ALT0 EXTMC emi_DRAM_D[24 Output
]
ALT0 EXTMC emi_DRAM_D[25 Output
]
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
159
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
DRAM_D26
DRAM_D27
DRAM_D28
DRAM_D29
Y21
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_D[26 Output
]
High
High
High
High
W22
AA23
V23
ALT0 EXTMC emi_DRAM_D[27 Output
]
ALT0 EXTMC emi_DRAM_D[28 Output
]
ALT0 EXTMC emi_DRAM_D[29 Output
]
DRAM_D3
G20
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_D[3]
Output
High
High
DRAM_D30
AA22
ALT0 EXTMC emi_DRAM_D[30 Output
]
DRAM_D31
W23
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_D[31 Output
]
High
DRAM_D4
DRAM_D5
DRAM_D6
DRAM_D7
DRAM_D8
DRAM_D9
J23
G23
J22
G22
E21
D21
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_D[4]
ALT0 EXTMC emi_DRAM_D[5]
ALT0 EXTMC emi_DRAM_D[6]
ALT0 EXTMC emi_DRAM_D[7]
ALT0 EXTMC emi_DRAM_D[8]
ALT0 EXTMC emi_DRAM_D[9]
Output
Output
Output
Output
Output
Output
Output
High
High
High
High
High
High
Low
DRAM_DQM0 H21
DRAM_DQM1 E20
DRAM_DQM2 T20
DRAM_DQM3 W20
ALT0 EXTMC emi_DRAM_DQ
M[0]
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_DQ
M[1]
Output
Output
Output
Low
Low
Low
ALT0 EXTMC emi_DRAM_DQ
M[2]
ALT0 EXTMC emi_DRAM_DQ
M[3]
DRAM_RAS
J19
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_RAS
Output
Output
High
Low
DRAM_RESE P18
T
ALT0 EXTMC emi_DRAM_RES
ET
DRAM_SDBA R19
0
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_SDB
A[0]
Output
Output
Low
Low
DRAM_SDBA P20
1
ALT0 EXTMC emi_DRAM_SDB
A[1]
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
160
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
DRAM_SDBA N19
2
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_SDB
A[2]
Output
Low
Low
DRAM_SDCK H19
E0
ALT0 EXTMC emi_DRAM_SDC Output
KE[0]
DRAM_SDCK T19
E1
ALT0 EXTMC emi_DRAM_SDC Output
KE[1]
Low
DRAM_SDCL K23
K_0
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDC Output
LK0
Floating
Floating
Floating
Floating
Low
DRAM_SDCL K22
K_0_B
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDC Output
LK0_B
DRAM_SDCL P22
K_1
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDC Output
LK1
DRAM_SDCL P23
K_1_B
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDC Output
LK1_B
DRAM_SDOD J18
T0
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_ODT Output
[0]
DRAM_SDOD R18
T1
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_ODT Output
[1]
Low
DRAM_SDQS H23
0
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDQ
S[0]
Input
Input
Input
Input
Input
Input
Input
Input
Output
Low
DRAM_SDQS H22
0_B
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDQ
S_B[0]
High
DRAM_SDQS D23
1
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDQ
S[1]
Low
DRAM_SDQS D22
1_B
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDQ
S_B[1]
High
DRAM_SDQS T22
2
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDQ
S[2]
Low
DRAM_SDQS T23
2_B
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDQ
S_B[2]
High
DRAM_SDQS Y22
3
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDQ
S[3]
Low
DRAM_SDQS Y23
3_B
NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SDQ
S_B[3]
High
DRAM_SDWE L19
NVCC_EMI_DRAM DDR3
ALT0 EXTMC emi_DRAM_SD
WE
High
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
161
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
ECKIL
AC10
NVCC_SRTC_POW ANALOG
—
SRTC
ECKIL {no block
I/O by this name
in RM}
—
—
EIM_A16
EIM_A17
EIM_A18
EIM_A19
EIM_A20
EIM_A21
EIM_A22
EIM_A23
EIM_A24
EIM_A25
EIM_BCLK
EIM_CS0
EIM_CS1
EIM_D16
EIM_D17
EIM_D18
EIM_D19
EIM_D20
EIM_D21
EIM_D22
EIM_D23
EIM_D24
EIM_D25
EIM_D26
EIM_D27
EIM_D28
EIM_D29
AA5
V7
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_SEC
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
ALT0 EXTMC emi_EIM_A[16]
ALT0 EXTMC emi_EIM_A[17]
ALT0 EXTMC emi_EIM_A[18]
ALT0 EXTMC emi_EIM_A[19]
ALT0 EXTMC emi_EIM_A[20]
ALT0 EXTMC emi_EIM_A[21]
ALT0 EXTMC emi_EIM_A[22]
ALT0 EXTMC emi_EIM_A[23]
ALT0 EXTMC emi_EIM_A[24]
ALT0 EXTMC emi_EIM_A[25]
ALT0 EXTMC emi_EIM_BCLK
ALT0 EXTMC emi_EIM_CS[0]
ALT0 EXTMC emi_EIM_CS[1]
ALT1 GPIO-3 gpio3_GPIO[16]
ALT1 GPIO-3 gpio3_GPIO[17]
ALT1 GPIO-3 gpio3_GPIO[18]
ALT1 GPIO-3 gpio3_GPIO[19]
ALT1 GPIO-3 gpio3_GPIO[20]
ALT1 GPIO-3 gpio3_GPIO[21]
ALT1 GPIO-3 gpio3_GPIO[22]
ALT1 GPIO-3 gpio3_GPIO[23]
ALT1 GPIO-3 gpio3_GPIO[24]
ALT1 GPIO-3 gpio3_GPIO[25]
ALT1 GPIO-3 gpio3_GPIO[26]
ALT1 GPIO-3 gpio3_GPIO[27]
ALT1 GPIO-3 gpio3_GPIO[28]
ALT1 GPIO-3 gpio3_GPIO[29]
Output2
Output2
Output2
Output2
Output2
Output2
Output2
Output
Output
Output
Output
Output
Output
Input
—
—
AB3
W7
Y6
—
—
—
AA4
AA3
V6
—
—
—
Y5
—
W6
W11
W8
Y7
—
—
—
—
U6
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
360 KΩ PD
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
U5
Input
V1
Input
V2
Input
W1
V3
Input
Input
W2
Y1
Input
Input
Y2
Input
W3
V5
Input
Input
V4
Input
AA1
AA2
Input
Input
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
162
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
EIM_D30
EIM_D31
EIM_DA0
W4
W5
Y8
NVCC_EIM_SEC
NVCC_EIM_SEC
NVCC_EIM_MAIN
UHVIO
UHVIO
UHVIO
ALT1 GPIO-3 gpio3_GPIO[30]
ALT1 GPIO-3 gpio3_GPIO[31]
Input
Input
Input2
100 KΩ PU
360 KΩ PD
100 KΩ PU
ALT0 EXTMC emi_NAND_EIM
_DA[0]
EIM_DA1
EIM_DA10
EIM_DA11
EIM_DA12
EIM_DA13
EIM_DA14
EIM_DA15
EIM_DA2
EIM_DA3
EIM_DA4
EIM_DA5
EIM_DA6
EIM_DA7
EIM_DA8
EIM_DA9
EIM_EB0
AC4
AB7
AC6
V10
AC7
Y10
AA9
AA7
W9
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
ALT0 EXTMC emi_NAND_EIM
_DA[1]
Input2
Input2
Input
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
—
ALT0 EXTMC emi_NAND_EIM
_DA[10]
ALT0 EXTMC emi_NAND_EIM
_DA[11]
ALT0 EXTMC emi_NAND_EIM
_DA[12]
Input
ALT0 EXTMC emi_NAND_EIM
_DA[13]
Input
ALT0 EXTMC emi_NAND_EIM
_DA[14]
Input
ALT0 EXTMC emi_NAND_EIM
_DA[15]
Input
ALT0 EXTMC emi_NAND_EIM
_DA[2]
Input2
Input2
Input2
Input2
Input2
Input2
Input2
Input2
Output2
ALT0 EXTMC emi_NAND_EIM
_DA[3]
AB6
V9
ALT0 EXTMC emi_NAND_EIM
_DA[4]
ALT0 EXTMC emi_NAND_EIM
_DA[5]
Y9
ALT0 EXTMC emi_NAND_EIM
_DA[6]
AC5
AA8
W10
AC3
ALT0 EXTMC emi_NAND_EIM
_DA[7]
ALT0 EXTMC emi_NAND_EIM
_DA[8]
ALT0 EXTMC emi_NAND_EIM
_DA[9]
ALT0 EXTMC emi_EIM_EB[0]
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
163
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
EIM_EB1
EIM_EB2
EIM_EB3
EIM_LBA
EIM_OE
EIM_RW
EIM_WAIT
EXTAL
AB5
Y3
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_EIM_MAIN
NVCC_XTAL
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
ANALOG
ALT0 EXTMC emi_EIM_EB[1]
ALT1 GPIO-2 gpio2_GPIO[30]
ALT1 GPIO-2 gpio2_GPIO[31]
ALT0 EXTMC emi_EIM_LBA
ALT0 EXTMC emi_EIM_OE
ALT0 EXTMC emi_EIM_RW
ALT0 EXTMC emi_EIM_WAIT
Output2
Input
—
100 KΩ PU
Y4
Input
100 KΩ PU
AA6
V8
Output2
Output
Output
Output
—
—
—
—
—
—
AB4
AB9
AB11
—
—
—
EXTAL EXTAL
OSC
FASTR_ANA
FASTR_DIG
E18
E17
NVCC_CKIH
NVCC_CKIH
ANALOG
ANALOG
—
(reserved, tie to
—
—
—
—
ground)
—
(reserved, tie to
ground)
FEC_CRS_DV D11
NVCC_FEC
NVCC_FEC
NVCC_FEC
NVCC_FEC
UHVIO
UHVIO
UHVIO
UHVIO
ALT1 GPIO-1 gpio1_GPIO[25]
ALT1 GPIO-1 gpio1_GPIO[31]
ALT1 GPIO-1 gpio1_GPIO[22]
ALT1 GPIO-1 gpio1_GPIO[23]
Input
Input
Input
Input
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
FEC_MDC
FEC_MDIO
E10
D12
FEC_REF_CL E12
K
FEC_RX_ER F12
NVCC_FEC
NVCC_FEC
NVCC_FEC
NVCC_FEC
NVCC_FEC
NVCC_FEC
NVCC_GPIO
NVCC_GPIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
ALT1 GPIO-1 gpio1_GPIO[24]
ALT1 GPIO-1 gpio1_GPIO[27]
ALT1 GPIO-1 gpio1_GPIO[26]
ALT1 GPIO-1 gpio1_GPIO[28]
ALT1 GPIO-1 gpio1_GPIO[30]
ALT1 GPIO-1 gpio1_GPIO[29]
ALT1 GPIO-1 gpio1_GPIO[0]
ALT1 GPIO-1 gpio1_GPIO[1]
ALT0 GPIO-4 gpio4_GPIO[0]
Input
Input
Input
Input
Input
Input
Input
Input
Input
100 KΩ PU
100 KΩ PU
100 KΩ PU
360 KΩ PD
100 KΩ PU
100 KΩ PU
360 KΩ PD
360 KΩ PD
100 KΩ PU
FEC_RXD0
FEC_RXD1
FEC_TX_EN
FEC_TXD0
FEC_TXD1
GPIO_0
C11
E11
C10
F10
D10
C8
GPIO_1
B7
GPIO_10
W16
TVDAC_AHVDDRG GPIO
B
GPIO_11
GPIO_12
V17
TVDAC_AHVDDRG GPIO
B
ALT0 GPIO-4 gpio4_GPIO[1]
ALT0 GPIO-4 gpio4_GPIO[2]
Input
Input
100 KΩ PU
100 KΩ PU
W17
TVDAC_AHVDDRG GPIO
B
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
Freescale Semiconductor
164
Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
GPIO_13
GPIO_14
AA18
W18
TVDAC_AHVDDRG GPIO
B
ALT0 GPIO-4 gpio4_GPIO[3]
ALT0 GPIO-4 gpio4_GPIO[4]
Input
Input
100 KΩ PU
100 KΩ PU
TVDAC_AHVDDRG GPIO
B
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_2
C6
A3
D7
B4
C7
A6
D8
A5
B6
A4
B5
E8
C9
D9
B8
A7
A8
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_KEYPAD
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
NVCC_JTAG
NVCC_JTAG
NVCC_JTAG
NVCC_JTAG
NVCC_JTAG
NVCC_JTAG
NVCC_KEYPAD
NVCC_KEYPAD
NVCC_KEYPAD
NVCC_KEYPAD
NVCC_KEYPAD
NVCC_KEYPAD
NVCC_KEYPAD
NVCC_KEYPAD
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
GPIO
ALT1 GPIO-7 gpio7_GPIO[11]
ALT1 GPIO-7 gpio7_GPIO[12]
ALT1 GPIO-7 gpio7_GPIO[13]
ALT1 GPIO-4 gpio4_GPIO[5]
ALT1 GPIO-1 gpio1_GPIO[2]
ALT1 GPIO-1 gpio1_GPIO[3]
ALT1 GPIO-1 gpio1_GPIO[4]
ALT1 GPIO-1 gpio1_GPIO[5]
ALT1 GPIO-1 gpio1_GPIO[6]
ALT1 GPIO-1 gpio1_GPIO[7]
ALT1 GPIO-1 gpio1_GPIO[8]
ALT1 GPIO-1 gpio1_GPIO[9]
Input
Input
Input
Input3
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input4
Input
Input
Input
Input
Input
Input
Input
360 KΩ PD
360 KΩ PD
360 KΩ PD
100 KΩ PU
360 KΩ PD
360 KΩ PD
100 KΩ PU
360 KΩ PD
360 KΩ PD
360 KΩ PD
360 KΩ PD
100 KΩ PU
100 KΩ PU
100 KΩ PD
47 KΩ PU
Keeper
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
JTAG_MOD
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
ALT0 SJC
ALT0 SJC
ALT0 SJC
ALT0 SJC
ALT0 SJC
ALT0 SJC
sjc_MOD
sjc_TCK
sjc_TDI
GPIO
GPIO
GPIO
sjc_TDO
sjc_TMS
sjc_TRSTB
GPIO
47 KΩ PU
47 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
360 KΩ PD
100 KΩ PU
100 KΩ PU
JTAG_TRSTB E9
GPIO
KEY_COL0
KEY_COL1
KEY_COL2
KEY_COL3
KEY_COL4
KEY_ROW0
KEY_ROW1
KEY_ROW2
C5
E7
C4
F6
E5
B3
D6
D5
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
ALT1 GPIO-4 gpio4_GPIO[6]
ALT1 GPIO-4 gpio4_GPIO[8]
ALT1 GPIO-4 gpio4_GPIO[10]
ALT1 GPIO-4 gpio4_GPIO[12]
ALT1 GPIO-4 gpio4_GPIO[14]
ALT1 GPIO-4 gpio4_GPIO[7]
ALT1 GPIO-4 gpio4_GPIO[9]
ALT1 GPIO-4 gpio4_GPIO[11]
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Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
KEY_ROW3
KEY_ROW4
D4
E6
NVCC_KEYPAD
NVCC_KEYPAD
NVCC_LVDS_BG
UHVIO
ALT1 GPIO-4 gpio4_GPIO[13]
ALT1 GPIO-4 gpio4_GPIO[15]
Input
Input
—
100 KΩ PU
360 KΩ PD
—
UHVIO
LVDS_BG_RE AA14
S
ANALOG
—
LDB
LVDS_BG_RES
LVDS0_CLK_ AB16
N
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
LVDS
LVDS
LVDS
ALT0 GPIO-7 gpio7_GPI[25]
ALT0 GPIO-7 gpio7_GPI[24]
ALT0 GPIO-7 gpio7_GPI[31]
Input
Input
Input
Floating
Floating
Floating
LVDS0_CLK_ AC16
P
LVDS0_TX0_ Y17
N
LVDS0_TX0_P AA17
NVCC_LVDS
NVCC_LVDS
LVDS
LVDS
ALT0 GPIO-7 gpio7_GPI[30]
ALT0 GPIO-7 gpio7_GPI[29]
Input
Input
Floating
Floating
LVDS0_TX1_ AB17
N
LVDS0_TX1_P AC17
NVCC_LVDS
NVCC_LVDS
LVDS
LVDS
ALT0 GPIO-7 gpio7_GPI[28]
ALT0 GPIO-7 gpio7_GPI[27]
Input
Input
Floating
Floating
LVDS0_TX2_ Y16
N
LVDS0_TX2_P AA16
NVCC_LVDS
NVCC_LVDS
LVDS
LVDS
ALT0 GPIO-7 gpio7_GPI[26]
ALT0 GPIO-7 gpio7_GPI[23]
Input
Input
Floating
Floating
LVDS0_TX3_ AB15
N
LVDS0_TX3_P AC15
NVCC_LVDS
NVCC_LVDS
LVDS
LVDS
ALT0 GPIO-7 gpio7_GPI[22]
ALT0 GPIO-6 gpio6_GPI[27]
Input
Input
Floating
Floating
LVDS1_CLK_ AA13
N
LVDS1_CLK_ Y13
P
NVCC_LVDS
NVCC_LVDS
LVDS
LVDS
ALT0 GPIO-6 gpio6_GPI[26]
ALT0 GPIO-6 gpio6_GPI[31]
Input
Input
Floating
Floating
LVDS1_TX0_ AC14
N
LVDS1_TX0_P AB14
NVCC_LVDS
NVCC_LVDS
LVDS
LVDS
ALT0 GPIO-6 gpio6_GPI[30]
ALT0 GPIO-6 gpio6_GPI[29]
Input
Input
Floating
Floating
LVDS1_TX1_ AC13
N
LVDS1_TX1_P AB13
NVCC_LVDS
NVCC_LVDS
LVDS
LVDS
ALT0 GPIO-6 gpio6_GPI[28]
ALT0 GPIO-6 gpio6_GPI[25]
Input
Input
Floating
Floating
LVDS1_TX2_ AC12
N
LVDS1_TX2_P AB12
NVCC_LVDS
LVDS
ALT0 GPIO-6 gpio6_GPI[24]
Input
Floating
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Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
LVDS1_TX3_ AA12
N
NVCC_LVDS
LVDS
ALT0 GPIO-6 gpio6_GPI[23]
Input
Floating
LVDS1_TX3_P Y12
NANDF_ALE Y11
NANDF_CLE AA10
NANDF_CS0 W12
NANDF_CS1 V13
NANDF_CS2 V14
NANDF_CS3 W13
NANDF_RB0 U11
NANDF_RE_B AC8
NVCC_LVDS
LVDS
ALT0 GPIO-6 gpio6_GPI[22]
ALT1 GPIO-6 gpio6_GPIO[8]
ALT1 GPIO-6 gpio6_GPIO[7]
ALT1 GPIO-6 gpio6_GPIO[11]
ALT1 GPIO-6 gpio6_GPIO[14]
ALT1 GPIO-6 gpio6_GPIO[15]
ALT1 GPIO-6 gpio6_GPIO[16]
ALT1 GPIO-6 gpio6_GPIO[10]
ALT1 GPIO-6 gpio6_GPIO[13]
ALT1 GPIO-6 gpio6_GPIO[12]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Floating
NVCC_NANDF
NVCC_NANDF
NVCC_NANDF
NVCC_NANDF
NVCC_NANDF
NVCC_NANDF
NVCC_NANDF
NVCC_EIM_MAIN
NVCC_EIM_MAIN
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
NANDF_WE_ AB8
B
NANDF_WP_ AC9
B
NVCC_NANDF
NVCC_PATA
UHVIO
UHVIO
ALT1 GPIO-6 gpio6_GPIO[9]
ALT1 GPIO-7 gpio7_GPIO[1]
Input
Input
100 KΩ PU
100 KΩ PU
PATA_BUFFE K4
R_EN
PATA_CS_0
PATA_CS_1
PATA_DA_0
PATA_DA_1
PATA_DA_2
PATA_DATA0
PATA_DATA1
L5
L2
K6
L3
L4
L1
M1
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
ALT1 GPIO-7 gpio7_GPIO[9]
ALT1 GPIO-7 gpio7_GPIO[10]
ALT1 GPIO-7 gpio7_GPIO[6]
ALT1 GPIO-7 gpio7_GPIO[7]
ALT1 GPIO-7 gpio7_GPIO[8]
ALT1 GPIO-2 gpio2_GPIO[0]
ALT1 GPIO-2 gpio2_GPIO[1]
ALT1 GPIO-2 gpio2_GPIO[10]
ALT1 GPIO-2 gpio2_GPIO[11]
ALT1 GPIO-2 gpio2_GPIO[12]
ALT1 GPIO-2 gpio2_GPIO[13]
ALT1 GPIO-2 gpio2_GPIO[14]
ALT1 GPIO-2 gpio2_GPIO[15]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
PATA_DATA10 N4
PATA_DATA11 M6
PATA_DATA12 N5
PATA_DATA13 N6
PATA_DATA14 P6
PATA_DATA15 P5
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Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
PATA_DATA2
PATA_DATA3
PATA_DATA4
PATA_DATA5
PATA_DATA6
PATA_DATA7
PATA_DATA8
PATA_DATA9
PATA_DIOR
PATA_DIOW
L6
NVCC_PATA
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
ALT1 GPIO-2 gpio2_GPIO[2]
ALT1 GPIO-2 gpio2_GPIO[3]
ALT1 GPIO-2 gpio2_GPIO[4]
ALT1 GPIO-2 gpio2_GPIO[5]
ALT1 GPIO-2 gpio2_GPIO[6]
ALT1 GPIO-2 gpio2_GPIO[7]
ALT1 GPIO-2 gpio2_GPIO[8]
ALT1 GPIO-2 gpio2_GPIO[9]
ALT1 GPIO-7 gpio7_GPIO[3]
ALT1 GPIO-6 gpio6_GPIO[17]
ALT1 GPIO-6 gpio6_GPIO[18]
ALT1 GPIO-7 gpio7_GPIO[0]
ALT1 GPIO-7 gpio7_GPIO[2]
ALT1 GPIO-7 gpio7_GPIO[5]
ALT1 GPIO-7 gpio7_GPIO[4]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
M2
M3
M4
N1
M5
N2
N3
K3
J3
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
NVCC_PATA
PATA_DMACK J2
PATA_DMARQ J1
PATA_INTRQ K5
PATA_IORDY K1
PATA_RESET K2
_B
PMIC_ON_RE W14
Q
NVCC_SRTC_POW GPIO
NVCC_SRTC_POW GPIO
ALT0 SRTC
ALT0 CCM
srtc_SRTCALAR
M
Output
Output
—
—
PMIC_STBY_ W15
REQ
ccm_PMIC_VST
BY_REQ
POR_B
C19
NVCC_RESET
NVCC_RESET
VPH
LVIO
ALT0 SRC
ALT0 SRC
src_POR_B
Input
Input
—
100 KΩ PU
100 KΩ PU
—
RESET_IN_B A21
LVIO
src_RESET_B
SATA_REFCLKM
SATA_REFCL A14
KM
ANALOG
—
SATA
SATA_REFCL B14
KP
VPH
ANALOG
—
SATA
SATA_REFCLKP
—
—
SATA_REXT
SATA_RXM
SATA_RXP
SATA_TXM
SATA_TXP
C13
A12
B12
B10
A10
VPH
VPH
VPH
VPH
VPH
ANALOG
ANALOG
ANALOG
ANALOG
ANALOG
—
—
—
—
—
SATA
SATA
SATA
SATA
SATA
SATA_REXT
SATA_RXM
SATA_RXP
SATA_TXM
SATA_TXP
—
—
—
—
—
—
—
—
—
—
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Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
SD1_CLK
E16
F18
A20
C17
F17
F16
E14
C15
D13
C14
D14
E13
NVCC_SD1
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
LVIO
ALT1 GPIO-1 gpio1_GPIO[20]
ALT1 GPIO-1 gpio1_GPIO[18]
ALT1 GPIO-1 gpio1_GPIO[16]
ALT1 GPIO-1 gpio1_GPIO[17]
ALT1 GPIO-1 gpio1_GPIO[19]
ALT1 GPIO-1 gpio1_GPIO[21]
ALT1 GPIO-1 gpio1_GPIO[10]
ALT1 GPIO-1 gpio1_GPIO[11]
ALT1 GPIO-1 gpio1_GPIO[15]
ALT1 GPIO-1 gpio1_GPIO[14]
ALT1 GPIO-1 gpio1_GPIO[13]
ALT1 GPIO-1 gpio1_GPIO[12]
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PU
100 KΩ PD
SD1_CMD
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3
SD2_CLK
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD1
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_SD2
NVCC_RESET
SD2_CMD
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
TEST_MODE D17
ALT0
tcu_TEST_MOD
E
TVCDC_IOB_ AB19
BACK
TVDAC_AHVDDRG ANALOG
B
—
TVE
TVE
TVE
TVE
TVE
TVE
TVE
TVE
USB
TVCDC_IOB_BA
CK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TVCDC_IOG_ AC20
BACK
TVDAC_AHVDDRG ANALOG
B
—
TVCDC_IOG_BA
CK
TVCDC_IOR_ AB21
BACK
TVDAC_AHVDDRG ANALOG
B
—
TVCDC_IOR_BA
CK
TVDAC_COM AA19
P
TVDAC_AHVDDRG ANALOG
B
—
TVDAC_COMP
TVDAC_IOB
TVDAC_IOG
TVDAC_IOR
TVDAC_VREF
USB_H1_DN
TVDAC_IOB
TVDAC_IOG
TVDAC_IOR
AC19
AB20
AC21
TVDAC_AHVDDRG ANALOG
B
—
TVDAC_AHVDDRG ANALOG
B
—
TVDAC_AHVDDRG ANALOG
B
—
TVDAC_VREF Y18
USB_H1_DN B17
TVDAC_AHVDDRG ANALOG
B
—
USB_H1_VDDA25,
USB_H1_VDDA33
ANALOG50 —
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Package Information and Contact Assignments
Table 113. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Out of Reset Condition1
Package
Contact
Assign
ment
I/O Buffer
Type
Contact Name
Power Rail
Alt.
Mode
Config./
Value
Block I/O
Direction
USB_H1_DP
A17
USB_H1_VDDA25,
USB_H1_VDDA33
ANALOG50 —
ANALOG25 —
ANALOG25 —
ANALOG50 —
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB_H1_DP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
USB_H1_GPA A16
NAIO
USB_H1_VDDA25,
USB_H1_VDDA33
USB_H1_GPANA
IO
USB_H1_RRE B16
FEXT
USB_H1_VDDA25,
USB_H1_VDDA33
USB_H1_RREFE
XT
USB_H1_VBU D15
S
USB_H1_VDDA25,
USB_H1_VDDA33
USB_H1_VBUS
USB_OTG_DN
USB_OTG_DP
USB_OTG_D A19
N
USB_OTG_VDDA25, ANALOG50 —
USB_OTG_VDDA33
USB_OTG_DP B19
USB_OTG_VDDA25, ANALOG50 —
USB_OTG_VDDA33
USB_OTG_G F15
PANAIO
USB_OTG_VDDA25, ANALOG25 —
USB_OTG_VDDA33
USB_OTG_GPA
NAIO
USB_OTG_ID C16
USB_OTG_VDDA25, ANALOG25 —
USB_OTG_VDDA33
USB_OTG_ID
USB_OTG_R D16
REFEXT
USB_OTG_VDDA25, ANALOG25 —
USB_OTG_VDDA33
USB_OTG_RRE
FEXT
USB_OTG_VB E15
US
USB_OTG_VDDA25, ANALOG50 —
USB_OTG_VDDA33
USB_OTG_VBU
S
XTAL
AC11
NVCC_XTAL
ANALOG
—
XTALO XTAL
SC
1
2
The state immediately after reset and before ROM firmware or software has executed.
During power-on reset, this port acts as input for fuse override. See Section 5.1, “Boot Mode Configuration Pins” for details.
For appropriate resistor values, see Chapter 1 of i.MX53 System Development User's Guide, document number MX53UG.
3
4
During power-on reset this port acts as output for diagnostic signal INT_BOOT
During power-on reset this port acts as output for diagnostic signal ANY_PU_RST
NOTE
KEY_COL0 and GPIO_19 act as output for diagnostic signals during
power-on reset.
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Package Information and Contact Assignments
6.2
19 x 19 mm, 0.8 Pitch Ball Map
Table 114 shows the 19 × 19 mm, 0.8 pitch ball map.
Table 114. 19 x 19 mm, 0.8 Pitch Ball Map
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Package Information and Contact Assignments
Table 114. 19 x 19 mm, 0.8 Pitch Ball Map
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Package Information and Contact Assignments
Table 114. 19 x 19 mm, 0.8 Pitch Ball Map
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Package Information and Contact Assignments
Table 114. 19 x 19 mm, 0.8 Pitch Ball Map
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Revision History
7 Revision History
Table 115 provides a revision history for this data sheet.
Table 115. i.MX53xA Data Sheet Document Revision History
Substantive Change(s)
Rev.
Number
Date
Rev 2
05/2011 • Updated Table 1, "Ordering Information," on page 3.
• Updated the note on page 6 in Section 1.2, “Features.”
• Modified VDD_FUSE design best practice footnote on Table 6, "i.MX53xA Operating Ranges," on
page 20.
• Changed VDD_FUSE max current to 120 mA in Table 8, "Maximal Supply Currents," on page 22.
• In Table 9, "USB Interface Current Consumption," on page 24, removed the row for Suspend
specification.
• Made changes related to text, tables, and figures in Section 4.6.7, “DDR SDRAM Specific
Parameters (DDR2/LVDDR2, LPDDR2, and DDR3). Changes include adding LPDDR2 waves,
updating timings by ACCZ test results, and changing note about DDR load model.
• Removed the Standard Serial Interfaces section.
• In Table 10, "GPIO I/O DC Electrical Characteristics," on page 28, changed input current with no
pull-up/down from 250/120 nA to 2 μA, all input currents with pull-up from 0.12 μΑ to 2 μA when
Vin = OVDD, and input current with pull-down from 0.25 μA to 2 μA when Vin = 0.
• In Table 11, Table 12, and Table 13, changed input current from the nA range to 1 μA.
• In Table 14, "LVIO DC Electrical Characteristics," on page 32, changed input current with no
pull-up/down from 250/120 nA to 1 μA, all input currents with pull-up from 0.12 μΑ to 1 μA when
Vin = OVDD, and input current with pull-down from 0.25 μA to 1 μA when Vin = 0.
• In Table 15, "UHVIO DC Electrical Characteristics," on page 33, changed input current with no
pull-up/down from 300/63 nA to 1 μA, all input currents with pull-up from 0.06 μΑ to 1 μA when Vin
= OVDD, and input current with pull-down from 0.3 μA to 1 μA when Vin = 0.
• Updated keeper values in Table 10 through Table 15.
• Fixed titles of Figure 18 through Figure 26, to fit original EIM AC spec.
• Updated Figure 2, "Power Up Detailed Sequence," on page 26.
• Added Figure 27, "DTACK Write Access (DAP=0)," on page 61.
• Added Table 18, "DDR Output Driver Average Impedance," on page 37.
• Deleted the second footnote of Table 32, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page
46.
• Deleted the Revision 1.0 EIM Internal Module Multiplexing table.
• Deleted the CKIL Electrical Specifications table.
• Deleted the CSPI Slave Mode Timing Parameters table .
• Changed the title of Section 4.4.2, “DDR Output Driver Average Impedance,” from “LPDDR2 I/O
Output Buffer Impedance.”
• Updated the last paragragh of Section 4.7.8.6.1, “IPU Display Operating Signals.”
• Updated Table 35, " NFC—Timing Characteristics," on page 51.
• Removed the “Differential pulse skew” row from Table 29, "AC Electrical Characteristics of LVDS
Pad," on page 44.
• Updated Table 63, "Asynchronous Display Interface Timing Parameters (Pixel Level)," on page
104.
• Updated Table 64, "Asynchronous Parallel Interface Timing Parameters (Access Level)," on page
105.
• Updated Table 102, "USB Timing Specification for Normal ULPI Mode," on page 146.
• Updated the second footnote on Table 113, "19 x 19 mm Signal Assignments, Power Rails, and
I/O," on page 156.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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175
Revision History
Table 115. i.MX53xA Data Sheet Document Revision History (continued)
Date Substantive Change(s)
Rev.
Number
Rev 1
03/2011 • Updated the first sentence of Section 3.1, “Special Signal Considerations.”
• Deleted two tables, “Special Signal Considerations” and “JTAG Controller Interface Summary,” in
Section 3.1, “Special Signal Considerations.”
• Updated Table 6, "i.MX53xA Operating Ranges," on page 20.
•
Changed VDDGP voltages as follows:
—
—
800 MHz from 1.0/1.05/1.1 to 1.05/1.1/1.15 V minimum/nominal/maximum.
Stop mode from 0.9/0.95/1.1 to 0.8/0.85/1.15 V minimum/nominal/maximum.
•
Added statements to footnotes 4 and 5.
Rev 0
02/2011 Initial release.
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 2
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Freescale Semiconductor
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Document Number: IMX53AEC
Rev. 2
5/2011
相关型号:
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