MC9S08LG32 [FREESCALE]
; - 12号的铝制车身绘（ RAL 7032 ）
| 型号： | MC9S08LG32 |
| 厂家： | 
Freescale |
| 描述： |
|
| 文件： | 总51页 (文件大小：2553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08LG32
Rev. 7, 8/2009
MC9S08LG32 Series
Covers: MC9S08LG32 and
MC9S08LG16
MC9S08LG32
64-LQFP
80-LQFP
Case 840F
10 mm × 10 mm
Case 917A
14 mm × 14 mm
Features
48-LQFP
• 8-bit HCS08 Central Processor Unit (CPU)
– Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature
range of –40 °C to 85 °C and –40 °C to 105 °C
– HCS08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
Case 932
7 mm × 7mm
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes; eight deep FIFO
for storing change-of-flow addresses and event-only data;
debug module supports both tag and force breakpoints
• Peripherals
– 32 KB or 18 KB dual array flash; read/program/erase
over full operating voltage and temperature
– 1984 byte random access memory (RAM)
– Security circuitry to prevent unauthorized access to
RAM and flash contents
– LCD — Up to 4 × 41 or 8 × 37 LCD driver with internal
charge pump.
– ADC — Up to 16-channel, 12-bit resolution; 2.5 μs
conversion time; automatic compare function; temperature
sensor; internal bandgap reference channel; runs in stop3 and
can wake up the system; fully functional from 5.5 V to 2.7 V
– SCI — Full duplex non-return to zero (NRZ); LIN master
extended break generation; LIN slave extended break
detection; wakeup on active edge
– SPI — Full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave mode;
MSB-first or LSB-first shifting
– IIC — With up to 100 kbps with maximum bus loading;
multi-master operation; programmable slave address;
interrupt driven byte-by-byte data transfer; supports
broadcast mode and 10-bit addressing
– TPMx — One 6 channel and one 2 channel; selectable input
capture, output compare, or buffered edge or center-aligned
PWM on each channel
– MTIM — 8-bit counter with match register; four clock
sources with prescaler dividers; can be used for periodic
wakeup
– RTC — 8-bit modulus counter with binary or decimal based
prescaler; three clock sources including one external source;
can be used for time base, calendar, or task scheduling
functions
• Power-Saving Modes
– Two low-power stop modes (stop2 and stop3)
– Reduced-power wait mode
– Peripheral clock gating register can disable clocks to
unused modules, thereby reducing currents
– Low power on-chip crystal oscillator (XOSC) that can
be used in low-power modes to provide accurate clock
source to real time counter and LCD controller
– 100 μs typical wakeup time from stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution
and 2% deviation over temperature and voltage; supports
bus frequencies from 1 MHz to 20 MHz.
• System Protection
– COP reset with option to run from dedicated 1 kHz
internal clock or bus clock
– KBI — One keyboard control module capable of supporting
8 × 8 keyboard matrix
– Low-voltage warning with interrupt
– Low-voltage detection with reset
– IRQ — External pin for wakeup from low-power modes
• Input/Output
– Illegal opcode detection with reset
– Illegal address detection with reset
– 39, 53, or 69 GPIOs
– Flash and RAM protection
– 8 KBI and 1 IRQ interrupt with selectable polarity
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
• Package Options
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging (plus two more breakpoints
in on-chip debug module)
– 48-pin LQFP, 64-pin LQFP, and 80-pin LQFP
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1
2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 17.Internal Oscillator Deviation from Trimmed Frequency 25
Figure 18.ADC Input Impedance Equivalency Diagram. . . . . . . 26
Figure 19.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 21.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 22.Timer Input Capture Pulse. . . . . . . . . . . . . . . . . . . . . 30
Figure 23.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 32
Figure 24.SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . 32
Figure 25.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 33
Figure 26.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 33
Figure 27.4 MHz, Positive Polarity Pins 1 – 41 . . . . . . . . . . . . . 36
Figure 28.4 MHz, Positive Polarity Pins 42 – 80 . . . . . . . . . . . . 36
Figure 29.4 MHz, Negative Polarity Pins 1 – 41. . . . . . . . . . . . . 37
Figure 30.4 MHz, Negative Polarity Pins 42 – 80. . . . . . . . . . . . 37
Figure 31.Device Number Example for Auto Parts. . . . . . . . . . . 39
Figure 32.Device Number Example for IMM Parts. . . . . . . . . . . 39
Figure 33.80-pin LQFP Package Drawing (Case 917A, Doc
#98ASS23237W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .10
2.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .10
2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .11
2.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .12
2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .17
2.8 External Oscillator (XOSC) Characteristics . . . . . . . . .22
2.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .24
2.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.11.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .30
2.11.3 SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.12 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.14.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . .35
2.14.2 Conducted Transient Susceptibility . . . . . . . . . .35
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .39
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.1.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.1.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.1.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 34.64-pin LQFP Package Drawing (Case 840F, Doc
#98ASS23234W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 35.48-pin LQFP Package Drawing (Case 932, Doc
#98ASH00962A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3
4
List of Tables
Table 1. MC9S08LG32 Series Features by MCU and Package . 4
Table 2. Pin Availability by Package Pin-Count . . . . . . . . . . . . . . 8
Table 3. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 11
Table 5. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. ESD and Latch-Up Test Conditions. . . . . . . . . . . . . . . 12
Table 7. ESD and Latch-Up Protection Characteristics. . . . . . . 13
Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 17
Table 10.Oscillator Electrical Specifications (Temperature Range =
–40 °C to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . 22
5
List of Figures
Figure 1.MC9S08LG32 Series Block Diagram . . . . . . . . . . . . . . 3
Figure 2.80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3.64-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4.48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5.Typical Low-side Drive (sink) characteristics – High Drive
(PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 11.ICS Frequency Specifications (Temperature Range
=
–40 °C to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . 24
Figure 6.Typical Low-side Drive (sink) characteristics – Low Drive
(PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7.Typical High-side Drive (source) characteristics – High
Drive (PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8.Typical High-side Drive (source) characteristics – Low Drive
(PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9.Typical Run IDD for FBE Mode at 1 MHz. . . . . . . . . . . 19
Figure 10.Typical Run IDD for FBE Mode at 20 MHz . . . . . . . . . 20
Figure 11.Typical Run IDD for FEE Mode at 1 MHz . . . . . . . . . . 20
Figure 12.Typical Run IDD for FEE Mode at 20 MHz . . . . . . . . . 21
Figure 13.Typical Stop2 IDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14.Typical Stop3 IDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15.Typical Crystal or Resonator Circuit: High Range and Low
Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12.12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 25
Table 13.12-bit ADC Characteristics (VREFH = VDDAD, VREFL
VSSAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
=
Table 14.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16.SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17.LCD Electricals, 3 V Glass . . . . . . . . . . . . . . . . . . . . . 34
Table 18.Flash Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19.Radiated Emissions, Electric Field . . . . . . . . . . . . . . . 35
Table 20.Conducted Susceptibility, EFT/B . . . . . . . . . . . . . . . . . 35
Table 21.Susceptibility Performance Classification . . . . . . . . . . 38
Table 22.Device Numbering System . . . . . . . . . . . . . . . . . . . . . 38
Table 23.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 24.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 16.Typical Crystal or Resonator Circuit: Low Range/Low
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MC9S08LG32 Series Data Sheet, Rev. 7
2
Freescale Semiconductor
HCS08 CORE
LCD28/ADC5/TPMCLK/PTA7
LCD27/ADC4/TPM2CH1/KBI7/PTA6
LCD26/ADC3/TPM2CH0/KBI6/PTA5
ON-CHIP ICE (ICE) and
DEBUG MODULE (DBG
)
CPU
INT
LCD25/ADC2/RX2/KBI5/PTA4
LCD24/ADC1/TX2/KBI4/PTA3
LCD23/ADC0/SDA/PTA2
LCD22/SCL/PTA1
Real Time Counter
BKGD/MS
BKGD
BKP
(RTC)
LCD21/PTA0
TMRCLK
KBI[7:0]
Modulo Timer
MTIM
HCS08 SYSTEM CONTROL
LCD[40:37]/PTB[7:4]
LCD[32:29]/PTB[3:0]
(
)
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
8-BIT KEYBOARD
INTERRUPT (KBI
)
RESET/PTC6
BKGD/MS/PTC5
LCD[20:16]/PTC[4:0]
SS
SPSCK
MISO
RESET
IRQ
COP
SERIAL PERIPHERAL
INTERFACE (SPI
)
IRQ
LVD
MOSI
SCL
SDA
LCD[7:0]/PTD[7:0]
LCD[15:8]/PTE[7:0]
IIC MODULE (IIC
)
USER FLASH A
(LG32 = 16K BYTES)
(LG16 = 2K BYTES)
TPM2CH[5:0]
TPMCLK
6-CHANNEL TIMER/PWM
TPM2
(
)
USER FLASH B
(LG32 = 16K BYTES)
(LG16 = 16K BYTES)
TPM1CH[1:0]
TPMCLK
EXTAL/PTF7
XTAL/PTF6
TPM2CH3/KBI2/MOSI/PTF5
2-CHANNEL TIMER/PWM
TPM1
(
)
TxD1
RxD1
TPM2CH4/KBI1/MISO/PTF4
TPM2CH5/KBI0/SS/PTF3
ADC14/IRQ/TPM1CH1/SPSCK/PTF2
ADC13/TPM1CH0/RX1/PTF1
ADC12/TPM2CH2/KBI3/TX1/PTF0
SERIAL COMMUNICATIONS
INTERFACE (SCI1
USER RAM
1984 BYTES
)
TxD2
RxD2
SERIAL COMMUNICATIONS
INTERFACE (SCI2
)
INTERNAL CLOCK
LCD[44:41]/PTG[7:4]
LCD[36:33]/PTG[3:0]
Source (ICS
)
XTAL
EXTAL
LOW-POWER OSCILLATOR
TPM2CH4/KBI1/PTH7
ADC15/KBI0/TPM2CH5/PTH6
ADC11/TPM1CH0/KBI3/TX1/PTH5
ADC10/TPM1CH1/KBI2/RX1/PTH4
ADC[9:6]/KBI[7:4]/PTH[3:0]
12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC
V
LL3_2
AD[15:0]
VLL3
VLL1
)
LIQUID CRYSTAL
DISPLAY DRIVER
VLL2
VCAP1
VCAP2
SS/SCL/TPM2CH0/PTI5
(LCD)
SPSCK/SDA/TPM2CH1/PTI4
MOSI/TPM2CH2/PTI3
MISO/TPM2CH3/PTI2
TX2/TMRCLK/PTI1
RX2/PTI0
LCD[44:0]
VDD
VSS
VOLTAGE
REGULATOR
Available only on 80-pin package
Available only on 64-pin and 80-pin package
*/Default function out of reset/*
VSS2
VDDA/VREFH
VSSA/VREFL
Figure 1. MC9S08LG32 Series Block Diagram
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
3
Pin Assignments
Table 1. MC9S08LG32 Series Features by MCU and Package
Feature
MC9S08LG32
MC9S08LG16
Flash size (bytes)
RAM size (bytes)
Pin quantity
ADC
32,768
18,432
1984
48
80
64
64
48
16 ch
12 ch
9 ch
12 ch
9 ch
LCD
8 x 37
4 x 41
8 x 29
4 x 33
8 x 21
4 x 25
8 x 29
4 x 33
8 x 21
4 x 25
ICE + DBG
ICS
yes
yes
yes
IIC
IRQ
yes
KBI
8 pin
GPIOs
RTC
69
53
39
53
39
yes
yes
yes
yes
yes
2
MTIM
SCI1
SCI2
SPI
TPM1 channels
TPM2 channels
XOSC
6
yes
1
Pin Assignments
This section shows the pin assignments for the MC9S08LG32 series devices. The priority of functions on a pin is in ascending
order from left to right and bottom to top. Another view of pinouts and function priority is given in Table 2.
MC9S08LG32 Series Data Sheet, Rev. 7
4
Freescale Semiconductor
Pin Assignments
PTC4/LCD20
PTA0/LCD21
PTG2/LCD35
PTG3/LCD36
PTA1/SCL/LCD22
PTA2/SDA/ADC0/LCD23
PTA3/KBI4/TX2/ADC1/LCD24
PTA4/KBI5/RX2/ADC2/LCD25
PTA5/KBI6/TPM2CH0/ADC3/LCD26
PTA6/KBI7/TPM2CH1/ADC4/LCD27
PTA7/TPMCLK/ADC5/LCD28
PTC5/BKGD/MS
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTB3/LCD32
PTB2/LCD31
PTB7/LCD40
PTB6/LCD39
PTB5/LCD38
PTB4/LCD37
PTB1/LCD30
PTB0/LCD29
PTD1/LCD1
PTD0/LCD0
VCAP1
1
2
3
4
5
6
7
8
9
80-Pin LQFP
10
11
12
13
14
15
16
17
18
19
20
PTC6/RESET
PTH0/KBI4/ADC6
PTH1/KBI5/ADC7
PTH2KBI6/ADC8
PTH3/KBI7/ADC9
PTH4/RX1/KBI2/TPM1CH1/ADC10
PTH5/TX1/KBI3/TPM1CH0/ADC11
PTF3/SS/KBI0/TPM2CH5
VCAP2
VLL1
VLL2
Figure 2. 80-Pin LQFP
NOTE
V
/V
are internally connected to V
/V
.
REFH REFL
DDA SSA
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
5
Pin Assignments
PTC4/LCD20
PTA0/LCD21
PTG2/LCD35
PTG3/LCD36
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTB3/LCD32
PTB2/LCD31
PTB1/LCD30
PTB0/LCD29
PTD1/LCD1
PTD0/LCD0
VCAP1
1
2
3
4
5
6
7
8
PTA1/SCL/LCD22
PTA2/SDA/ADC0/LCD23
PTA3/KBI4/TX2/ADC1/LCD24
PTA4/KBI5/RX2/ADC2/LCD25
PTA5/KBI6/TPM2CH0/ADC3/LCD26
PTA6/KBI7/TPM2CH1/ADC4/LCD27
PTA7/TPMCLK/ADC5/LCD28
PTC5/BKGD/MS
64-Pin LQFP
9
10
11
12
13
14
15
16
PTC6/RESET
PTH4/RX1/KBI2/TPM1CH1/ADC10
PTH5/TX1/KBI3/TPM1CH0/ADC11
PTF3/SS/KBI0/TPM2CH5
VCAP2
VLL1
VLL2
Figure 3. 64-Pin LQFP
NOTE
V
/V
are internally connected to V
/V
.
REFH REFL
DDA SSA
MC9S08LG32 Series Data Sheet, Rev. 7
6
Freescale Semiconductor
Pin Assignments
37
48
47 46 45 44 43 42 41 40 39 38
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTC4/LCD20
PTA0/LCD21
1
36
35
34
33
2
3
4
5
6
7
8
9
PTA1/SCL/LCD22
PTA2/SDA/ADC0/LCD23
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
32
31
30
29
28
27
26
PTA3/KBI4/TX2/ADC1/LCD24
PTA4/KBI5/RX2/ADC2/LCD25
48-Pin LQFP
PTD1/LCD1
PTD0/LCD0
VCAP1
PTA5/KBI6/TPM2CH0/ADC3/LCD26
PTA6/KBI7/TPM2CH1/ADC4/LCD27
PTA7/TPMCLK/ADC5/LCD28
10
11
VCAP2
VLL1
PTC5/BKGD/MS
PTC6/RESET
PTF3/SS/KBI0/TPM2CH5
25
VLL2
12
19 20 21 22 23
14 15
17 18
16
24
13
Figure 4. 48-Pin LQFP
NOTE
V
/V
are internally connected to V
/V
.
REFH REFL
DDA SSA
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
7
Pin Assignments
Table 2. Pin Availability by Package Pin-Count
Packages
64
<-- Lowest Priority --> Highest
80
48
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
1
1
1
PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTB3
PTB2
PTB7
PTB6
PTB5
PTB4
PTB1
PTB0
PTD1
PTD0
VCAP1
VCAP2
VLL1
LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD32
LCD31
LCD40
LCD39
LCD38
LCD37
LCD30
LCD29
LCD1
LCD0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADC14
2
2
2
—
3
3
3
—
—
4
4
4
—
—
5
5
5
—
—
6
6
6
—
—
7
7
—
—
—
—
—
—
—
—
7
—
—
8
8
—
—
9
—
—
—
—
9
—
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
—
—
—
—
—
—
—
—
10
11
12
13
14
15
16
17
18
19
20
21
—
—
—
—
22
23
24
25
26
27
28
29
30
—
—
—
—
8
—
—
9
—
—
10
11
12
13
14
15
—
—
—
—
—
—
—
16
17
18
19
20
21
—
22
—
—
—
—
—
—
VLL2
—
—
—
VLL3
—
—
—
PTF5
PTF4
PTI5
MOSI
MISO
TPM2CH0
TPM2CH1
TPM2CH2
TPM2CH3
TMRCLK
RX2
KBI2
KBI1
SCL
SDA
MOSI
MISO
TX2
—
TPM2CH3
TPM2CH4
SS
SPSCK
—
PTI4
PTI3
PTI2
—
PTI1
—
PTI0
—
PTH7
VSS
KBI1
TPM2CH4
—
—
—
—
VDD
—
—
—
PTF7
PTF6
VDDA
VSSA
PTH6
PTF2
EXTAL
XTAL
—
—
—
—
VREFH
VREFL
TPM2CH5
SPSCK
—
—
—
—
KBI0
TPM1CH1
ADC15
IRQ
MC9S08LG32 Series Data Sheet, Rev. 7
8
Freescale Semiconductor
Pin Assignments
Table 2. Pin Availability by Package Pin-Count (continued)
Packages
64
<-- Lowest Priority --> Highest
80
48
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
31
32
33
34
35
—
—
—
—
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
—
—
—
—
57
58
59
60
23
24
25
—
—
—
—
—
—
26
27
28
29
30
31
32
33
34
—
—
35
36
37
38
39
40
41
42
—
—
—
—
—
—
—
—
43
44
PTF1
PTF0
PTF3
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
PTC6
PTC5
PTA7
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTG3
PTG2
PTA0
PTC4
PTC3
PTC2
PTC1
PTC0
PTE7
PTE6
VSS2
RX1
TX1
TPM1CH0
KBI3
KBI0
KBI3
KBI2
ADC9
ADC8
ADC7
ADC6
—
ADC13
—
ADC12
—
TPM2CH2
SS
TPM2CH5
TX1
TPM1CH0
ADC11
ADC10
—
RX1
TPM1CH1
—
KBI7
KBI6
—
—
KBI5
—
—
KBI4
—
—
RESET
BKGD/MS
TPMCLK
KBI7
—
—
—
—
—
ADC5
TPM2CH1
TPM2CH0
RX2
TX2
ADC0
LCD22
—
LCD28
ADC4
ADC3
ADC2
ADC1
LCD23
—
—
LCD27
LCD26
LCD25
LCD24
—
KBI6
KBI5
KBI4
SDA
SCL
—
LCD36
LCD35
LCD21
LCD20
LCD19
LCD18
LCD17
LCD16
LCD15
LCD14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VLL3_2
PTG7
PTG6
PTG5
PTG4
PTG1
PTG0
PTE5
PTE4
—
—
—
—
LCD44
LCD43
LCD42
LCD41
LCD34
LCD33
LCD13
LCD12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
9
Electrical Characteristics
Packages
Table 2. Pin Availability by Package Pin-Count (continued)
<-- Lowest Priority --> Highest
80
64
48
Port Pin
Alt 1
Alt 2
Alt 3
Alt 4
77
78
79
80
61
62
63
64
45
46
47
48
PTE3
PTE2
PTE1
PTE0
LCD11
LCD10
LCD9
—
—
—
—
—
—
—
—
—
—
—
—
LCD8
2
Electrical Characteristics
2.1
Introduction
This section contains electrical and timing specifications for the MC9S08LG32 series of microcontrollers available at the time
of publication.
2.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3. Parameter Classifications
Those parameters are guaranteed during production testing on each individual device.
P
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
Those parameters are derived mainly from simulations.
D
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
2.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry that protects against damage due to high static voltage or electrical fields. However, it is advised
that normal precautions should be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ) or the programmable pull-up resistor associated with the pin is enabled.
SS
DD
MC9S08LG32 Series Data Sheet, Rev. 7
10
Freescale Semiconductor
Electrical Characteristics
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
ID
–0.3 to +5.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
Instantaneous maximum current
±25
±2
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages and use the largest of the two resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in an external power supply going
out of regulation. Ensure that the external VDD load will shunt current greater than maximum
injection current, this will be of greater risk when the MCU is not consuming power. For instance,
If no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
2.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take P into account in power calculations, determine
I/O
the difference between actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of
SS
DD
unusually high pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 5. Thermal Characteristics
Symbol
Rating
Value
Unit
Operating temperature range
(packaged)
TA
TL to TH
–40 to +105
°C
Maximum junction temperature
TJ
125
°C
Thermal resistance
Single-layer board
80-pin LQFP
θJA
61
71
80
°C/W
64-pin LQFP
48-pin LQFP
Thermal resistance
Four-layer board
80-pin LQFP
θJA
48
52
56
°C/W
64-pin LQFP
48-pin LQFP
The average chip-junction temperature (T ) in °C can be obtained from:
J
T = T + (P × θ )
JA
Eqn. 1
J
A
D
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
11
Electrical Characteristics
where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
DD DD
= Power dissipation on input and output pins — user determined
int
I/O
For most applications, P << P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
P = K ÷ (T + 273 °C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
K = P × (T + 273 °C) + θ × (P )
2
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving Equation 1 and Equation 2 iteratively
A
D
J
for any value of T .
A
2.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for automotive grade integrated circuits. During the
device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge
device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 6. ESD and Latch-Up Test Conditions
Model
Description
Symbol
Value
Unit
Human Body Series resistance
R1
C
1500
100
3
Ω
pF
—
V
Model
Storage capacitance
Number of pulses per pin
—
—
—
Latch-up
Minimum input voltage limit
Maximum input voltage limit
–2.5
7.5
V
MC9S08LG32 Series Data Sheet, Rev. 7
12
Freescale Semiconductor
Electrical Characteristics
Unit
Table 7. ESD and Latch-Up Protection Characteristics
No.
Rating1
Symbol
Min
Max
1
2
3
Human body model (HBM)
Charge device model (CDM)
Latch-up current at TA = 85 °C
VHBM
VCDM
ILAT
2500
750
—
—
—
V
V
±100
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
2.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
2
— Operating Voltage
—
2.7
—
5.5
V
V
P Output high voltage — Low Drive (PTxDSn = 0)
VOH
5 V, ILoad = –2 mA
3 V, ILoad = –0.6 mA
VDD – 0.8
VDD – 0.8
—
—
—
—
Output high voltage — High Drive (PTxDSn = 1) V
5 V, ILoad = –10 mA
3 V, ILoad = –3 mA
VDD – 0.8
VDD – 0.8
—
—
—
—
3
P Output low voltage — Low Drive (PTxDSn = 0)
VOL
—
V
5 V, ILoad = 2 mA
3 V, ILoad = 0.6 mA
—
—
0.8
0.8
Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 10 mA
3 V, ILoad = 3 mA
—
—
0.8
0.8
4
5
P Output high current — Max total IOH for all ports
IOHT
—
—
—
mA
mA
5 V
3 V
100
60
C Output high current — Max total IOL for all ports
IOLT
—
5 V
3 V
100
60
6
7
8
9
P Bandgap voltage reference
VBG
VIH
VIL
—
0.65 x VDD
—
1.225
—
—
V
V
P Input high voltage; all digital inputs
P Input low voltage; all digital inputs
P Input hysteresis; all digital inputs
—
—
0.35 x VDD
V
Vhys
|IIn|
0.06 x VDD
—
—
—
1
mV
μA
10 P Input leakage current; input only pins2
0.1
VIn = VDD or VSS
VIn = VDD or VSS
11 P High impedence (off-state) leakage current
|IOZ
|
—
0.1
1
μA
12 P Internal pullup resistors3
13 P Internal pulldown resistors4
RPU
RPD
20
20
45
45
65
65
kΩ
kΩ
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
13
Electrical Characteristics
Num C
Table 8. DC Characteristics (continued)
Characteristic
Symbol
Min
Typ1
Max
Unit
14 D DC injection
current 5, 6, 7
VIN < VSS, VIN
VDD
Single pin limit
IIC
—
—
—
—
2
mA
mA
Total MCU limit, includes sum of
all stressed pins
25
>
15 C Input Capacitance, all non-supply pins
16 C RAM retention voltage
CIn
—
2
—
—
8
pF
V
VRAM
VPOR
tPOR
—
2.0
—
17 P POR rearm voltage
0.9
10
1.4
—
V
18 D POR rearm time
μs
V
19 P Low-voltage detection threshold — high range
VLVD1
VDD falling
VDD rising
3.9
4.0
4.0
4.1
4.1
4.2
20 P Low-voltage detection threshold — low range
21 P Low-voltage warning threshold — high range 1
22 P Low-voltage warning threshold — high range 0
23 P Low-voltage warning threshold — low range 1
24 P Low-voltage warning threshold — low range 0
25 P Low-voltage inhibit reset/recover hysteresis
VLVD0
VLVW3
VLVW2
VLVW1
VLVW0
Vhys
V
V
V
DD falling
2.48
2.54
2.56
2.62
2.64
2.70
VDD rising
VDD falling
4.5
4.6
4.6
4.7
4.7
4.8
VDD rising
V
VDD falling
VDD rising
4.2
4.3
4.3
4.4
4.4
4.5
V
VDD falling
2.84
2.90
2.92
2.98
3.00
3.06
VDD rising
V
VDD falling
2.66
2.72
2.74
2.80
2.82
2.88
VDD rising
—
—
mV
5 V
3 V
100
60
1
2
3
4
5
6
Typical values are measured at 25 °C. Characterized, not tested
Measured with VIn = VDD or VSS.
Measured with VIn = VSS.
Measured with VIn = VDD.
All functional non-supply pins, except for PTC6 are internally clamped to VSS and VDD
.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
7
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. For instance, if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
MC9S08LG32 Series Data Sheet, Rev. 7
14
Freescale Semiconductor
Electrical Characteristics
Typical VOL vs. IOL AT VDD = 5V
Typical VOL vs. IOL AT VDD = 3V
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
Hot (105°C)
Room (25°C)
Cold (-40°C)
Hot (105°C)
Room (25°C)
Cold (-40°C)
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOL (mA)
IOL (mA)
Figure 5. Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1)
Typical VOL vs. IOL AT VDD = 5V
Typical VOL vs. IOL AT VDD = 3V
0.90
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
Hot (105°C)
Hot (105°C)
Room (25°C)
Cold (-40°C)
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
Room(25°C)
Cold (-40°C)
0
1
2
3
0
1
2
3
4
5
IOL (mA)
IOL (mA)
Figure 6. Typical Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0)
Typical VDD - VOH vs. IOH AT VDD = 5V
Typical VDD - VOH vs. IOH AT VDD=3V
1.2
0.8
Hot (105°C)
Hot (105°C)
1.0
0.8
0.6
0.4
0.2
0.0
Room (25°C)
Cold (-40°C)
Room (25°C)
Cold (-40°C)
0.6
0.4
0.2
0.0
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
0
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13
IOH (mA)
IOH (mA)
Figure 7. Typical High-side Drive (source) characteristics – High Drive (PTxDSn = 1)
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
15
Electrical Characteristics
Typical VDD - VOH vs. IOH AT VDD=3V
Typical VDD - VOH vs. IOH AT VDD = 5V
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Hot (105°C)
Room (25°C)
Cold (-40°C)
Hot (105°C)
Room (25°C)
Cold (-40°C)
0
-1
-2
-3
-4
-5
0
-1
-2
-3
IOH (mA)
IOH (mA)
Figure 8. Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0)
MC9S08LG32 Series Data Sheet, Rev. 7
16
Freescale Semiconductor
Electrical Characteristics
2.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
VDD
(V)
Bus
Temp
Typ1
Num
C
Parameter
Run supply current
Symbol
Max
Unit
Freq
(°C)
1
C
C
C
C
P
P
C
C
T
T
T
T
T
T
T
T
T
T
T
T
P
P
T
T
C
C
P
P
C
C
P
P
RIDD
20 MHz
1 MHz
20 MHz
1 MHz
20 MHz
1 MHz
20 MHz
1 MHz
20 MHz
1 MHz
20 MHz
1 MHz
n/a
3
5
3
5
3
5
16.38
27.85
28.05
2.84
mA
mA
mA
mA
mA
mA
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
–40 °C to 85 °C
–40 °C to105 °C
FEI mode, all modules on
1.67
16.55
1.77
11.9
1.16
12.68
1.4
2.87
28.14
28.35
3.01
3.05
2
Run supply current
FEI mode, all modules off
RIDD
20.25
21.72
1.95
1.98
21.56
23.12
2.39
2.41
3
Wait mode supply current
FEI mode, all modules off
WIDD
7.9
13.42
13.59
1.49
0.88
8.13
1.12
1.1
1.51
13.81
13.98
1.91
1.94
4
5
Stop2 mode supply current
S2IDD
3
5
3
5
16.0
μA
μA
μA
μA
39.0
1.2
18.7
46.1
Stop3 mode supply current
No clocks active
S3IDD
n/a
1.2
22.4
56.2
1.32
25.5
63.9
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
17
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
VDD
(V)
Bus
Temp
Typ1
Num
C
Parameter
Stop2 adders: RTC using LPO
Symbol
Max
Unit
Freq
(°C)
6
T
—
n/a
3
5
3
5
210
—
—
nA
–40 °C to 105 °C
RTC using low
power crystal
oscillator
4.25
μA
LCD2 with rbias
(Low Gain)
1.23
184
—
—
LCD2 with rbias
(High Gain)
LCD2 with Cpump
4.053
210
—
—
—
–40 °C to 85 °C
–40 °C to 105 °C
RTC using LPO
nA
RTC using low
power crystal
oscillator
4.22
μA
LCD2 with rbias
(Low Gain)
1.53
324
—
—
LCD2 with rbias
(High Gain)
LCD2 with Cpump
7.123
210
—
—
—
–40 °C to 85 °C
–40 °C to 105 °C
7
T
Stop3 adders:
RTC using LPO
—
n/a
nA
RTC using low
power crystal
oscillator
4.75
μA
LCD2 with rbias
(Low Gain)
1.23
184
—
—
LCD2 with rbias
(High Gain)
LCD2 with Cpump
4.353
230
—
—
—
–40 °C to 85 °C
–40 °C to 105 °C
RTC using LPO
nA
RTC using low
power crystal
oscillator
4.74
μA
LCD2 with rbias
(Low Gain)
1.53
324
—
—
—
LCD2 with rbias
(High Gain)
LCD2 with Cpump
7.493
–40 °C to 85 °C
MC9S08LG32 Series Data Sheet, Rev. 7
18
Freescale Semiconductor
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
VDD
(V)
Bus
Temp
Typ1
Num
C
Parameter
Stop3 adders: EREFSTEN = 1
Symbol
Max
Unit
Freq
(°C)
8
T
—
n/a
3
4.58
71.7
—
—
—
—
—
—
μA
–40 °C to 105 °C
IREFSTEN = 1
LVD
94.35
4.61
EREFSTEN = 1
IREFSTEN = 1
LVD
5
μA
71.69
107.34
1
2
3
4
Typical values are measured at 25 °C. Characterized, not tested.
LCD configured for Charge Pump Enabled VLL3 connected to VDD..
This does not include current required for 32 kHz oscillator.
This is the maximum current when all LCD inputs/outputs are used.
IDD
VDD
Figure 9. Typical Run I for FBE Mode at 1 MHz
DD
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
19
Electrical Characteristics
IDD
VDD
Figure 10. Typical Run I for FBE Mode at 20 MHz
DD
IDD
VDD
Figure 11. Typical Run I for FEE Mode at 1 MHz
DD
MC9S08LG32 Series Data Sheet, Rev. 7
20
Freescale Semiconductor
Electrical Characteristics
IDD
VDD
Figure 12. Typical Run I for FEE Mode at 20 MHz
DD
IDD
VDD
Figure 13. Typical Stop2 I
DD
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
21
Electrical Characteristics
IDD
VDD
Figure 14. Typical Stop3 I
DD
2.8
External Oscillator (XOSC) Characteristics
Table 10. Oscillator Electrical Specifications (Temperature Range = –40 °C to 105 °C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
D
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
• Low range (RANGE = 0)
flo
fhi
fhi-hgo
fhi-lp
32
1
1
—
—
—
—
38.4
5
16
8
kHz
MHz
MHz
MHz
• High range (RANGE = 1) FEE or FBE mode2
• High range (RANGE = 1, HGO = 1) BLPE mode
• High range (RANGE = 1, HGO = 0) BLPE mode
1
2
D
Load capacitors
C1
C2
See crystal or resonator
manufacturer’s recommendation.
MC9S08LG32 Series Data Sheet, Rev. 7
22
Freescale Semiconductor
Electrical Characteristics
Table 10. Oscillator Electrical Specifications (Temperature Range = –40 °C to 105 °C Ambient) (continued)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
3
D
Feedback resistor
RF
MΩ
• Low range (32 kHz to 100 kHz)
• High range (1 MHz to 16 MHz)
—
—
10
1
—
—
4
5
D
D
Series resistor
• Low range, low gain (RANGE = 0, HGO = 0)
• Low range, high gain (RANGE = 0, HGO = 1)
RS
RS
kΩ
kΩ
0
100
Series resistor
• High range, low gain (RANGE = 1, HGO = 0)
• High range, high gain (RANGE = 1, HGO = 1)
≥8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
6
7
T
Crystal start-up time3, 4
• Low range (HGO = 0)
• Low range (HGO = 1)
• High range (HG0 = 0)5
• High range (HG0 = 1)5
ms
tCSTL-LP
tCSTL-HGO
tCSTH-LP
—
—
—
—
500
3570
4
—
—
—
—
tCSTH-HGO
4
D
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
fextal
MHz
• FEE or FBE mode2
• BLPE mode
0.03125
0
—
—
5
40
1
2
Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz
to 39.0625 kHz.
3
4
5
This parameter is characterized and not tested on each device.
Proper PC board layout procedures must be followed to achieve specifications.
4 MHz crystal
XOSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
23
Electrical Characteristics
XOSC
EXTAL
XTAL
Crystal or Resonator
Figure 16. Typical Crystal or Resonator Circuit: Low Range/Low Power
2.9
Internal Clock Source (ICS) Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = –40 °C to 105 °C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
P
Average internal reference frequency — factory trimmed
fint_ft
—
32.768
—
kHz
at VDD = 5.0 V and temperature = 25 °C
2
3
4
C
C
P
P
P
P
Average internal reference frequency — user trimmed
Internal reference start-up time
fint_t
tIRST
fdco_t
31.25
—
—
60
39.0625 kHz
100
20
40
—
μs
DCO output frequency range — Low range (DRS = 00)
16
—
MHz
trimmed2
Mid range (DRS = 01)
32
—
5
DCO output frequency2
Reference = 32768 Hz
and
Low range (DRS = 00) fdco_DMX32
Mid range (DRS = 01)
—
19.92
39.85
MHz
—
—
DMX32 = 1
6
7
8
9
C
C
C
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)3
Δfdco_res_t
Δfdco_res_t
Δfdco_t
—
—
—
—
±0.1
±0.2
±0.2
±0.4
±2
%fdco
%fdco
%fdco
%fdco
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)3
Total deviation of trimmed DCO output frequency over
voltage and temperature3
–1.0
to +0.5
Total deviation of trimmed DCO output frequency over
Δfdco_t
±0.5
±1
fixed voltage and temperature range of 0 °C to 70 °C3
10
11
C
C
FLL acquisition time3, 4
tAcquire
CJitter
—
—
—
1
mS
Long term jitter of DCO output clock (averaged over 2 ms
interval)5
0.02
0.2
%fdco
1
2
3
4
Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This parameter is characterized and not tested on each device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
5
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter percentage
for a given interval.
MC9S08LG32 Series Data Sheet, Rev. 7
24
Freescale Semiconductor
Electrical Characteristics
65.00
60.00
55.00
50.00
45.00
40.00
35.00
30.00
25.00
20.00
ICS Trim values
-40°C
25°C
110°C
Figure 17. Internal Oscillator Deviation from Trimmed Frequency
2.10 ADC Characteristics
Table 12. 12-bit ADC Operating Conditions
Characteristic
Conditions
Absolute
Symb
Min
Typ1
Max
Unit
Comment
Supply voltage
VDDAD
2.7
—
0
5.5
V
—
—
Delta to VDD
ΔVDDAD
–100
+100
mV
2
(VDD – VDDAD
)
Ground voltage Delta to VSS
(VSS – VSSAD
ΔVSSAD
VREFH
VREFL
–100
—
0
+100
—
mV
V
—
2
)
Ref Voltage
High
—
—
—
—
VREFH shorted to
VDDAD
Ref Voltage
Low
—
—
V
VREFLshorted to
VSSAD
Input Voltage
—
—
VADIN
CADIN
VREFL
—
—
VREFH
5.5
V
—
—
Input
4.5
pF
Capacitance
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
25
Electrical Characteristics
Characteristic
Table 12. 12-bit ADC Operating Conditions (continued)
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Input
—
RADIN
—
5
7
kΩ
—
Resistance
Analog Source
Resistance
12-bit mode
RAS
kΩ
External to MCU
f
ADCK > 4MHz
—
—
—
—
2
5
fADCK < 4MHz
10-bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
5
10
8-bit mode (all valid fADCK
High Speed (ADLPC = 0)
Low Power (ADLPC = 1)
)
—
—
—
—
10
8.0
4.0
ADC
Conversion
Clock Freq.
fADCK
0.4
0.4
MHz
—
1
2
Typical values assume VDDAD = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
DC potential difference.
SIMPLIFIED
INPUT PIN EQUIVALENT
Z
CIRCUIT
ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
Z
AS
leakage
due to
ADC SAR
ENGINE
input
protection
R
R
AS
ADIN
+
V
ADIN
–
C
AS
V
+
–
AS
R
R
R
ADIN
ADIN
ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C
ADIN
Figure 18. ADC Input Impedance Equivalency Diagram
MC9S08LG32 Series Data Sheet, Rev. 7
26
Freescale Semiconductor
Electrical Characteristics
Table 13. 12-bit ADC Characteristics (V
= V
, V
= V
)
SSAD
REFH
DDAD REFL
Num
C
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
1
T
Supply Current
ADLPC = 1
ADLSMP = 1
ADCO = 1
—
IDDAD
IDDAD
IDDAD
IDDAD
—
195
—
—
—
1
μA
—
2
3
4
T
T
P
Supply Current
ADLPC = 1
ADLSMP = 0
ADCO = 1
—
—
—
—
—
—
347
407
μA
μA
—
—
—
—
Supply Current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply Current
ADLPC = 0
ADLSMP = 0
ADCO = 1
0.755
mA
5
6
—
P
Supply Current Stop, Reset, Module Off
IDDAD
0.011
3.3
2
1
5
μA
ADC
Asynchronous
Clock Source
High Speed (ADLPC=0)
Low Power (ADLPC=1)
fADACK
2
MHz
tADACK =
1/fADACK
1.25
3.3
7
8
C
C
Conversion
Time(Including
sample time)
Short sample (ADLSMP=0)
Long sample (ADLSMP=1)
tADC
—
—
20
40
—
—
ADCK
cycles
See ADC
chapter in the
LG32
Reference
Manual for
conversion
time variances
Sample Time
Short sample (ADLSMP=0)
Long sample (ADLSMP=1)
tADS
—
—
3.5
—
—
ADCK
cycles
23.5
9
T
P
T
T
P
T
T
P
T
T
P
T
Total
Unadjusted
Error
12-bit mode
10-bit mode
8-bit mode
12-bit mode
10-bit mode3
8-bit mode3
12-bit mode
10-bit mode
8-bit mode
12-bit mode
10-bit mode
8-bit mode
ETUE
DNL
INL
—
—
—
—
—
—
—
—
—
—
—
—
±3.0
±1
—
±2.5
±1
LSB2
LSB2
LSB2
LSB2
Includes
quantization
±0.5
±1.75
±0.5
±0.3
±1.5
±0.5
±0.3
±1.5
±0.5
±0.5
10
11
12
Differential
Non-Linearity
—
±1.0
±0.5
—
Integral
Non-Linearity
±1
±0.5
—
Zero-Scale
Error
EZS
VADIN = VSSAD
±1.5
±0.5
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
27
Electrical Characteristics
Table 13. 12-bit ADC Characteristics (V
= V
, V
= V
) (continued)
SSAD
REFH
DDAD REFL
Num
C
Characteristic
Conditions
12-bit mode
Symb
EFS
Min
Typ1
Max
Unit
Comment
13
T
P
T
D
Full-Scale
Error
—
—
—
—
—
—
—
—
—
—
—
—
±1
—
±1
LSB2
VADIN = VDDAD
10-bit mode
8-bit mode
12-bit mode
10-bit mode
8-bit mode
12-bit mode
10-bit mode
8-bit mode
–40 °C to 25 °C
25 °C to 125°C
25 °C
±0.5
±0.5
±0.5
—
14
15
Quantization
Error
EQ
–1 to 0
—
LSB2
LSB2
—
±0.5
±0.5
—
—
D
Input Leakage
Error
EIL
±1
Padleakage4 *
RAS
±0.2
±0.1
1.646
1.769
701.2
±2.5
±1
16
17
C
C
Temp Sensor
Slope
m
—
mV/°C
—
—
—
Temp Sensor
Voltage
VTEMP25
—
mV
1
Typical values assume VDDAD = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only
and are not tested in production.
2
3
4
1 LSB = (VREFH – VREFL)/2N
Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
Based on input pad leakage current. Refer to pad electricals.
MC9S08LG32 Series Data Sheet, Rev. 7
28
Freescale Semiconductor
Electrical Characteristics
2.11 AC Characteristics
This section describes timing characteristics for each peripheral system.
2.11.1 Control Timing
Table 14. Control Timing
Num
C
Rating
Symbol
Min
Typ1
Max
Unit
1
2
3
4
5
D
D
D
D
D
Bus frequency (tcyc = 1/fBus
)
Internal low power oscillator period
External reset pulse width2
Reset low drive
fBus
tLPO
dc
700
—
—
—
—
—
20
1300
—
MHz
μs
textrst
trstdrv
tMSSU
100
ns
66 x tcyc
500
—
ns
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
—
ns
6
7
D
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
—
—
μs
IRQ pulse width
ns
Asynchronous path2
Synchronous path4
tILIH
tIHIL
100
1.5 x tcyc
—
—
—
—
8
9
D
C
Keyboard interrupt pulse width
Asynchronous path2
ns
ns
tILIH
tIHIL
100
1.5 x tcyc
—
—
—
—
Synchronous path4
Port rise and fall time — (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise
tFall
—
—
3
30
—
—
1
2
3
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5
6
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 105 °C.
Except for LCD pins in Open Drain mode.
textrst
RESET PIN
Figure 19. Reset Timing
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
29
Electrical Characteristics
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 20. IRQ/KBIPx Timing
2.11.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 15. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TPMCLK
tclkl
Figure 21. Timer External Clock
t
ICPW
TPMCHn
TPMCHn
t
ICPW
Figure 22. Timer Input Capture Pulse
MC9S08LG32 Series Data Sheet, Rev. 7
30
Freescale Semiconductor
Electrical Characteristics
2.11.3 SPI Timing
Table 16 and Figure 23 through Figure 26 describe the timing requirements for the SPI system.
Table 16. SPI Timing
No.
C
Function
Operating frequency
Symbol
Min
Max
Unit
—
D
fop
Hz
Master
Slave
fBus/2048
0
fBus/2
fBus/4
D
D
D
D
D
D
SPSCK period
Master
Slave
tSPSCK
tLead
tLag
1
2
3
4
5
6
2
4
2048
—
tcyc
tcyc
Enable lead time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
D
D
D
Slave access time
ta
tdis
tv
—
1
tcyc
7
8
9
Slave MISO disable time
—
1
tcyc
Data valid (after SPSCK edge)
Master
Slave
—
—
25
25
ns
ns
D
D
D
Data hold time (outputs)
Master
Slave
tHO
10
11
12
0
0
—
—
ns
ns
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
31
Electrical Characteristics
SS1
(OUTPUT)
1
2
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MS BIN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 23. SPI Master Timing (CPHA = 0)
SS1
(OUTPUT)
1
2
11
12
3
12
11
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
10
BIT 6 . . . 1
LSB IN
9
MOSI
(OUTPUT)
MASTER MSB OUT2
PORT DATA
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 24. SPI Master Timing (CPHA =1)
MC9S08LG32 Series Data Sheet, Rev. 7
32
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
11
12
3
1
12
11
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
10
9
10
MISO
(OUTPUT)
SEE
NOTE 1
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
SLAVE
6
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received.
Figure 25. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
12
2
11
SPSCK
(CPOL = 0)
(INPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(INPUT)
9
10
c
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE MSB OUT
NOTE 1
o
6
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received
Figure 26. SPI Slave Timing (CPHA = 1)
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
33
Electrical Characteristics
2.12 LCD Specifications
Table 17. LCD Electricals, 3 V Glass
C
Characteristic
VLL3 Supply Voltage
Symbol
Min
Typ
Max
Units
D
D
D
D
D
VLL3
fFrame
CLCD
2.7
28
—
—
—
—
30
5.5
64
V
LCD Frame Frequency
Hz
pF
LCD Charge Pump Capacitance
LCD Bypass Capacitance
LCD Glass Capacitance
100
100
2000
100
100
8000
CBYLCD
Cglass
2.13 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
Program and erase operations do not require any special power sources other than the normal V supply. For more detailed
DD
information about program/erase operations, see the Memory section.
Table 18. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
–40 °C to 85 °C
D
Vprog/erase
VRead
fFCLK
2.7
2.7
150
5
5.5
5.5
V
D
D
D
C
C
C
C
D
D
Supply voltage for read operation
Internal FCLK frequency1
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
Page erase time2
Mass erase time2
Byte program current3
Page erase current3
V
200
6.67
kHz
μs
tFcyc
tprog
9
tFcyc
tFcyc
tFcyc
tFcyc
mA
mA
tBurst
4
4000
20,000
4
tPage
tMass
RIDDBP
RIDDPE
—
—
—
—
6
Program/erase endurance4
TL to TH = –40 °C to + 85 °C
T = 25 °C
C
10,000
15
—
100,000
—
—
cycles
years
C
Data retention5
tD_ret
100
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3
4
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures
with VDD = 5.0 V, bus frequency = 4.0 MHz.
Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
MC9S08LG32 Series Data Sheet, Rev. 7
34
Freescale Semiconductor
Electrical Characteristics
2.14 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
2.14.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 19. Radiated Emissions, Electric Field
Level1
Parameter
Symbol
Conditions
Frequency
fOSC/fBUS
Unit
(Max)
Radiated emissions,
electric field
VRE_TEM
VDD = 5.5
TA = +25 oC
Package type =
80 LQFP
0.15 – 50 MHz
50 – 150 MHz
150 – 500 MHz
500 – 1000 MHz
IEC Level
4 MHz crystal
16 MHz bus
10
14
8
dBμV
5
L
—
—
SAE Level
2
1
Data based on qualification test results.
2.14.2 Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 20.
Table 20. Conducted Susceptibility, EFT/B
Amplitude1
Parameter
Symbol
Conditions
fOSC/fBUS Result
Unit
(Min)
Conducted susceptibility, electrical VCS_EFT
fast transient/burst (EFT/B)
VDD = 5.5
TA = +25 oC
Package type = 80-pin LQFP
4 kHz crystal
4 MHz bus
A
B
C
D
>4.02
>4.03
>4.04
>4.0
kV
1
Data based on qualification test results. Not tested in production.
Exceptions as covered in footnotes 3 and 4.
2
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
35
Electrical Characteristics
3
Except pins PHT1, PTH2, PTH3, PTH4, PTH5. See figures below for values.
4
Except pins PTF3, PTH5, PTH4, PHT0, Reset, and BKGD. See figures below for values.
Individual performance of each pin is shown in Figure 27, Figure 28, Figure 29, and Figure 30.
Figure 27. 4 MHz, Positive Polarity Pins 1 – 41
Note:
RESET retested with 0.1 μF capacitor from pin to ground is Class A compliant as shown by 48*.
Figure 28. 4 MHz, Positive Polarity Pins 42 – 80
MC9S08LG32 Series Data Sheet, Rev. 7
36
Freescale Semiconductor
Electrical Characteristics
Figure 29. 4 MHz, Negative Polarity Pins 1 – 41
Note:
RESET retested with 0.1 μF capacitor from pin to ground is Class A compliant as shown by 48*.
Figure 30. 4 MHz, Negative Polarity Pins 42 – 80
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
37
Ordering Information
The susceptibility performance classification is described in Table 21.
Table 21. Susceptibility Performance Classification
Result
Performance Criteria
A
B
No failure
The MCU performs as designed during and after exposure.
Self-recovering The MCU does not perform as designed during exposure. The MCU returns
failure
automatically to normal operation after exposure is removed.
C
D
E
Soft failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.
Hard failure
Damage
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.
The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.
3
Ordering Information
This section contains ordering information for MC9S08LG32 and MC9S08LG16 devices.
Table 22. Device Numbering System
Memory
LCD Mode
Operation
Device Number1
Temperature Range (°C)
Available Packages2
FLASH
RAM
Auto
S9S08LG32J0CLK
S9S08LG32J0CLH
S9S08LG32J0CLF
S9S08LG32J0VLK
S9S08LG32J0VLH
S9S08LG32J0VLF
S9S08LG16J0VLH
S9S08LG16J0VLF
32 KB
1984
-40 °C to +85 °C
Charge Pump
Register Bias
80-pin LQFP
64-pin LQFP
48-pin LQFP
80-pin LQFP
64-pin LQFP
48-pin LQFP
64-pin LQFP
48-pin LQFP
32 KB
18 KB
1984
1984
-40 °C to +105 °C
IMM
MC9S08LG32CLK
MC9S08LG32CLH
MC9S08LG32CLF
MC9S08LG16CLH
MC9S08LG16CLF
32 KB
18 KB
1984
1984
-40 °C to + 85 °C
Charge Pump
80-pin LQFP
64-pin LQFP
48-pin LQFP
64-pin LQFP
48-pin LQFP
1
2
See the MC9S08LG32 Reference Manual (document MC9S08LG32RM), for a complete description of modules included on
each device.
See Table 23 for package information.
MC9S08LG32 Series Data Sheet, Rev. 7
38
Freescale Semiconductor
Package Information
3.1
Device Numbering System
Example of the device numbering system:
32 J0
S
9 S08 LG
X
XX
Package designator (see Table 23)
Temperature range
(C = –40 °C to 85 °C)
(V = –40 °C to 105 °C)
Maskset Identifier Suffix
(First digit usually references wafer fab
Second digit usually differentiates mask rev)
Status/Partnumber Type
(S = Maskset specific partnumber)
Memory
(9 = FLASH-based)
Core
Family
Approximate Flash size in KB
Figure 31. Device Number Example for Auto Parts
32
C
XX
9
MC S08 LG
Status
(MC = Fully Qualified)
Package designator (see Table 23)
Temperature range
(C = –40 °C to 85 °C)
Memory
(9 = FLASH-based)
Core
Approximate Flash size in KB
Family
Figure 32. Device Number Example for IMM Parts
4
Package Information
Table 23. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
80
64
48
Low Quad Flat Package
Low Quad Flat Package
Low Quad Flat Package
LQFP
LQFP
LQFP
LK
LH
LF
917A
840F
932
98ASS23237W
98ASS23234W
98ASH00962A
4.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 23. For the latest
available drawings please visit our web site (http://www.freescale.com) and enter the package’s document
number into the keyword search box.
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
39
Package Information
4.1.1
80-pin LQFP
MC9S08LG32 Series Data Sheet, Rev. 7
40
Freescale Semiconductor
Package Information
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
41
Package Information
Figure 33. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)
MC9S08LG32 Series Data Sheet, Rev. 7
42
Freescale Semiconductor
Package Information
4.1.2
64-pin LQFP
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
43
Package Information
MC9S08LG32 Series Data Sheet, Rev. 7
44
Freescale Semiconductor
Package Information
Figure 34. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W)
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
45
Package Information
4.1.3
48-pin LQFP
MC9S08LG32 Series Data Sheet, Rev. 7
46
Freescale Semiconductor
Package Information
Figure 35. 48-pin LQFP Package Drawing (Case 932, Doc #98ASH00962A)
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
47
Revision History
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document.
Table 24. Revision History
Revision
Date
Description of Changes
1
2
3
4
5
6
7
8/2008
9/2008
11/2008
2/2009
4/2009
4/2009
8/2009
First Initial release.
Second Initial Release.
Alpha Customer Release.
Launch Release.
Added EMC Radiated Emission and Transient Susceptibility data in Table 19 and Table 20.
Updated EMC performance data.
Updated auto part numbers, changed TCLK, T0CH0, T0CH1, T1CH0, T1CH1, T1CH2, T1CH3,
T1CH3, T1CH4, and T1CH5 to TPMCLK, TPM0CH0, TPM0CH1,TPM1CH0, TPM1CH1,
TPM1CH2, TPM1CH3, TPM1CH4, and TPM1CH5, and changed the maximum LCD frame
frequency to 64 Hz.
MC9S08LG32 Series Data Sheet, Rev. 7
48
Freescale Semiconductor
THIS PAGE INTENTIONALLY BLANK
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
49
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Rev. 7
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