MC9S08LH36CLH [FREESCALE]
Advanced Information; 先进的信息
| 型号： | MC9S08LH36CLH |
| 厂家： | 
Freescale |
| 描述： | Advanced Information |
| 文件： | 总44页 (文件大小：950K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC9S08LH64
Rev. 4, 04/2010
Freescale Semiconductor
Data Sheet: Advanced Information
An Energy Efficient Solution by Freescale
80-LQFP
Case 917A
64-LQFP
Case 840F
MC9S08LH64 Series
Covers: MC9S08LH64 and MC9S08LH36
•
8-Bit HCS08 Central Processor Unit (CPU)
– Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature range
of –40 °C to 85 °C
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip
debug module)
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes
– Up to 20 MHz at 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
On-Chip Memory
– Dual array flash read/program/erase over full operating
voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
flash contents
Power-Saving Modes
– Two low-power stop modes
– Reduced-power wait mode
•
Peripherals
•
•
– LCD — Up to 8×36 or 4×40 LCD driver with internal charge
pump and option to provide an internally-regulated LCD
reference that can be trimmed for contrast control
– ADC —16-bit resolution; with a dedicated differential ADC
input, and 8 single-ended ADC inputs; up to 2.5 μs conversion
time; hardware averaging; calibration registers, automatic
compare function; temperature sensor; operation in stop3;
fully functional from 3.6 V to 1.8 V
– IIC — Inter-integrated circuit bus module to operate at up to
100 kbps with maximum bus loading; multi-master operation;
programmable slave address; interrupt-driven byte-by-byte
data transfer; broadcast mode; 10-bit addressing
– ACMP — Analog comparator with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
– SCIx — Two full-duplex non-return to zero (NRZ) modules
(SCI1 and SCI2); LIN master extended break generation; LIN
slave extended break detection; wakeup on active edge
– SPI — Full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave mode;
MSB-first or LSB-first shifting
– TPMx — Two 2-channel (TPM1 and TPM2); selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel
– TOD — (Time-of-day) 8-bit, quarter second counter with
match register; external clock source for precise time base,
time-of-day, calendar, or task scheduling functions
– VREFx — Trimmable via an 8-bit register in 0.5 mV steps;
automatically loaded with room temperature value upon reset;
can be enabled to operate in stop3 mode; trim register is not
available in stop modes
– Low-power run and wait modes allow peripherals to run while
voltage regulator is in standby
– Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents
– Very low-power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to time-of-day
(TOD) module
– 6 μs typical wakeup time from stop3 mode
Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; crystal
or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz
to 16 MHz
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by
internal or external reference; precision trimming of internal
reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supporting bus frequencies from
1 MHz to 20 MHz
•
•
System Protection
– Watchdog computer operating properly (COP) reset with
option to run from dedicated 1 kHz internal clock source or bus
clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode detection with reset; illegal address detection
with reset
– Flash block protection
Development Support
– Single-wire background debug interface
•
•
Input/Output
– Dedicated accurate voltage reference output pin, 1.2 V output
(VREFOx); trimmable with 0.5 mV resolution
– Up to 39 GPIOs, two output-only pins
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins
Package Options
•
– 14mm × 14mm 80-pin LQFP, 10 mm × 10 mm 64-pin LQFP
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Contents
1
2
3
Devices in the MC9S08LH64 Series . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 ESD Protection and Latch-Up Immunity. . . . . . . . . . . . 11
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . 23
3.8 External Oscillator (XOSCVLP) Characteristics . . . . . . 25
3.9 Internal Clock Source (ICS) Characteristics. . . . . . . . . 26
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.1 Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . .29
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .33
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.13 VREF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.15 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.16.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . .42
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .42
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .43
4
•
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
1
2
10/2007
7/2008
Intial Release of the electrical characteristics in the Reference Manual.
Initial Release after product redefinition and restructuring of information into a separate Data
Sheet and Reference Manual.
3
4
1/2009
Refreshed the draft to include the new VREF module and the latest revisions.
4/8/2010
Completed RIDD in the Table 9; updated ERREFSTEN in the Table 10; changed all VDDAD to
VDDA, VSSAD to VSSA; updated the min. of VREFH
;
Added 64-pin LQFP package information for LH36 MCU; Updated V Room Temp in the
Table 20. Updated S2IDD at VDD = 2 and Temp at –40 to 25 °C
Added 64-pin LQFP package for LH36.
Updated ADC data in the 3.12/33
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual —MC9S08LH64RM
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
1
Devices in the MC9S08LH64 Series
Table 1 summarizes the feature set available in the MC9S08LH64 Series of MCUs.
Table 1. MC9S08LH64 Series Features by MCU and Package
Feature
MC9S08LH64
MC9S08LH36
80-pin
LQFP
64-pin
LQFP
80-pin
LQFP
64-pin
LQFP
Package
64 KB
36 KB
FLASH
(32,768 and 32,768 Arrays)
(24,576 and 12,288 Arrays)
RAM
4000
yes
4000
yes
ACMP
ADC
Single-ended
Channels
8-ch
1
8-ch
0
8-ch
8-ch
ADC Differential
Channels1
1
0
IIC
IRQ
yes
yes
8
yes
yes
8
KBI
SCI1
SCI2
SPI
yes
yes
yes
2-ch
2-ch
yes
yes
yes
yes
2-ch
2-ch
yes
TPM1
TPM2
TOD
8×36
4×40
8×24
4×28
8×36
4×40
8×24
4×28
LCD
VREFO1
VREFO2
I/O pins2
yes
no
no
yes
37
yes
no
no
yes
37
39
39
1
2
Each differential channel consists of two pins (DADPx and DADMx).
The 39 I/O pins include two output-only pins and 18 LCD GPIO.
The block diagram in Figure 1 shows the structure of the MC9S08LH64 Series MCU.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
3
HCS08 CORE
ON-CHIP ICE
DEBUG MODULE (DBG)
PTA7/KBIP7/ADP11/ACMP–
PTA6/KBIP6/ADP10/ACMP+
CPU
INT
PTA5/KBIP5/ADP9/LCD42
PTA4/KBIP4/ADP8/LCD43
TIME OF DAY MODULE
BKGD
BKP
(TOD)
PTA3/MOSI/SCL/KBIP3/ADP7
PTA2/MISO/SDA/KBIP2/ADP6
KBI[7:0]
SS
HCS08 SYSTEM CONTROL
8-BIT KEYBOARD
PTA1/SPSCK/KBIP1/ADP5
PTA0/SS/KBIP0/ADP4
INTERRUPT (KBI
)
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
BKGD/MS
SPSCK
MISO
SERIAL PERIPHERAL
PTB7/TxD2/SS
PTB6/RxD2/SPSCK
INTERFACE (SPI)
RESET
IRQ
MOSI
COP
SCL
SDA
IRQ
LVD
IIC MODULE (IIC
)
PTB5/MOSI/SCL
PTB4/MISO/SDA
USER FLASH A
(LH64 = 32,768 BYTES)
(LH36 = 24,576 BYTES)
TPM2CH0
TPM2CH1
TCLK
∞
PTB2/RESET
2-CHANNEL TIMER/PWM
TPM2
(
)
PTB1/XTAL
USER FLASH B
(LH64 = 32,768 BYTES)
(LH36 = 12,288 BYTES)
PTB0/EXTAL
TPM1CH0
2-CHANNEL TIMER/PWM
TPM1
TPM1CH1
TCLK
PTC7/IRQ/TCLK
PTC6/ACMPO//BKGD/MS
(
)
◊
PTC5/TPM2CH1
PTC4/TPM2CH0
TxD1
RxD1
USER RAM
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
4K BYTES
PTC3/TPM1CH1
PTC2/TPM1CH0
TxD2
RxD2
INTERNAL CLOCK
SOURCE (ICS)
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
PTC1/TxD1
PTC0/RxD1
XTAL
EXTAL
LOW-POWER OSCILLATOR
DADP0
•
•
ADP[11:4]
DADP0
V
DDA
16-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
VSSA
DADM0
•
♦
♦
VREFH
VREFL
DADM0
•
V
DD
PTD[7:0]/LCD[7:0]
VOLTAGE
V
REGULATOR
SS
ACMP–
ACMP+
ANALOG COMPARATOR
•
VREFO1
♦ VREFO2
VREF1
VREF2
(
ACMP)
PTE[7:0]/LCD[13:20]
VLCD
ACMPO
VLL1
NOTES
VLL2
VLL3
•
♦
∞
◊
Pins not available on 64-pin packages. LCD[8:12] and LCD[31:37] are not
available on the 64-pin package.
REFH and VREFL are internally connected to VDDA and VSSA for the 64-pin
package. VREFO2 is only available on the 64-pin package.
When PTB2 is configured as RESET, the pin becomes bi-directional with
output being an open-drain drive.
LIQUID CRYSTAL
DISPLAY
VCAP1
VCAP2
V
LCD
LCD[43:0]
When PTC6 is configured as BKGD, the pin becomes bi-directional.
Figure 1. MC9S08LH64 Series Block Diagram
MC9S08LH64 Series MCU Data Sheet, Rev. 4
4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
2
Pin Assignments
This section shows the pin assignments for the This section shows the pin assignments for the
MC9S08LH64 Series devices.
LCD38
LCD39
LCD40
LCD41
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTE1/LCD14
PTE0/LCD13
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
VCAP1
1
2
3
4
5
6
7
8
PTA5/KBIP5/ADP9/LCD42
PTA4/KBIP4/ADP8/LCD43
PTA3/KBIP3/SCL/MOSI/ADP7
PTA2/KBIP2/SDA/MISO/ADP6
PTA1/KBIP1/SPSCK/ADP5
PTA0/KBIP0/SS/ADP4
PTC7/IRQ/TCLK
PTC6/ACMPO/BKGD/MS
PTC5/TPM2CH1
PTC4/TPM2CH0
64-Pin LQFP
9
10
11
12
13
14
15
16
VCAP2
VLL1
VLL2
VLL3
PTC3/TPM1CH1
PTC2/TPM1CH0
VLCD
Figure 2. 64-Pin LQFP
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
5
PTE0/LCD13
LCD12
LCD34
LCD35
LCD36
LCD37
LCD38
LCD39
LCD40
LCD41
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
LCD11
LCD10
LCD9
LCD8
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
VCAP1
PTA5/KBIP5/ADP9/LCD42
9
80-Pin
LQFP
10
11
12
13
14
15
16
17
18
19
20
PTA4/KBIP4/ADP8/LCD43
PTA3/KBIP3/SCL/MOSI/ADP7
PTA2/KBIP2/SDA/MISO/ADP6
PTA1/KBIP1/SPSCK/ADP5
PTA0/KBIP0/SS/ADP4
PTC7/IRQ/TCLK
PTC6/ACMPO/BKGD/MS
PTC5/TPM2CH1
PTC4/TPM2CH0
VCAP2
VLL1
VLL2
VLL3
PTC3/TPM1CH1
PTC2/TPM1CH0
VLCD
Figure 3. 80-Pin LQFP
Table 2. Pin Availability by Package Pin-Count
<-- Lowest Priority --> Highest
80
64
Port Pin
Alt 1
Alt 2
Alt3
Alt4
1
2
3
4
5
6
7
8
2
PTE0
LCD12
LCD11
LCD10
LCD9
LCD8
PTD7
PTD6
LCD13
3
4
LCD7
LCD6
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
6
Freescale Semiconductor
Table 2. Pin Availability by Package Pin-Count (continued)
<-- Lowest Priority --> Highest
80
64
Port Pin
Alt 1
Alt 2
Alt3
Alt4
9
5
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
VCAP1
VCAP2
VLL1
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
6
7
8
9
10
11
12
13
14
15
16
17
18
VLL2
VLL3
VLCD
PTA6
PTA7
VSSA
KBIP6
KBIP7
ADP10
ADP11
ACMP+
ACMP–
19
VREFL
DADP0
DADM0
VREFO1
VREFH
VDDA
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
PTB0
PTB1
VDD
EXTAL
XTAL
VSS
PTB2
VREFO2
PTB4
PTB5
PTB6
PTB7
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
RESET
35
36
37
38
39
40
41
42
43
44
45
MISO
MOSI
SDA
SCL
RxD2
SPSCK
SS
TxD2
RxD1
TxD1
TPM1CH0
TPM1CH1
TPM2CH0
TPM2CH1
ACMPO
BKGD
MS
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
7
Table 2. Pin Availability by Package Pin-Count (continued)
<-- Lowest Priority --> Highest
80
64
Port Pin
Alt 1
Alt 2
Alt3
Alt4
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
38
39
40
41
42
43
44
45
46
47
48
PTC7
PTA0
IRQ
TCLK
KBIP0
KBIP1
KBIP2
KBIP3
KBIP4
KBIP5
SS
ADP4
ADP5
ADP6
ADP7
PTA1
SPSCK
MISO
PTA2
SDA
SCL
PTA3
MOSI
PTA4
ADP8
ADP9
LCD43
LCD42
PTA5
LCD41
LCD40
LCD39
LCD38
LCD37
LCD36
LCD35
LCD34
LCD33
LCD32
LCD31
LCD30
LCD29
LCD28
LCD27
LCD26
LCD25
LCD24
LCD23
LCD22
LCD21
PTE7
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
LCD20
LCD19
LCD18
LCD17
LCD16
LCD15
LCD14
PTE6
PTE5
PTE4
PTE3
PTE2
PTE1
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
8
Freescale Semiconductor
Introduction
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08LH64 Series of microcontrollers
available at the time of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 3. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
T
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either V or V ) or the programmable
SS
DD
pullup resistor associated with the pin is enabled.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
9
Thermal Characteristics
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
IDD
VIn
–0.3 to +3.8
120
V
mA
V
Maximum current into VDD
Digital input voltage
–0.3 to VDD + 0.3
Instantaneous maximum current
ID
± 25
mA
Single pin limit (applies to all port pins)1, 2, 3
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take P into account in power calculations, determine the difference between actual pin
I/O
voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high
SS
DD
pin current (heavy loads), the difference between pin voltage and V or V will be very small.
SS
Table 5. Thermal Characteristics
DD
Rating
Symbol
Value
Unit
Operating temperature range
(packaged)
TL to TH
–40 to 85
TA
TJ
°C
°C
Maximum junction temperature
95
Thermal resistance
Single-layer board
80-pin LQFP
64-pin LQFP
55
73
θJA
°C/W
°C/W
Thermal resistance
Four-layer board
80-pin LQFP
64-pin LQFP
42
54
θJA
The average chip-junction temperature (T ) in °C can be obtained from:
J
MC9S08LH64 Series MCU Data Sheet, Rev. 4
10
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
ESD Protection and Latch-Up Immunity
T = T + (P × θ )
JA
Eqn. 1
J
A
D
where:
T = Ambient temperature, °C
A
θ
= Package thermal resistance, junction-to-ambient, °C/W
JA
P = P + P
D
int
I/O
P
P
= I × V , Watts — chip internal power
= Power dissipation on input and output pins — user determined
int
I/O
DD DD
For most applications, P << P and can be neglected. An approximate relationship between P and T
I/O
int
D
J
(if P is neglected) is:
I/O
P = K ÷ (T + 273°C)
Eqn. 2
D
J
Solving Equation 1 and Equation 2 for K gives:
2
K = P × (T + 273°C) + θ × (P )
Eqn. 3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving Equation 1 and Equation 2 iteratively for any value of T .
A
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Series resistance
Symbol
Value
1500
100
3
Unit
W
R1
C
Human
Body Model
Storage capacitance
Number of pulses per pin
Series resistance
pF
—
R1
C
0
W
Charge
Device
Model
Storage capacitance
Number of pulses per pin
200
3
pF
—
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
11
DC Characteristics
Table 6. ESD and Latch-up Test Conditions (continued)
Minimum input voltage limit
Maximum input voltage limit
–2.5
7.5
V
V
Latch-up
Table 7. ESD and Latch-Up Protection Characteristics
1
No.
1
Symbol
VHBM
VCDM
ILAT
Min
±2000
±500
±100
Max
—
Unit
V
Rating
Human body model (HBM)
Charge device model (CDM)
Latch-up current at TA = 85°C
2
—
V
3
—
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
3.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C
Characteristic
Symbol
Condition
Min
Typ1
Max
Unit
1
Operating Voltage
1.8
3.6
V
PTA[0:3], PTA[6:7],
VDD >1.8 V
ILoad = –0.6 mA
C
PTB[0:7], PTC[0:7]2,
low-drive strength
V
DD – 0.5
DD – 0.5
—
—
Output high
2
VOH
VDD > 2.7 V
ILoad = –10 mA
V
P voltage
V
—
—
—
—
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7]2,
high-drive strength
VDD > 1.8 V
ILoad = –3 mA
C
C
VDD – 0.5
VDD – 0.5
PTA[4:5], PTD[0:7],
PTE[0:7],
low-drive strength
VDD > 1.8 V
ILoad = –0.5 mA
—
—
Output high
3
4
5
VOH
VDD > 2.7 V
ILoad = –2.5 mA
V
mA
V
P voltage
VDD – 0.5
VDD – 0.5
—
—
—
—
—
—
PTA[4:5], PTD[0:7],
PTE[0:7],
high-drive strength
VDD > 1.8 V
ILoad = –1 mA
C
Output high
current
D
C
Max total IOH for all ports IOHT
100
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7],
low-drive strength
VDD >1.8 V
ILoad = 0.6 mA
—
—
0.5
Output low
VOL
VDD > 2.7 V
ILoad = 10 mA
P voltage
—
—
—
—
0.5
0.5
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7],
high-drive strength
VDD > 1.8 V
ILoad = 3 mA
C
MC9S08LH64 Series MCU Data Sheet, Rev. 4
12
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Table 8. DC Characteristics (continued)
Num C
Characteristic
PTA[4:5], PTD[0:7],
Symbol
Condition
Min
Typ1
Max
Unit
VDD > 1.8 V
Load = 0.5 mA
C
PTE[0:7],
low-drive strength
—
—
0.5
I
Output low
6
VOL
VDD > 2.7 V
V
P voltage
—
—
—
—
—
—
0.5
0.5
PTA[4:5], PTD[0:7],
PTE[0:7],
high-drive strength
I
Load = 3 mA
VDD > 1.8 V
ILoad = 1 mA
C
D
Output low
current
7
8
Max total IOL for all ports
all digital inputs
IOLT
VIH
100
mA
V
P
C
P
C
VDD > 2.7 V
VDD > 1.8 V
VDD > 2.7 V
VDD > 1.8 V
0.70 x VDD
—
—
—
—
—
Input high
voltage
0.85 x VDD
—
—
—
0.35 x VDD
0.30 x VDD
Input low
voltage
9
all digital inputs
all digital inputs
VIL
Input
hysteresis
10
C
Vhys
0.06 x VDD
—
—
mV
Input
11 P leakage
current
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
VIn = VDD or VSS
VIn = VDD or VSS
—
0.025
1
μA
Hi-Z
(off-state)
leakage
current
all input/output
(per pin)
12
P
|IOZ
|
—
0.025
1
μA
Total
Total leakage current for all
pins
13 P leakage
|IInT
|
—
17.5
35
—
—
—
3
μA
kΩ
kΩ
current3
Pullup,
14 P Pulldown
resistors
all non-LCD pins when RPU,
enabled RPD
52.5
77
Pullup,
15 P Pulldown
resistors
LCD/GPIO pins when RPU,
enabled RPD
Single pin limit
–0.2
–5
—
—
0.2
5
mA
mA
DCinjection
16 D current 4, 5,
IIC
VIN < VSS, VIN > VDD
Total MCU limit, includes
sum of all stressed pins
6
17 C Input Capacitance, all pins
18 C RAM retention voltage
19 C POR re-arm voltage7
20 D POR re-arm time
CIn
—
—
—
0.6
1.4
—
8
pF
V
VRAM
VPOR
tPOR
1.0
2.0
—
0.9
10
V
μs
VDD falling
VDD rising
1.80
1.88
1.84
1.92
1.88
1.96
Low-voltage detection threshold
Low-voltage warning threshold
21
22
23
P
P
P
VLVD
VLVW
V
V
VDD falling
VDD rising
2.08
2.14
2.2
Low-voltage inhibit reset/recover
hysteresis
24 P Bandgap Voltage Reference8
Vhys
VBG
—
80
—
mV
V
1.15
1.17
1.18
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
13
DC Characteristics
1
Typical values are measured at 25°C. Characterized, not tested
All I/O pins except for LCD pins in Open Drain mode.
2
3
Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but
characterization data shows that individual pin leakage current maximums are less than 250 nA.
4
All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD
.
5
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
6
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
7
8
POR will occur below the minimum voltage.
Factory trimmed at VDD = 3.0 V, Temp = 25 °C
Figure 4. Non LCD pins I/O Pullup Typical Resistor Values
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
14
Freescale Semiconductor
DC Characteristics
Figure 5. Typical Low-Side Driver (Sink) Characteristics (Non LCD Pins) — Low Drive (PTxDSn = 0)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
15
DC Characteristics
Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
16
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Figure 7. Typical High-Side (Source) Characteristics (Non LCD Pins)— Low Drive (PTxDSn = 0)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
17
DC Characteristics
Figure 8. Typical High-Side (Source) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
18
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Figure 9. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
19
DC Characteristics
Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
20
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Figure 11. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
21
DC Characteristics
Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
22
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
Supply Current Characteristics
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Bus
Freq
VDD
(V)
Temp
(°C)
Num
C
Parameter
Symbol
Typ1
Max
Unit
T
T
T
T
T
T
20 MHz
8 MHz
1 MHz
20 MHz
8 MHz
1 MHz
13.75
7
17.9
—
Run supply current
1
RIDD
3
3
mA
–40 to 85
–40 to 85
FEI mode, all modules on
2
—
8.9
5.5
0.9
185
—
Run supply current
FEI mode, all modules off
2
3
RIDD
—
mA
—
32 kHz
FBILP
T
T
—
—
Run supply current
LPS=0, all modules off
RIDD
3
3
μA
–-40 to 85
16 kHz
FBELP
115
Run supply current
LPS=1, all modules off, running from
Flash
—
—
—
—
6
0 to 70
–40 to 85
0 to 70
T
T
21.9
16 kHz
FBELP
4
5
RIDD
μA
Run supply current
LPS=1, all modules off, running from
RAM
7.3
–40 to 85
T
T
Wait mode supply current
FEI mode, all modules off
20 MHz
8 MHz
1 MHz
4.57
2
WIDD
3
3
2
3
2
—
—
1.3
6
mA
–40 to 85
T
0.73
0.4
4
P
C
P
C
C
C
P
C
P
C
C
C
Stop2 mode supply current
–40 to 25
70
85
8.5
0.35
3.9
7.7
0.65
5.7
12.2
0.6
5
13
1.0
5
6
S2IDD
n/a
μA
–40 to 25
70
10
1.8
8.0
20
1.5
6.8
14
85
Stop3 mode supply current
No clocks active
–40 to 25
70
85
7
S3IDD
n/a
μA
–40 to 25
70
11.5
85
1
Typical values are measured at 25 °C. Characterized, not tested
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
23
Supply Current Characteristics
Table 10. Stop Mode Adders
Condition
Temperature (°C)
Num
C
Parameter
Units
–40
25
70
85
1
2
3
4
5
6
T
T
T
T
T
T
LPO
100
750
63
100
750
70
150
800
77
175
850
81
nA
nA
μA
nA
μA
μA
ERREFSTEN
IREFSTEN1
TOD
RANGE = HGO = 0
Does not include clock source current
LVDSE = 1
50
50
75
100
115
23
LVD1
110
12
110
12
112
20
ACMP1
Not using the bandgap (BGBE = 0)
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0)
7
T
ADC1
95
95
101
120
μA
VIREG enabled for Contrast control, 1/8
Duty cycle, 8x24 configuration for
driving 192 segments, 32 Hz frame rate,
No LCD glass connected.
8
T
LCD
1
1
6
13
μA
1
Not available in stop2 mode.
Figure 13. Typical Run I for FBE and FEI, I vs. V
DD
DD
DD
(ACMP and ADC off, All Other Modules Enabled)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
24
Freescale Semiconductor
External Oscillator (XOSCVLP) Characteristics
3.8
External Oscillator (XOSCVLP) Characteristics
Reference Figure 14 and Figure 15 for crystal or resonator circuits.
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
1
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
See Note 2
See Note 3
C1,C2
2
3
D
D
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
—
—
—
—
10
1
—
—
—
RF
MΩ
kΩ
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
—
—
—
—
100
0
—
—
—
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
RS
4
D
≥ 8 MHz
4 MHz
1 MHz
—
—
—
0
0
0
0
10
20
Crystal start-up time 4
Low range, low power
Low range, high gain
High range, low power
High range, high gain
—
—
—
—
600
400
5
—
—
—
—
t
CSTL
5
6
C
D
ms
t
CSTH
15
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
fextal
FEE mode
FBE or FBELP mode
0.03125
0
—
—
20
20
MHz
MHz
1
2
3
4
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
See crystal or resonator manufacturer’s recommendation.
Proper PC board layout procedures must be followed to achieve specifications.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
25
Internal Clock Source (ICS) Characteristics
XOSCVLP
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85 °C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
2
3
4
C
P
P
T
Average internal reference frequency — untrimmed
Average internal reference frequency — user-trimmed
Average internal reference frequency — factory-trimmed
Internal reference start-up time
fint_ut
fint_t
25
31.25
—
32.7
—
41.66
39.06
—
kHz
kHz
kHz
μs
fint_t
32.7
60
tIRST
—
100
P
C
P
P
Low range (DFR = 00)
DCO output frequency
12.8
25.6
16
16.8
33.6
—
21.33
42.67
20
5
6
fdco_ut
MHz
MHz
range — untrimmed
Mid range (DFR = 01)
Low range (DFR = 00)
DCO output frequency
fdco_t
range — trimmed
Mid range (DFR = 01)
32
—
40
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
7
8
C
C
Δfdco_res_t
Δfdco_res_t
—
—
±0.1
±0.2
±0.2
±0.4
%fdco
%fdco
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
26
Freescale Semiconductor
AC Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85 °C Ambient) (continued)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Total deviation of trimmed DCO output frequency over
voltage and temperature
+0.5
–1.0
9
C
Δfdco_t
—
±2
%fdco
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0 °C to 70 °C
FLL acquisition time2
10
11
12
C
C
C
Δfdco_t
tAcquire
CJitter
—
—
—
±0.5
—
±1
1
%fdco
ms
Long term jitter of DCO output clock (averaged over 2-ms
interval)3
0.02
0.2
%fdco
1
2
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
3
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.10 AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
27
AC Characteristics
3.10.1 Control Timing
Table 13. Control Timing
Symbol
Num
C
Rating
Bus frequency (tcyc = 1/fBus
Min
Typ1
Max
Unit
)
1
D
VDD ≤ 2.1V
VDD > 2.1V
fBus
dc
dc
—
—
10
20
MHz
2
3
4
D
D
D
Internal low power oscillator period
External reset pulse width2
Reset low drive
tLPO
textrst
trstdrv
700
100
—
—
—
1300
—
μs
ns
ns
34 x tcyc
—
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
5
6
D
D
tMSSU
tMSH
500
100
—
—
—
—
ns
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
μs
IRQ pulse width
7
8
D
D
Asynchronous path2
Synchronous path4
100
1.5 × tcyc
—
—
—
—
tILIH, IHIL
t
ns
ns
ns
Keyboard interrupt pulse width
Asynchronous path2
100
1.5 × tcyc
—
—
—
—
tILIH, IHIL
t
Synchronous path4
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t
Rise, tFall
—
—
16
23
—
—
9
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
—
—
5
9
—
—
1
2
3
Typical values are based on characterization data at VDD = 3.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD
.
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5
6
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C.
Except for LCD pins in Open Drain mode.
textrst
RESET PIN
Figure 17. Reset Timing
MC9S08LH64 Series MCU Data Sheet, Rev. 4
28
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
AC Characteristics
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 18. IRQ/KBIPx Timing
3.10.2 TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 14. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
2
3
4
5
D
D
D
D
D
External clock frequency
External clock period
fTCLK
tTCLK
tclkh
0
fBus/4
—
Hz
tcyc
tcyc
tcyc
tcyc
4
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
t
ICPW
TPMCHn
TPMCHn
t
ICPW
Figure 20. Timer Input Capture Pulse
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
29
AC Characteristics
3.10.3 SPI Timing
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 15. SPI Timing
No.
C
Function
Operating frequency
Symbol
Min
Max
Unit
—
D
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
SPSCK period
Master
Slave
D
D
D
D
D
D
tSPSCK
tLead
tLag
2
4
2048
—
tcyc
tcyc
1
2
3
4
5
6
Enable lead time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Enable lag time
Master
Slave
1/2
1
—
—
tSPSCK
tcyc
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
D
D
Slave access time
ta
—
—
1
1
tcyc
7
8
Slave MISO disable time
tdis
tcyc
Data valid (after SPSCK edge)
D
D
D
D
Master
Slave
tv
—
—
25
25
ns
ns
9
Data hold time (outputs)
Master
Slave
tHO
0
0
—
—
ns
ns
10
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
11
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
12
MC9S08LH64 Series MCU Data Sheet, Rev. 4
30
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
AC Characteristics
SS1
(OUTPUT)
1
2
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MS BIN2
LSB IN
BIT 6 . . . 1
9
9
10
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA = 0)
SS1
(OUTPUT)
1
2
11
12
3
12
11
SPSCK
(CPOL = 0)
(OUTPUT)
4
4
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
10
BIT 6 . . . 1
LSB IN
9
MOSI
(OUTPUT)
MASTER MSB OUT2
PORT DATA
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA =1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
31
AC Characteristics
SS
(INPUT)
11
12
3
1
12
11
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
10
9
10
MISO
(OUTPUT)
SEE
NOTE 1
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
6
SLAVE
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received.
Figure 23. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
12
2
11
SPSCK
(CPOL = 0)
(INPUT)
4
4
11
12
SPSCK
(CPOL = 1)
(INPUT)
9
10
c
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE
‘c
MSB OUT
6
NOTE 1
7
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received
Figure 24. SPI Slave Timing (CPHA = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
32
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
Analog Comparator (ACMP) Electricals
3.11 Analog Comparator (ACMP) Electricals
Table 16. Analog Comparator Electrical Specifications
C
Characteristic
Symbol
Min
Typical
Max
Unit
D
P
D
P
C
P
C
Supply voltage
VDD
IDDAC
VAIN
VAIO
VH
1.8
—
—
20
—
3.6
35
V
μA
V
Supply current (active)
Analog input voltage
VSS – 0.3
VDD
40
Analog input offset voltage
Analog comparator hysteresis
Analog input leakage current
Analog comparator initialization delay
20
9.0
—
mV
mV
μA
μs
3.0
—
15.0
1.0
1.0
IALKG
tAINIT
—
—
3.12 ADC Characteristics
Table 17. 16-bit ADC Operating Conditions
Charact
eristic
Num
Conditions
Symb
Min
Typ1
Max
Unit
Comment
1
2
Absolute
Delta to VDD (VDD–VDDA
VDDA
1.8
—
0
3.6
V
Supply
voltage
2
)
ΔVDDA
–100
100
mV
Ground
voltage
2
3
4
Delta to VSS (VSS–VSSA
)
ΔVSSA
–100
1.15
0
100
mV
V
Ref
Voltage
High
VREFH
VDDA
VDDA
Ref
5
6
7
Voltage
Low
VREFL
VADIN
CADIN
VSSA
VREFL
—
VSSA
VSSA
V
V
Input
Voltage
—
VREFH
Input
Capacit
ance
16-bit modes
8/10/12-bit modes
8
4
10
5
pF
Input
Resista
nce
8
RADIN
—
2
5
kΩ
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
33
ADC Characteristics
Table 17. 16-bit ADC Operating Conditions
Charact
Num
Conditions
16 bit modes
Symb
Min
Typ1
Max
Unit
Comment
eristic
fADCK > 8MHz
4MHz < fADCK < 8MHz
—
—
—
—
—
—
0.5
1
2
9
f
ADCK < 4MHz
13/12 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
1
2
5
10
Analog
External to MCU
Source
Resista
nce
RAS
kΩ
Assumes
ADLSMP=0
11/10 bit modes
fADCK > 8MHz
—
—
—
—
—
—
2
5
10
11
12
4MHz < fADCK < 8MHz
fADCK < 4MHz
9/8 bit modes
f
ADCK > 8MHz
—
—
—
—
5
10
fADCK < 8MHz
13
ADLPC = 0, ADHSC = 1
1.0
1.0
1.0
—
—
—
8
5
ADC
Convers
ion
Clock
Freq.
14
15
ADLPC = 0, ADHSC = 0
ADLPC = 1, ADHSC = 0
fADCK
MHz
2.5
1
2
Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
DC potential difference.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
34
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
ADC Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
For Differential Mode, this figure
applies to both inputs
CADIN
Figure 25. ADC Input Impedance Equivalency Diagram
Table 18. 16-bit ADC Characteristics full operating range(V
= V
> 1.8, V
= V
, F
< 8MHz)
REFH
DDA
REFL
SSA ADCK
Characteristic
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
Supply Current ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
—
—
—
—
—
—
—
215
470
610
0.01
2.4
—
—
—
—
—
—
—
ADLSMP = 0
ADCO = 1
T
IDDA
μA
μA
ADLPC=0, ADHSC=1
Supply Current Stop, Reset, Module Off
C
IDDA
ADC
Asynchronous
Clock Source
ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1
5.2
P
fADACK
MHz
tADACK
=
1/fADACK
6.2
Sample Time
See reference manual for sample times
See reference manual for conversion times
Conversion
Time
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
35
ADC Characteristics
Table 18. 16-bit ADC Characteristics full operating range(V
= V
> 1.8, V
= V
, F
< 8MHz)
REFH
DDA
REFL
SSA ADCK
Characteristic
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
Total
Unadjusted
Error
16-bit differential mode
16-bit single-ended mode
T
TUE
—
—
±16
±20
+48/-40
+56/-28
LSB3
LSB2
LSB2
LSB2
32x
Hardware
Averaging
(AVGE = %1
AVGS = %11)
13-bit differential mode
12-bit single-ended mode
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
—
—
±1.5
±1.75
±3.0
±3.5
11-bit differential mode
10-bit single-ended mode
—
—
±0.7
±0.8
±1.5
±1.5
9-bit differential mode
8-bit single-ended mode
—
—
±0.5
±0.5
±1.0
±1.0
Differential
Non-Linearity
16-bit differential mode
16-bit single-ended mode
DNL
—
—
±2.5
±2.5
+5/-3
+5/-3
13-bit differential mode
12-bit single-ended mode
—
—
±0.7
±0.7
±1
±1
11-bit differential mode
10-bit single-ended mode
—
—
±0.5
±0.5
±0.75
±0.75
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
Integral
Non-Linearity
16-bit differential mode
16-bit single-ended mode
INL
—
—
±6.0
±10.0
±16.0
±20.0
13-bit differential mode
12-bit single-ended mode
—
—
±1.0
±1.0
±2.5
±2.5
11-bit differential mode
10-bit single-ended mode
—
—
±0.5
±0.5
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
—
—
±0.3
±0.3
±0.5
±0.5
Zero-Scale
Error
16-bit differential mode
16-bit single-ended mode
EZS
—
—
±4.0
±4.0
+32/-24
+24/-16
VADIN = VSSA
13-bit differential mode
12-bit single-ended mode
—
—
±0.7
±0.7
±2.5
±2.0
11-bit differential mode
10-bit single-ended mode
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
36
Freescale Semiconductor
ADC Characteristics
= V , F < 8MHz)
REFL SSA ADCK
Table 18. 16-bit ADC Characteristics full operating range(V
= V
> 1.8, V
REFH
DDA
Characteristic
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
VADIN = VDDA
Full-Scale
Error
16-bit differential mode
16-bit single-ended mode
T
EFS
—
—
+10/0
+14/0
+42/-2
+46/-2
LSB2
13-bit differential mode
12-bit single-ended mode
T
T
T
D
—
—
±1.0
±1.0
±3.5
±3.5
11-bit differential mode
10-bit single-ended mode
—
—
±0.4
±0.4
±1.5
±1.5
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
Quantization
Error
16 bit modes
EQ
—
—
-1 to 0
—
—
LSB2
Bits
<13 bit modes
±0.5
Effective
Number of Bits
16 bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
C
ENOB
Fin
=
12.8
12.7
12.6
12.5
11.9
14.2
13.8
13.6
13.3
12.5
—
—
—
—
—
Fsample/100
Avg=1
16 bit single-ended mode
D
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
—
—
—
—
—
13.2
12.8
12.6
12.3
11.5
—
—
—
—
—
Signal to Noise
plus Distortion
See ENOB
SINAD
THD
dB
dB
SINAD = 6.02 ⋅ ENOB + 1.76
Total Harmonic
Distortion
16-bit differential mode
Avg = 32
C
D
C
D
D
Fin
=
—
—
-91.5
-85.5
92.2
-74.3
—
Fsample/100
16-bit single-ended mode
Avg = 32
Spurious Free
Dynamic
Range
16-bit differential mode
Avg = 32
SFDR
dB
Fin =
Fsample/100
75.0
—
—
16-bit single-ended mode
Avg = 32
86.2
—
IIn = leakage
current
(refer to DC
characteristics)
Input Leakage
Error
all modes
EIL
IIn * RAS
mV
Temp Sensor
Slope
-40°C– 25°C
25°C– 125°C
25°C
C
C
m
—
—
—
1.646
1.769
701.2
—
—
—
mV/°C
Temp Sensor
Voltage
VTEMP25
mV
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
37
ADC Characteristics
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDA
2
Typical values assume VDDA = 3.0V, Temp = 25°C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
1 LSB = (VREFH - VREFL)/2N
3
Table 19. 16-bit ADC Characteristics(V
= V
> 2.7V, V
Min
= V
, F
< 4MHz, ADHSC=1)
REFH
DDA
REFL
SSA ADCK
Characteristic
Conditions1
C
Symb
Typ2
Max
Unit
Comment
Total
Unadjusted
Error
16-bit differential mode
16-bit single-ended mode
T
TUE
—
—
±16
±20
+24/-24
+32/-20
LSB3
32x
Hardware
Averaging
(AVGE = %1
AVGS = %11)
13-bit differential mode
12-bit single-ended mode
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
—
—
±1.5
±1.75
±2.0
±2.5
11-bit differential mode
10-bit single-ended mode
—
—
±0.7
±0.8
±1.0
±1.25
9-bit differential mode
8-bit single-ended mode
—
—
±0.5
±0.5
±1.0
±1.0
Differential
Non-Linearity
16-bit differential mode
16-bit single-ended mode
DNL
—
—
±2.5
±2.5
±3
±3
LSB2
LSB2
LSB2
13-bit differential mode
12-bit single-ended mode
—
—
±0.7
±0.7
±1
±1
11-bit differential mode
10-bit single-ended mode
—
—
±0.5
±0.5
±0.75
±0.75
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
Integral
Non-Linearity
16-bit differential mode
16-bit single-ended mode
INL
—
—
±6.0
±10.0
±12.0
±16.0
13-bit differential mode
12-bit single-ended mode
—
—
±1.0
±1.0
±2.0
±2.0
11-bit differential mode
10-bit single-ended mode
—
—
±0.5
±0.5
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
—
—
±0.3
±0.3
±0.5
±0.5
Zero-Scale
Error
16-bit differential mode
16-bit single-ended mode
EZS
—
—
±4.0
±4.0
+16/0
+16/-8
VADIN = VSSA
13-bit differential mode
12-bit single-ended mode
—
—
±0.7
±0.7
±2.0
±2.0
11-bit differential mode
10-bit single-ended mode
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
38
Freescale Semiconductor
ADC Characteristics
< 4MHz, ADHSC=1)
Table 19. 16-bit ADC Characteristics(V
= V
> 2.7V, V
Min
= V
, F
REFH
DDA
REFL
SSA ADCK
Characteristic
Conditions1
C
Symb
Typ2
Max
Unit
Comment
Full-Scale
Error
16-bit differential mode
16-bit single-ended mode
T
EFS
—
—
+8/0
+12/0
+24/0
+24/0
LSB2
VADIN = VDDA
13-bit differential mode
12-bit single-ended mode
T
T
T
D
—
—
±0.7
±0.7
±2.0
±2.5
11-bit differential mode
10-bit single-ended mode
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
Quantization
Error
16 bit modes
EQ
—
—
-1 to 0
—
—
LSB2
Bits
<13 bit modes
±0.5
Effective
Number of Bits
16 bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
C
ENOB
Fin
=
14.3
13.8
13.4
13.1
12.4
14.5
14.0
13.7
13.4
12.6
—
—
—
—
—
Fsample/100
Avg=1
16 bit single-ended mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
TBD
TBD
TBD
TBD
TBD
13.5
13.0
12.7
12.4
11.6
—
—
—
—
—
Signal to Noise
plus Distortion
See ENOB
SINAD
THD
dB
dB
SINAD = 6.02 ⋅ ENOB + 1.76
Total Harmonic
Distortion
16 bit differential mode
Avg=32
C
D
C
D
D
Fin
=
—
—
-95.8
—
-90.4
—
Fsample/100
16 bit single-ended mode
Avg=32
Spurious Free
Dynamic
Range
16 bit differential mode
Avg=32
SFDR
dB
Fin =
Fsample/100
91.0
—
96.5
—
16 bit single-ended mode
Avg=32
—
—
IIn = leakage
current
(refer to DC
characteristics)
Input Leakage
Error
all modes
EIL
IIn * RAS
mV
Temp Sensor
Slope
-40°C– 25°C
25°C– 125°C
25°C
D
D
m
—
—
—
1.646
1.769
701.2
—
—
—
mV/°C
Temp Sensor
Voltage
VTEMP25
mV
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
39
VREF Specifications
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDA
2
Typical values assume VDDA = 3.0V, Temp = 25°C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
1 LSB = (VREFH - VREFL)/2N
3
3.13 VREF Specifications
Table 20. VREF Electrical Specifications
Num
Characteristic
Supply voltage
Symbol
Min
Max
Unit
1
2
3
VDD
Top
—
1.80
–40
—
3.60
105
10
V
C
Operating temperature range
Maximum Load
mA
Operation across Temperature
4
5
6
V Room Temp
V Room Temp
Untrimmed –40 °C
Trimmed –40 °C
Untrimmed 0 °C
Trimmed 0 °C
1.135
1.165
V
–2 to –6 from Room Temp
Voltage
Untrimmed –40 °C
Trimmed –40 °C
Untrimmed 0 °C
Trimmed 0 °C
mV
mV
mV
mV
mV
±1 from Room Temp Voltage
+1 to –2 from Room Temp
Voltage
7
±0.5 from Room Temp Voltage
+1 to –2 from Room Temp
Voltage
8
Untrimmed 50 °C
Untrimmed 50 °C
Trimmed 50 °C
9
Trimmed 50 °C
Untrimmed 85 °C
Trimmed 85 °C
±0.5 from Room Temp Voltage
mV
mV
mV
10
11
Untrimmed 85 °C 0 to –4 from Room Temp Voltage
Trimmed 85 °C
±0.5 from Room Temp Voltage
–2 to –6 from Room Temp
Voltage
12
Untrimmed 125 °C
Untrimmed 125 °C
mV
13
14
15
Trimmed 125 °C
Trimmed 125 °C
±1 from Room Temp Voltage
mV
—
Load Bandwidth
—
—
—
Load Regulation Mode = 10 at 1mA load
Mode = 10
20
100
μV/mA
mV
DC
AC
±0.1 from Room Temp Voltage
Line Regulation (Power Supply
Rejection)
16
–60
dB
Power Consumption
Powered down Current (Stop Mode,
VREFEN = 0, VRSTEN = 0)
17
I
—
.100
μA
18
19
20
Bandgap only (Mode[1:0] 00)
I
I
I
—
—
—
75
125
1.1
μA
μA
Low-Power buffer (Mode[1:0] 01)
Tight-Regulation buffer (Mode[1:0] 10)
mA
MC9S08LH64 Series MCU Data Sheet, Rev. 4
40
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
LCD Specifications
Table 20. VREF Electrical Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
21
RESERVED (Mode[1:0] 11)
—
—
—
—
3.14 LCD Specifications
Table 21. LCD Electricals, 3-V Glass
#
C
Characteristic
Symbol
Min
Typ
Max
Unit
1
D
LCD Supply Voltage
VLCD
V
.9
28
1.5
30
1.8
58
2
3
4
5
6
7
D
D
D
D
LCD Frame Frequency
fFrame
CLCD
CBYLCD
Cglass
Hz
nF
nF
pF
LCD Charge Pump Capacitance
LCD Bypass Capacitance
LCD Glass Capacitance
—
100
100
100
—
100
—
2000
1.00
1.67
8000
1.15
1.851
HRefSel = 0
HRefSel = 1
.89
1.49
D
D
VIREG
VIREG
V
V
IREG TRIM Resolution
VIREG Ripple
LCD Buffered Adder2
%
VIREG
8
ΔRTRIM
1.5
—
—
9
HRefSel = 0
HRefSel = 1
—
—
—
—
—
—
.1
D
D
V
10
.15
11
V
IBuff
—
1
μA
1
2
VIREG Max can not exceed VDD –.15 V
VSUPPLY = 10, BYPASS = 0
3.15 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal V supply.
DD
For more detailed information about program/erase operations, see the Memory section.
Table 22. Flash Characteristics
#
C
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
–40 °C to 85 °C
1
D
—
Vprog/erase
VRead
fFCLK
1.8
1.8
150
5
3.6
3.6
V
V
2
3
4
5
6
D
D
D
P
P
Supply voltage for read operation
Internal FCLK frequency1
—
—
—
9
200
6.67
kHz
μs
Internal FCLK period (1/FCLK)
Byte program time (random location)2
Byte program time (burst mode)2
tFcyc
tprog
tFcyc
tFcyc
tBurst
4
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
41
EMC Performance
Table 22. Flash Characteristics (continued)
#
C
Characteristic
Page erase time2
Mass erase time2
Symbol
Min
Typical
Max
Unit
7
8
9
P
P
D
tPage
tMass
4000
20,000
4
tFcyc
tFcyc
mA
Byte program current3
RIDDBP
—
—
1
2
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with
VDD = 3.0 V, bus frequency = 4.0 MHz.
3.16 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
3.16.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East).
4
Ordering Information
This appendix contains ordering information for the device numbering system.
Table 23. Device Numbering System
Memory
Device Number1
Available Packages2
Flash
RAM
64 KB
64 KB
36 KB
36 KB
4000
4000
4000
4000
80-pin LQFP
64-pin LQFP
80-pin LQFP
64-pin LQFP
MC9S08LH64
MC9S08LH36
1
2
See Table 1 for a complete description of modules included on each device.
See Table 24 for package information.
4.1
Device Numbering System
Example of the device numbering system:
MC9S08LH64 Series MCU Data Sheet, Rev. 4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
42
Freescale Semiconductor
Package Information
64
C
XX
9
MC S08 LH
Status
(MC = Fully Qualified)
Package designator (see Table 24)
Temperature range
(C = –40 °C to 85 °C)
Memory
(9 = Flash-based)
Core
Approximate flash size in KB
Family
4.2
Package Information
Table 24. Package Descriptions
Pin Count
Package Type
Abbreviation
Designator
Case No.
Document No.
80
64
Low Quad Flat Package
Low Quad Flat Package
LQFP
LQFP
LK
LH
917A
840F
98ASS23237W
98ASS23234W
4.3
Mechanical Drawings
Table 24 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MC9S08LH64 Series Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
•
•
Click on the appropriate link in Table 24, or
Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate
document number (from Table 24) in the “Enter Keyword” search box at the top of the page.
®
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
43
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MC9S08LH64
Rev. 4, 04/2010
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