MC33993DWBR2 [FREESCALE]
Multiple Switch Detection Interface; 多开关检测接口
| 型号： | MC33993DWBR2 |
| 厂家： | 
Freescale |
| 描述： | Multiple Switch Detection Interface |
| 文件： | 总28页 (文件大小：1260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33993
Rev. 6, 5/2008
Freescale Semiconductor
Advance Information
Multiple Switch Detection
Interface
33993
The 33993 Multiple Switch Detection Interface is designed to detect
the closing and opening of up to 22 switch contacts. The switch status,
either open or closed, is transferred to the microprocessor unit (MCU)
through a serial peripheral interface (SPI). The device also features a
22-to-1 analog multiplexer for reading inputs as analog. The analog
input signal is buffered and provided on the AMUX output pin for the
MCU to read.
MULTIPLE SWITCH
DETECTION INTERFACE
The 33993 device has two modes of operation, Sleep and Normal.
The Sleep mode provides low quiescent current and enables the
wake-up features of the device. Normal mode allows programming of
the device and supplies switch contacts with pull-up or pull-down
current as it monitors switch change of state.
DW SUFFIX
EW SUFFIX (PB-FREE)
98ARH99137A
The 33993 is packaged in the 32-pin wide-body SOIC, reducing
circuit board area. Low quiescent current makes the 33993 ideal for
automotive and industrial products requiring low sleep state currents.
32-PIN SOICW
ORDERING INFORMATION
Features
Temperature
Package
• Designed to Operate 5.5 V ≤ VPWR ≤ 26 V
• Switch Input Voltage Range -14 V to VPWR, 40 V Max
Device
Range (T )
A
MC33993DWB/R2
MCZ33993EW/R2
• Interfaces Directly to Microprocessor Using 3.3 V/5.0 V SPI
Protocol
-40°C to 125°C
32 SOICW
• Selectable Wake-Up on Change of State
• Selectable Wetting Current (16 mA or 2.0 mA)
• 8 Programmable Inputs (Switches to Battery or Ground)
• 14 Switch-to-Ground Inputs
• VPWR Standby Current 100 µA Typical, VDD Standby Current 20 µA Typical
• Active Interrupt (INT) on Change-of-Switch State
• Pb-Free Packaging Designated by Suffix Code EW
VDD
Power Supply
LVI
VBAT
VBAT
33993
MCU
Enable
SP0
SP1
VPWR
Watchdog
Reset
VDD
VBAT
VDD
SP7
WAKE
SI
MOSI
SCLK
CS
SCLK
CS
SG0
SG1
SO
MISO
INT
INT
AMUX
AN0
SG12
SG13
GND
Figure 1. MC33993 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2003-2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V
VPWR
VPWR VPWR
SP0
VPWR, VDD, 5.0 V
VPWR
VDD
16.0
mA
2.0
mA
POR
Bandgap
Sleep PWR
GND
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
To
+
4.0 V
Ref
2.0
mA
16.0
mA
–
SPI
Comparator
VPWR VPWR
SP7
16.0
mA
2.0
mA
5.0 V
VPWR
Oscillator
and
Clock Control
To
SPI
+
4.0 V
Ref
2.0
mA
16.0
mA
–
Comparator
5.0 V
Temperature
Monitor and
Control
5.0 V
VPWR
VPWR VPWR
SG0
5.0 V
125 kΩ
16.0
mA
2.0
mA
5.0 V
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
To
+
4.0 V
Ref
–
SPI
WAKE Control
Comparator
VDD
125 k
SPI Interface
and Control
Ω
INT
INT Control
VDD
MUX Interface
40 µA
CS
SCLK
SI
V
DD
SO
VPWR VPWR
SG13
16.0
mA
2.0
mA
VDD
Analog Mux
Output
+
–
AMUX
To
SPI
+
4.0 V
Ref
–
Comparator
Figure 2. 33993 Simplified Internal Block Diagram
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
PIN CONNECTIONS
PIN CONNECTIONS
GND
SI
SCLK
CS
SO
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
AMUX
INT
SP7
SP6
2
3
4
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VPWR
5
6
7
SP5
SP4
8
9
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
10
11
12
13
14
15
16
Figure 3. 33993 Pin Connections
Table 1. 33993 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
Pin Number Pin Name
Formal Name
Definition
1
2
3
4
GND
SI
Ground
Ground for logic, analog, and switch to battery inputs.
SPI control data input pin from MCU to the 33993.
SPI control clock input pin.
SPI Slave In
Serial Clock
Chip Select
SCLK
CS
SPI control chip select input pin from MCU to the 33993. Logic 0 allows data to be
transferred in.
5–8
25–28
SP0–3
SP4–7
Programmable Switches Programmable switch-to-battery or switch-to-ground input pins.
0–7
9–15,
18–24
SG0–6,
SG13–7
Switch-to-Ground Inputs Switch-to-ground input pins.
0–13
16
V
Battery Input
Wake-Up
Interrupt
Battery supply input pin. Pin requires external reverse battery protection.
Open drain wake-up output. Designed to control a power supply enable pin.
Open-drain output to the MCU. Used to indicate an input switch change of state.
PWR
17
29
30
31
WAKE
INT
AMUX
Analog Multiplex Output Analog multiplex output.
V
Voltage Drain Supply
SPI Slave Out
3.3/5.0 V supply. Sets SPI communication level for the SO driver.
Provides digital data from 33993 to the MCU.
DD
32
SO
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage
V
–
–
-0.3 to 7.0
-0.3 to 7.0
V
V
DD
DC
DC
CS, SI, SO, SCLK, INT, AMUX (1)
(1)
–
–
-0.3 to 40
-0.3 to 50
V
V
V
DC
DC
DC
WAKE
V
Supply Voltage (1)
PWR
Switch Input Voltage Range
–
–
-14 to 40
6.0
Frequency of SPI Operation (VDD = 5.0 V)
MHz
V
ESD Voltage (2)
Human Body Model
Machine Model
VESD1
VESD2
±4000
±200
THERMAL RATINGS
Storage Temperature
T
-55 to 150
-40 to 125
-40 to 150
°C
°C
°C
STG
Operating Case Temperature
Operating Junction Temperature
THERMAL RESISTANCE
TC
TJ
Power Dissipation (TA = 25°C) (3)
PD
1.7
W
Thermal Resistance
Junction to Ambient
Junction to Lead
°C/W
R
74
25
JA
θ
R
JL
θ
(5)
Peak Package Reflow Temperature During Reflow (4)
,
TPPRT
Note 5
°C
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM)
(CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).
3. Maximum power dissipation at TJ =150°C junction temperature with no heat sink used.
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted. Typical values noted reflect the approximate parameter means VPWR = 13 V, TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Supply Voltage
V
Supply Voltage Range Quasi-Functional (6)
Fully Operational
PWR QF
V
5.5
8.0
26
–
–
–
8.0
26
40
(
)
V
V
(
)
PWR FO
Supply Voltage Range Quasi-Functional (6)
PWR
(
)
QF
Supply Current
I
mA
PWR
ON
( )
All Switches Open, Normal Mode, Tri-State Disabled
–
2.0
4.0
Sleep State Supply Current
I
µA
PWR
SS
( )
Scan Timer = 64 ms, Switches Open
40
70
–
100
Logic Supply Voltage
V
3.1
5.25
V
DD
Logic Supply Current
I
mA
DD
All Switches Open, Normal Mode
–
–
0.25
10
0.5
20
Sleep State Logic Supply Current
Scan Timer = 64 ms, Switches Open
I
µA
DD
SS
( )
SWITCH INPUT
Pulse Wetting Current Switch-to-Battery (Current Sink)
Pulse Wetting Current Switch-to-Ground (Current Source)
Sustain Current Switch-to-Battery Input (Current Sink)
Sustain Current Switch-to-Ground Input (Current Source)
I
12
12
15
16
18
18
mA
mA
mA
mA
%
PULSE
PULSE
I
I
1.8
1.8
2.0
2.0
2.2
2.2
SUSTAIN
SUSTAIN
I
Sustain Current Matching Between Channels on Switch-to-Ground
Inputs
I
MATCH
–
2.0
4.0
ISUS(MAX)
I
SUS(MIN)
-
X 100
ISUS(MIN)
Input Offset Current when Selected as Analog
I
-2.0
-10
1.4
2.5
2.0
10
µA
OFFSET
Input Offset Voltage when Selected as Analog
V(SP&SGINPUTS) to AMUX Output
V
mV
OFFSET
Analog Operational Amplifier Output Voltage
V
mV
V
OL
Sink 250 µA
–
10
30
Analog Operational Amplifier Output Voltage
V
OH
Source 250 µA
V
- 0.1
–
4.0
–
–
DD
Switch Detection Threshold
V
3.70
-14
4.3
40
V
V
TH
Switch Input Voltage Range
V
IN
(8)
Temperature Monitor (7)
,
T
155
5.0
–
185
15
°C
°C
LIM
LIM(HYS
Temperature Monitor Hysteresis (8)
T
10
)
Notes
6. Device operational. Table parameters may be out of specification.
7. Thermal shutdown of 16 mA pull-up and pull-down current sources only. 2.0 mA current source/sink and all other functions remain
active.
8. This parameter is guaranteed by design but is not production tested.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted. Typical values noted reflect the approximate parameter means VPWR = 13 V, TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic Voltage Thresholds (9)
SCLK, SI, Tri-State SO Input Current
V
0.8
-10
–
–
2.2
10
V
INLOGIC
I
I
µA
SCLK, SI,
I
0 V to V
DD
SO(TRI)
CS Input Current
µA
I
I
CS
CS
CS = V
-10
30
–
10
DD
CS Pull-Up Current
CS = 0 V
µA
–
–
100
SO High-State Output Voltage
V
V
SO(HIGH)
I
= -200 µA
V
- 0.8
V
DD
SO(HIGH)
DD
SO Low-State Output Voltage
= 1.6 mA
V
V
SO(LOW)
I
–
–
0.4
SO(HIGH)
Input Capacitance on SCLK, SI, Tri-State SO (10)
INT Internal Pull-Up Current
C
–
–
20
pF
µA
V
IN
–
15
40
100
INT Voltage
V
HIGH
INT( )
INT = Open Circuit
V
- 0.5
–
V
DD
DD
INT Voltage
V
V
INT(LOW)
I
= 1.0 mA
–
0.2
40
0.4
INT
WAKE Internal Pull-Up Current
20
100
µA
I
PU
WAKE( )
WAKE Voltage
V
V
WAKE
(
)
HIGH
WAKE = Open Circuit
4.0
–
4.3
0.2
5.3
0.4
WAKE Voltage
V
V
V
V
WAKE(LOW)
WAKE(MAX)
I
= 1.0 mA
WAKE
WAKE Voltage
Maximum Voltage Applied to WAKE Through External Pull-Up
–
–
40
Notes
9. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK.
10. This parameter is guaranteed by design but is not production tested.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 125°C, unless otherwise
noted. Typical values noted reflect the approximate parameter means VPWR = 13 V, TA = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCH INPUT
Pulse Wetting Current Time
t
15
16
20
ms
PULSE
(
ON
)
Interrupt Delay Time
Normal Mode
t
µs
INT-DLY
–
5.0
16
Sleep Mode Switch Scan Time
t
100
200
300
µs
SCAN
Calibrated Scan Timer Accuracy
Sleep Mode
t
%
SCAN TIMER
–
–
–
–
10
10
Calibrated Interrupt Timer Accuracy
Sleep Mode
t
%
INT TIMER
DIGITAL INTERFACE TIMING (11)
Required Low State Duration on VPWR for Reset (12)
t
µs
RESET
VPWR ≤ 0.2 V
–
–
–
10
–
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
t
ns
LEAD
100
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
t
ns
ns
ns
LAG
50
16
–
–
–
–
SI to Falling Edge of SCLK
Required Setup Time
t
SI(SU
)
Falling Edge of SCLK to SI
Required Hold Time
t
SI(HOLD)
20
–
–
–
–
–
SI, CS, SCLK Signal Rise Time (13)
t
t
5.0
5.0
ns
ns
R
F
(SI)
(SI)
SI, CS, SCLK Signal Fall Time (13)
–
Time from Falling Edge of CS to SO Low Impedance (14)
Time from Rising Edge of CS to SO High Impedance (15)
Time from Rising Edge of SCLK to SO Data Valid (16)
Notes
t
–
–
–
–
–
55
55
55
ns
ns
ns
SO(EN
)
t
SO(DIS
)
25
t
VALID
11. These parameters are guaranteed by design. Production test equipment uses a 4.16 MHz, 5.0 V SPI interface.
12. This parameter is guaranteed by design but not production tested.
13. Rise and Fall time of the incoming SI, CS, and SCLK signals are suggested for design considerations to prevent the occurrence of double
pulsing.
14. Time required for valid output status data to be available on SO pin.
15. Time required for output states data to be terminated at SO pin.
16. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
0.2 V
DD
t
t
lag
lead
0.7 V
0.2 V
DD
SCLK
DD
t
t
SI(hold)
SI(su)
0.7 V
0.2 V
DD
SI
MSB in
DD
t
t
valid
SO(en)
t
SO(dis)
0.7 V
0.2 V
DD
SO
MSB out
LSB out
DD
Figure 4. 33993 SPI Timing Characteristics
V
V
PWR
DD
WAKE
INT
Wake-Up From Interrupt
Timer Expire
CS
Wake-Up From
Closed Switch
SGn
Power-Up
Normal Mode
Tri-State
Command
(Disable Tri-State)
Sleep
Command
Sleep Mode
Normal
Mode
Sleep Command
Sleep Mode
Normal
Mode
Sleep Command
Figure 5. Sleep Mode to Normal Mode Operation
.
Switch state change with
CS low generates INT
Switch state change with
CS low generates INT
INT
CS
Latch switch status
on falling edge of CS
Rising edge of CS does not
clear INT because state change
occurred while CS was low
SGn
Switch open “0”
Switch closed “1”
1
1
0
0
1
0
SGn Bit in SPI Word
Switch
Switch
Switch
Switch
Status
Switch
Status
Switch
Status
Status
Status
Status
Command
Command
Command
Command
Command
Command
Figure 6. Normal Mode Interrupt Operation
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33993 device is an integrated circuit designed to
provide systems with ultra-low quiescent sleep/wake-up
modes and a robust interface between switch contacts and a
microprocessor. The 33993 replaces many of the discrete
components required when interfacing to microprocessor-
based systems while providing switch ground offset
protection, contact wetting current, and system wake-up.
switch inputs may be read as analog inputs through the
analog multiplexer (AMUX). Other features include a
programmable wake-up timer, programmable interrupt timer,
programmable wake-up/interrupt bits, and programmable
wetting current settings.
This device is designed primarily for automotive
applications but may be used in a variety of other applications
such as computer, telecommunications, and industrial
controls.
The 33993 features 8-programmable switch-to-ground or
switch-to-battery inputs and 14 switch-to-ground inputs. All
FUNCTIONAL PIN DESCRIPTION
CHIP SELECT (CS)
SPI SLAVE IN (SI)
The system MCU selects the 33993 to receive
The SI pin is used for serial instruction data input. SI
information is latched into the input register on the falling
edge of SCLK. A logic high state present on SI will program
a one in the command word on the rising edge of the CS
signal. To program a complete word, 24 bits of information
must be entered into the device.
communication using the chip select (CS) pin. With the CS in
a logic low state, command words may be sent to the 33993
via the serial input (SI) pin, and switch status information can
be received by the MCU via the serial output (SO) pin. The
falling edge of CS enables the SO output, latches the state of
the INT pin, and the state of the external switch inputs.
SPI SLAVE OUT (SO)
Rising edge of the CS initiates the following operation:
1. Disables the SO driver (high impedance)
The SO pin is the output from the shift register. The SO pin
remains tri-stated until the CS pin transitions to a logic low
state. All open switches are reported as zero, all closed
switches are reported as one. The negative transition of CS
enables the SO driver.
2. INT pin is reset to logic [1], except when additional
switch changes occur during CS low. (See Figure 6.)
Activates the received command word, allowing the 33993
to act upon new data from switch inputs.
The first positive transition of SCLK will make the status
data bit 24 available on the SO pin. Each successive positive
clock will make the next status data bit available for the MCU
to read on the falling edge of SCLK. The SI/SO shifting of the
data follows a first-in-first-out protocol, with both input and
output words transferring the most significant bit (MSB) first.
To avoid any spurious data, it is essential the high-to-low
and low-to-high transitions of the CS signal occur only when
SCLK is in a logic low state. A clean CS signal is needed to
ensure no incomplete SPI words are sent to the device.
Internal to the 33993 device is an active pull-up to V on the
DD
CS.
In Sleep mode the negative edge of the CS (V applied)
will wake up the 33993 device. Data received from the device
during CS wake-up may not be accurate.
DD
INTERRUPT (INT)
The INT pin is an interrupt output from the 33993 device.
The INT pin is an open-drain output with an internal pull-up to
V
. In Normal mode, a switch state change will trigger the
DD
SERIAL CLOCK (SCLK)
INT pin (when enabled). The INT pin and INT bit in the SPI
register are latched on the falling edge of CS. This permits
the MCU to determine the origin of the interrupt. When two
33993 devices are used, only the device initiating the
interrupt will have the INT bit set. The INT pin is cleared on
the rising edge of CS. The INT pin will not clear with rising
edge of CS if a switch contact change has occurred while CS
was low.
The system clock (SCLK) pin clocks the internal shift
register of the 33993. The SI data is latched into the input
shift register on the falling edge of SCLK signal. The SO pin
shifts the switch status bits out on the rising edge of SCLK.
The SO data is available for the MCU to read on the falling
edge of SCLK. False clocking of the shift register must be
avoided to ensure validity of data. It is essential the SCLK pin
be in a logic low state whenever CS makes any transition. For
this reason, it is recommended, though not necessary, that
the SCLK pin is commanded to a low logic state as long as
the device is not accessed and CS is in a logic high state.
When the CS is in a logic high state, any signal on the SCLK
and SI pins will be ignored and the SO pin is tri-state.
In a multiple 33993 device system with WAKE high and
on (Sleep mode), the falling edge of INT will place all
V
DD
33993s in Normal mode.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
WAKE-UP (WAKE)
GROUND (GND)
The WAKE pin is an open-drain output and a wake-up
input. The pin is designed to control a power supply Enable
pin. In the Normal mode, the WAKE pin is low. In the Sleep
mode, the WAKE pin is high. The WAKE pin has a pull-up to
the internal +5.0 V supply.
The GND pin provides ground for the IC as well as ground
for inputs programmed as switch-to-battery inputs.
PROGRAMMABLE SWITCHES 0–7 (SP0–SP7)
The 33993 device has 8 switch inputs capable of being
programmed to read switch-to-ground or switch-to-battery
contacts. The input is compared with a 4.0 V reference.
When programmed to be switch-to-battery, voltages greater
than 4.0 V are considered closed. Voltages less than 4.0 V
are considered open. The opposite holds true when inputs
are programmed as switch-to-ground. Programming features
are defined in Table 5 through Table 10 in the Logic
In Sleep mode with the WAKE pin high, falling edge of
WAKE will place the 33993 in Normal mode. In Sleep mode
with V applied, the INT pin must be high for negative edge
DD
of WAKE to wake up the device. If V is not applied to the
DD
device in Sleep mode, INT does not affect the WAKE
operation.
BATTERY INPUT (VPWR)
Commands and Registers section of this datasheet. Voltages
greater than the V
through the SP inputs to the V
voltages greater than 40 V must be clamped by an external
device.
supply voltage will source current
PWR
The VPWR pin is battery input and Power-ON Reset to the
33993 IC. The VPWR pin requires external reverse battery
and transient protection. Maximum input voltage on VPWR is
50 V. All wetting, sustain, and internal logic current is
provided from the VPWR pin.
pin. Transient battery
PWR
SWITCH-TO-GROUND INPUTS 0–13 (SG0–SG13)
The SGn pins are switch-to-ground inputs only. The input
is compared with a 4.0 V reference. Voltages greater than
4.0 V are considered open. Voltages less than 4.0 V are
considered closed. Programming features are defined in
Table 5 through Table 10 in the Logic Commands and
Registers section of this datasheet. Voltages greater than the
VOLTAGE DRAIN SUPPLY (VDD)
The VDD input pin is used to determine logic levels on the
microprocessor interface (SPI) pins. Current from VDD is
used to drive SO output and the pull-up current for CS and
INT pins. V must be applied for wake-up from negative
DD
edge of CS or INT.
VPWR supply voltage will source current through the SG
inputs to the VPWR pin. Transient battery voltages greater
than 40 V must be clamped by an external device.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DEVICE OPERATION
MCU INTERFACE DESCRIPTION
The 33993 device directly interfaces to a 3.3 V or 5.0 V
microcontroller unit (MCU). SPI serial clock frequencies up to
6.0 MHz may be used for programming and reading switch
input status (production tested at 4.16 MHz). Figure 7
illustrates the configuration between an MCU and one 33993.
MC68HCXX
Microcontroller
33993
MOSI
SI
Shift Register
Serial peripheral interface (SPI) data is sent to the 33993
device through the SI input pin. As data is being clocked into
the SI pin, status information is being clocked out of the
device by the SO output pin. The response to a SPI
command will always return the switch status, interrupt flag,
and thermal flag. Input switch states are latched into the SO
register on the falling edge of the chip select (CS) pin.
Twenty-four bits are required to complete a transfer of
information between the 33993 and the MCU.
MISO
SCLK
SO
SCLK
CS
Parallel
Ports
INT
INT
33993
SI
SO
MC68HCXX
Microcontroller
33993
SCLK
CS
MOSI
MISO
SI
INT
Shift Register
24-Bit Shift Register
SO
Figure 8. SPI Parallel Interface with Microprocessor
SCLK
INT
Receive
Buffer
To Logic
MC68HCXX
CS
Microcontroller
33993
Parallel
Ports
INT
MOSI
SI
Shift Register
MISO
Figure 7. SPI Interface with Microprocessor
SO
SCLK
SCLK
Two or more 33993 devices may be used in a module
system. Multiple ICs may be SPI-configured in parallel or
serial. Figures 8 and 9 show the configurations. When using
the serial configuration, 48-clock cycles are required to
transfer data in/out of the ICs.
Parallel
CS
Ports
INT
INT
33993
SI
SO
SCLK
CS
INT
Figure 9. SPI Serial Interface with Microprocessor
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
OPERATIONAL MODES
POWER SUPPLY
NORMAL MODE
The 33993 is designed to operate from 5.5 V to 40 V on
the VPWR pin. Characteristics are provided from 8.0 V to
16 V for the device. Switch contact currents and the internal
logic supply are generated from the VPWR pin. The VDD
supply pin is used to set the SPI communication voltage
levels, current source for the SO driver, and pull-up current
on INT and CS.
Normal mode may be entered by the following events:
• Application of VPWR to the IC
• Change-of-Switch State (when enabled)
• Falling Edge of WAKE
• Falling Edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
• Falling Edge of CS (with VDD = 5.0 V)
• Interrupt Timer Expires
The VDD supply may be removed from the device to
reduce quiescent current. If V is removed while the device
DD
Only in Normal mode with VDD applied can the registers of
the 33993 be programmed through the SPI.
is in Normal mode, the device will remain in Normal mode. If
V
is removed in Sleep mode, the device will remain in
DD
The registers that may be programmed in Normal mode
are listed below. Further explanation of each register is
provided in subsequent paragraphs.
Sleep mode until wake-up input is received (WAKE high to
low, switch input or interrupt timer expires).
Removing V from the device disables SPI
DD
• Programmable Switch Register (Settings Command)
• Wake-Up/Interrupt Register (Wake-Up/Interrupt
Command)
communication and will not allow the device to wake up from
INT and CS pins.
• Wetting Current Register (Metallic Command)
• Wetting Current Timer Register (Wetting Current Timer
Enable Command)
POWER-ON RESET (POR)
Applying VPWR to the device will cause a Power-ON Reset
and place the device in Normal mode.
• Tri-State Register (Tri-State Command)
• Analog Select Register (Analog Command)
• Calibration of Timers (Calibration Command)
• Reset (Reset Command)
Default settings from Power-ON Reset via VPWR or Reset
Command are as follows:
• Programmable Switch – Set to Switch to Battery
• All Inputs Set as Wake-Up
Figure 6 is a graphical description of the device operation
in Normal mode. Switch states are latched into the input
register on the falling edge of CS. The INT to the MCU is
cleared on the rising edge of CS. However, INT will not clear
on rising edge of CS if a switch has closed during SPI
communication (CS low). This prevents switch states from
being missed by the MCU.
• Wetting Current On (16 mA)
• Wetting Current Timer On (20 ms)
• All Inputs Tri-State
• Analog Select 00000 (No Input Channel Selected)
MODES OF OPERATION
The 33993 has two operating modes, Normal mode and
Sleep mode. A discussion on Normal mode begins below.
A discussion on Sleep mode begins on page 17.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
PROGRAMMABLE SWITCH REGISTER
Inputs SP0 to SP7 may be programmable for switch-to-
battery or switch-to-ground. These inputs types are defined
using the settings command (refer to Table 5). To set an SPn
input for switch-to-battery, a logic [1] for the appropriate bit
must be set. To set an SPn input for switch-to-ground, a logic
[0] for the appropriate bit must be set. The MCU may change
or update the Programmable Switch Register via software at
any time in Normal mode. Regardless of the setting, when the
SPn input switch is closed a logic [1] will be placed in the
Serial Output Response Register (refer to Table 16,
page 17).
Table 5. Settings Command
Settings Command
Not used
Battery/Ground Select
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
waking the IC in Sleep mode (refer to Table 6). Programming
the wake-up/interrupt bit to logic [1] will enable the specific
input to generate an interrupt with switch change of state and
will enable the specific input as wake-up. The MCU may
change or update the Wake-Up/Interrupt Register via
software at any time in Normal mode.
WAKE-UP/INTERRUPT REGISTER
The Wake-Up/Interrupt Register defines the inputs that
are allowed to wake the 33993 from Sleep mode or set the
INT pin low in Normal mode. Programming the wake-up/
interrupt bit to logic [0] will disable the specific input from
generating an interrupt and will disable the specific input from
Table 6. Wake-Up /Interrupt Command
Wake-Up/Interrupt Command
Command Bits
23 22 21 20 19 18 17 16 15 14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
X
X
X
X
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
WETTING CURRENT REGISTER
The 33993 has two levels of switch contact current, 16 mA
and 2.0 mA (see Figure 10). The metallic command is used
to set the switch contact current level (refer to Table 7).
Programming the metallic bit to logic [0] will set the switch
wetting current to 2.0 mA. Programming the metallic bit to
logic [1] will set the switch contact wetting current to 16 mA.
The MCU may change or update the Wetting Current
Register via software at any time in Normal mode.
Switch Contact Voltage
16 mA Switch Wetting Current
Wetting current is designed to provide higher levels of
current during switch closure. The higher level of current is
designed to keep switch contacts from building up oxides that
form on the switch contact surface.
2.0 mA Switch Sustain Current
20 ms Wetting Current Timer
Figure 10. Contact Wetting and Sustain Current
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 7. Metallic Command
Metallic Command
Command Bits
23 22 21 20 19 18 17 16 15 14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
X
X
X
X
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
closed switch contact. With multiple wetting current timers
disabled, power dissipation for the IC must be considered.
WETTING CURRENT TIMER REGISTER
Each switch input has a designated 20 ms timer. The timer
starts when the specific switch input crosses the comparator
threshold (4.0 V). When the 20 ms timer expires, the contact
current is reduced from 16 mA to 2.0 mA. The wetting current
timer may be disabled for a specific input. When the timer is
disabled, 16 mA of current will continue to flow through the
The MCU may change or update the Wetting Current
Timer Register via software at any time in Normal mode. This
allows the MCU to control the amount of time wetting current
is applied to the switch contact. Programming the wetting
current timer bit to logic [0] will disable the wetting current
timer. Programming the wetting current timer bit to logic [1]
will enable the wetting current timer (refer to Table 8).
Table 8. Wetting Current Timer Enable Command
Wetting Current Timer Commands
Command Bits
23 22 21 20 19 18 17 16 15 14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
X
X
X
X
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
comparator on each input remains active. This command
allows the use of each input as a comparator with a 4.0 V
threshold. The MCU may change or update the Tri-State
Register via software at any time in Normal mode.
TRI-STATE REGISTER
The tri-state command is use to set the SPn or SGn input
node as high impedance (refer to Table 9). By setting the
Tri-State Register bit to logic [1], the input will be high
impedance regardless of the metallic command setting. The
Table 9. Tri-State Command
Tri-State Commands
Command Bits
23 22 21 20 19 18 17 16 15 14
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
sg1 sg1 sg1 sg1 sg9 sg8 sg7 sg6 sg5 sg4 sg3 sg2 sg1 sg0
3
2
1
0
selects the input as high impedance. Setting bit 6 and bit 5 to
0,1 selects 2.0 mA, and 1,0 selects 16 mA. Setting bit 6 and
bit 5 to 1,1 in the Analog Select Register is not allowed and
will place the input as an analog input with high impedance.
ANALOG SELECT REGISTER
The analog voltage on switch inputs may be read by the
MCU using the analog command (refer to Table 10). Internal
to the IC is a 22-to-1 analog multiplexer. The voltage present
on the selected input pin is buffered and made available on
the AMUX output pin. The AMUX output pin is clamped to a
Analog currents set by the analog command are pull-up
currents for all SGn and SPn inputs (refer to Table 10). The
analog command does not allow pull-down currents on the
SPn inputs. Setting the current to 16 mA or 2.0 mA may be
useful for reading sensor inputs. Further information is
provided in the Typical Applications section of this datasheet
beginning on page 20. The MCU may change or update the
maximum of V volts regardless of the higher voltages
DD
present on the input pin. After an input has been selected as
the analog, the corresponding bit in the next SO data stream
will be logic [0]. When selecting a channel to be read as
analog, the user must also set the desired current (16 mA,
2.0 mA, or high impedance). Setting bit 6 and bit 5 to 0,0
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Analog Select Register via software at any time in Normal
mode.
Table 10. Analog Command
Analog Command
Current
Not used
Analog Channel Select
Select
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
16 mA 2.0m
A
CALIBRATION OF TIMERS
Table 11. Analog Channel
In cases where an accurate time base is required, the user
may calibrate the internal timers using the calibration
command (refer to Table 12). After the 33993 device
receives the calibration command, the device expects 512 µs
logic [0] calibration pulse on the CS pin. The pulse is used to
calibrate the internal clock. No other SPI pins should
transition during this 512 µs calibration pulse. Because the
oscillator frequency changes with temperature, calibration is
required for an accurate time base. Calibrating the timers has
no affect on the quiescent current measurement. The
calibration command simply makes the time base more
accurate. The calibration command may be used to update
the device on a periodic basis.
Analog Channel
Bits 43210
Analog Channel
Select
Bits 43210
Select
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
No Input Selected
SG0
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
SG11
SG12
SG13
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
Table 12. Calibration Command
Calibration Command
Command Bits
23
0
22
0
21
0
20
0
19
1
18
0
17
1
16
1
15
X
14
X
13
X
12
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
states or the paragraph entitled Power-ON Reset (POR) on
page 12 of this datasheet.
RESET
The reset command resets all registers to Power-ON
Reset (POR) state. Refer to Table 14, page 16, for POR
Table 13. Reset Command
Reset Command
Command Bits
23
0
22
1
21
1
20
1
19
1
18
1
17
1
16
1
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Output (SO) data for input voltages greater or less than the
threshold level. Open switches are always indicated with a
logic [0], closed switches are indicated with logic [1].
SPI COMMAND SUMMARY
Table 14 below provides a comprehensive list of SPI
commands recognized by the 33993 and the reset state of
each register. Table 15 and Table 16 contain the Serial
Table 14. SPI Command Summary
MSB
Command Bits
Setting Bits
LSBI
23
22
0
21
0
20
0
19
0
18
0
17
0
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
Switch Status
Command
0
0
X
X
X
X
X
X
X
X
X
X
Settings Command
Bat=1, Gnd=0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
(Default state = 1)
Wake-Up/Interrupt
Bit
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
X
X
X
X
Wake-Up=1
Nonwake-Up=0
(Default state = 1)
SG1 SG1 SG1 SG1
3
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
2
1
0
Metallic Command
Metallic = 1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Non-metallic = 0
(Default state = 1)
SG1 SG1 SG1 SG1
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
3
X
X
2
X
X
1
X
X
0
X
X
16m 2.0m
Analog Command
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
X
X
X
X
X
X
X
X
X
A
0
A
0
0
0
0
0
0
Wetting Current
Timer
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
Enable Command
Timer ON = 1
SG1 SG1 SG1 SG1
0
0
0
0
1
0
0
0
X
X
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
Timer OFF = 0
(Default state = 1)
3
2
1
0
Tri-State Command
Input Tri-State=1
Input Active = 0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG1 SG1 SG1 SG1
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
3
2
1
0
(Default state = 1)
Calibration
Command
0
0
0
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(Default state -
uncalibrated)
Sleep Command
int
int
int scan scan scan
0
0
0
1
0
1
0
1
1
1
1
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(See Sleep Mode
on page 17)
timer timer timer timer timer timer
Reset Command
X
X
X
X
X
X
them int
SO Response Will
Always Send
SG1 SG1 SG1 SG1
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
3
2
1
0
flg
flg
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 15. Serial Output (SO) Bit Data
Table 15. Serial Output (SO) Bit Data
Input
Programmed
Voltage on
Input Pin
Type of Input
SO SPI Bit
Input
Programmed
Voltage on
Input Pin
Type of Input
SO SPI Bit
N/A
N/A
SGn < 4.0 V
SGn > 4.0 V
1
0
Switch to
Ground
SPn < 4.0 V
SPn > 4.0 V
SPn < 4.0 V
SPn > 4.0 V
1
SG
Switch to
Ground
0
0
1
SP
Switch to
Battery
Switch to
Battery
Table 16. Serial Output (SO) Response Register
them int
SO Response Will
Always Send
SG1 SG1 SG1 SG1
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
SG9 SG8 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0
3
2
1
0
flg
flg
EXAMPLE OF NORMAL MODE OPERATION
SLEEP MODE
The operation of the device in Normal Mode is defined by
the states of the programmable internal control registers. A
typical application may have the following settings:
Sleep mode is used to reduce system quiescent currents.
Sleep mode may be entered only by sending the sleep
command. All register settings programmed in Normal mode
will be maintained in Sleep mode.
• Programmable Switch – Set to Switch-to-Ground
• All Inputs Set as Wake-Up
• Wetting Current On (16 mA)
The 33993 will exit Sleep mode and enter Normal mode
when any of the following events occur:
• Input Switch Change of State (when enabled)
• Interrupt Timer Expire
• Falling Edge of WAKE
• Wetting Current Timer On (20 ms)
• All inputs Tri-State-Disabled (comparator is active)
• Analog select 00000 (no input channel selected)
• Falling Edge of INT (with VDD = 5.0 V and WAKE at
Logic [1])
• Falling Edge of CS (with VDD = 5.0 V)
• Power-ON Reset (POR)
With the device programmed as above, an interrupt will be
generated with each switch contact change of state (open-to-
close or close-to-open) and 16 mA of contact wetting current
will be source for 20 ms. The INT pin will remain low until
switch status is acknowledged by the microprocessor. It is
critical to understand INT will not be cleared on the rising
edge of CS if a switch closure occurs while CS is low. The
maximum duration a switch state change can exist without
acknowledgement depends on the software response time to
the interrupt. Figure 4, page 8, shows the interaction
The V supply may be removed from the device during
DD
Sleep mode. However removing V from the device in
DD
Sleep mode will disable a wake-up from falling edge of INT
and CS.
Note In cases where CS is used to wake the device, the
first SO data message is not valid.
between changing input states and the INT and CS pins.
The sleep command contains settings for two
programmable timers for Sleep mode, the interrupt timer and
the scan timer, as shown in Table 17.
If desired the user may disable interrupts (wake up/
interrupt command) from the 33993 device and read the
switch states on a periodic basis. Switch activation and
deactivation faster than the MCU read rate will not be
acknowledged.
The interrupt timer is used as a periodic wake-up timer.
When the timer expires, an interrupt is generated and the
device enters Normal mode. Table 18 shows the
programmable settings of the Interrupt timer.
The 33993 device will exit the Normal mode and enter the
Sleep mode only with a valid sleep command.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 17. Sleep Command
Sleep Command
Command Bits
23
0
22
0
21
0
20
0
19
1
18
1
17
0
16
0
15
X
14
X
13
X
12
X
11
X
10
X
9
8
7
6
5
4
3
2
1
0
X
X
X
X
Table 19. Scan Timer
Bits 210
Table 18. Interrupt Timer
Bits 543
Scan Period
Interrupt Period
110
111
32 ms
64 ms
000
001
010
011
100
101
110
111
32 ms
64 ms
Note The interrupt and scan timers are disabled in the
Normal mode.
128 ms
256 ms
512 ms
1.024 s
2.048 s
4.096 s
Figure 5, page 8, is a graphical description of how the
33993 device exits Sleep mode and enters Normal mode.
Notice that the device will exit Sleep mode when the interrupt
timer expires or when a switch change of state occurs. The
falling edge of INT triggers the MCU to wake from Sleep
state. Figure 11 illustrates the current consumed during
Sleep mode. During the 125 µs, the device is fully active and
switch states are read. The quiescent current is calculated by
integrating the normal running current over scan period plus
approximately 60 µA.
The scan timer sets the polling period between input
switch reads in Sleep mode. The period is set in the sleep
command and may be set to 000 (no period) to 111 (64 ms).
In Sleep mode when the scan timer expires, inputs will
behave as programmed prior to sleep command. The 33993
will wake up for approximately 125 µs and read the switch
inputs. At the end of the 125 µs, the input switch states are
compared with the switch state prior to sleep command.
When switch state changes are detected, an interrupt (when
I=V/R or 0.270 V/100 Ω=2.7 mA
enabled; refer to wake-up/interrupt command description on
page 13) is generated and the device enters Normal mode.
Without switch state changes, the 33993 will reset the scan
timer, inputs become tri-state, and the Sleep mode continues
until the scan timer expires again.
Table 19 shows the programmable settings of the Scan
timer.
Inputs active for
A
6.0 mV/100 Ω=60 µA
I=V/R or
125 µs out of 32 ms
Table 19. Scan Timer
Bits 210
Scan Period
Figure 11. Sleep Current Waveform
TEMPERATURE MONITOR
000
001
010
011
100
101
No Scan
1.0 ms
2.0 ms
4.0 ms
8.0 ms
16 ms
With multiple switch inputs closed and the device
programmed with the wetting current timers disabled,
considerable power will be dissipated by the IC. For this
reason temperature monitoring has been implemented. The
temperature monitor is active in the Normal mode only. When
the IC temperature is above the thermal limit, the temperature
monitor will do all of the following:
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
• Generate an interrupt
The thermal flag bit in the SPI word will be cleared on rising
edge of CS provided the die temperature has cooled below
the thermal limit. When die temperature has cooled below
thermal limit, the device will resume previously programmed
settings.
• Force all 16 mA pull-up and pull-down current sources
to revert to 2.0 mA current sources.
• Maintain the 2.0 mA current source and all other
functionality
• Set the thermal flag bit in the SPI output register
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
TYPICAL APPLICATIONS
INTRODUCTION
TYPICAL APPLICATIONS
INTRODUCTION
The 33993’s primary function is the detection of open or
closed switch contacts. However, there are many features
that allow the device to be used in a variety of applications.
The following is a list of applications to consider for the IC:
METALLIC/ELASTOMERIC SWITCH
Metallic switch contacts often develop higher contact
resistance over time owing to contact corrosion. The
corrosion is induced by humidity, salt, and other elements
that exist in the environment. For this reason the 33993
provides two settings for contacts. When programmed for
metallic switches, the device provides higher wetting current
to keep switch contacts free of oxides. The higher current
occurs for the first 20 ms of switch closure. Where longer
duration of wetting current is desired, the user may send the
wetting current timer command and disable the timer. Wetting
current will be continuous to the closed switch. After the time
period set by the MCU, the wetting current timer command
may be sent again to enable the timer. The user must
consider power dissipation on the device when disabling the
timer. (Refer to the paragraph entitled Temperature Monitor,
page 18.)
• Sensor Power Supply
• Switch Monitor for Metallic or Elastomeric Switches
• Analog Sensor Inputs (Ratiometric)
• Power MOSFET/LED Driver and Monitor
• Multiple 33993 Devices in a Module System
The following paragraphs describe the applications in
detail.
SENSOR POWER SUPPLY
Each input may be used to supply current to sensors
external to a module. Many sensors such as Hall effect,
pressure sensors, and temperature sensors require a supply
voltage to power the sensor and provide an open collector or
analog output. Figure 12 shows how the 33993 may be used
to supply power and interface to these types of sensors. In an
application where the input makes continuous transitions,
consider using the wake-up/interrupt command to disable
the interrupt for the particular input.
To increase the amount of wetting current for a switch
contact, the user has two options. Higher wetting current to a
switch may be achieved by paralleling SGn or SPn inputs.
This will increase wetting current by 16 mA for each input
added to the switch contact. The second option is to simply
add an external resistor pull-up to the V
supply for switch-
PWR
to-ground inputs or a resistor to ground for a switch-to-battery
input. Adding an external resistor has no effect on the
operation of the device.
33993
VBAT
Elastomeric switch contacts are made of carbon and have
a high contact resistance. Resistance of 1.0 kΩ is common.
In applications with elastomeric switches, the pull-up and
pull-down currents must be reduced to prevent excessive
power dissipation at the contact. Programming for a lower
current settings is provided in the Functional Device
Operation Section beginning on page 11 under Table 7,
Metallic Command.
SP0
VPWR
SP1
V
DD
MCU
VDD
VBAT
SP7
WAKE
SI
MOSI
SCLK
CS
SG0
SG1
SCLK
CS
V
V
PWR PWR
SO
MISO
INT
16
mA
2.0
mA
ANALOG SENSOR INPUTS (RATIOMETRIC)
INT
16 mA
SG12
SG13
The 33993 features a 22-to-1 analog multiplexer. Setting
the binary code for a specific input in the analog command
allows the microcontroller to perform analog to digital
conversion on any of the 22 inputs. On rising edge of CS the
multiplexer connects a requested input to the AMUX pin. The
V
V
PWR PWR
Hall-Effect
Sensor
16
2.0
mA
mA
Reg
AMUX pin is clamped to max of V volts regardless of the
DD
X
higher voltages present on the input pin. After an input has
been selected as the analog, the corresponding bit in the next
SO data stream will be logic [0].
2.5 k
Ω
IOC[7:0]
Input Capture
Timer Port
2.5 k
Ω
The input pin, when selected as analog, may be
configured as analog with high impedance, analog with
2.0 mA pull-up, or analog with 16 mA pull-up. Figure 13,
page 21, shows how the 33993 may be used to provide a
ratiometric reading of variable resistive input.
Figure 12. Sensor Power Supply
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
TYPICAL APPLICATIONS
INTRODUCTION
I1 x R1
I2 x R2
33993
VBAT
VBAT
ADC =
x 225
SP0
SP1
VPWR
2.0 mA x 2.0 kΩ
2.0 mA x 2.39 kΩ
VDD
ADC =
x 225
MCU
VDD
ADC = 213 counts
SP7
WAKE
SI
The ADC value of 213 counts is the value with 0% error
(neglecting the resistor tolerance and AMUX input offset
voltage). Now we can calculate the count value induced by
the mismatch in current sources. From a sample device the
maximum current source was measured at 2.05 mA and
minimum current source was measured at 1.99 mA. This
yields 3% error in A/D conversion. The A/D measurement
will be as follows:
MOSI
SCLK
CS
SG0
SG1
SCLK
CS
V
V
PWR PWR
MISO
INT
SO
16
mA
2.0
mA
I
INT
1
2.0 mA
SG12
AMUX
AN0
V
V
R
PWR PWR
1
Analog
Ports
16
mA
2.0
mA
Analog Sensor
or Analog Switch
SG13
1.99 mA x 2.0 kΩ
ADC =
x 225
2.05 mA x 2.39 kΩ
I
2.02mA
4.54 V to 5.02 V
ADC = 207 counts
V
REF(H)
REF(L)
2.39 k
Ω
R
2
0.1%
This A/D conversion is 3% low in value. The error
V
correction factor of 1.03 may be used to correct the value:
Figure 13. Analog Ratiometric Conversion
To read a potentiometer sensor, the wiper should be
grounded and brought back to the module ground, as
illustrated in Figure 13. With the wiper changing the
impedance of the sensor, the analog voltage on the input will
represent the position of the sensor.
ADC = 207 counts x 1.03
ADC = 213 counts
An error correction factor may then be stored in E2
memory and used in the A/D calculation for the specific input.
Each input used as analog measurement will have a
dedicated calibrated error correction factor.
Using the Analog feature to provide 2.0 mA of pull-up
current to an analog sensor may induce error due to the
accuracy of the current source. For this reason, a ratiometric
conversion must be considered. Using two current sources
(one for the sensor and one to set the reference voltage to the
A/D converter) will yield a maximum error (owing to the
33993) of 4%.
POWER MOSFET/LED DRIVER AND MONITOR
Because of the flexible programming of the 33993 device,
it may be used to drive small loads like LEDs or MOSFET
gates. It was specifically designed to power up in the Normal
mode with the inputs tri-state. This was done to ensure the
LEDs or MOSFETs connected to the 33993 power up in the
off-state. The Switch Programmable (SP0–SP7) inputs have
a source-and-sink capability, providing effective MOSFET
gate control. To complete the circuit, a pull-down resistor
should be used to keep the gate from floating during the
Sleep modes. Figure 14, page 22, shows an application
where the SG0 input is used to monitor the drain-to-source
voltage of the external MOSFET. The 1.5 kΩ resistor is used
to set the drain-to-source trip voltage. With the 2.0 mA
current source enabled, an interrupt will be generated when
the drain-to-source voltage is approximately 1.0 V.
Higher accuracy may be achieved through module level
calibration. In this example, we use the resistor values from
Figure 13 and assume the current sources are 4% from each
other. The user may use the module end-of-line tester to
calculate the error in the A/D conversion. By placing a
2.0 kΩ, 0.1% resistor in the end-of-line test equipment and
assuming a perfect 2.0 mA current source from the 33993, a
calculated A/D
conversion may be obtained. Using the equation yields the
following:
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
TYPICAL APPLICATIONS
INTRODUCTION
current to the 1.5 kΩ resistor, the analog voltage on the SGn
pin will be approximately:
VBAT
V
V
PWR PWR
SG0
VSGn = ISGn x 1.5 kΩ + VDS
16
mA
2.0
mA
As the voltage on the drain of the MOSFET increases, so
does the voltage on the SGn pin. With the SGn pin selected
as analog, the MCU may perform the A/D conversion.
1.5 k
Ω
SG0
AMUX
100 k
Ω
+
To SPI
4.0 V Ref
-
Using this method for controlling unclamped inductive
Comparator
loads is not recommended. Inductive flyback voltages greater
V
V
PWR
PWR
SG0
than V
may damage the IC.
PWR
16
mA
2.0
mA
The SP0–SP7 pins of this device may also be used to
send signals from one module to another. Operation is similar
to the gate control of a MOSFET.
SP0
+
To SPI
4.0 V
Ref
Comparator
-
For LED applications a resistor in series with the LED is
recommended but not required. The switch-to-ground inputs
are recommended for LED application. To drive the LED use
the following commands:
16
mA
2.0 mA
V
V
PWR PWR
SG13
•
wetting current timer enable command –Disable SGn
wetting current timer
16
mA
2.0
mA
SG13
•
metallic command –Set SGn to 16 mA
From this point forward the LED may be turned on and off
using the tri-state command:
+
To SPI
4.0 V Ref
-
Comparator
•
•
tri-state command –Disable tri-state for SGn (LED ON)
tri-state command –Enable tri-state for SGn (LED OFF)
These parameters are easily programmed via SPI
commands in Normal mode.
Figure 14. MOSFET or LED Driver Output
The sequence of commands (from Normal mode with
inputs tri-state) required to set up the device to drive a
MOSFET are as follows:
MULTIPLE 33993 DEVICES IN A MODULE SYSTEM
Connecting power to the 33993 and the MCU for Sleep
mode operation may be done in several ways. Table 20
shows several system configurations for power between the
MCU and the 33993 and their specific requirements for
functionality.
•
•
•
•
wetting current timer enable command –Disable SPn
wetting current timer (refer to Table 8, page 14)
metallic command –Set SPn to 16 mA or 2.0 mA gate
drive current (refer to Table 7, page 14)
settings command –Set SPn as switch-to-battery (refer
to Table 5, page 13)
Table 20. Sleep Mode Power Supply
tri-state command –Disable tri-state for SPn (refer to
Table 9, page 14)
MCU
VDD
33993
VDD
Comments
After the tri-state command has been sent (tri-state
disable), the MOSFET gate will be pulled to ground. From this
point forward the MOSFET may be turned on and off by
sending the settings command:
All wake-up conditions apply. (Refer to Sleep Mode,
page 17.)
5.0 V
5.0 V
5.0 V
0 V
SPI wake-up is not possible.
•
settings command –SPn as switch-to-ground
(MOSFET ON)
settings command –SPn as switch-to-battery
(MOSFET OFF)
Sleep mode not possible. Current from CS pull up will
•
0 V
0 V
5.0 V flow through MCU to V that has been switched off.
DD
Negative edge of CS will put 33993 in Normal mode.
Monitoring of the MOSFET drain in the OFF state provides
open load detection. This is done by using an SGn input
comparator. With the SGn input in tri-state, the load will pull
up the SGn input to battery. With open load the SGn pin is
pulled down to ground through an external resistor. The open
load is indicated by a logic [1] in the SO data bit.
0 V
SPI wake-up is not possible.
Multiple 33993 devices may be used in a module system.
SPI control may be done in parallel or serial. However when
parallel mode is used, each device is addressed
independently (refer to MCU Interface Description, page 11).
Therefore when sending the sleep command, one device will
enter sleep before the other. For multiple devices in a system,
it is recommended that the devices are controlled in serial (S0
The analog command may be used to monitor the drain
voltage in the MOSFET ON state. By sourcing 2.0 mA of
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
TYPICAL APPLICATIONS
INTRODUCTION
from first device is connected to SI of second device). With
two devices, 48 clock pulses are required to shift data in.
When the WAKE feature is used to enable the power supply,
both WAKE pins should be connected to the enable pin on
the power supply. The INT pins may be connected to one
interrupt pin on the MCU or may have their own dedicated
interrupt to the MCU.
of transients on the V
pin, an internal reset may occur.
PWR
Upon reset the 33993 will enter Normal mode with the
internal registers as defined in Table 14, page 16. Therefore
it is recommended that the MCU periodically update all
registers internal to the IC.
USING THE WAKE FEATURE
The transition from Normal to Sleep mode is done by
sending the sleep command. With the devices connected in
serial and the sleep command sent, both will enter Sleep
mode on the rising edge of CS. When Sleep mode is entered,
the WAKE pin will be logic [1]. If either device wakes up, the
WAKE pin will transition low, waking the other device.
The 33993 provides a WAKE output and wake-up input
designed to control an enable pin on system power supply.
While in the Normal mode, the WAKE output is low, enabling
the power supply. In the Sleep mode, the WAKE pin is high,
disabling the power supply. The WAKE pin has a passive
pull-up to the internal 5.0 V supply but may be pulled up
through a resistor to V
supply (see Figure 16, page 24)
A condition exists where the MCU is sending the sleep
command (CS logic [0]) and a switch input changes state.
With this event the device that detects this input will not
transition to Sleep mode, while the second device will enter
Sleep mode. In this case two switch status commands must
be sent to receive accurate switch status data. The first
switch status command will wake the device in Sleep mode.
Switch status data may not be valid from the first switch
status command because of the time required for the input
voltage to rise above the 4.0 V input comparator threshold.
This time is dependant on the impedance of SGn or SPn
node. The second switch status command will provide
accurate switch status information. It is recommended that
software wait 10 ms to 20 ms between the two switch status
commands, allowing time for switch input voltages to
stabilize. With all switch states acknowledged by the MCU,
the sleep sequence may be initiated. All parameters for Sleep
mode should be updated prior to sending the sleep
command.
PWR
When the WAKE output is not used the pin should be
pulled up to the VDD supply through a resistor as shown in
Figure 15, page 24.
During the Sleep mode, a switch closure will set the WAKE
pin low, causing the 33993 to enter the Normal mode. The
power supply will then be activated, supplying power to the
VDD pin and the microprocessor and the 33993. The
microprocessor can determine the source of the wake-up by
reading the interrupt flag.
COST AND FLEXIBILITY
Systems requiring a significant number of switch
interfaces have many discrete components. Discrete
components on standard PWB consume board space and
must be checked for solder joint integrity. An integrated
approach reduces solder joints, consumes less board space,
and offers wider operating voltage, analog interface
capability, and greater interfacing flexibility.
The 33993 IC has an internal 5.0 V supply from V
pin.
PWR
A POR circuit monitors the internal 5.0 V supply. In the event
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
TYPICAL APPLICATIONS
INTRODUCTION
VPWR
VDD
VDD
VBAT
VBAT
Power
Supply
33993
VPWR
VPWR
SP0
SP1
VDD
VDD
VBAT
MC68HCXX
Microprocessor
SP7
WAKE
CS
CS
SG0
SG1
INT
SI
INT
MOSI
MISO
SO
SCLK
SCLK
AN0
AMUX
SG12
SG13
Figure 15. Power Supply Active in Sleep Mode
VPWR VDD
VDD
VBAT
VBAT
Power
Supply
33993
VPWR
Enable
VPWR
SP0
SP1
VDD
WAKE
VDD
VBAT
MC68HCXX
Microprocessor
SP7
CS
CS
SG0
SG1
INT
SI
INT
MOSI
MISO
SO
SCLK
SCLK
AN0
AMUX
SG12
SG13
Figure 16. Power Supply Shutdown in Sleep Mode
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
DWB SUFFIX
EW SUFFIX (PB-FREE)
32-PIN SOICW
98ARH99137A
REVISION B
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
PACKAGING
PACKAGE DIMENSIONS
DWB SUFFIX
EW SUFFIX (PB-FREE)
32-PIN SOICW
98ARH99137A
REVISION B
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
• Implemented Revision History page
• Converted to Freescale form and style.
• Added MCZ33993EW/R2 to the ordering information.
6/2007
4.0
6/2007
5/2008
• Corrected package type designation
5.0
6.0
• Added statement to Chip Select description on page 9.
33993
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
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MC33993
Rev. 6
5/2008
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