K30P81M100SF2_11 [FREESCALE]
Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz; 高达100 MHz的ARM Cortex -M4内核，提供1.25 Dhrystone MIPS的每MHz的DSP指令
| 型号： | K30P81M100SF2_11 |
| 厂家： | 
Freescale |
| 描述： | Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz |
| 文件： | 总62页 (文件大小：1730K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: K30P81M100SF2
Rev. 4, 3/2011
Freescale Semiconductor
Data Sheet: Product Preview
K30P81M100SF2
K30 Sub-Family Data Sheet
Supports the following:
MK30N512VLK100, MK30N512VMB100
Features
Human-machine interface
•
•
Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
– Segment LCD controller supporting up to 40
frontplanes and 8 backplanes, or 44 frontplanes and
4 backplanes
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
•
•
•
Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
Analog modules
– Two 16-bit SAR ADCs
– Programmable gain amplifier (up to x64) integrated
into each ADC
– 12-bit DAC
– Three analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
Memories and memory interfaces
– Up to 512 KB program flash memory on non-
FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
Timers
•
Clocks
•
•
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timer
– Two 2-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
System peripherals
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Software watchdog
Communication interfaces
– Controller Area Network (CAN) module
– Two SPI modules
– Two I2C modules
– Four UART modules
•
– Low-leakage wakeup unit
– Secure Digital host controller (SDHC)
– I2S module
Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
•
– 128-bit unique identification (ID) number per chip
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2011 Freescale Semiconductor, Inc.
Preliminary
Table of Contents
1 Ordering parts...........................................................................3
5.3.2 Thermal attributes.................................................18
6 Peripheral operating requirements and behaviors....................19
6.1 Core modules....................................................................19
6.1.1 Debug trace timing specifications.........................19
6.1.2 JTAG electricals....................................................20
6.2 System modules................................................................23
6.3 Clock modules...................................................................23
6.3.1 MCG specifications...............................................23
6.3.2 Oscillator electrical specifications.........................26
6.3.3 32kHz Oscillator Electrical Characteristics............28
6.4 Memories and memory interfaces.....................................28
6.4.1 Flash (FTFL) electrical specifications....................29
6.4.2 EzPort Switching Specifications............................30
6.5 Security and integrity modules..........................................31
6.6 Analog...............................................................................31
6.6.1 ADC electrical specifications.................................31
6.6.2 CMP and 6-bit DAC electrical specifications.........38
6.6.3 12-bit DAC electrical characteristics.....................41
6.6.4 Voltage reference electrical specifications............44
6.7 Timers................................................................................45
6.8 Communication interfaces.................................................45
6.8.1 CAN switching specifications................................46
6.8.2 DSPI switching specifications (low-speed mode)..46
6.8.3 DSPI switching specifications (high-speed mode) 47
6.8.4 I2C switching specifications..................................49
6.8.5 UART switching specifications..............................49
6.8.6 SDHC specifications.............................................49
6.8.7 I2S switching specifications..................................50
6.9 Human-machine interfaces (HMI)......................................52
6.9.1 TSI electrical specifications...................................52
6.9.2 LCD electrical characteristics................................53
7 Dimensions...............................................................................54
7.1 Obtaining package dimensions.........................................54
8 Pinout........................................................................................54
8.1 K30 Signal Multiplexing and Pin Assignments..................54
8.2 K30 Pinouts.......................................................................58
9 Revision History........................................................................60
1.1 Determining valid orderable parts......................................3
2 Part identification......................................................................3
2.1 Description.........................................................................3
2.2 Format...............................................................................3
2.3 Fields.................................................................................3
2.4 Example............................................................................4
3 Terminology and guidelines......................................................4
3.1 Definition: Operating requirement......................................4
3.2 Definition: Operating behavior...........................................5
3.3 Definition: Attribute............................................................5
3.4 Definition: Rating...............................................................6
3.5 Result of exceeding a rating..............................................6
3.6 Relationship between ratings and operating
requirements......................................................................6
3.7 Guidelines for ratings and operating requirements............7
3.8 Definition: Typical value.....................................................7
3.9 Typical value conditions....................................................8
4 Ratings......................................................................................8
4.1 Thermal handling ratings...................................................9
4.2 Moisture handling ratings..................................................9
4.3 ESD handling ratings.........................................................9
4.4 Voltage and current operating ratings...............................9
5 General.....................................................................................10
5.1 Nonswitching electrical specifications...............................10
5.1.1 Voltage and current operating requirements.........10
5.1.2 LVD and POR operating requirements.................11
5.1.3 Voltage and current operating behaviors..............11
5.1.4 Power mode transition operating behaviors..........12
5.1.5 Power consumption operating behaviors..............13
5.1.6 EMC radiated emissions operating behaviors.......16
5.1.7 Designing with radiated emissions in mind...........17
5.1.8 Capacitance attributes..........................................17
5.2 Switching specifications.....................................................17
5.2.1 Device clock specifications...................................17
5.2.2 General switching specifications...........................17
5.3 Thermal specifications.......................................................18
5.3.1 Thermal operating requirements...........................18
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
2
Freescale Semiconductor, Inc.
Preliminary
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PK30 and MK30.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
M
Kinetis family
• K30
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
3
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• EX = 64 QFN (9 mm x 9 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• MB = 81 MAPBGA (8 mm x 8 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
• MF = 196 MAPBGA (15 mm x 15 mm)
• MJ = 256 MAPBGA (17 mm x 17 mm)
CCC
Maximum CPU frequency (MHz)
Packaging type
• 50 = 50 MHz
• 72 = 72 MHz
• 100 = 100 MHz
• 120 = 120 MHz
• 150 = 150 MHz
N
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK30N512VMD100
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
4
Freescale Semiconductor, Inc.
Preliminary
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
3.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
3.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
6
Freescale Semiconductor, Inc.
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
Fatal
range
Normal
operating
range
Fatal
range
- Probable permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
- No permanent failure
–∞
∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
7
Preliminary
Ratings
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
V
VDD
3.3 V supply voltage
3.3
4 Ratings
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
8
Freescale Semiconductor, Inc.
Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
2
TSDR
Solder temperature, lead-free
Solder temperature, leaded
—
—
260
245
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
ILAT
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 85°C
-500
-100
+500
+100
V
2
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
5.5
mA
V
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
9
General
Symbol
VAIO
ID
Description
Min.
Max.
Unit
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
VDDA
VBAT
Analog supply voltage
VDD – 0.3
–0.3
VDD + 0.3
3.8
V
V
RTC battery supply voltage
5 General
5.1 Nonswitching electrical specifications
5.1.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
–0.1
–0.1
1.71
3.6
0.1
0.1
3.6
V
V
V
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
VBAT
VIH
RTC battery supply voltage
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IIC
Input hysteresis
0.06 × VDD
—
V
DC injection current — single pin
• VIN < VSS
1
1
0
–0.2
mA
DC injection current — total MCU limit, includes sum
of all stressed pins
0
–5
mA
• VIN < VSS
VRAM
VDD voltage required to retain RAM
1.2
—
—
V
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
TBD
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
10
Freescale Semiconductor, Inc.
General
1. All functional non-supply pins are internally clamped to VSS, and induce an injection current when VIN is less than VSS. The
IIC maximum operating requirement should not be exceeded. If this requirement cannot be met, the input must be current
limited to the value specified.
5.1.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR
Falling VDD POR detect voltage
TBD
1.1
TBD
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
TBD
2.56
TBD
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
TBD
TBD
TBD
TBD
2.70
2.80
2.90
3.00
TBD
TBD
TBD
TBD
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
60
mV
V
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
TBD
1.60
TBD
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
TBD
TBD
TBD
TBD
1.80
1.90
2.00
2.10
TBD
TBD
TBD
TBD
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
40
mV
VBG
tLPO
Bandgap voltage reference
TBD
TBD
1.00
TBD
TBD
V
Internal low power oscillator period
factory trimmed
1000
μs
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
TBD
1.1
TBD
V
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
11
General
5.1.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
VDD – 0.5
—
—
V
V
Output high voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
—
100
mA
Output low voltage — high drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
—
0.5
0.5
V
V
Output low voltage — low drive strength
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
Input leakage current (per pin)
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
—
—
30
30
100
1
mA
μA
μA
kΩ
kΩ
1
IOZ
1
RPU
RPD
50
50
2
3
Internal pulldown resistors
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.1.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus clock = 50 MHz
• Flash clock = 25 MHz
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
12
Freescale Semiconductor, Inc.
Preliminary
General
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
1
RUN → VLLS1 → RUN
• RUN → VLLS1
—
—
4.1
μs
μs
• VLLS1 → RUN
123.8
RUN → VLLS2 → RUN
• RUN → VLLS2
—
—
4.1
μs
μs
• VLLS2 → RUN
49.3
RUN → VLLS3 → RUN
• RUN → VLLS3
—
—
4.1
μs
μs
• VLLS3 → RUN
49.2
RUN → LLS → RUN
• RUN → LLS
—
—
4.1
5.9
μs
μs
• LLS → RUN
RUN → STOP → RUN
• RUN → STOP
—
—
4.1
4.2
μs
μs
• STOP → RUN
RUN → VLPS → RUN
• RUN → VLPS
—
—
4.1
5.8
μs
μs
• VLPS → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
5.1.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
TBD
mA
1
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
2
• @ 1.8V
• @ 3.0V
—
—
40
42
TBD
TBD
mA
mA
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
13
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
3
• @ 1.8V
• @ 3.0V
—
—
55
56
TBD
TBD
mA
mA
IDD_RUN_M Run mode current — all peripheral clocks
4
enabled and peripherals active, code executing
AX
from flash
• @ 1.8V
—
—
85
85
TBD
TBD
mA
mA
• @ 3.0V
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
—
35
15
TBD
TBD
mA
mA
2
5
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
—
—
0.4
TBD
TBD
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
1.25
6
7
8
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
TBD
TBD
mA
IDD_VLPW Very-low-power wait mode current at 3.0 V
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
1.05
50
TBD
TBD
TBD
mA
μA
μA
IDD_LLS
Low leakage stop mode current at 3.0 V
12
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
• 128KB RAM devices
—
8
TBD
μA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
4
2
TBD
TBD
TBD
μA
μA
nA
IDD_VBAT Average current when CPU is not accessing
RTC registers at 3.0 V
550
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock . MCG configured for FEI mode. All peripheral
clocks disabled.
3. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, but peripherals are not in active operation.
4. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled, and peripherals are in active operation.
5. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz flash clock. MCG configured for FEI mode.
6. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
disabled. Code executing from flash.
7. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
8. 2 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral clocks
disabled.
9. Includes 32kHz oscillator current and RTC operation.
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
14
Freescale Semiconductor, Inc.
Preliminary
General
5.1.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks disabled except FTFL
• LVD disabled
• No GPIOs toggled
• Code execution from flash
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
• MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
• All peripheral clocks enabled but peripherals are not in active operation
• LVD disabled
• No GPIOs toggled
• Code execution from flash
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
15
Preliminary
General
Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled
5.1.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
VRE1
VRE2
VRE3
VRE4
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
0.15–50
50–150
TBD
TBD
TBD
TBD
TBD
dBμV
1, 2
150–500
500–1000
0.15–1000
VRE_IEC_SAE IEC and SAE level
—
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/
Wideband TEM (GTEM) Cell Method.
2. VDD = 3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
16
Freescale Semiconductor, Inc.
Preliminary
General
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
5.1.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.1.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.2 Switching specifications
5.2.1 Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
100
50
MHz
MHz
MHz
fFLASH
Flash clock
25
VLPR mode
fSYS
fBUS
System and core clock
Bus clock
—
—
—
2
2
1
MHz
MHz
MHz
fFLASH
Flash clock
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
17
General
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I2C signals.
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
16
—
—
ns
2
2
GPIO pin interrupt pulse width (digital glitch filter
ns
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
TBD
2
—
—
Mode select (EZP_CS) hold time after reset
deassertion
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
3
4
—
—
12
36
ns
ns
• Slew enabled
Port rise and fall time (low drive strength)
• Slew disabled
—
—
32
36
ns
ns
• Slew enabled
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
4. 15pF load
5.3 Thermal specifications
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
Ambient temperature
–40
–40
125
°C
TA
105
°C
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
18
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
5.3.2 Thermal attributes
Board
type
Symbol Description
81
MAPBGA
80 LQFP Unit
Notes
Single-
layer (1s)
RθJA
Thermal resistance, junction to ambient (natural TBD
convection)
TBD
TBD
TBD
TBD
°C/W
°C/W
°C/W
°C/W
1
Four-layer RθJA
(2s2p)
Thermal resistance, junction to ambient (natural TBD
convection)
1
1
1
Single-
layer (1s)
RθJMA
Thermal resistance, junction to ambient (200 ft./ TBD
min. air speed)
Four-layer RθJMA
(2s2p)
Thermal resistance, junction to ambient (200 ft./ TBD
min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction to board
Thermal resistance, junction to case
TBD
TBD
TBD
TBD
TBD
°C/W
°C/W
°C/W
2
3
4
Thermal characterization parameter, junction to TBD
package top outside center (natural convection)
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
6 Peripheral operating requirements and behaviors
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
Table 10. Debug trace operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Twh
High pulse width
2
—
ns
Tr
Tf
Clock and data rise time
Clock and data fall time
Data setup
—
—
3
3
3
ns
ns
ns
ns
Ts
Th
—
—
Data hold
2
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 11. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
TCLK cycle period
1/J1
—
ns
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 11. JTAG limited voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J3
TCLK clock pulse width
• Boundary Scan
ns
50
20
10
—
—
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
17
17
—
—
J6
J7
—
—
8
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 12. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
ns
50
25
—
—
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
J6
J7
J8
J9
TCLK rise and fall times
—
20
0
3
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
—
—
25
25
—
—
—
8
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
Table 12. JTAG full voltage range electricals (continued)
Symbol
J10
Description
Min.
1.4
—
Max.
—
Unit
ns
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high-Z
J11
22.1
22.1
—
ns
J12
—
ns
J13
TRST assert time
100
8
ns
J14
TRST setup time (negation) to TCLK high
—
ns
J2
J4
J3
J3
TCLK (input)
J4
Figure 5. Test clock input timing
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 6. Boundary scan (JTAG) timing
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 7. Test Access Port timing
TCLK
TRST
J14
J13
Figure 8. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
23
Preliminary
Peripheral operating requirements and behaviors
6.3.1 MCG specifications
Table 13. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25°C
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
—
—
—
TBD
TBD
0.1
—
4
µA
µs
tirefsts
Internal reference (slow clock) startup time
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
and SCFTRIM
0.3
%fdco
1
1
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+ 0.5
- 1.0
0.5
3.5
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
TBD
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
3.4
3
—
—
4
5
MHz
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
Iintf
Internal reference (fast clock) current
—
—
TBD
TBD
—
—
TBD
—
µA
µs
tirefstf
floc_low
Internal reference startup time (fast clock)
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
640 × ffll_ref
20.97
MHz
2, 3
frequency range
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
41.94
62.91
83.89
50
75
MHz
MHz
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
100
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
—
23.99
—
MHz
4, 5
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
—
—
47.97
71.99
95.98
—
—
—
MHz
MHz
MHz
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
Jacc_fll
FLL period jitter
—
—
TBD
TBD
TBD
TBD
ps
ps
6
6
FLL accumulated jitter of DCO output over a 1µs
time window
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
8
950
• PLL @ 96 MHz (fosc_hi_1=8MHz,
fpll_ref=2MHz, VDIV multiplier=48)
fpll_ref
Jcyc_pll
Jacc_pll
Dlock
PLL reference frequency range
PLL period jitter
2.0
—
—
400
TBD
—
4.0
—
MHz
ps
9, 10
9, 10
PLL accumulated jitter over 1µs window
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
—
—
ps
1.49
4.47
—
2.98
5.97
%
Dunl
—
%
tpll_lock
—
0.15 +
ms
11
1075(1/
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification was obtained at TBD frequency.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification was obtained at internal frequency of TBD.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
25
Preliminary
Peripheral operating requirements and behaviors
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
Table 14. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
700
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
25
400
800
1.5
3
—
—
—
—
—
—
μA
μA
μA
mA
mA
mA
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
10
—
1
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
RS Series resistor — low-frequency, low-power
—
—
—
kΩ
mode (HGO=0)
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
—
200
—
—
—
kΩ
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 15. Oscillator frequency specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low
32
—
40
kHz
frequency mode (MCG_C2[RANGE]=00)
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
8
—
—
8
MHz
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal
tdc_extal
Input clock frequency (external clock mode)
Input clock duty cycle (external clock mode)
—
—
50
60
MHz
%
1
40
50
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 15. Oscillator frequency specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tcst Crystal startup time — 32 kHz low-frequency,
—
TBD
—
ms
2, 3
low-power mode (HGO=0)
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
800
4
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
3
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL
2. Proper PC board layout procedures must be followed to achieve specifications.
3. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.3.3 32kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1 32kHz oscillator DC electrical specifications
Table 16. 32kHz oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
—
3.6
V
RF
Internal feedback resistor
—
—
—
—
100
2.5
15
—
—
—
—
MΩ
pF
pF
V
Cpara
Cload
Vpp
Parasitical capacitance of EXTAL32 and XTAL32
Internal load capacitance (programmable)
Peak-to-peak amplitude of oscillation
0.6
6.3.3.2 32kHz oscillator frequency specifications
Table 17. 32kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
1000
—
1
1. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.4.1 Flash (FTFL) electrical specifications
This section describes the electrical characteristics of the FTFL module.
6.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 18. NVM program/erase timing specifications
Symbol Description
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
Min.
Typ.
Max.
Unit
Notes
—
20
TBD
μs
—
—
20
100
800
ms
ms
1
1
thversblk256k Erase Block high-voltage time for 256 KB
160
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2 Flash timing specifications — commands
Table 19. Flash command timing specifications
Symbol Description
Read 1s Block execution time
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
• 256 KB data flash
—
—
1.4
ms
trd1sec2k
tpgmchk
trdrsrc
Read 1s Section execution time (flash sector)
Program Check execution time
—
—
—
—
—
—
—
50
40
35
μs
μs
μs
μs
1
1
1
Read Resource execution time
35
tpgm4
Program Longword execution time
TBD
Erase Flash Block execution time
• 256 KB data flash
2
2
tersblk256k
tersscr
—
—
160
20
800
100
ms
ms
Erase Flash Sector execution time
Program Section execution time
• 512 B flash
tpgmsec512
tpgmsec1k
tpgmsec2k
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
ms
ms
ms
• 1 KB flash
• 2 KB flash
trd1all
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
50
2.8
35
ms
μs
μs
trdonce
1
tpgmonce Program Once execution time
TBD
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
Table 19. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tersall
Erase All Blocks execution time
Verify Backdoor Access Key execution time
—
320
1600
ms
2
tvfykey
—
—
35
μs
1
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3 Flash (FTFL) current and power specfications
Table 20. Flash (FTFL) current and power specfications
Symbol
Description
Typ.
Unit
mA
IDD_PGM
Worst case programming current in program flash
10
6.4.1.4 Reliability specifications
Table 21. NVM reliability specifications
Typ.1
Symbol Description
Min.
Program Flash
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
tnvmretp100 Data retention after up to 100 cycles
nnvmcycp Cycling endurance
5
10
TBD
TBD
TBD
TBD
—
—
—
—
years
years
years
cycles
2
2
2
3
15
10 K
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
6.4.2 EzPort Switching Specifications
Table 22. EzPort switching specifications
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Operating voltage
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 22. EzPort switching specifications (continued)
Num
EP5
EP6
EP7
EP8
EP9
Description
EZP_D input valid to EZP_CK high (setup)
Min.
Max.
Unit
ns
2
—
—
12
—
12
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
5
—
0
ns
ns
ns
—
ns
EZP_CK
EP3
EP4
EP2
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the
differential pins ADCx_DP0, ADCx_DM0, ADCx_DP1, ADCx_DM1, ADCx_DP3, and
ADCx_DP3.
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
31
Preliminary
Peripheral operating requirements and behaviors
The ADCx_DP2 and ADCx_DM2 ADC inputs are used as the PGA inputs and are not
direct device pins. Accuracy specifications for these pins are defined in Table 25 and
Table 26.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1 16-bit ADC operating conditions
Table 23. 16-bit ADC operating conditions
Typ.1
Symbol Description
Conditions
Absolute
Min.
1.71
-100
Max.
3.6
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD (VDD
-
0
+100
mV
2
2
VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-
-100
0
+100
mV
VSSA
)
VREFH
ADC reference
voltage high
1.13
VSSA
VREFL
VDDA
VSSA
—
VDDA
V
V
VREFL
Reference
voltage low
VSSA
VADIN
CADIN
Input voltage
VREFH
V
Input
capacitance
• 16 bit modes
—
—
8
4
10
5
pF
• 8/10/12 bit
modes
RADIN
RAS
Input resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
13/12 bit modes
fADCK < 4MHz
3
—
fADCK
fADCK
Crate
ADC conversion ≤13 bit modes
clock frequency
4
5
6
1.0
2.0
—
—
—
18.0
12.0
MHz
MHz
Ksps
ADC conversion 16 bit modes
clock frequency
ADC conversion ≤13
rate
bit modes
18.484
818.330
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock =
50MHz
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 23. 16-bit ADC operating conditions (continued)
Typ.1
Symbol Description
Conditions
Min.
Max.
Unit
Notes
Crate
ADC conversion 16 bit modes
rate
7
No ADC hardware
37.037
—
361.402
Ksps
averaging
Continuous
conversions enabled
Peripheral clock =
50MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
4. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
5. In order to use the maximum ADC conversion clock frequency ADHSC bit should be set and the ADLPC should be clear.
6. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
7. For guidelines and examples of conversion rate calculation please download the ADC calculator tool http://
cache.freescale.com/files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 10. ADC input impedance equivalency diagram
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
33
Preliminary
Peripheral operating requirements and behaviors
6.6.1.2 16-bit ADC electrical characteristics
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
IDDA
Supply current
0.215
—
1.7
mA
3
ADC
asynchronous
clock source
• ADLPC=1, ADHSC=0
—
—
—
—
2.4
4.0
5.2
6.2
—
—
—
—
tADACK = 1/
fADACK
MHz
MHz
MHz
MHz
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
fADACK
Sample Time
See Reference Manual chapter for sample times
Conversion Time The ADC calculator tool can be used to determine ADC conversion times for different ADC
configurations: http://cache.freescale.com/files/soft_dev_tools/software/app_software/
converters/ADC_CALCULATOR_CNV.zip?fpsp=1
LSB4
TUE
Total unadjusted
error
• ≤13 bit modes
• <12 bit modes
0.8
0.5
TBD
1
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
DNL
Differential non-
linearity
• ≤13 bit modes
• <12 bit modes
0.7
0.2
TBD
0.5
ADC
conversion
clock
<12MHz,
Max
hardware
averaging
(AVGE =
%1, AVGS
= %11)
LSB4
LSB4
LSB4
INL
EFS
EQ
Integral non-
linearity
• ≤13 bit modes
• <12 bit modes
• ≤13 bit modes
• <12 bit modes
• 16 bit modes
• ≤13 bit modes
—
—
—
—
—
—
1.0
0.5
TBD
TBD
TBD
TBD
—
Max
averaging
Full-scale error
0.4
VADIN
VDDA
=
1.0
Quantization
error
-1 to 0
—
0.5
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Conditions1
Typ.2
Symbol Description
Min.
Max.
Unit
Notes
ENOB
Effective number 16 bit differential mode
5
of bits
• Avg=32
TBD
TBD
13.6
13.2
TBD
TBD
bits
bits
• Avg=1
16 bit single-ended mode
• Avg=32
TBD
TBD
TBD
TBD
TBD
TBD
bits
bits
• Avg=1
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16 bit differential mode
• Avg=32
5
5
—
—
-94
TBD
TBD
dB
dB
16 bit single-ended mode
• Avg=32
TBD
SFDR
Spurious free
dynamic range
16 bit differential mode
• Avg=32
TBD
TBD
95
—
—
dB
16 bit single-ended mode
• Avg=32
TBD
dB
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
• –40°C to 25°C
• 25°C to 105°C
—
—
TBD
TBD
—
—
mV/°C
mV/°C
VTEMP25 Temp sensor
voltage
25°C
—
TBD
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
1 LSB = (VREFH - VREFL)/2N
4.
5. Input data is 1 kHz sine wave.
FIGURE TBD
Figure 11. Typical TUE vs. ADC conversion rate 12-bit single-ended mode
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
FIGURE TBD
Figure 12. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended
modes
6.6.1.3 16-bit ADC with PGA operating conditions
Table 25. 16-bit ADC with PGA operating conditions
Typ.1
Symbol Description
VDDA Supply voltage
VREFPGA PGA ref voltage
Conditions
Min.
Max.
Unit
V
Notes
Absolute
1.71
—
3.6
VREFOUT VREFOUT VREFOUT
V
2, 3
VADIN
VCM
Input voltage
VSSA
VSSA
—
—
VDDA
VDDA
V
Input Common
Mode range
V
IN+ to IN-4
RPGAD
Differntial input
impedance
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
—
—
—
—
128
64
—
—
—
—
kΩ
32
RAS
TS
Analog source
resistance
100
Ω
5
6
ADC sampling
time
1.25
—
—
µs
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
6.6.1.4 16-bit ADC with PGA characteristics
Table 26. 16-bit ADC with PGA characteristics
Typ.1
Symbol
Description
Conditions
Min.
Max.
Unit
μA
A
Notes
IDDA_PGA Supply current
—
590
TBD
IDC_PGA
Input DC current
2
3
IILKG
Input Leakage
current
PGA disabled
—
TBD
TBD
μA
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Typ.1
0.98
1.99
3.97
7.95
15.8
31.4
61.2
Symbol
Description
Conditions
• PGAG=0
Min.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
Notes
Gain4
G
R
AS < 100Ω
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
BW
Input signal
bandwidth
• 16-bit modes
• < 16-bit modes
—
—
—
—
4
kHz
kHz
dB
40
—
PSRR
Power supply
rejection ration
Gain=1
TBD
TBD
VDDA= 3V
100mV,
fVDDA= 50Hz,
60Hz
CMRR
Common mode
rejection ratio
• Gain=1
TBD
TBD
TBD
TBD
—
—
dB
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• Gain=64
VOFS
TGSW
dG/dT
Input offset
voltage
—
—
0.2
—
TBD
10
mV
µs
Gain=1, ADC
Averaging=32
Gain switching
settling time
5
Gain drift over
temperature
• Gain=1
• Gain=64
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
ppm/°C
ppm/°C
0 to 50°C
dVOFS/dT Offset drift over
temperature
Gain=1
ppm/°C 0 to 50°C, ADC
Averaging=32
dG/dVDDA Gain drift over
supply voltage
• Gain=1
• Gain=64
—
—
TBD
TBD
TBD
TBD
%/V
%/V
mV
VDDA from 1.71
to 3.6V
EIL
Input leakage
error
All modes
IIn × RAS
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF
Maximum
V
6
differential input
signal swing
where VX = VREFPGA × 0.583
SNR
Signal-to-noise
ratio
• Gain=1
• Gain=64
TBD
TBD
83.0
57.5
—
—
dB
dB
16-bit
differential
mode,
Average=32
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Typ.1
89.4
90.0
Symbol
Description
Conditions
Min.
TBD
TBD
Max.
—
Unit
dB
Notes
THD
Total harmonic
distortion
• Gain=1
• Gain=64
16-bit
differential
mode,
—
dB
Average=32,
fin=500Hz
SFDR
ENOB
Spurious free
dynamic range
• Gain=1
• Gain=64
TBD
TBD
90.9
77.0
—
—
dB
dB
16-bit
differential
mode,
Average=32,
fin=500Hz
Effective number
of bits
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
12.3
12.7
8.4
—
—
—
—
—
—
—
—
—
—
—
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
16-bit
differential
mode,
fin=500Hz
8.7
13.3
13.1
12.5
11.8
11.1
10.2
9.3
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function if input common mode voltage (VCM) and the PGA gain.
3. This is the input leakage current of the module in addition to the PAD leakage current.
Gain = 2PGAG
4.
5. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 27. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
VAIO
VH
Analog input voltage
VSS – 0.3
—
—
—
VDD
20
V
Analog input offset voltage
mV
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
120
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
TBD
—
ns
IDAC6b
INL
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
39
Preliminary
Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
HYSTCTR
Setting
00
01
10
11
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 13. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
40
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
0.1
HYSTCTR
Setting
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinlevel (V)
Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
Table 28. 12-bit DAC operating requirements
Symbol
Desciption
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
VDACR
TA
Reference voltage
Temperature
1.13
−40
—
3.6
105
100
1
V
1
°C
pF
mA
CL
Output load capacitance
Output load current
2
IL
—
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
41
Preliminary
Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACLP Supply current — low-power mode
—
—
150
μA
IDDA_DACH Supply current — high-speed mode
—
—
700
μA
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) — low-
power mode
—
—
—
1
100
15
200
30
μs
μs
1
1
1
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) — high-
power mode
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
—
5
μs
tCCDACHP Code-to-code settling time (0xBF8 to 0xC08) —
high-speed mode
TBD
100
—
—
μs
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
—
TBD
VDACR
mV
mV
Vdacouth DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
VDACR
−100
INL
DNL
DNL
Integral non-linearity error — high speed mode
Differential non-linearity error — VDACR > 2 V
—
—
—
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR
VREFO (1.15 V)
=
VOFFSET Offset error
0.4
0.1
60
—
—
—
0.8
0.6
90
—
%FSR
%FSR
dB
5
5
EG
PSRR
TCO
Gain error
Power supply rejection ratio, VDDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
TBD
TBD
μV/C
TGE
—
—
ppm of
FSR/C
AC
Rop
SR
Offset aging coefficient
—
—
—
—
TBD
250
μV/yr
Ω
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
V/μs
• High power (SPHP
)
1.2
1.7
—
—
0.05
0.12
• Low power (SPLP
)
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
)
550
40
—
—
—
—
• Low power (SPLP
)
1. Settling within 1 LSB
2. The INL is measured for 0+100mV to VDACR−100 mV
3. The DNL is measured for 0+100 mV to VDACR−100 mV
4. The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
42
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
5. Calculated by a best fit curve from VSS+100 mV to VREF−100 mV
Figure 15. Typical INL error vs. digital code
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
43
Peripheral operating requirements and behaviors
Figure 16. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 30. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
V
TA
CL
Temperature
−40
—
105
100
°C
nF
Output load capacitance
Table 31. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
TBD
1.2
TBD
V
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
44
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 31. VREF full-range operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Vout
Voltage reference output with factory trim
TBD
—
TBD
V
Voltage reference output user trim
Voltage reference trim step
1.198
—
—
0.5
—
1.202
—
V
Vstep
Vdrift
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
20
See
Figure 17
Ac
Ibg
Itr
Aging coefficient
—
—
—
—
—
—
—
—
TBD
TBD
1.1
ppm/year
Bandgap only (MODE_LV = 00) current
Tight-regulation buffer (MODE_LV =10) current
µA
mA
V
Load regulation (MODE_LV = 10) current =
1.0mA
TBD
Tstup
DC
Buffer startup time
—
—
—
—
—
100
TBD
TBD
µs
mV
dB
Line regulation (power supply rejection)
–60
Table 32. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
Notes
TA
Temperature
0
50
°C
Table 33. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Vout
Voltage reference output with factory trim
TBD
TBD
V
TBD
Figure 17. Typical output vs.temperature
Figure 18. Typical output vs. VDD
TBD
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
45
Preliminary
Peripheral operating requirements and behaviors
6.8.1 CAN switching specifications
See General switching specifications.
6.8.2 DSPI switching specifications (low-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 34. Master mode DSPI timing (low-speed mode)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output cycle time
4 x tBCLK
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
(tSCK/2) - 4 (tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
(tSCK/2) - 4
—
—
10
—
—
—
(tSCK/2) - 4
—
-2
15
0
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 19. DSPI classic SPI timing — master mode
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
46
Freescale Semiconductor, Inc.
Preliminary
Peripheral operating requirements and behaviors
Table 35. Slave mode DSPI timing (low-speed mode)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
—
6.25
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBCLK
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
20
—
—
—
15
15
5
15
—
—
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 20. DSPI classic SPI timing — slave mode
6.8.3 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 36. Master mode DSPI timing (high-speed mode)
Num
Description
Min.
2.7
—
Max.
3.6
Unit
V
Operating voltage
Frequency of operation
25
MHz
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
47
Peripheral operating requirements and behaviors
Table 36. Master mode DSPI timing (high-speed mode) (continued)
Num
Description
DSPI_SCK output cycle time
Min.
Max.
Unit
DS1
2 x tBCLK
—
ns
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
ns
ns
ns
ns
ns
ns
DSPI_PCSn to DSPI_SCK output valid
DSPI_SCK to DSPI_PCSn output hold
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
(tSCK/2) − 2
—
—
8.5
—
—
—
(tSCK/2) − 2
—
−2
TBD
0
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 21. DSPI classic SPI timing — master mode
Table 37. Slave mode DSPI timing (high-speed mode)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
2.7
Frequency of operation
12.5
—
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBCLK
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2 + 2
ns
ns
ns
ns
ns
ns
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
TBD
—
2
—
7
—
—
—
14
14
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
48
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
Last data
DSPI_SOUT
Data
Data
DS13
First data
DSPI_SIN
Figure 22. DSPI classic SPI timing — slave mode
I2C switching specifications
6.8.4
See General switching specifications.
6.8.5 UART switching specifications
See General switching specifications.
6.8.6 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 38. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
Clock frequency (low speed)
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
0
0
400
25
20
400
—
kHz
MHz
MHz
kHz
ns
0
0
SD2
SD3
SD4
7
Clock high time
7
—
ns
Clock rise time
—
3
ns
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
49
Peripheral operating requirements and behaviors
Table 38. SDHC switching specifications
(continued)
Num
Symbol
Description
Clock fall time
Min.
Max.
Unit
SD5
tTHL
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
tOD SDHC output delay (output valid) -5 6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
ns
SD7
SD8
tTHL
tTHL
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 23. SDHC timing
I2S switching specifications
6.8.7
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
I2S master mode timing
Table 39.
Num
Description
Min.
Max.
Unit
V
Operating voltage
I2S_MCLK cycle time
2.7
3.6
S1
2 x tSYS
ns
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
50
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
I2S master mode timing (continued)
Table 39.
Num
S2
Description
Min.
Max.
55%
—
Unit
MCLK period
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
45%
5 x tSYS
45%
—
S3
S4
S5
S6
S7
S8
S9
S10
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
55%
15
—
BCLK period
ns
ns
ns
ns
ns
ns
-2.5
—
15
—
I2S_BCLK to I2S_TXD invalid
-3
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
20
—
0
—
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S6
S10
S9
S7
S8
S7
S8
S9
S10
I2S_RXD
Figure 24. I2S timing — master mode
Table 40.
I2S slave mode timing
Num
Description
Operating voltage
Min.
Max.
3.6
Unit
V
2.7
8 x tSYS
45%
10
S11
S12
S13
S14
S15
S16
S17
I2S_BCLK cycle time (input)
—
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
55%
—
MCLK period
ns
ns
ns
ns
ns
3
—
—
20
—
0
10
—
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
51
Peripheral operating requirements and behaviors
I2S slave mode timing (continued)
Table 40.
Num
Description
Min.
Max.
Unit
S18
I2S_RXD hold after I2S_BCLK
2
—
ns
S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 25. I2S timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 41. TSI electrical specifications
Symbol Description
VDDTSI Operating voltage
CELE
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
Target electrode capacitance range
Reference oscillator frequency
1
20
5.5
0.5
1
500
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
1
fREFmax
fELEmax
CREF
—
MHz
MHz
pF
Electrode oscillator frequency
—
Internal reference capacitor
TBD
TBD
TBD
TBD
—
VDELTA
IREF
Oscillator delta voltage
600
1
mV
μA
μA
%
Reference oscillator current source base current
Electrode oscillator current source base current
Electrode capacitance measurement precision
Electrode capacitance measurement precision
2
2
3
4
5
IELE
1
Pres5
Pres20
TBD
TBD
TBD
—
%
Pres100 Electrode capacitance measurement precision
—
%
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
52
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 41. TSI electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
MaxSens2 Maximum sensitivity @ 20 pF electrode
0
0.003
0.25
—
fF/count
6
MaxSens Maximum sensitivity
0.003
—
—
—
—
16
fF/count
bits
7
8
Res
Resolution
TCon20
Response time @ 20 pF
8
15
25
μs
ITSI_RUN Current added in run mode
ITSI_LP Low power mode current adder
—
TBD
1
—
μA
—
TBD
μA
1. The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
2. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
3. Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
4. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
5. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
6. Measured with a 20 pF electrode, reference oscillator frequency of ~5 MHz (IREF = 5 μA, REFCHRG = 4), PS = 128,
NSCN = 2; Iext = 16 (EXTCHRG = 15).
7. Typical value depends on the configuration used.
8. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, DELVOL = 2, EXTCHRG = 15.
6.9.2 LCD electrical characteristics
Table 42. LCD electricals
Symbol Description
fFrame LCD frame frequency
CLCD
Min.
Typ.
Max.
Unit
Notes
28
30
58
Hz
LCD charge pump capacitance — nominal value
LCD bypass capacitance — nominal value
LCD glass capacitance
—
—
—
100
100
—
—
nF
nF
pF
1
1
CBYLCD
CGlass
VIREG
2000
8000
VIREG — HREFSEL = 0
• HREFSEL = 0
2
0.89
1.49
1.00
1.67
1.15
1.85
V
V
• HREFSEL = 1
ΔRTRIM
VIREG TRIM resolution
3.0
—
—
% VIREG
—
VIREG ripple
—
—
—
—
30
50
mV
mV
• HREFSEL = 0
• HREFSEL = 1
IVIREG
IRBIAS
VIREG current adder — RVEN = 1
—
1
—
µA
3
3
RBIAS current adder
• HREFSEL = 0
• HREFSEL = 1
—
—
10
1
—
—
µA
µA
Table continues on the next page...
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
53
Dimensions
Table 42. LCD electricals (continued)
Symbol Description
Min.
Typ.
0.28
2.98
Max.
—
Unit
MΩ
MΩ
Notes
RRBIAS
RBIAS resistor values
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
—
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
—
—
VLL2
VLL3
VLL2 voltage
• HREFSEL = 0
• HREFSEL = 1
2.0 − 5%
3.3 − 5%
2.0
3.3
—
—
V
V
VLL3 voltage
• HREFSEL = 0
• HREFSEL = 1
3.0 − 5%
5 − 5%
3.0
5
—
—
V
V
1. The actual value used could vary with tolerance.
2. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
3. 2000 pF load LCD, 32 Hz frame frequency
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
80-pin LQFP
Then use this document number
98ASS23174W
81-pin MAPBGA
98ASA10631D
8 Pinout
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
54
Freescale Semiconductor, Inc.
Pinout
8.1 K30 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
The 81-pin ballmap assignments are currently being developed.
The • in the entries in this package column indicate which
signals are present on the package.
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQF
BGA
P
•
1
PTE0
PTE1
PTE2
PTE3
ADC1_SE4
a
ADC1_SE4
a
PTE0
SPI1_PCS1 UART1_TX
SDHC0_D1
I2C1_SDA
I2C1_SCL
•
•
•
2
3
4
ADC1_SE5
a
ADC1_SE5
a
PTE1
PTE2
PTE3
SPI1_SOUT UART1_RX SDHC0_D0
ADC1_SE6
a
ADC1_SE6
a
SPI1_SCK
SPI1_SIN
UART1_CT
S_b
SDHC0_DC
LK
ADC1_SE7
a
ADC1_SE7
a
UART1_RT
S_b
SDHC0_CM
D
•
•
•
•
•
5
6
7
8
9
PTE4
PTE5
VDD
DISABLED
DISABLED
VDD
PTE4
PTE5
SPI1_PCS0 UART3_TX
SDHC0_D3
SPI1_PCS2 UART3_RX SDHC0_D2
VDD
VSS
VSS
VSS
PTE16
ADC0_SE4
a
ADC0_SE4
a
PTE16
PTE17
PTE18
PTE19
SPI0_PCS0 UART2_TX
FTM_CLKIN
0
FTM0_FLT3
•
•
•
•
10
11
12
13
PTE17
ADC0_SE5
a
ADC0_SE5
a
SPI0_SCK
UART2_RX FTM_CLKIN
1
LPT00_ALT
3
PTE18
ADC0_SE6
a
ADC0_SE6
a
SPI0_SOUT UART2_CT
S_b
I2C0_SDA
PTE19
ADC0_SE7
a
ADC0_SE7
a
SPI0_SIN
UART2_RT
S_b
I2C0_SCL
PGA0_DP/
PGA0_DP/
PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3
ADC1_DP3
ADC1_DP3
•
•
•
14
15
16
PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
PGA0_DM/
PGA0_DM/
PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3
PGA1_DM/
PGA1_DP/
PGA1_DP/
ADC0_DP3
PGA1_DM/
ADC0_DP3
PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
•
•
•
17
18
19
VDDA
VDDA
VDDA
VREFH
VREFL
VREFH
VREFL
VREFH
VREFL
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
55
Pinout
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQF
BGA
P
•
•
20
21
VSSA
VSSA
VSSA
VREF_OUT/ VREF_OUT VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
•
22
DAC0_OUT/ DAC0_OUT DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
CMP1_IN3/
ADC0_SE2
3
•
•
•
•
23
24
25
26
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
PTA0
JTAG_TCL
K/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CT
S_b
FTM0_CH5
JTAG_TCL
K/
SWD_CLK
EZP_CLK
EZP_DI
•
•
27
28
PTA1
PTA2
JTAG_TDI/
EZP_DI
TSI0_CH2
PTA1
PTA2
UART0_RX FTM0_CH6
JTAG_TDI
JTAG_TDO/ TSI0_CH3
TRACE_SW
O/EZP_DO
UART0_TX
FTM0_CH7
JTAG_TDO/ EZP_DO
TRACE_SW
O
•
•
•
•
•
•
29
30
31
32
33
34
PTA3
JTAG_TMS/ TSI0_CH4
SWD_DIO
PTA3
UART0_RT
S_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
FTM1_CH0
FTM1_CH1
JTAG_TMS/
SWD_DIO
PTA4
NMI_b/
TSI0_CH5
PTA4
NMI_b
EZP_CS_b
EZP_CS_b
PTA5
DISABLED
CMP2_IN0
CMP2_IN1
DISABLED
PTA5
CMP2_OUT I2S0_RX_B JTAG_TRS
CLK
T
PTA12
PTA13
PTA14
CMP2_IN0
CMP2_IN1
PTA12
PTA13
PTA14
CAN0_TX
CAN0_RX
I2S0_TXD
FTM1_QD_
PHA
I2S0_TX_F
S
FTM1_QD_
PHB
SPI0_PCS0 UART0_TX
I2S0_TX_B
CLK
•
•
35
36
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
UART0_RX
I2S0_RXD
SPI0_SOUT UART0_CT
S_b
I2S0_RX_F
S
•
37
PTA17
ADC1_SE1
7
ADC1_SE1
7
PTA17
SPI0_SIN
UART0_RT
S_b
I2S0_MCLK I2S0_CLKIN
•
•
•
38
39
40
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
EXTAL
EXTAL
PTA18
PTA19
FTM0_FLT2 FTM_CLKIN
0
•
•
41
42
PTA19
XTAL
XTAL
FTM1_FLT0 FTM_CLKIN
1
LPT0_ALT1
RESET_b
RESET_b
RESET_b
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
56
Freescale Semiconductor, Inc.
Pinout
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQF
BGA
P
•
43
PTB0
LCD_P0/
ADC0_SE8/ ADC0_SE8/
ADC1_SE8/ ADC1_SE8/
LCD_P0/
PTB0
I2C0_SCL
FTM1_CH0
FTM1_QD_ LCD_P0
PHA
TSI0_CH0
TSI0_CH0
•
44
PTB1
LCD_P1/
ADC0_SE9/ ADC0_SE9/
ADC1_SE9/ ADC1_SE9/
LCD_P1/
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_ LCD_P1
PHB
TSI0_CH6
TSI0_CH6
•
•
45
46
PTB2
PTB3
LCD_P2/
ADC0_SE1
2/TSI0_CH7 2/TSI0_CH7
LCD_P2/
ADC0_SE1
PTB2
PTB3
I2C0_SCL
I2C0_SDA
UART0_RT
S_b
FTM0_FLT3 LCD_P2
FTM0_FLT0 LCD_P3
LCD_P3/
ADC0_SE1
LCD_P3/
ADC0_SE1
UART0_CT
S_b
3/TSI0_CH8 3/TSI0_CH8
•
•
•
47
48
49
PTB8
PTB9
PTB10
LCD_P8
LCD_P9
LCD_P8
LCD_P9
PTB8
PTB9
PTB10
UART3_RT
S_b
LCD_P8
LCD_P9
SPI1_PCS1 UART3_CT
S_b
LCD_P10/
ADC1_SE1
4
LCD_P10/
ADC1_SE1
4
SPI1_PCS0 UART3_RX
FTM0_FLT1 LCD_P10
•
50
PTB11
LCD_P11/
ADC1_SE1
5
LCD_P11/
ADC1_SE1
5
PTB11
SPI1_SCK
UART3_TX
FTM0_FLT2 LCD_P11
•
•
•
•
•
51
52
53
54
55
PTB16
PTB17
PTB18
PTB19
PTC0
LCD_P12/
TSI0_CH9
LCD_P12/
TSI0_CH9
PTB16
PTB17
PTB18
PTB19
PTC0
SPI1_SOUT UART0_RX
EWM_IN
LCD_P12
LCD_P13
LCD_P13/
LCD_P13/
SPI1_SIN
CAN0_TX
CAN0_RX
UART0_TX
FTM2_CH0
FTM2_CH1
EWM_OUT
_b
TSI0_CH10 TSI0_CH10
LCD_P14/ LCD_P14/
TSI0_CH11 TSI0_CH11
LCD_P15/ LCD_P15/
TSI0_CH12 TSI0_CH12
I2S0_TX_B
CLK
FTM2_QD_ LCD_P14
PHA
I2S0_TX_F
S
FTM2_QD_ LCD_P15
PHB
LCD_P20/
ADC0_SE1
4/
LCD_P20/
ADC0_SE1
4/
SPI0_PCS4 PDB0_EXT
RG
I2S0_TXD
FTM0_CH0
FTM0_CH1
LCD_P20
LCD_P21
LCD_P22
TSI0_CH13 TSI0_CH13
•
•
56
57
PTC1
PTC2
LCD_P21/
ADC0_SE1
5/
LCD_P21/
ADC0_SE1
5/
PTC1
PTC2
SPI0_PCS3 UART1_RT
S_b
TSI0_CH14 TSI0_CH14
LCD_P22/
ADC0_SE4
b/
LCD_P22/
ADC0_SE4
b/
SPI0_PCS2 UART1_CT
S_b
CMP1_IN0/
CMP1_IN0/
TSI0_CH15 TSI0_CH15
•
58
PTC3
LCD_P23/
CMP1_IN1
LCD_P23/
CMP1_IN1
PTC3
SPI0_PCS1 UART1_RX FTM0_CH2
LCD_P23
•
•
59
60
VSS
VSS
VSS
VLL3
VLL3
VLL3
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
57
Pinout
81
80
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQF
BGA
P
•
•
•
•
•
•
•
61
62
63
64
65
66
67
VLL2
VLL2
VLL2
VLL1
VLL1
VLL1
VCAP2
VCAP1
PTC4
PTC5
PTC6
VCAP2
VCAP1
LCD_P24
LCD_P25
VCAP2
VCAP1
LCD_P24
LCD_P25
PTC4
SPI0_PCS0 UART1_TX
SPI0_SCK
FTM0_CH3
LPT0_ALT2
CMP1_OUT LCD_P24
CMP0_OUT LCD_P25
LCD_P26
PTC5
PTC6
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
SPI0_SOUT PDB0_EXT
RG
•
•
68
69
PTC7
PTC8
LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7
PTC8
SPI0_SIN
LCD_P27
LCD_P28
LCD_P28/
ADC1_SE4
b/
LCD_P28/
ADC1_SE4
b/
I2S0_MCLK I2S0_CLKIN
CMP0_IN2
CMP0_IN2
•
•
•
70
71
72
PTC9
LCD_P29/
ADC1_SE5
b/
LCD_P29/
ADC1_SE5
b/
PTC9
I2S0_RX_B
CLK
FTM2_FLT0 LCD_P29
LCD_P30
CMP0_IN3
CMP0_IN3
PTC10
PTC11
LCD_P30/
ADC1_SE6
b/
LCD_P30/
ADC1_SE6
b/
PTC10
PTC11
I2C1_SCL
I2C1_SDA
I2S0_RX_F
S
CMP0_IN4
CMP0_IN4
LCD_P31/
ADC1_SE7
b
LCD_P31/
ADC1_SE7
b
I2S0_RXD
LCD_P31
•
•
73
74
PTD0
PTD1
LCD_P40
LCD_P40
PTD0
PTD1
SPI0_PCS0 UART2_RT
S_b
LCD_P40
LCD_P41
LCD_P41/
ADC0_SE5
b
LCD_P41/
ADC0_SE5
b
SPI0_SCK
UART2_CT
S_b
•
•
•
75
76
77
PTD2
PTD3
PTD4
LCD_P42
LCD_P43
LCD_P44
LCD_P42
LCD_P43
LCD_P44
PTD2
PTD3
PTD4
SPI0_SOUT UART2_RX
SPI0_SIN UART2_TX
LCD_P42
LCD_P43
SPI0_PCS1 UART0_RT
S_b
FTM0_CH4
FTM0_CH5
EWM_IN
LCD_P44
•
•
78
79
PTD5
PTD6
LCD_P45/
ADC0_SE6
b
LCD_P45/
ADC0_SE6
b
PTD5
PTD6
SPI0_PCS2 UART0_CT
S_b
EWM_OUT
_b
LCD_P45
LCD_P46/
ADC0_SE7
b
LCD_P46/
ADC0_SE7
b
SPI0_PCS3 UART0_RX FTM0_CH6
FTM0_FLT0 LCD_P46
•
•
—
VSS
VSS
VSS
80
PTD7
LCD_P47
LCD_P47
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
FTM0_FLT1 LCD_P47
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
58
Freescale Semiconductor, Inc.
Pinout
8.2 K30 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
NOTE
The 81 MAPBGA ballmap assignments are currently being
developed.
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
59
Preliminary
Revision History
1
PTE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VLL3NC
VSS
2
PTE1
3
PTE2
PTC3
4
PTE3
PTC2
5
PTE4
PTC1
6
PTE5
PTC0
7
VDD
VSS
PTB19
PTB18
PTB17
PTB16
PTB11
PTB10
PTB9
8
9
PTE16
10
11
12
13
14
15
16
17
18
19
20
PTE17
PTE18
PTE19
P/ADC0_DP0/ADC1_DP3
/ADC0_DM0/ADC1_DM3
P/ADC1_DP0/ADC0_DP3
/ADC1_DM0/ADC0_DM3
VDDA
PTB8
PTB3
PTB2
PTB1
VREFHNC
PTB0
VREFLNC
RESET_b
PTA19
VSSA
Figure 26. K30 80 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
60
Freescale Semiconductor, Inc.
Preliminary
Revision History
Table 43. Revision History
Rev. No.
Date
11/2010
3/2011
Substantial Changes
1
2
Initial public revision
Many updates throughout
Corrected 81- and 104-pin package codes
3
4
3/2011
3/2011
Added sections that were inadvertently removed in previous revision
Reworded IIC footnote in "Voltage and Current Operating Requirements"
table.
Added paragraph to "Peripheral operating requirements and behaviors"
section.
Added "JTAG full voltage range electricals" table to the "JTAG electricals"
section.
K30 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Preliminary
Freescale Semiconductor, Inc.
61
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Document Number: K30P81M100SF2
Rev. 4, 3/2011
Preliminary
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