AOD607 [FREESCALE]
Complementary Enhancement; 加强互补
| 型号： | AOD607 |
| 厂家： | 
Freescale |
| 描述： | Complementary Enhancement |
| 文件： | 总9页 (文件大小：641K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOD607
Complementary Enhancement
Mode Field Effect Transistor
General Description
excellent RDS(ON) and low gate charge.
The AOD607 uses advanced trench
technology MOSFETs to provide
The complementary MOSFETs may be
used in H-bridge, Inverters and other
applications.
Features
n-channel
DS (V) = 30V
p-channel
-30V
V
ID = 12A (VGS=10V)
RDS(ON)
-12A (VGS = -10V)
RDS(ON)
< 25 mΩ (VGS=10V)
< 34 mΩ (VGS=4.5V)
< 37 mΩ (VGS = -10V)
< 62 mΩ (VGS = -4.5V)
D1/D2
G1
G2
S1
S2
n-channel
p-channel
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Symbol
Max n-channel Max p-channel
Units
VDS
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain
Current G
Pulsed Drain Current C
Avalanche Current C
30
±20
12
-30
±20
V
VGS
V
A
TC=25°C
-12
TC=100°C
ID
9.4
-9.4
-40
IDM
IAR
EAR
40
18
-18
A
Repetitive avalanche energy L=0.1mH C
40
40
mJ
TC=25°C
25
25
PD
W
Power Dissipation B
TC=100°C
12.5
2.1
12.5
2.1
TA=25°C
PDSM
W
Power Dissipation A
TA=70°C
1.3
1.3
TJ, TSTG
Junction and Storage Temperature Range
-55 to 175
-55 to 175
°C
Thermal Characteristics: n-channel and p-channel
Parameter
Symbol Device Typ
Max
23
60
6
Maximum Junction-to-Ambient A
n-ch
n-ch
n-ch
19
47
4.5
°C/W
°C/W
°C/W
t ≤ 10s
RθJA
RθJC
RθJA
RθJC
Maximum Junction-to-Ambient A
Steady-State
Maximum Junction-to-Case B
Steady-State
Maximum Junction-to-Ambient A
Maximum Junction-to-Ambient A
p-ch
p-ch
p-ch
19
47
4.5
23
60
6
°C/W
°C/W
°C/W
t ≤ 10s
Steady-State
Maximum Junction-to-Case B
Steady-State
1/9
www.freescale.net.cn
AOD607
Complementary Enhancement
Mode Field Effect Transistor
N-Channel Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STATIC PARAMETERS
ID=250µA, VGS=0V
BVDSS
Drain-Source Breakdown Voltage
30
V
VDS=24V, VGS=0V
1
5
IDSS
Zero Gate Voltage Drain Current
µA
TJ=55°C
V
V
V
DS=0V, VGS= ±20V
DS=VGS ID=250µA
GS=4.5V, VDS=5V
IGSS
Gate-Body leakage current
Gate Threshold Voltage
On state drain current
100
2.5
nA
V
VGS(th)
ID(ON)
1.5
40
1.7
A
VGS=10V, ID=12A
20
28
25
34
34
mΩ
RDS(ON)
Static Drain-Source On-Resistance
TJ=125°C
V
GS=4.5V, ID=5A
27.5
25
mΩ
S
VDS=5V, ID=12A
IS=1A,VGS=0V
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
0.75
1
V
Maximum Body-Diode Continuous Current
Pulsed Body-Diode CurrentC
18
40
A
ISM
A
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
1040
180
110
0.7
1250
1.5
pF
pF
pF
Ω
VGS=0V, VDS=15V, f=1MHz
GS=0V, VDS=0V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
V
SWITCHING PARAMETERS
Qg(10V) Total Gate Charge
Qg(4.5V) Total Gate Charge
19.8
9.8
2.5
3.5
4.5
3.9
17.4
3.2
19
25
nC
nC
nC
nC
ns
12.5
VGS=10V, VDS=15V, ID=12A
Qgs
Qgd
tD(on)
tr
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
V
GS=10V, VDS=15V, RL=1.25Ω,
ns
RGEN=3Ω
tD(off)
tf
ns
ns
trr
IF=12A, dI/dt=100A/µs
IF=12A, dI/dt=100A/µs
25
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
ns
Qrr
8
nC
A: The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The
Power dissipation PDSM is based on R θJA and the maximum allowed junction temperature of 150°C. The value in any given application depends
on the user's specific board design, and the maximum temperature of 175°C may be used if the PCB allow s it.
B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used.
C: Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C.
D. The R θJA is the sum of the thermal impedence from junction to case R θJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.
F. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25°C. The SOA
curve provides a single pulse rating.
G. The maximum current rating is limited by bond-wires.
*This device is guaranteed green after data code 8X11 (Sep 1ST 2008).
Rev3: Oct 2008
2/9
www.freescale.net.cn
AOD607
Complementary Enhancement
Mode Field Effect Transistor
N-CHANNEL TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
30
25
20
15
10
5
20
16
12
8
4V
10V
4.5V
VDS=5V
3.5V
125°C
25°C
VGS=3V
4
0
0
0
1
2
3
4
5
1.5
2
2.5
3
3.5
4
V
DS (Volts)
V
GS(Volts)
Fig 1: On-Region Characteristics
Figure 2: Transfer Characteristics
35
1.6
VGS=10V
ID=12A
VGS=4.5V
30
25
20
15
10
1.4
1.2
1
VGS=4.5V
ID=5A
VGS=10V
0.8
0
5
10
15
20
0
25
50
75
100
125
150
175
ID (A)
Temperature (°C)
Figure 4: On-Resistance vs. Junction
Temperature
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage
50
1.0E+01
1.0E+00
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
40
30
20
10
ID=12A
125°C
25°C
125°C
25°C
0.0
0.2
0.4
SD (Volts)
Figure 6: Body-Diode Characteristics
0.6
0.8
1.0
2
4
6
8
10
V
V
GS (Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
3/9
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AOD607
Complementary Enhancement
Mode Field Effect Transistor
N-CHANNEL TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
1500
1250
1000
750
500
250
0
10
8
VDS=15V
ID=12A
Ciss
6
4
Coss
2
Crss
0
0
4
8
12
16
20
0
5
10
15
DS (Volts)
20
25
30
Qg (nC)
Figure 7: Gate-Charge Characteristics
V
Figure 8: Capacitance Characteristics
100.0
10.0
1.0
50
40
30
20
10
0
TJ(Max)=150°C
TA=25°C
RDS(ON)
limited
1ms
10µs
10ms
100µs
0.1s
1s
10s
DC
TJ(Max)=150°C
TA=25°C
0.1
0.1
1
10
100
0.001
0.01
0.1
1
10
100
1000
V
DS (Volts)
Pulse Width (s)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
Figure 10: Single Pulse Power Rating Junction-to-
Ambient (Note F)
10
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
1
0.1
PD
D=Ton/T
0.01
TJ,PK=TA+PDM.ZθJA.RθJA
Ton
Single Pulse
RθJA=60°C/W
T
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance
4/9
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AOD607
Complementary Enhancement
Mode Field Effect Transistor
P-Channel Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STATIC PARAMETERS
ID=-250µA, VGS=0V
BVDSS
Drain-Source Breakdown Voltage
-30
V
VDS=-24V, VGS=0V
-0.003
-1
-5
IDSS
Zero Gate Voltage Drain Current
µA
TJ=55°C
V
V
V
V
DS=0V, VGS=±20V
DS=VGS ID=-250µA
GS=-10V, VDS=-5V
GS=-10V, ID=-12A
IGSS
Gate-Body leakage current
Gate Threshold Voltage
On state drain current
±100
-2.4
nA
V
VGS(th)
ID(ON)
-1.5
-40
-2
A
30
42
37
50
62
mΩ
RDS(ON)
Static Drain-Source On-Resistance
TJ=125°C
VGS=-4.5V, ID=-5A
VDS=-5V, ID=-12A
IS=-1A,VGS=0V
50
mΩ
S
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
17
-0.76
-1
V
Maximum Body-Diode Continuous Current
Pulsed Body-Diode CurrentC
-18
-40
A
ISM
A
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
920
190
122
3.6
1100
5
pF
pF
pF
Ω
VGS=0V, VDS=-15V, f=1MHz
VGS=0V, VDS=0V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
SWITCHING PARAMETERS
Qg(10V) Total Gate Charge (10V)
Qg(4.5V) Total Gate Charge (4.5V)
18.7
9.7
2.54
5.4
9
23
nC
nC
nC
nC
ns
11.7
V
GS=-10V, VDS=-15V, ID=-12A
Qgs
Qgd
tD(on)
tr
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
13
35
30
18
V
GS=-10V, VDS=-15V, RL=1.25Ω,
25
ns
RGEN=3Ω
tD(off)
tf
20
ns
12
ns
trr
IF=-12A, dI/dt=100A/µs
IF=-12A, dI/dt=100A/µs
21.4
13
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
26
16
ns
Qrr
nC
A: The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The
Power dissipation PDSM is based on steady-state R θJA and the maximum allowed junction temperature of 150°C. The value in any given
application depends on the user's specific board design, and the maximum temperature fo 175°C may be u sed if the PCB or heatsink allows it.
B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
C: Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C.
D. The R θJA is the sum of the thermal impedence from junction to case R θJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.
F. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25°C. The SOA
curve provides a single pulse rating.
G. The maximum current rating is limited by the package current capability.
*This device is guaranteed green after data code 8X11 (Sep 1ST 2008).
Rev3: Oct. 2008
5/9
www.freescale.net.cn
AOD607
Complementary Enhancement
Mode Field Effect Transistor
P-CHANNEL TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
30
25
20
15
10
5
30
25
20
15
10
5
-4.5V
-6V
-5V
-10V
VDS=-5V
-4V
-3.5V
125°C
VGS=-3V
3
25°C
3.5
0
0
0
1
2
4
5
0
0.5
1
1.5
2
2.5
3
4
4.5
5
-VGS(Volts)
-VDS (Volts)
Figure 2: Transfer Characteristics
Fig 1: On-Region Characteristics
80
1.60
1.40
1.20
1.00
0.80
70
60
50
40
30
20
10
VGS=-4.5V
ID=-5A
VGS=-4.5V
VGS=-10V
ID=-12A
VGS=-10V
0
25
50
75
100
125
150
175
0
5
10
15
20
25
Temperature (°C)
-ID (A)
Figure 4: On-Resistance vs. Junction
Temperature
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage
100
90
80
70
60
50
40
30
20
10
0
1.0E+01
1.0E+00
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
ID=-12A
125°C
125°C
25°C
25°C
0.0
0.2
0.4
-VSD (Volts)
Figure 6: Body-Diode Characteristics
0.6
0.8
1.0
3
4
5
6
7
8
9
10
-VGS (Volts)
Figure 5: On-Resistance vs. Gate-Source Voltage
6/9
www.freescale.net.cn
AOD607
Complementary Enhancement
Mode Field Effect Transistor
P-CHANNEL TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
1500
1250
1000
750
500
250
0
10
8
VDS=-15V
ID=-12A
Ciss
6
4
Coss
Crss
2
0
0
4
8
12
16
20
0
5
10
15
-VDS (Volts)
20
25
30
-Qg (nC)
Figure 7: Gate-Charge Characteristics
Figure 8: Capacitance Characteristics
100.0
10.0
1.0
40
30
20
10
0
TJ(Max)=150°C, T A=25°C
TJ(Max)=150°C
TA=25°C
10µs
100µs
RDS(ON)
limited
1ms
10ms
0.1s
1s
10s
DC
0.1
0.1
1
10
100
0.001
0.01
0.1
1
10
100
1000
-VDS (Volts)
Pulse Width (s)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
Figure 10: Single Pulse Power Rating Junction-to-
Ambient (Note F)
10
D=Ton/T
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
TJ,PK=TA+PDM.ZθJA.RθJA
θJA=60°C/W
R
1
0.1
PD
Ton
10
Single Pulse
T
0.01
0.00001
0.0001
0.001
0.01
0.1
1
100
1000
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
7/9
www.freescale.net.cn
AOD607
Complementary Enhancement
Mode Field Effect Transistor
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
VDC
+
Qgs
Qgd
Vds
VDC
-
-
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
10%
+
DUT
Vdd
Vgs
VDC
Rg
-
Vgs
Vgs
td(on)
t
r
td(off)
t
f
ton
toff
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
EAR= 1/2 LIA2R
BVDSS
Vds
Id
Vds
+
Vgs
I AR
Vdd
Vgs
VDC
Id
Rg
-
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Qrr = - Idt
Vds +
Vds -
Ig
DUT
Vgs
trr
L
Isd
I F
Isd
Vgs
dI/dt
I RM
+
Vdd
VDC
Vdd
-
Vds
8/9
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AOD607
Complementary Enhancement
Mode Field Effect Transistor
Gate Charge Test Circuit & Waveform
Vgs
Qg
-
-10V
-
VDC
Qgs
Qgd
+
Vds
VDC
+
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
toff
ton
t
td(off)
td(on)
t
r
f
Vgs
-
90%
10%
DUT
Vdd
Vgs
VDC
+
Rg
Vgs
Vds
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
EAR= 1/2 LIA2R
L
Vds
Id
Vgs
Vds
-
BVDSS
Vgs
Vdd
VDC
+
Id
Rg
I AR
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Qrr = - Idt
Vds +
DUT
Vgs
trr
Vds -
L
-Isd
-IF
Isd
Vgs
dI/dt
-IRM
+
Vdd
VDC
Vdd
-
-Vds
Ig
9/9
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