FS511 [FORTUNE]
18-bit ADC with 1 low noise OPAMP;
| 型号： | FS511 |
| 厂家： | 
Fortune Semiconductor |
| 描述： | 18-bit ADC with 1 low noise OPAMP |
| 文件： | 总18页 (文件大小：948K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REV. 1.7 FS511-DS-17_EN
MAY 2014
Datasheet
FS511
18-bit ADC with 1 low noise OPAMP
Fortune Semiconductor Corporation
富晶電子股份有限公司
23F., No.29-5, Sec. 2, Zhongzheng E. Rd.,
Danshui Town, Taipei County 251, Taiwan
Tel.：886-2-28094742
Fax：886-2-28094874
www.ic-fortune.com
This manual continnew product information. Fortune Semiconductor Corporation reserves the rights to
modify the product specification without further notice. No liability is assumed by Fortune Semiconductor
Corporation as a result of the use of this product. No rights under any patent accompany the sale of the
product.
Contents
1. GENERAL DESCRIPTION.........................................................................................................................4
2. FEATURES.................................................................................................................................................4
3. APPLICATIONS .........................................................................................................................................4
4. ORDERING INFORMATION.......................................................................................................................4
5. PIN CONFIGURATION..............................................................................................................................4
6. PIN DESCRIPTION .................................................................................................................................5
7. FUNCTIONAL BLOCK DIAGRAM..........................................................................................................5
8. TYPICAL APPLICATION CIRCUIT ........................................................................................................6
9. ABSOLUTE MAXIMUM RATINGS.......................................................................................6
10. ELECTRICAL CHARACTERISTICS ............................................................................7
11. FUNCTION DESCRIPTION...................................................................................................................8
11.1 Microprocessor Inteface ....................................................................................................8
11.2 Power Sy.......................................................................................................................8
11.2.1 power (VDD, VSSA) and Digital power (VCC, VSS) ..........................................8
11.2.2 Sh-able Power Output......................................................................................8
11AGND Generator ...........................................................................................................9
dgap Voltage Refernd Temperature sensr.................................................9
Current Source Ge......................................................................................9
1.3 Clock Generator .....................................................................................................10
1.4 Function Network.........................................................................................................10
11.4.1 Analog Multipex: ........................................................................................................... 11
11.4.2 OPA.............................................................................................................. 11
11.4.3 The ation of the Delta-Sigma (Modulator ADC............................................... 11
12. APPLICATION SAMPLE.........................................................................................................................15
13. PACKAGE INFORMATION .............................................................................................................17
13.1 Package Outline, DIP20 ....................................................................................................17
13.2 Package Outline, SOP2.......................................................................................................17
14. REVISION HISTORY...............................................................................................................................18
1. General Description
The FS511 is a high-resolution analog-to-digital converter (ADC) chip. The core of this chip is an 18-bit
resolution ADC. Besides the ADC, FS511 consists of switching circuits, operational amplifier, digital filter,
crystal oscillation circuits, digital control logic, and microprocessor interface. Under 5V working voltage, this
chip consumes 1.2mA power.
2. Features
Delta-Sigma ADC, 18-bit high-resolution 10Hz output rate (Programmable).
Linearity Error: 0.005%FS
Voltage operation ranges from 4.5V to 6V.
4MHz crystal oscillator.
Operation current is less than 1.2mA; sleep mde curenis about 1A.
SPI Interface to Micro-Processor
Package: 20-pin DIP, 20-pin SOP.
3. Applications
Electronics Weigh Scale
Sensor or Transducer mesuremnt applcation
Others
4. Ordering Infotion
Product Number
FS511-PI
cription
Package Type
P20 Pb free package parmbe
SOP20 Pb free package part number.
SOP20 “ROHS” packnumber.
DIP20 Pb free package)
SOP20 (Pb free package)
SOP20 (“ROHS” package)
FS511-PHB
FS511-GH
5. Pin Conation
1
2
FTB
FTC
CS
K
20
19
18
17
16
15
14
13
12
11
3
OPO
PN
OPP
DI
DO/IRQO
XTALI
FS511
6
RL
SGND
VRH
AGND
VS
XTALO
VCC
7
8
VSS
9
VDD
10
VSSA
6. Pin Description
Name
FTB
FTC
OPO
OPN
OPP
VRL
SGND
VRH
AGND
VS
VSSA
VDD
Attribute
Pin No Description
AIO
AIO
AIO
AIO
AIO
AIO
AI
1
2
3
ADC Pre-Filter Capacitor Connection and input high
ADC Pre-Filter Capacitor Connection and input low
OPAMP Output
4
OPAMP Negative Input
5
OPAMP PositivInput
6
7
Input Reference Voltage low of the ADC
Signal Gound
AI
8
9
Input Reerence Voltage high of the ADC
Analg Grond
APIO
APO
API
PI
API
DPO
DO
DI
10
11
12
13
14
15
16
17
8
19
20
Voltage source
nalog Netive Power Supply
Positive Power Supply
Digital Negative Power Supply
Power Supply for Digitanal
4MHz Oscillator Outpu
4MHz Oscillator Input
SPI Data Outpor interrupt request output
SPI Data Inpt
SPI Clock Inut
Chip select of Digital Interface
VSS
VCC
XTALO
XTALI
SDO/IRQO
SDI
SCLK
/CS
DO
DI
Notations: D stands for Dgital. A stands for Analog. stands for Power. O stands for Output. I stands for Input.
For example: ns “Dgital Input/Output”
7. Functional Block Diagram
VRL
VS
FTB FTC
VRH
VDD
OPN OPO
VSSA
AGND
VCC
VSS
Power system
OPP
OPAMP
& Network
Δ Σ Modulator
SGND
Digital
Filter
Digital Interface
and Control Registors
Clock or
___
CS
XTALI XTALO
DI
SK
DO/IRQO
8. Typical Application Circuit
VS
1
2
FTB
FTC
CS
SK
20
19
18
17
16
15
14
13
12
11
27nF
Micro-
Processor
2.5k
250k
Bridge
sensor
3
OPO
OPN
OPP
DI
4
DO/IRQO
XTALI
5
1M
4MHz
FS511
2.5k
250k
6
VRL
SGN
VRH
AGND
VS
XTALO
VCC
10uF
40k
10k
10k
8
VSS
40
9
Re
5
Battery
10uF
10uF
0.1uF
10
VA
uF
9. Absoluaximum Ratings
Parameter
Rating
-0.3 to 10
Unit
Supply Voltagnd Potential
Apped Input/Output Voltage
Ambiet Operating Temperature Range
Storage Temperature Ran
Soldering Temperature
V
V
-0.3 to VDD3
-40 to +5
-55 +150
2
℃
℃
℃
Human body Model (HBM): ≧2KV
Machine Model (MM): ≧200V
ESD Tolerance
10. Electrical Characteristics
DC Characteristics (VDD=5V, TA=25℃, unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog-to-Digital Converter
μ V
μ V
Zero Input Reading
VIN=0V, Vref=500mV , CYS=01
-15
-25
15
25
VIN= ± 0.9 Vref, Vref=500mV
CYS=01
,
Linearity (Max. deviation from best
straight line fit)
VCM=AGND
Vref=500mV
± 1V, VIN=0.25V,
μ V/V
μ V
Input Common-Mode Rejection Ratio
150
10
Noise (p-p Value not Exceeding 95%
of Time)
VIN=0V, 500mV Scale
5
Rollover Error (Difference in reading
for equal positive and negative inputs -VIN=+VIN=500.0mV
near Full Scale)
μ V
0
10
50
VIN=00.00mV, -10℃<TA<+50℃
/℃
Scale Factor Temperature Coefficient
Current Consumption
10
0.7
A
Instrumentation Amplifier
Input Offset Voltage without chopper Rs<100Ω
Input Offset Voltage pper Rs<100Ω
Input Referred Ne withut chopper Rs=100Ω, 0.1z~1Hz
30
1
mV
μ V
μ Vpp
μ Vpp
pA
Input Referrh chopper
Input Bias Current
Rs=1Hz~1Hz
0.3
100
300
3
Input Cmmon-Mode Voltage Rane
Current Consumption
2
V
μ A
200
300
General Electrical Characteristics
VDD Operating Current
Sleep Current
Enable ADPAMP
1
2
5
mA
μ A
Ω
OSC, AGND
1
VS switch resister
Digital Output High
Digital Output Low
Digital Input High
Digital Input Low
20
4.7
0.3
IOUT=-1mA
IOUT=1mA
V
V
3.5
V
1.5
V
[1] These parameters are guaranteed by design and are tested only by sampling while mass production.
[2] While a voltage source with large output impedance is measured by an instrumentation amplifier having
input bias current, an additional input offset voltage will be introduced. However, this offset voltage could
be cancelled by mirrored offset cancellation technique.
11. Function Description
Microprocessor Interface
FS511 can be directly connected to any microprocessor by pins of CS_, SK, DI, DO/IRQO. It can access
the read/write of the control registers, handle interrupts, and access the measure registers.
Writing Mode
CS_
DI
SK
DO
……
……
……
0
A<2>
A<1>
A<0>
A<0>
0
D<7>
D<6>
D<5>
D<4>
D<3>
D<2>
D<1>
D<0>
…
QO
ReadiMode
CS_
DI
A<1>
…………
SK
DO
IRQ
D<7>
D<6>
>
D>
D<3>
D<2>
D<
D<0>
IRQO
Reading ADC
CS_
DI
……………
…………
…
…
SK
DO
IRQO
D<23>
D<22>
D<21>
D<2>
D<1>
D<0>
IRQO
If ADC Data converse complete, IRQill be high to Low
Power System
11..1
Analog power (VD, VSSA) and Digital power VCC, VSS)
ADC, OPAMP and analog circuit used Analpowr (VDD, VSSA). VDD typically is 5V.
Digital Interface and Digital circuit uDigitapower (VCC, VSS).
11..2
Switch-able Power Output
VDD
VS
ENVS
Terminals of VS is the witch-able power output of VDD. The PMOS switch is controlled by ENVS control signal.
When ENVS = 1, the switch is short.
11..3
AGND Generator
VDD
600K
AGND
10uF
ENGNDB
600K
VSSA
VSSA
AGND is analog common voltage. Wen ENGNB=0, analog commvoltge generator will ac
11..4
Bandgap Voltage Reference and Temperature sesor
REFI
K
50K
Voltage Reference
and
Temperature Sen
TEMPH
TEMPL
AGND
E
.
REFO ilow temperature coefficiet bandp voltage reference utput. When ENBAND=1, the circuit will
active. Thoutput voltage tGND is about 1.2V. Typical temperature coefficient is 100ppm/℃.
{TEMPH, TEMPL} is prto ambient temperaure. Ycan elect them to ADC input and transfer to
digital code. (Typical 500u50uV/℃)
11..5
Bias Current Source Genera
3uA
400K
REFO
(1.2V)
ENGNDB
AGND
VSS
The bias current for all the og circuits of FS511. If the embedded op amp works, REFO will be pulled to
AGND by the fedbac; there are 1.2V in resistor 400K, and 3uA bias current can be obtained.
Clock Generator
1M
4MHz
4MHz Crystal
Ocillator Circuit
CLK Divider
FS
ENXTB
We connect a 4MHz crystal oscillatr to the clock generator to generate a 4MHz clocy. A
frequency divider is used to divide the clock sinal to generate a signal FS, and the ADC uses l to
do data conversion.
ENXTB
ENAD
FS
L
H
H
L
83.33 kHz
0, (L)
Function Networ
Adress
ame
7
6
5
4
3
2
1
0
NET[7:0]
ETB[70]
TC[7:0]
TD[7:0]
R/W
SINL[1:0]
SIN[1:0]
ENREF
SFTA[1
PL[1:0]
R/W OPEN
R/W ENAD
C[1:0]
SVR1
SVR0
SVRL
SVRH
ADG:0]
ENGNDB
R/W ENXTB
CYS[1:0]
TPS[2:0]
4
ADCO[23:0]
R
27nF
OPP
OPN
OPO
FTB
F
VRL
SGND
VRH
VDD
ENVS
SVR0
SVR1
5K
SVR0
5K
SVR0
45K
0K
45K
_
VS
OP
+
SFTA[0]
S1]
ADO[23:0]
IN+
IN+
OPC[1:0]
OPEN
FTIN
FTB
SINH[1:0]
SINL[1:0]
TPS[2:0]
ENAD
ADC
TEMPH
ND
TEMPL
SGND
VRH
ADG[5:0]
FTIN
IN-
IN-
OPH
OPO
VRL
VR+
VR-
*(REFI, AGND)= 0.5V
SVRH
REFI
VR+
Voltage Reference
and
Temperature Sensor
VRH
TEMPH
TEMPL
SVRL
AGND
VRL
VR-
ENREF
11..1
Analog Multiplex:
1. Low Pass Filter Input:
SINH[1:0]
Select
00
OPO
01
OPH
10
SGND
11
TEMPH
2. ADC Negative Input:
SINL[1:0]
Select
00
VRL
01
VRH
10
SGND
11
TEMPL
3. Low Pass Filter Output, ADC Positive Input:
SFTA[0]
Select
0
FTB
1
FTIN
4. External Filter Control: SFTA[1]=1, FTIN and FTB hort; SFTA[1]=0, FTIN and FTB open.
5. Internal Reference Voltage Control: SVR0=1, (VRH,VRL) = 1V (at VDD=5V). SVR1=1,
SGND=1/2(VRH,VRL).
6. ADC Reference Voltage Negative Inpu:
SVRL
Select
0
VRL
1
AGND
7. ADC Reference Voltage Positive Input:
SVRH
Select
0
VRH
1
REFI
8. OPAMP Refeltage Input:
SOPL[1:0]
Select
0
VRL
01
VRH
10
SGND
11
AGND
11..2
OP
OPEN is the OPAMP enable coal.
OC [1:0] can set OPAMP input oon mode as follow00: +Offset, 01: -Offset, 10: 2KHz chopper
frequency, 11: 1KHz Choppefrequency.
1.
2.
11..3
The Operation othe Delta-Sigma () Modulator ADC
This high resolution ADC is designed by tchnology of delta-sigma () modulator. The continuous
analog signals are sampled by a very high samg rae that is much higher than the bandwidth of the input
signal. The delta-sigma modulator conthe input signal to a series of 1-bit codes. These 1-bit codes are
then fed to the digital filter to filter high frequency quantization noise to find high resolution digital
outputs. This kind of ADC quantizes in the analog part, therefore, it has very good linearity. Because it is
in a fully differential configuration, the cmmon mode rejection ratio (CMRR) is very high and can reduce the
common mode signals effectively.
ANALO
INTEGRGATO
R
Vin
DIGITAL LOW PASS
DECIMATION
FILTER
Dout
ANALO
INGPU
T
COMPARATOR
Vref, -Vref, -Vref, Vref, Vref, Vref,...
1, -1, -1, 1, 1, 1,....
DA
C
The Symbolic Diagram of the Delta-Sigma Analog-to-Digital Converter
The symbolic diagram of the delta-sigma ADC is shown as above. It consists of an analog subtractor, an
integrator, a comparator, a 1-bit digital-to-analog converter (DAC), and a low-pass digital filter. The analog
signals are continuously sampled and are subtracted by the expected voltage. The difference of the signals is
fed into the integrator, and then the signal is compared with a reference voltage to find a digital output. This
digital output is converted by the 1-bit DAC to become an analog signal (+Vref or -Vref) and then negatively fed
back into the integrator. Due to the infinitive DC gain of the integrator, if the change of the input signal is much
slower than the sampling speed, the average voltage obtained by the delta-sigma modulator will be very close
to the input signal. In some resolution they can be treated to be the same, therefore, the 1-bit output data from
the comparator are equivalent to the Vref analog signal values. The digital filter then decimates the 1-bit data
to get a very high resolution digital code.
ENAD(ADG<7>) is the enable control signal for the ADC. It is 1 to enable the ADC; it is 0 to turn off the ADC
and can save power.
11..3.1.
Gain Stage Setting
There are four different gain paths to the input of the FS511 ADC, and they are controlled by cotrol
register ADG[3:0]. Two different gain pahs control the input reference voltageand they are ed b
control register ADG[5:4]. The gains shown here are not accurate. The accurate gains can be feful
calibration.
0.5
ADG[0]
0.5
1.0
To ADC
signal
input
To ADC
reference
input
Vin
(IN+, IN-)
ADG[1]
AD3]
ref (VRVR-)
ADG[
ADG[5]
0.25
0.1
0.25
Diagram of FSSetting
By proper selection of the gain phis ADC can be appliethe ptimum dynamic range for all the
mesuring applications. Table shows ADG[5:0] for threfreqently used applications.
Table: FS511 ADC Typical Gain Setting
First Scale
01_001
1.0
Second Scale
11_0111
1.25
Third Scale
11_1000
1.25
ADG<5:0>
Reference Voltage Gain（EFi
）
Input Voltage Gain（GSIGi
）
1.0
1.25
0.1
The transfer function for each scale is as llows,
vx
i
G
Equation 1
Dx
F v
E
ir e
The gains for the reference voltages and input voltages shown in Table are approximate values. The
accurate gains for the reference oltages and input voltages can be found by careful calibration.
11..3.2.
Digital Filter
In Symbolic Diagram of the Delta-Sigma Analog-to-Digital Converter, the 1-bit output of the comparator
should be fed to the digital low pass filter to do decimation to find the high resolution multiple-bit digital output.
The transfer function of the FS511 digital filter is:
2
s i
Nnf fS
1
H
f
Equation 2
N 2
s i
nf fS
Where N is TAP of the digital filter.
Suppose the sampling rate of the ADC is 83.3KH, the TAP of the digital filter is 8192. We can find the
frequency response diagram of the digital filter as shown in Fig . The first zero is at:
fS
N
8333Hz
8192
Equation 3
fZ1
10Hz
The Frequency Response Diagram of FS51 Digital Filter
0
-
-100
-150
-200
0
20
0
60
80
100
Hz
The zell at multiples of 10Hzigital filter will filter out all he signals near the zero points.
From bove fige can find that thises 50Hz and 60Hz uppressed very well. If the sampling
rate s 83KHz and the TAP of the filter , the irst zero-frequeis at 5Hz.
The outut rate is selected by TP[2:0].
TPS [
TAP (N)
ADutput Rate and First Zero Frequency（Hz）
1
101
100
011
010
001
000
16384
8192
4096
2048
1024
512
5
10
20
40
80
160
320
640
6
28
11..3.3.
Reading and Calculating of Digital-to-Analog Converter
Due to the manufacture process drift, there is an offset voltage in the FS511 ADC such that an offset
value is existed in the ADC output. In order to eliminate the offset value, FS511 provides three operation modes,
which can be set by CYS <1:0> of control register NETD. The ADO output and calculation are different in
different operation modes, and they are described in the following subsection.
ADC Output ADO
Set CYS<1:0>=00, the ADC inputs are short circuited, and we can find the negative offset voltage of the ADC
from ADO[23:0].
Set CYS<1:0>=11, we can find the equivalent voltage of he input signal from ADO[23:0].
Set CYS<1:0>=01, and the ADO[23:0] output is the value of an ideal ADC. This mode is suitable for high
resolution measurement.
When CYS<1:0>01, the output rate of ADO[23:0] s the fist zero frequency,
Equation 3. When CYS<1:0> =01, the outpurate equafZ1
f
Z1 , of COMB as described in
2
.
11..3.4.
The Conversion of the Digital Coes and Equivalent Voltage
The output of the FS511 ADC is ADO[23:0], whh is a 24-bit 2’s coment number. ADO[23] bit;
0 represents a positive number, and repreents a negative nuber. he decimal point lies tween
ADO[22] and ADO[21].
If ADO[23:0]=0010_1000_0000_000_0000_0000, the equivalent floating point numbe
ADO _1000_ 0000_ 0000_ 0000_ 0000
21 0 22 1 23 24 0 25 ...... 0 222
0.5 0.125 0.625
Equation 4
If ADO[23:0_1111_1111_1111_1quivalent floating point number is:
A11.01_1111_1111_11_1111_1111
(00.10_ 0000_ 0000_ 0000_ 001)
(1 21 0 22 0 23 0 24 ...... 1 222
002384
Equation 5
G'
Vref
From Equation 1, if gain
equals 1 and reference voltage
=1.00000V, the value of ADO,
0010_1000_0000_0000_0000_0000, can be uscalculate the measured voltage as:
Vref
G'
1.00000V
1
vx
Dx
0.0.62500V
。
If ADO=1101_1111_1111_1111_1111_1111, he measured voltage can be calculated:
Vref
G'
1.00000V
1
vx
Dx
0.5000002384 0.50000V
。
G'
1%
However, due to he manufe process drift
is not exactly equal to 1, and there will be around
V
offset. Similarly te reference voltage source and resistors may affect the reference voltage ref , and make
Vref
not to be exact 100000V. Therefore, we have to calibrate the ADC.
11..3.5.
Other Control Setting
CPVR is the enhancement mode for resistance measuring. It is set to 1 to improve the linearity when
measuring resistance.
12. Application sample
Example Network setting:
Mode
NETA
NETB
00h
NETC
93h
NETD
57h
ADC
88h
88h
OPAMP+ADC
E0h
93h
57h
Demo Assembly code for Digital Interface:
endm
sk_1 m
bFS511_PT,2
; 3.2us
;===========================
; FS511_RW.ASM
; FS511 Read/Write use FS9822
; Edit by Jong 2003/6/27
version 0.0
dly
endm
di_0 macro
;=======================
Addr_bf EQU E
bcf FS511_PT,1
dly
endm
RW_bf
EQU AL
Rd_cnt1 EQunter0
Rd_cnt2 ter1
di_1 macro
bsf FS511_PT,1
CS_
SK_
DI_
DO_
E
EQU 1
EQU 0
Port3 bit 3
; Port3 bit 2
; Port3 bit 1
; Port3 bit 0
dly
en
sk_pls
maro
sk_
sk_0
endm
FS511_T
FS511_PTEN EQU PTN
FS511_PTPU EQU
EQU PT3
Status
Work
C
EQU 4
EQU 5
EQU 1
Wr511 macro d1,d2
movlfd1,Addr_bf
movlfd2,RW_bf
call _511W
endm
;-------------------------------------------
; user define macro
;-------------------------------------------
dly macro
nop
Rd511 macro d1
movlfd1,Addr_bf
call _511R
endm
endm
cs_0 macro
bcf FS511_PT,3
dly
;-------------------------------------------
; Initial of port
;-------------------------------------------
511_ini:
endm
cs_1 macro
bsf FS511_PT,3
dly
bsf FS511_PTEN,CS_
bsf FS511_PTEN,SK_
bsf FS511_PTEN,DI_
bcf FS511_PTEN,DO_
bsf FS511_PTPU,DO_
bsf FS511_PT,CS_
return
endm
sk_0 macro
bcf FS511_PT,2
dly
;-------------------------------------------
; FS511 Register Write sub function
; use Addr_bf as address Buffer
; use RW_bf as Write Data buffer
;-------------------------------------------
_511W:
di_0
return
Get_data:
clrf work
bsf rd_cnt1,3
GetLoop:
clrf Status,C
rlf work,1
; rd_tmp
cs_0
di_0
sk_pls
di_0
; 0
;
btfsc FS511_PT,0
bsf work,0
sk_pls
btfsc addr_bf,1 ;A<1>
di_1
;
sk_pls
di_0
btfsc addr_bf,0 ;A<0>
decfsz
goto GetLoop
return
rd_Cnt1,1
;
di_1
sk_pls
di_0
;
Get_adc:
movwf
call Get_data
;WR
RW_bf+2
sk_pls
Send_data:
movwf
RW_bf+1
bsf RD_cnt1,3
clrf Status,C
SendLoop:
rlf RW_bf,1
di_0
call Get_dat
return
;
btfsc Status,C ;D<x>
di_1
sk_pls
;
SendLoopDec:
decfsz
rd_1,1
goto SendLoop
di_0
cs_1
return
;------------------------------------------
; FS511 Register Read function
; use Adr_bf as address Buffe
; use RW_bf, ~+1, ~+2 as Read Data buffer
;----------------------------------
_511R:
cs_0
di_0
;
btfsc addr_bf,2 ;A<2>
di_1
sk_pls
di_0
;
;
btfsc addr_bf,1 ;A<1>
di_1
;
sk_pls
di_0
;
btfsc addr_bf,0 ;A<0>
di_1
;
sk_pls
di_1
;RD
sk_pls
call Get_daa
btfsc addr_bf,2
call Get_adc
movwf
cs_1
RW_bf
13. Package Information
Package Outline, DIP20
DIP20
Package OutlinP20
14. Revision History
Ver.
0.3
Date
unknown
Page
Description
Initial version of document.
-
1.0
2003/12/08
1
Revise "Electrical Characteristics, Micro-process
Interface, Power System, Clock Generator, Function
Network, Application Note”
2
18-bit
high-resolution
10Hz
output
rate
(Programmable).
3-4
8
Revise “Specification Table”.
Delete
Temperature sensor”
Deleted andgap Voltage
“Bandgap
Voltage
Reference
Reference
and
and
9-10
Temperature ssor Nework setting.
15-16
Add “Example Newok setting” and “ Demo code for
Digital interface”
1.1
2004/09/13
All
7
10
Refmat and crrect the contents
Add “Asolute Maximum Rating”.
Adbac“Bandgap Voltage Refeence and
Temprature sensor”
12
Add ack “Bandgap ge Reference and
Temperature sensor” netwo.
9
4
20
21
6
13
15
All
4
Add “Package Information”
Add SOP20 Pb free packagpart number.
Add Package Ouline, SOP20
1.2
1.3
2005/07/31
2006/02
Add Revision Hisory
Correct “Typal Appication Circuit”
Complete ng of OPAMP input operaon mehod
Correct deriptioof the sign bit
Revisatasheet format
1.4
1.5
1.6
2006/05/19
2
Ad-GHB” in “Ordering Infrmation”
1.7
2
2
Revismpany address
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