FPD6836SOT343E [FILTRONIC]
暂无描述;
| 型号： | FPD6836SOT343E |
| 厂家： | 
FILTRONIC COMPOUND SEMICONDUCTORS |
| 描述： | 暂无描述 晶体 晶体管 |
| 文件： | 总4页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FPD6836SOT343
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
• PERFORMANCE (1850 MHz)
♦ 0.5 dB Noise Figure
♦ 20 dBm Output Power (P1dB
)
♦ 20 dB Small-Signal Gain (SSG)
♦ 32 dBm Output IP3
♦ Evaluation Boards Available
• DESCRIPTION AND APPLICATIONS
The FPD6836SOT343 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron
Mobility Transistor (pHEMT). It utilizes a 0.25 µm x 360 µm Schottky barrier Gate, defined by
high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes
parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a
range of bias conditions and input power levels. The FPD6836 is available in die form and in other
packages.
Typical applications include drivers or output stages in PCS/Cellular base station high-intercept-
point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
• ELECTRICAL SPECIFICATIONS AT 22°C
Parameter
Symbol
Test Conditions
Min
Typ
Max Units
RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL
Minimum Noise Figure
NF
IP3
VDS = 3.0 V; IDS = 50% IDSS
VDS = 3.0 V; IDS = 25% IDSS
VDS = 3.0 V; IDS = 50% IDSS
0.5
0.4
0.9
dB
Output Third-Order Intercept Point
32
dBm
(from 15 to 5 dB below P1dB
)
V
DS = 3.0 V; IDS = 25% IDSS
Tuned for Optimum IP3
30
Small-Signal Gain
SSG
P1dB
VDS = 3.0 V; IDS = 50% IDSS
VDS = 3.0 V; IDS = 25% IDSS
VDS = 3.0 V; IDS = 50% IDSS
VDS = 3.0 V; IDS = 25% IDSS
18
18
20
18
20
18
dB
Power at 1dB Gain Compression
dBm
Saturated Drain-Source Current
Maximum Drain-Source Current
Transconductance
Gate-Source Leakage Current
Pinch-Off Voltage
IDSS
IMAX
GM
IGSO
|VP|
VDS = 1.3 V; VGS = 0 V
VDS = 1.3 V; VGS ≅ +1 V
VDS = 1.3 V; VGS = 0 V
VGS = -5 V
VDS = 1.3 V; IDS = 0.75 mA
IGS = 0.75 mA
90
135
mA
mA
mS
µA
V
200
100
1
1.0
18
10
1.3
0.7
12
12
Gate-Source Breakdown Voltage
Gate-Drain Breakdown Voltage
|VBDGS
|VBDGD
|
|
V
V
IGD = 0.75 mA
18
Phone: +1 408 850-5790
Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 09/15/05
Email: sales@filcsi.com
PRELIMINARY
FPD6836SOT343
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
1
• ABSOLUTE MAXIMUM RATINGS
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain-Source Current
Gate Current
Symbol
VDS
VGS
IDS
IG
PIN
TCH
TSTG
PTOT
Comp.
Test Conditions
-3V < VGS < +0V
0V < VDS < +8V
Min
Max
6
-3
IDSS
5
60
175
150
0.5
5
Units
V
V
mA
mA
mW
ºC
ºC
W
dB
%
For VDS > 2V
Forward or reverse current
Under any acceptable bias state
Under any acceptable bias state
Non-Operating Storage
See De-Rating Note below
Under any bias conditions
2 or more Max. Limits
RF Input Power2
Channel Operating Temperature
Storage Temperature
Total Power Dissipation
-40
Gain Compression
Simultaneous Combination of Limits3
1TAmbient = 22°C unless otherwise noted
80
2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes:
•
•
Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device.
Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where:
DC: DC Bias Power
PIN: RF Input Power
OUT: RF Output Power
Total Power Dissipation to be de-rated as follows above 22°C:
P
P
•
P
TOT= 0.5W – (0.0056W/°C) x TPACK
where TPACK = source tab lead temperature above 22°C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C source lead temperature: PTOT = 0.5W – (0.0056 x (65 – 22)) = 0.26W
• HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
• APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site. Evaluation Boards available upon request.
Phone: +1 408 850-5790
Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 09/15/05
Email: sales@filcsi.com
PRELIMINARY
FPD6836SOT343
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
• BIASING GUIDELINES
¾ Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD750SOT343.
¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source
bias voltage, and such circuits provide some temperature stabilization for the device. A nominal
value for circuit development is 5.45 Ω for a 50% of IDSS operating point.
¾ For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at
50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25%
to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3
performance.
• PACKAGE OUTLINE
(dimensions in mm)
All information and specifications subject to change without notice.
Phone: +1 408 850-5790
Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 09/15/05
Email: sales@filcsi.com
PRELIMINARY
FPD6836SOT343
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Gain & Noise Figure vs Frequency
25.00
20.00
15.00
10.00
5.00
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
Gain
NF
Frequency (GHz)
Phone: +1 408 850-5790
Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 09/15/05
Email: sales@filcsi.com
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