FPD750 [FILTRONIC]
0.5W POWER PHEMT; 0.5W功率PHEMT
| 型号： | FPD750 |
| 厂家： | 
FILTRONIC COMPOUND SEMICONDUCTORS |
| 描述： | 0.5W POWER PHEMT |
| 文件： | 总2页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FPD750
0.5W POWER PHEMT
DRAIN
BOND
• FEATURES
PAD (2X)
♦ 27 dBm Linear Output Power at 12 GHz
♦ 11.5 dB Power Gain at 12 GHz
♦ 14.5 dB Maximum Stable Gain at 12 GHz
♦ 38 dBm Output IP3
SOURCE
BOND
PAD (2x)
GATE
BOND
♦ 50% Power-Added Efficiency
PAD (2X)
DIE SIZE (µm): 340 x 470
DIE THICKNESS: 75 µm
BONDING PADS (µm): >60 x 60
• DESCRIPTION AND APPLICATIONS
The FPD750 is an AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (PHEMT),
featuring a 0.25 µm by 750 µm Schottky barrier gate, defined by high-resolution stepper-based
photolithography. The recessed and offset Gate structure minimizes parasitics to optimize
performance. The epitaxial structure and processing have been optimized for reliable high-power
applications. The FPD750 also features Si3N4 passivation and is available in a P100 flanged ceramic
package and in the low cost plastic SOT89 and SOT343 plastic packages.
Typical applications include commercial and other narrowband and broadband high-performance
amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output
amplifiers, and medium-haul digital radio transmitters.
• ELECTRICAL SPECIFICATIONS AT 22°C
Parameter
Symbol
Test Conditions
Min
Typ
Max Units
RF SPECIFICATIONS MEASURED AT f = 12 GHz USING CW SIGNAL
Power at 1dB Gain Compression
Maximum Stable Gain (S21/S12)
Power Gain at P1dB
P1dB
SSG
G1dB
PAE
VDS = 8 V; IDS = 50% IDSS
VDS = 8 V; IDS = 50% IDSS
VDS = 8 V; IDS = 50% IDSS
26.5
13.5
10.5
27.0
14.5
11.5
45
dBm
dB
dB
%
Power-Added Efficiency
V
DS = 8 V; IDS = 50% IDSS
;
P
OUT = P1dB
Output Third-Order Intercept Point
IP3
VDS = 10V; IDS = 50% IDSS
Matched for optimal power
Tuned for best IP3
(from 15 to 5 dB below P1dB
)
38
40
dBm
Saturated Drain-Source Current
Maximum Drain-Source Current
Transconductance
Gate-Source Leakage Current
Pinch-Off Voltage
Gate-Source Breakdown Voltage
Gate-Drain Breakdown Voltage
Thermal Resistivity (see Notes)
IDSS
IMAX
GM
IGSO
|VP|
VDS = 1.3 V; VGS = 0 V
VDS = 1.3 V; VGS ≅ +1 V
VDS = 1.3 V; VGS = 0 V
VGS = -5 V
VDS = 1.3 V; IDS = 0.75 mA
IGS = 0.75 mA
185
230
370
200
10
280
mA
mA
mS
µA
V
1.0
|VBDGS
|VBDGD
|
|
12.0
14.5
14.0
16.0
65
V
V
IGD = 0.75 mA
V
DS > 6V
θJC
°C/W
Phone: +1 408 850-5790
Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 11/17/04
Email: sales@filcsi.com
FPD750
0.5W POWER PHEMT
• ABSOLUTE MAXIMUM RATINGS*
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain-Source Current
Gate Current
Symbol
Test Conditions
-3V < VGS < +0V
0V < VDS < +8V
Min
Max
8
-3
IDSS
7.5
175
175
150
2.3
5
Units
V
V
mA
mA
mW
ºC
ºC
W
dB
%
VDS
VGS
IDS
IG
PIN
TCH
TSTG
PTOT
Comp.
For VDS > 2V
Forward or reverse current
Under any acceptable bias state
Under any acceptable bias state
Non-Operating Storage
See De-Rating Note below
Under any bias conditions
2 or more Max. Limits
RF Input Power
Channel Operating Temperature
Storage Temperature
-40
Total Power Dissipation
Gain Compression
Simultaneous Combination of Limits**
80
*TAmbient = 22°C unless otherwise noted
**Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes:
•
•
•
Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device.
Thermal Resitivity specification assumes a Au/Sn eutectic die attach onto a Au-plated copper heatsink or rib.
Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where
P
DC: DC Bias Power
PIN: RF Input Power
OUT: RF Output Power
Absolute Maximum Power Dissipation to be de-rated as follows above 22°C:
TOT= 2.3W – (0.015W/°C) x THS
P
•
P
where THS = heatsink or ambient temperature above 22°C
Example: For a 85°C heatsink temperature: PTOT = 2.3W – (0.015 x (85 – 22)) = 1.4W
• HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
• ASSEMBLY INSTRUCTIONS
The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage
temperature should be 280-290°C; maximum time at temperature is one minute. The recommended
wire bond method is thermo-compression wedge bonding with 0.7 or 1.0 mil (0.018 or 0.025 mm)
gold wire. Stage temperature should be 250-260°C.
• APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site.
All information and specifications are subject to change without notice.
Phone: +1 408 850-5790
Fax: +1 408 850-5766
http://www.filtronic.co.uk/semis
Revised: 11/17/04
Email: sales@filcsi.com
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