TMC3533KRC50_技术文档

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TMC3533

Triple Video D/A Converter

8 bit, 80 Msps, 3.3V

Features

Description

• 8-bit resolution

• 80, 50, and 30 megapixels per second

• ±0.5 LSB linearity error

• Sync, blank, and white controls

• Independent sync current output

• 1.0V p-p video into 37.5Ω or 75Ω load

• Enhancement of the ADV7120

– Internal bandgap voltage reference

– Double-buffered data for low distortion

– Power-down sleep mode

The TMC3533 is a high-speed triple 8-bit D/A converter

especially suited for video and graphics applications.

It offers 8-bit resolution, TTL-compatible inputs, low power

consumption, a power-down sleep mode, and requires only a

single +3.3V±5% Volt power supply. It has single-ended

current outputs, SYNC and BLANK control inputs, and a

separate current source for adding sync pulses to any D/A

converter output. WHITE and SLEEP control inputs are

available on PLCC parts. It is ideal for generating analog

RGB from digital RGB and driving computer display and

video monitors. Three speed grades are available: 30, 50, and

80 Msps.

• Double-buffered data for low distortion

• TTL-compatible inputs

• Low glitch energy

• Single +3.3V±5% Volt power supply

The TMC3533 triple D/A converter is available in a 44-lead

plastic J-leaded PLCC. It is also available in a 48-lead plastic

LQFP package. It is fabricated on a sub-micron CMOS pro-

cess with performance guaranteed from 0°C to 70°C.

Applications

• Video and graphics displays

• Image processing systems

• Video signal conversion

• Broadcast television equipment

• Digital synthesis

Block Diagram

IO

SYNC

BLANK

SYNC

S

WHITE [PLCC only]

[LQFP only]

8

8 bit D/A

Converter

IO

G

7-0

8

8 bit D/A

Converter

IO

B

7-0

8

8 bit D/A

Converter

IO

R

7-0

SLEEP [PLCC only]

CLOCK

COMP

R

REF

+1.235V

Ref

V

65-3533-01

1

REV. 0.9.1 11/24/99

TMC3533

PRODUCT SPECIFICATION

Functional Description

SLEEP

The TMC3533 is a low-cost triple 8-bit CMOS D/A con-

verter designed to directly drive computer CRT displays at

pixel rates up to 80 Msps. It comprises three identical 8-bit

D/A converters with registered data inputs, common clock,

and internal voltage reference. An independent current

source allows sync to be added to any D/A converter output.

The SLEEP control, when HIGH, places the TMC3533 in a

power-down state. This function operates asynchronously.

D/A Outputs

Each D/A output is a current source. To obtain a voltage out-

put, a resistor must be connected to ground. Output voltage

depends upon this external resistor, the reference voltage,

and the value of the gain-setting resistor connected between

Digital Inputs

All digital inputs are TTL-compatible. Data are registered on

the rising edge of the CLK signal. The analog output

R

REF

and GND.

changes t

after the rising edge of CLK. There is one stage

DO

Normally, a source termination resistor of 75 Ohms is con-

nected between the D/A current output pin and GND near

the D/A converter. A 75 Ohm coaxial cable may then be con-

nected with another 75 Ohm termination resistor at the far

end of the cable. This "double termination" presents the D/A

converter with a net resistive load of 37.5 Ohms.

of pipeline delay on the chip. The guaranteed clock rates of

the TMC3533 are 80, 50, and 30 MHz.

SYNC and BLANK

SYNC and BLANK inputs control the output level

(Figure 1 and Table 1) of the D/A converters during CRT

retrace intervals. BLANK forces the D/A outputs to the

blanking level while SYNC turns off a separate current

The TMC3533 may also be operated with a single 75 Ohm

terminating resistor. To lower the output voltage swing to the

source which is brought off the chip through the IO pin.

S

desired range, the value of the resistor on R

increased.

should be

REF

Voltage Reference

data: 660 mV max.

pedestal: 54 mV

The TMC3533 has an internal bandgap voltage reference of

+1.235 Volts. An external voltage reference may be con-

nected to the V

pin, overriding the internal voltage refer-

REF

ence. All three D/A converters are driven from the same

reference.

sync: 286 mV

65-3503-02

A 0.1µF capacitor must be connected between the COMP

Figure 1. Nominal Output Levels

pin and V

to stabilize internal bias circuitry and ensure

DD

low-noise operation.

IO may be connected to any one D/A output, or used inde-

S

pendently. It is commonly tied to the green D/A converter for

“Sync on Green” operation. This connection adds a 40 IRE

sync pulse to the D/A output and brings that D/A output to

0.0 Volts during the sync tip. SYNC and BLANK are regis-

tered on the rising edge of CLK.

Power and Ground

The TMC3533 D/A converter requires a single +3.3 Volt

power supply. The analog (V ) power supply voltage

should be decoupled to GND to reduce power supply

induced noise. 0.1µF decoupling capacitors should be placed

as close as possible to the power pins.

DD

BLANK gates the D/A inputs and sets the pedestal voltage.

If BLANK = HIGH, the D/A inputs are added to a pedestal

which offsets the current output. If BLANK = LOW, data

inputs and the pedestal are disabled.

The high slew-rate of digital data makes capacitive coupling

to the outputs of any D/A converter a potential problem.

Since the digital signals contain high-frequency components

of the CLK signal, as well as the video output signal, the

resulting data feedthrough often looks like harmonic distor-

tion or reduced signal-to-noise performance. All ground pins

should be connected to a common solid ground plane for

best performance.

WHITE

The WHITE control drives all three D/As to full-scale, over-

riding the data inputs. It is overridden by the BLANK input,

and is independent of SYNC.

2

REV. 0.9.1 11/24/99

PRODUCT SPECIFICATION

TMC3533

Table 1. Output Voltage versus Input Code, SYNC, BLANK, and WHITE

V

REF

= 1.235 V, R = 572 Ω, R = 37.5 Ω

REF L

All D/As

D/A with IOS Connected

RGB7-0

(MSB…LSB)

XXXX XXXX

1111 1111

1111 1110

1111 1101

SYNC

BLANK

WHITE

V

SYNC

BLANK

WHITE

V

OUT

1.000

0.997

0.995

X

1

0

0.714

0.711

0.709

1

0

•

0000 0000

1111 1111

X

1

0

0.385

0.383

1

0

0.671

0.669

•

0000 0010

0000 0001

0000 0000

XXXX XXXX

X

1

0

0.059

0.057

0.054

0.000

1

0

1

0

0.345

0.343

0.340

0.286

0.000

0

X

Pin Assignments

LQFP Package

PLCC Package

G

7

39

38

37

36

35

34

33

32

31

30

29

IO

0

1

2

3

4

5

6

7

R

G

S

8

IO

V

36

R

V

1

2

3

4

5

6

7

8

9

GND

REF

9

G

35

34

33

32

31

30

29

28

0

G

10

11

12

13

14

15

16

17

COMP

1

2

3

4

5

6

7

DD

IO

R

V

IO

G

TMC3533

OV

DD

TMC3533

V

DD

IO

B

IO

B

GND

CLOCK

NC

BLANK

10

11

12

27

26

25

BLANK

SYNC

V

DD

V

DD

65-3533-06

65-3533-03

Notes (LQFP Package Only):

1. Pin functions White and Sleep are not available.

2. IO function is internally tied to IO pin.

S

G

REV. 0.9.1 11/24/99

3

TMC3533

PRODUCT SPECIFICATION

Pin Descriptions

Pin Number

Name

LQFP

PLCC

Value

Pin Function Description

Clock and Pixel I/O

CLK

26

27

TTL

Clock Input. The clock input is TTL-compatible and all pixel

data is registered on the rising edge of CLK. It is recommended

that CLK be driven by a dedicated TTL buffer to avoid reflection

induced jitter, overshoot, and undershoot.

R

47-40

9-2

23-16

6-1, 44-43

14-7

25-18

TTL

Red, Green, and Blue Pixel Inputs. The R, G, and B digital

inputs are TTL-compatible and registered on the rising edge of

CLK.

7-0

G

7-0

B

Controls

SYNC

11

16

Sync Pulse Input. Bringing SYNC LOW, turns off a 40 IRE

(7.62 mA) current source which forms a sync pulse on any D/A

converter output connected to IO . SYNC is registered on the

S

rising edge of CLK along with pixel data and has the same

pipeline latency as BLANK and pixel data. SYNC does not

override any other data and should be used only during the

blanking interval. If the system does not require sync pulses,

SYNC and IO should be connected to GND.

S

BLANK

WHITE

10

—

15

26

TTL

Blanking Input. When BLANK is LOW, pixel inputs are ignored

and the D/A converter outputs are driven to the blanking level.

BLANK is registered on the rising edge of CLK and has the

same two-pipe latency as SYNC and Data.

Force Full Scale Input. When WHITE is HIGH, pixel inputs are

ignored and the D/A converter outputs are driven to their full-

scale output level. A BLANK input overwrites a WHITE input.

WHITE is register on the rising edge of CLK and has the same

two-pipe latency as SYNC and Data.

SLEEP

—

28

TTL

Power-down Control Input. When HIGH, SLEEP places the D/

A converter in a low-power-dissipation mode. The D/A current

sources and the digital processing are disabled. The last data

loaded into the input and D/A registers is retained. This control is

asynchronous.

Video Outputs

IO

33

32

29

39

38

33

0.714 V

Red, Green, and Blue Data Outputs. The current source

outputs of the D/A converters are capable of driving RS-343A/

SMPTE-170M compatible levels into doubly-terminated 75 Ohm

lines. Sync pulses may be added to any D/A output.

R

G

B

p-p

IO

32

37

SYNC Current Output. When this pin is connected to any of the

D/A converter outputs, a 40 IRE offset can be added to the video

level. When the SYNC input is LOW, the current is turned off,

bring the sync tip voltage to 0.0V. If no sync pulse is required,

S

p-p

(connected

to IO )

G

IO should be grounded. When SYNC is HIGH, the current

S

flowing out of IO is:

S

IO = 3.64 (V

REF

/ R )

REF

S

Voltage Reference

35

V

41

+1.235 V Voltage Reference Input/Output. An internal voltage source of

+1.235 Volts is output on this pin. An external +1.235 Volt

REF

reference may be applied here which overrides the internal

reference. Decoupling V

capacitor is required.

to GND with a 0.1µF ceramic

REF

4

REV. 0.9.1 11/24/99

PRODUCT SPECIFICATION

TMC3533

Pin Descriptions (continued)

Pin Number

Name

LQFP

PLCC

Value

Pin Function Description

R

REF

36

42

572 Ω

Current-setting Resistor. The full-scale output current of each

D/A converter is determined by the value of the resistor

connected between R

and GND. The nominal value for

REF

R

is found from:

REF

R

= 9.1 (V /I ),

REF FS

but is optimized to be 572 Ω. I is the full-scale (white) output

FS

current (amps) from an output without sync. Sync current is 0.4

I

.

FS

D/A full-scale (white) current may also be calculated from:

I

= V /R

FS

L

Where V is the white voltage level and R is the total resistive

FS

L

load (ohms) on each D/A converter. V is the blank to full-scale

FS

voltage.

COMP

34

40

0.1 µF

Compensation Capacitor. A 0.1 µF ceramic capacitor must be

connected between COMP and V

circuitry.

to stabilize internal bias

DD

Power, Ground

12, 30, 31 17, 34–36

V

DD

+3.3 V

0.0V

Power Supply.

Ground.

GND

1, 14, 15,

27, 28, 38,

39, 48

29–32

NC

13, 24, 25,

37

—

No Connect

Equivalent Circuits

V

DD

V

DD

p

Digital

Input

n

p

V

DD

n

OUT

GND

27014D

27013B

Figure 2. Equivalent Digital Input Circuit Figure 3. Equivalent Analog Output Circuit

REV. 0.9.1 11/24/99

5

TMC3533

PRODUCT SPECIFICATION

Equivalent Circuits (continued)

V

DD

p

R

REF

V

REF

27012B

GND

Figure 4. Equivalent Analog Input Circuit

Absolute Maximum Ratings (beyond which the device may be damaged)¹

Parameter

Min

Typ

Max

Unit

Power Supply Voltage

V

DD

(Measured to GND)

-0.5

7.0

V

Inputs

Applied Voltage (measured to GND)²

Forced Current^3,4

-0.5

V

+ 0.5

V

DD

-10.0

10.0

mA

Outputs

Applied Voltage (measured to GND)²

-0.5

+ 0.5

V

DD

Forced Current^3,4

-60.0

60.0

mA

Short Circuit Duration (single output in HIGH state to ground)

inﬁnite

second

Temperature

Operating, Ambient

Junction

-20

110

150

300

220

150

°C

Lead Soldering (10 seconds)

Vapor Phase Soldering (1 minute)

Storage

-65

Notes:

1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if

Operating Conditions are not exceeded.

2. Applied voltage must be current limited to specified range.

3. Forcing voltage must be limited to specified range.

4. Current is specified as conventional current flowing into the device.

6

REV. 0.9.1 11/24/99

PRODUCT SPECIFICATION

TMC3533

Operating Conditions

Parameter

Min

Nom

Max

3.465

30

Units

V

Power Supply Voltage

Conversion Rate

3.135

3.3

DD

f

S

TMC3533-30

TMC3533-50

TMC3533-80

Msps

ns

50

80

t

CLK Pulsewidth, HIGH

CLK Pulsewidth, LOW

Input Data Setup Time

Input Date Hold Time

4

PWH

PWL

s

ns

3

ns

2

ns

h

V

Reference Voltage, External

Compensation Capacitor

Output Load

1.0

1.235

0.1

1.5

V

REF

C

R

µF

C

L

37.5

Ω

V

Input Voltage, Logic HIGH

Input Voltage, Logic LOW

Ambient Temperature, Still Air

2.0

GND

0

V_DD

0.8

70

V

IH

IL

A

V

T

°C

Electrical Characteristics

Parameter

Conditions³

Min

Typ¹

Max

Units

I

Power Supply Current²

V

DD

= Max

DD

TMC3533-30

TMC3533-50

TMC3533-80

95

105

mA

I

Power Supply Current,

Sleep Mode

Total Power Dissipation²

V

= Max

3

mA

DDS

DD

PD

= Max

TMC3533-30

DD

330

346

mW

TMC3533-50

TMC3533-80

R

C

Output Resistance

Output Capacitance

Input Current, HIGH

Input Current, LOW

100

kΩ

pF

µA

V

O

I

= 0mA

30

-1

O

OUT

I

V

= Max, V = 3.0V

IN

IH

DD

= Max, V = 0.4V

IN

1

IL

V

REF

Input Bias Current

0

1.235

0

±100

REF

V

REF

V

OC

Reference Voltage Output

Output Compliance

Referred to V

DD

-0.4

+1.5

10

V

C

Digital Input Capacitance

4

pF

DI

Notes:

1. Values shown in Typ column are typical for V

= +3.3V and T = 25°C

DD

A

2. Minimum/Maximum values with V

DD

= Max and T = Min

A

3. V

REF

= 1.235V, R

LOAD

= 37.5Ω, R = 572Ω

REF

REV. 0.9.1 11/24/99

7

TMC3533

PRODUCT SPECIFICATION

Switching Characteristics

Parameter

Conditions²

Min

Typ¹

10

1

Max

15

2

Units

ns

t

Clock to Output Delay

Output Skew

V_DD= Min

D

ns

SKEW

R

Output Risetime

Output Falltime

10% to 90% of Full Scale

90% to 10% of Full Scale

to 3%/FS

3

4

ns

3

4

ns

F

Output Settling Time

15

ns

SET

Notes:

1. Values shown in Typ column are typical for V

= +3.3V and T = 25°C.

A

DD

2. V

REF

= 1.235V, R

LOAD

= 37.5Ω, R

REF

= 572Ω.

System Performance Characteristics

Parameter

Conditions²

Min

Typ¹

Max

Units

%/FS

%

E

Integral Linearity Error

Differential Linearity Error

DAC to DAC Matching

Output Off Current

V

, V

= Nom

±0.1

7

±0.25

10

LI

DD REF

, V

DD REF

LD

, V

DD REF

DM

OFF

I

= Max, R, G, B = 000h

20

nA

DD

SYNC = BLANK = 0

PSRR Power Supply Rejection

Ratio

0.05

%/%

Notes:

1. Values shown in Typ column are typical for V

DD

= +3.3V and T = 25°C.

A

2. V

REF

= 1.235V, R

LOAD

= 37.5Ω, R = 572Ω.

REF

Timing Diagram

1/f

S

t

PWL

PWH

CLK

t

H

t

S

PIXEL DATA

& CONTROLS

DataN

DataN+1

DataN+2

3%/FS

90%

10%

t

D

t

SET

t

F

R

OUTPUT

50%

65-3503-04

8

REV. 0.9.1 11/24/99

PRODUCT SPECIFICATION

TMC3533

Application Notes

Figure 4 illustrates a typical TMC3533 interface circuit. In

this example, an optional 1.2 Volt bandgap reference is con-

2. The power plane for the TMC3533 should be separate

from that which supplies the digital circuitry. A single

nected to the V

output, overriding the internal voltage

power plane should be used for all of the V

pins. If

REF

DD

reference source.

the power supply for the TMC3533 is the same as that of

the system's digital circuitry, power to the TMC3533

should be decoupled with 0.1µF and 0.01µF capacitors

and isolated with a ferrite bead.

Grounding

It is important that the TMC3533 power supply is well-regu-

lated and free of high-frequency noise. Careful power supply

decoupling will ensure the highest quality video signals at

the output of the circuit. The TMC3533 has separate analog

and digital circuits. To keep digital system noise from the

D/A converter, it is recommended that power supply voltages

3. The ground plane should be solid, not cross-hatched.

Connections to the ground plane should have very short

leads.

4. If the digital power supply has a dedicated power plane

layer, it should not be placed under the TMC3533, the

voltage reference, or the analog outputs. Capacitive cou-

pling of digital power supply noise from this layer to the

TMC3533 and its related analog circuitry can have an

adverse effect on performance.

(V ) come from the system analog power source and all

DD

ground connections (GND) be made to the analog ground

plane. Power supply pins should be individually decoupled

at the pin.

Printed Circuit Board Layout

5. CLK should be handled carefully. Jitter and noise on

this clock will degrade performance. Terminate the

clock line carefully to eliminate overshoot and ringing.

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Overall system

performance is strongly inﬂuenced by the board layout.

Capacitive coupling from digital to analog circuits may

result in poor D/A conversion. Consider the following sug-

gestions when doing the layout:


型号：	TMC3533KRC50
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Triple Video D/A Converter 8 bit, 80 Msps, 3.3V 三路视频D / A转换器8位， 80 MSPS， 3.3V 转换器数模转换器
文件：	总12页 (文件大小：70K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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