NC7SV57L6X_10_技术文档

December 2010

NC7SV57 / NC7SV58

TinyLogic^®ULP-A Universal Configurable Two-Input

Logic Gates

Features

Description

The NC7SV57 and NC7SV58 are universal configurable

two-input logic gates from Fairchild’s Ultra-Low Power

(ULP-A) series of TinyLogic^®. ULP-A is ideal for

applications that require extreme high-speed, high

drive, and low power. This product is designed for a

0.9V to 3.6V V_CCSupply Operation

3.6V Over-Voltage Tolerant I/Os at V_CC

from 0.9V to 3.6V

Extremely High Speed tPD

wide low-voltage operating range (0.9V to 3.6V V_CC

)

- 2.5ns: Typical for 2.7V to 3.6V V_CC

- 3.1ns: Typical for 2.3V to 2.7V V_CC

- 4.0ns: Typical for 1.65V to 1.95V V_CC

- 6.0ns: Typical for 1.4V to 1.6V V_CC

- 8.0ns: Typical for 1.1V to 1.3V V_CC

- 23.0ns: Typical for 0.9V V_CC

and applications that require more drive and speed than

the TinyLogic^®ULP series, but still offer best-in-class,

low-power operation.

Each device is capable of being configured for 1 of 5

unique two-input logic functions. Any possible two-input

combinatorial logic function can be implemented, as

shown in the Function Selection Table. Device

functionality is selected by how the device is wired at

the board level. Figures 1 through 10 illustrate how to

connect the NC7SV57 and NC7SV58, respectively, for

the desired logic function. All inputs have been

implemented with hysteresis.

Power-Off High-Impedance Inputs and Outputs

High Static Drive (I_OH/I_OL

- ±24mA at 3.00V V_CC

- ±18mA at 2.30V V_CC

- ±6mA at 1.65V V_CC

- ±4mA at 1.4V V_CC

- ±2mA at 1.1V V_CC

- ±0.1mA at 0.9V V_CC

)

The NC7SV57 and NC7SV58 are uniquely designed for

optimized power and speed and are fabricated with an

advanced CMOS technology to achieve high-speed

operation while maintaining low CMOS power

dissipation.

Proprietary Quiet Series™ Noise/EMI Reduction

Ultra-Small MicroPak™ Package

Ultra-Low Dynamic Power

Ordering Information

Part Number

Top Mark

Package

Packing Method

3000 Units on

Tape & Reel

NC7SV57P6X

V57

6-Lead SC70, EIAJ SC-88a, 1.25mm Wide

NC7SV57L6X

NC7SV57FHX

H3

6-Lead Micropak™, 1.0mm Wide

5000 Units on

Tape & Reel

6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

3000 Units on

Tape & Reel

NC7SV58P6X

V58

6-Lead SC70, EIAJ SC-88a, 1.25mm Wide

NC7SV58L6X

NC7SV58FHX

H4

6-Lead Micropak™, 1.0mm Wide

5000 Units on

Tape & Reel

6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

Battery Life

Figure 1. Battery Life vs. V_CCSupply Voltage

Notes:

1. TinyLogic^®ULP and ULP-A with up to 50% less power consumption can extend your battery life significantly.

Battery Life = (V_battery•I_battery•.9)/(P_device)/24hrs/day

where P_device= (I_CC• V_CC) + (C_PD+ C_L) • V_CC²• f.

2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at

10MHz, with C_L= 15pF load.

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

2

Pin Configurations

Figure 2. SC70 (Top View)

Figure 3. MicroPak™ (Top Through View)

Figure 4. Pin 1 Orientation

Notes:

3. AAA represents product code top mark (see Ordering Information).

4. Orientation of top mark determines pin one location.

5. Reading the top mark left to right, pin one is the lower left pin.

Pin Definitions

Pin # SC70

Pin # MicroPak™

Name

Description

Data Input

1

2

3

4

5

6

1

2

3

4

5

6

I₁

GND

I₀

Ground

Data Input

Output

Y

V_CC

I₂

Supply Voltage

Data Input

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

3

Function Table

Inputs

NC7SV57

NC7SV58

I₂

L

I₁

L

I₀

L

Y = (I₀) • (I₂) + (I₁) • (I₂)

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H = HIGH Logic Level

L = LOW Logic Level

Function Selection Table

2-Input Logic Function

2-Input AND

Device Selection

Connection Configuration

Figure 5

NC7SV57

NC7SV58

NC7SV57

NC7SV58

NC7SV57

NC7SV58

NC7SV57

NC7SV58

NC7SV57

NC7SV58

NC7SV57

NC7SV58

NC7SV57

2-Input AND with Inverted Input

2-Input AND with Both Inputs Inverted

2-Input NAND

Figure 11, Figure 12

Figure 8

Figure 10

2-Input NAND with Inverted Input

2-Input NAND with Both Inputs Inverted

2-Input OR

Figure 6, Figure 7

Figure 13

2-Input OR with Inverted Input

2-Input OR with Both Inputs Inverted

2-Input NOR

Figure 6, Figure 7

Figure 10

Figure 8

2-Input NOR with Inverted Input

2-Input NOR with Both Inputs Inverted

2-Input XOR

Figure 10, Figure 11

Figure 5

Figure 14

2-Input XNOR

Figure 9

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

4

NC7SV57 Logic Configurations

Figure 5 through Figure 9 show the logical functions

that can be implemented using the NC7SV57. The

diagrams show the DeMorgan’s equivalent logic duals

implementation is next to the board-level physical

implementation of how the pins of the function should

be connected.

for

a

given two-input function. The logical

Figure 5. 2-Input AND Gate

Figure 6. 2-Input NAND Gate with Inverted A Input

Figure 7. 2-Input NAND with Inverted B Input

Figure 8. 2-Input NOR Gate

Figure 9.

2-Input XNOR Gate

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

5

NC7SV58 Logic Configurations

Figure 10 through Figure 14 show the logical functions

that can be implemented using the NC7SV58. The

diagrams show the DeMorgan’s equivalent logic duals

implementation is next to the board-level physical

implementation of how the pins of the function should

be connected.

for

a

given two-input function. The logical

Figure 10. 2-Input NAND Gate

Figure 11. 2-Input AND Gate with Inverted A Input

Figure 12. 2-Input AND with Inverted B Input

Figure 13. 2-Input OR Gate

Figure 14. 2-Input XOR Gate

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

6

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_CC

Parameter

Min.

-0.5

Max.

4.6

Unit

V

Supply Voltage

V_IN

DC Input Voltage

4.6

V

HIGH or LOW State⁽⁶⁾

V_CC+ 0.5

4.6

V_OUT

I_IK

DC Output Voltage

V

V_CC=0V

DC Input Diode Current

DC Output Diode Current

DC Output Source / Sink Current

V_IN< 0V

±50

mA

V_OUT< 0V

V_OUT> V_CC

-50

I_OK

+50

I_OH/ I_OL

I_CCor I_GND

T_STG

±50

mA

°C

DC V_CCor Ground Current per Supply Pin

Storage Temperature Range

±50

-65

+150

130

MicroPak™-6

SC70-6

MicroPak2™-6

P_D

Power Dissipation at +85°C

150

mW

V

120

Human Body Model, JEDEC:JESD22-A114

Charged Device Model, JEDEC:JESD22-C101

4000

2000

ESD

Note:

6. IO absolute maximum rating must be observed.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_CC

Parameter

Supply Voltage Operating

Input Voltage

Conditions

Min.

0.9

0

Max.

3.6

Unit

V

V_IN

3.6

V

V_CC=0V

0

3.6

V_OUT

Output Voltage

V

HIGH or LOW State

V_CC=3.0V to 3.6V

V_CC=2.3V to 2.7V

V_CC=1.65V to 1.95V

V_CC=1.4V to 1.6V

V_CC=1.1V to 1.3V

V_CC=0.9V

0

V_CC

±24.0

±18.0

±6.0

±4.0

±2.0

±0.1

mA

I_OH/I_OL

Output Current

µA

°C

T_A

Operating Temperature, Free Air

Minimum Input Edge Rate

-40

+85

V_IN=0.8V to 2.0, V_CC=3.0V

SC70-6

10

ns/V

Δt/ΔV

425

500

560

Thermal Resistance

MicroPak™-6

°C/W

θ_JA

MicroPak2™-6

Note:

7. Unused inputs must be held HIGH or LOW. They may not float.

www.fairchildsemi.com

NC7SV57 • NC7SV58 • Rev. 1.0.4

7

DC Electrical Characteristics

T_A=25°C

Min.

T_A=-40 to 85°C

Symbol

Parameter

V_CC

Conditions

Units

Max.

0.70

1.00

1.40

1.50

1.80

2.20

0.60

0.70

0.80

0.90

1.15

1.50

0.50

0.60

0.80

1.00

1.10

1.20

Min.

0.30

Max.

0.70

1.00

1.40

1.50

1.80

2.20

0.60

0.70

0.80

0.90

1.15

1.50

0.50

0.60

0.80

1.00

1.10

1.20

0.90

1.10

0.30

0.40

0.50

0.70

1.00

1.30

0.10

0.15

0.20

0.25

0.40

0.60

0.07

0.08

0.10

0.15

0.25

0.40

V_CC-0.1

0.40

1.40

0.50

Positive Threshold

Voltage

V_P

V

1.65

0.70

2.30

1.00

2.70

1.30

0.90

0.10

1.10

0.15

1.40

0.20

Negative Threshold

Voltage

V_N

V

1.65

0.25

2.30

0.40

2.70

0.60

0.90

0.07

1.10

0.08

1.40

0.10

V_H

Hysteresis Voltage

V

1.65

0.15

2.30

0.25

2.70

0.40

0.90

V_CC-0.1

V_CC-0.2

.75 x V_CC

1.25

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

V

_CC-0.2

I_OH=-100µA

I

_OH=-2mA

_OH=-4mA

.75 x V_CC

1.25

2.0

HIGH Level Output

Voltage

V_OH

V

I

_OH=-6mA

2.0

1.8

_OH=-12mA

2.2

1.7

I

_OH=-18mA

_OH=-24mA

2.4

2.2

Continued on following page….

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

8

DC Electrical Characteristics (Continued)

T_A=25°C

T_A=-40 to 85°C

Symbol

Parameter

V_CC

Conditions

Units

Min.

Max.

Min.

Max.

0.1

0.90

0.1

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

0.2

I

_OL=100µA

0.2

I

_OL=2mA

_OL=4mA

_OL=6mA

.25 x V_CC

0.3

.25 x V_CC

0.3

LOW Level Output

Voltage

V_OL

V

0.4

I_OL=12mA

0.4

0.6

I

_OL=18mA

_OL=24mA

0.4

0.55

Input Leakage

Current

I_IN

0.90 to 3.60

0

±0.1

±0.5

0.5

µA

0 ≤ V_IN≤ 3.6V

Power Off Leakage

Current

I_OFF

0.5

0.9

0 ≤ (V_IN,V_O) ≤ 3.60

V_IN=V_CCor GND

0.9

Quiescent Supply

Current

I_CC

0.90 to 3.60

µA

V_CC≤ V_IN≤ 3.6V

±0.9

AC Electrical Characteristics

T_A=25°C

T_A=-40 to 85°C

Symbol Parameter

V_CC

Conditions

Units Figure

Min. Typ. Min. Typ.

Min.

C_L=15pF,

R_L=1MΩ

0.90

15.0

4.0

2.0

1.5

1.2

8.0

6.0

4.0

3.1

2.5

16.5

10.0

9.1

3.3

2.0

1.9

1.4

1.2

31.0

12.0

10.0

6.7

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

C_L=15pF, R_L=2KΩ

Propagation

t_PHL, t_PLH

Figure 15

ns

Delay

Figure 16

C_L=30pF,

R_L=500Ω

6.2

5.4

6.1

Input

C_IN

0

8

pF

Capacitance

Output

C_OUT

12

Capacitance

Power

Dissipation

Capacitance

V_I=0V or V_CC

f=10MHz

,

C_PD

0.90 to 3.60

10

pF

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

9

AC Loadings and Waveforms

Figure 15. AC Test Circuit

Figure 16. AC Waveforms

V_CC

2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.10V 1.2V ± 0.10V

Symbol

3.3V ± 0.3V

1.5V

0.9V

V_CC/2

V_mi

V_CC/2

V_mo

1.5V

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

10

Physical Dimensions

SYMM

C

L

±0.20

A

2.00

0.65

0.50 MIN

6

4

B

PIN ONE

±0.10

1.25

1.90

1

3

0.30

0.15

(0.25)

0.40 MIN

0.10

A B

1.30

0.65

1.30

LAND PATTERN RECOMMENDATION

SEE DETAIL A

1.00

0.80

1.10

0.80

0.10 C

0.10

0.00

C

2.10±0.30

SEATING

PLANE

NOTES: UNLESS OTHERWISE SPECIFIED

GAGE

PLANE

A) THIS PACKAGE CONFORMS TO EIAJ

SC-88, 1996.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE BURRS

OR MOLD FLASH.

(R0.10)

0.25

0.10

D) DRAWING FILENAME: MKT-MAA06AREV6

0.20

30°

0°

0.46

0.26

DETAIL A

SCALE: 60X

Figure 17. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

3000

Cavity Status Cover Type Status

Empty

Filled

Sealed

P6X

Trailer (Hub End)

75 (Typical)

Empty

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

11

Physical Dimensions

2X

0.05 C

1.45

B

(1)

2X

0.05 C

(0.49)

5X

(0.254)

1.00

(0.75)

(0.52)

1X

TOP VIEW

A

PIN 1 IDENTIFIER

5

0.55MAX

(0.30)

6X

PIN 1

0.05 C

0.05

0.00

RECOMMENED

LAND PATTERN

0.05 C

C

0.45

0.35

0.10

6X

0.00

0.25

6X

0.15

1.0

DETAIL A

0.10

C B A

0.40

0.30

0.05

C

0.35

0.25

5X

0.40

0.30

DETAIL A

PIN 1 TERMINAL

0.075 X 45

CHAMFER

0.5

BOTTOM VIEW

(0.05)

6X

(0.13)

4X

Notes:

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

2. DIMENSIONS ARE IN MILLIMETERS

3. DRAWING CONFORMS TO ASME Y14.5M-1994

4. FILENAME AND REVISION: MAC06AREV4

5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY

OTHER LINE IN THE MARK CODE LAYOUT.

Figure 18. 6-Lead, MicroPak™, 1.0mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

5000

Cavity Status Cover Type Status

Empty

Filled

Sealed

L6X

Trailer (Hub End)

75 (Typical)

Empty

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

12

Physical Dimensions

0.89

0.35

0.05 C

2X

1.00

B

A

5X 0.40

1X 0.45

PIN 1

0.66

MIN 250uM

1.00

6X 0.19

0.05 C

TOP VIEW

RECOMMENDED LAND PATTERN

FOR SPACE CONSTRAINED PCB

2X

0.90

0.35

0.05 C

0.55MAX

C

5X 0.52

SIDE VIEW

0.73

0.57

1X

(0.08) 4X

0.09

0.19

6X

DETAIL A

1

2

3

0.20 6X

ALTERNATIVE LAND PATTERN

FOR UNIVERSAL APPLICATION

(0.05) 6X

0.35

5X

0.25

0.60

6

5

4

0.10

.05 C

C B A

0.40

0.30

0.35

(0.08)

4X

BOTTOM VIEW

NOTES:

A. COMPLIES TO JEDEC MO-252 STANDARD

B. DIMENSIONS ARE IN MILLIMETERS.

0.075X45°

CHAMFER

C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994

D. LANDPATTERN RECOMMENDATION IS BASED ON FSC

DESIGN.

DETAIL A

PIN 1 LEAD SCALE: 2X

E. DRAWING FILENAME AND REVISION: MGF06AREV3

Figure 19. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf

.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

5000

Cavity Status Cover Type Status

Empty

Filled

Sealed

FHX

Trailer (Hub End)

75 (Typical)

Empty

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

13

NC7SV57 • NC7SV58 • Rev. 1.0.4

www.fairchildsemi.com

14


型号：	NC7SV57L6X_10
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	TinyLogicÂ® ULP-A Universal Configurable Two-Input Logic Gates 栅
文件：	总14页 (文件大小：633K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NC7SV57L6X_10 [FAIRCHILD]

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