MM74HCT00MTCX_NL [FAIRCHILD]
Quad 2 Input NAND Gate; 四2输入与非门
| 型号： | MM74HCT00MTCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad 2 Input NAND Gate |
| 文件： | 总7页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1984
Revised January 2005
MM74HCT00
Quad 2 Input NAND Gate
General Description
Features
■ TTL, LS pin-out and threshold compatible
The MM74HCT00 is
a
NAND gates fabricated using
advanced silicon-gate CMOS technology which provides
the inherent benefits of CMOS—low quiescent power and
wide power supply range. This device is input and output
characteristic and pin-out compatible with standard 74LS
logic families. All inputs are protected from static discharge
damage by internal diodes to VCC and ground.
■ Fast switching: tPLH, tPHL=14 ns (typ)
■ Low power: 10 µW at DC
■ High fan out, 10 LS-TTL loads
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Ordering Code:
Package
Order Number
Package Description
Number
MM74HCT00M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT00MX_NL
MM74HCT00SJ
MM74HCT00MTC
MM74HCT00MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HCT00N
N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HCT00N_NL
N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Logic Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
(1 of 4 gates)
Top View
© 2005 Fairchild Semiconductor Corporation
DS005356
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC+1.5V
−0.5 to VCC+0.5V
±20 mA
Min
Max
5.5
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
4.5
0
V
V
)
VCC
)
)
)
±25 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
(tr, tf)
+85
°C
)
±50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
500
ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
600 mW
500 mW
Note 2: Unless otherwise specified all voltages are referenced to ground.
S.O. Package only
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
Lead Temperature (TL)
(Soldering 10 seconds)
260°C
DC Electrical Characteristics
V
= 5V ± 10% (unless otherwise specified)
CC
Symbol
VIH
T
A = 25°C
TA = −40 to 85°C TA = -55 to 125°C
Parameter
Conditions
Units
Typ
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
V
VIL
Maximum LOW Level
Input Voltage
0.8
0.8
V
VOH
Minimum HIGH Level
Output Voltage
VIN = VIH or VIL
|IOUT| = 20 µA
VCC
4.2
V
CC−0.1
3.98
V
CC−0.1
V
CC−0.1
V
V
V
|IOUT| = 4.0 mA, VCC = 4.5V
|IOUT| = 4.8 mA, VCC = 5.5V
3.84
3.7
5.2
4.98
4.84
4.7
VOL
Maximum LOW Level
Voltage
VIN = VIH
|IOUT| = 20 µA
0
0.1
0.26
0.26
±0.05
0.1
0.1
0.4
V
V
|IOUT| = 4.0 mA, VCC = 4.5V
|IOUT| = 4.8 mA, VCC = 5.5V
0.2
0.2
0.33
0.33
±0.5
0.4
V
IIN
Maximum Input
V
IN = VCC or GND,
VIH or VIL
IN = VCC or GND,
OUT = 0 µA
IN = 2.4V or 0.5V (Note 4)
Note 4: This is measured per input with all other inputs held at VCC or ground.
±1.0
µA
Current
ICC
Maximum Quiescent
Supply Current
V
1.0
0.3
10
40
µA
I
V
0.18
0.4
0.5
mA
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2
AC Electrical Characteristics
VCC = 5.0V, tr = tr = 6 ns, CL = 15 pF, TA = 25°C (unless otherwise noted)
Guaranteed
Limit
Symbol Parameter Conditions
Typ
Units
tPLH, tPHL
Maximum Propagation
Delay
14
18
ns
AC Electrical Characteristics
VCC = 5.0V ±10%, tr = tf = 6 ns, CL = 50 pF (unless otherwise noted)
T
A = 25°C
T
A = −40 to 85°C TA = −55 to 125°C
Symbol
Parameter
Conditions
Units
Typ
18
8
Guaranteed Limits
tPLH, tPHL
tTHL, tTLH
Maximum Propagation Delay
23
29
19
35
22
ns
ns
Maximum Output Rise & Fall
Time
15
CPD
CIN
Power Dissipation Capacitance (Note 5)
Input Capacitance
30
5
pF
pF
10
10
10
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
S = CPD VCC f + ICC
I
.
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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