MM74C89N [FAIRCHILD]
64-Bit 3-STATE Random Access Read/Write Memory; 64位三态随机存取存储器读/写
| 型号： | MM74C89N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 64-Bit 3-STATE Random Access Read/Write Memory |
| 文件： | 总6页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
MM74C89
64-Bit 3-STATE Random Access Read/Write Memory
Read Operation: The complement of the information
which was written into the memory is non-destructively
General Description
The MM74C89 is a 16-word by 4-bit random access read/
read out at the four outputs. This is accomplished by
write memory. Inputs to the memory consist of four address
selecting the desired address and bringing memory enable
lines, four data input lines, a write enable line and a mem-
LOW and write enable HIGH.
ory enable line. The four binary address inputs are
When the device is writing or disabled the output assumes
decoded internally to select each of the 16 possible word
a 3-STATE (Hi-z) condition.
locations. An internal address register latches the address
information on the positive to negative transition of the
memory enable input. The four 3-STATE data output lines
working in conjunction with the memory enable input pro-
vide for easy memory expansion.
Features
■ Wide supply voltage range: 3.0V to 15V
■ Guaranteed noise margin: 1.0V
Address Operation: Address inputs must be stable tSA
■ High noise immunity: 0.45 VCC (typ.)
prior to the positive to negative transition of memory
enable. It is thus not necessary to hold address information
stable for more than tHA after the memory is enabled (posi-
■ Low power TTL compatibility:
fan out of 2 driving 74L
■ Low power consumption: 100 nW/package (typ.)
■ Fast access time: 130 ns (typ.) at VCC = 10V
tive to negative transition of memory enable).
Write Operation: Information present at the data inputs is
written into the memory at the selected address by bringing
write enable and memory enable LOW.
■ 3-STATE output
Note: The timing is different than the DM7489 in that a positive to negative
transition of the memory enable must occur for the memory to be selected.
Ordering Code:
Order Number
Package Number Package Description
MM74C89N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Connection Diagram
Truth Table
ME WE
Operation
Write
Read
Condition of Outputs
3-STATE
Complement of Selected Word
Pin Assignments for DIP
L
L
L
H
L
H
H
Inhibit, Storage 3-STATE
Inhibit, Storage 3-STATE
H
Top View
© 1999 Fairchild Semiconductor Corporation
DS005888.prf
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Logic Diagram
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2
Absolute Maximum VCC
Lead Temperature (TL)
(Soldering, 10 seconds)
18V
Absolute Maximum Ratings(Note 1)
Voltage at any Pin
−0.3V to VCC +0.3V
260°C
Operating Temperature Range
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
−40°C to +85°C
−65°C to +150°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Range”
they are not meant to imply that the devices should be operated at these
limits. The table of “Electrical Characteristics” provides conditions for actual
700 mW
500 mW
Small Outline
device operation.
Operating VCC Range
3.0V to 15V
DC Electrical Characteristics
Min/Max limits apply across temperature range, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5.0V
= 10V
= 5.0V
= 10V
3.5
8.0
V
V
IN(1)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
1.5
2.0
V
IN(0)
V
= 5.0V, I = −10 µA
4.5
9.0
V
OUT(1)
OUT(0)
O
= 10V, I = −10 µA
V
O
= 5.0V, I = +10 µA
0.5
1.0
1.0
V
O
= 10V, I = +10 µA
V
O
I
I
I
Logical “1” Input Current
Logical “0” Input Current
Output Current in High
Impedance State
= 15V, V = 15V
−0.005
−0.005
0.005
−0.005
0.05
µA
µA
µA
µA
µA
IN(1)
IN(0)
OZ
IN
= 15V, V = 0V
−1.0
−1.0
IN
= 15V, V = 15V
1.0
= 15V, V = 0V
O
I
Supply Current
= 15V
300
CC
CMOS/LPTTL INTERFACE
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
= 4.75V
= 4.75V
V − 1.5
CC
V
V
V
V
IN(1)
CC
CC
CC
CC
0.8
0.4
IN(0)
= 4.75V, I = −360 µA
2.4
OUT(1)
OUT(0)
O
= 4.75V, I = +360 µA
O
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
I
I
I
I
Output Source Current
(P-Channel)
V
= 5.0V, V
= 0V
−1.75
−8.0
1.75
8.0
−3.3
−15
3.6
mA
mA
mA
mA
SOURCE
SOURCE
SINK
CC
OUT
OUT
T
= 25°C
A
Output Source Current
(P-Channel)
V
= 10V, V
CC
= 0V
T
= 25°C
A
Output Sink Current
(N-Channel)
V
= 5.0V, V
= V
CC
OUT
CC
T
= 25°C
A
Output Sink Current
(N-Channel)
V
= 10V, V
= V
16
SINK
CC
OUT
CC
T
= 25°C
A
3
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AC Electrical Characteristics (Note 2)
T
A = 25°C, C = 50 pF, unless otherwise noted
L
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay from
Memory Enable
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
270
100
350
130
500
220
650
280
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pd
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 10V
= 5V
Access Time from
Address Input
ACC
SA
= 10V
= 5V
Address Setup Time
150
60
60
40
400
150
0
= 10V
= 5V
Address Hold Time
HA
ME
SR
WS
WE
HD
SD
= 10V
= 5V
Memory Enable Pulse Width
250
90
= 10V
= 5V
Write Enable Setup
Time for a Read
= 10V
= 5V
0
Write Enable Setup
Time for a Write
t
t
ME
ME
= 10V
= 5V, t
Write Enable Pulse Width
= 0
300
100
50
160
60
WS
= 10V, t
= 5V
= 0
WS
Data Input Hold Time
Data Input Setup
= 10V
= 5V
25
50
= 10V
25
, t
Propagation Delay from a Logical
“1” or Logical “0” to the High
Impedance State from
Memory Enable
= 5V, C = 5 pF, R = 10k
180
300
1H 0H
L
L
= 10V, C = 5 pF, R = 10k
−85
120
L
L
t
, t
Propagation Delay from a Logical
“1” or Logical “0” to the High
Impedance State from
Write Enable
V
V
= 50V, C = 5 pF, R = 10k
180
85
300
120
ns
ns
1H 0H
CC
L
L
= 10V, C = 5 pF, R = 10k
CC
L
L
C
C
C
Input Capacity
Any Input (Note 3)
Any Output (Note 3)
(Note 4)
5
pF
pF
pF
IN
Output Capacity
6.5
230
OUT
PD
Power Dissipation Capacity
Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note,
PD
AN-90.
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4
AC Test Circuits
t0H
t1H
Switching Time Waveforms
t0H
t1H
Read Cycle
Write Cycle
Read Modify Write Cycle
t
= 10 ns
= 60 ns
f
t
r
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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