IRFF110 [FAIRCHILD]
Power Field-Effect Transistor, 3.5A I(D), 100V, 0.6ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF,;
| 型号： | IRFF110 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Field-Effect Transistor, 3.5A I(D), 100V, 0.6ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-205AF, 开关 脉冲 晶体管 |
| 文件： | 总7页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFF110
Data Sheet
March 1999
File Number 1562.3
3.5A, 100V, 0.600 Ohm, N-Channel
Power MOSFET
Features
• 3.5A, 100V
Title
FF1
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
• r = 0.600Ω
DS(ON)
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
b-
t
5A,
0V,
00
m,
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA17441.
an-
Ordering Information
Symbol
wer
OS-
T)
PART NUMBER
PACKAGE
BRAND
IRFF110
D
IRFF110
TO-205AF
NOTE: When ordering, use the entire part number.
utho
G
ey-
rds
5A,
0V,
00
S
m,
Packaging
JEDEC TO-205AF
an-
wer
OS-
T,
SOURCE
DRAIN
(CASE)
er-
GATE
rpo-
on,
-
5AF
e-
r ()
©2001 Fairchild Semiconductor Corporation
IRFF110 Rev. A
IRFF110
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
IRFF110
100
100
UNITS
V
V
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
3.5
A
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
14
A
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
20
V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
0.12
19
W
W/ C
D
o
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
mJ
AS
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Maximum Temperature for Soldering
T
-55 to 150
C
J, STG
o
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
300
260
C
L
o
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
C
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 125 C
J
o
Electrical Specifications
T
= 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
= 0V, I = 250µA (Figure 10)
MIN
TYP
-
MAX UNITS
Drain to Source Breakdown Voltage
Gate Threshold Voltage
BV
V
V
V
V
V
V
V
V
100
-
4.0
25
V
V
DSS
GS
GS
DS
DS
DS
GS
GS
DS
D
V
= V , I = 250µA
DS
2.0
-
GS(TH)
D
Zero Gate Voltage Drain Current
I
= Rated BV
, V
DSS GS
= 0V
-
-
µA
µA
A
DSS
o
= 100V, V
= 0V, T = 125 C
-
-
250
-
GS
x r
J
On-State Drain Current (Note 2)
Gate to Source Leakage Current
I
> I
=
, V
DS(ON)MAX GS
= 10V
3.5
-
D(ON)
D(ON)
20V
I
-
-
100
0.600
-
nA
Ω
GSS
Drain to Source On Resistance (Note 2)
Forward Transconductance (Note 2)
Turn-On Delay Time
r
= 10V, I = 1.5A (Figures 8, 9)
-
0.5
1.5
10
15
15
10
5.0
DS(ON)
D
g
> I
x r
, I = 1.5A (Figure 12)
DS(ON)MAX
1.0
S
fs
d(ON)
D(ON)
D
t
V
V
R
≅ 0.5 x Rated BV
, I ≈ 3.5A, R = 9.1Ω
-
-
-
-
-
20
ns
ns
ns
ns
nC
DD
GS
L
DSS
D
G
= 10V, R = 13Ω (Figures 17, 18),
L
Rise Time
t
25
r
= 14Ω for V
= 50V, R = 23Ω for V
= 80V,
DS
DS
L
Turn-Off Delay Time
t
25
d(OFF)
MOSFET Switching Times are Essentially
Independent of Operating Temperature
Fall Time
t
20
f
Total Gate Charge
Q
V
= 10V, I = 3.5A, V = 0.8 x Rated BV
DS DSS
,
7.5
g(TOT)
GS
D
(Gate to Source + Gate to Drain)
I
= 1.5mA (Figures 14, 19, 20), Gate Charge is
G(REF)
Essentially Independent of Operating Temperature
Gate to Source Charge
Gate to Drain “Miller” Charge
Input Capacitance
Q
Q
-
-
-
-
-
-
2.0
3.0
135
80
-
-
-
-
-
-
nC
nC
pF
pF
pF
nH
gs
gd
C
V
= 25V, V
= 0V, f = 1MHz (Figure 11)
GS
ISS
DS
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
Internal Drain Inductance
C
20
L
Measured from the Drain
Lead, 5.0mm (0.2in) from
Header to Center of Die
Modified MOSFET
Symbol Showing the
Internal Device
Inductances
5.0
D
Internal Source Inductance
L
Measured from the Source
Lead, 5.0mm (0.2in) from
Header to Source Bonding
Pad
-
15
-
nH
S
D
L
D
G
L
S
S
o
o
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
R
R
-
-
-
-
8.33
175
C/W
C/W
θJC
Free Air Operation
θJA
©2001 Fairchild Semiconductor Corporation
IRFF110 Rev. A
IRFF110
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNITS
Continuous Source to Drain Current
Pulse Source to Drain Current (Note 3)
I
Modified MOSFET Symbol
Showing the Integral
Reverse P-N Junction
Rectifier
-
-
-
-
3.5
14
A
A
SD
D
S
I
SM
G
o
Source to Drain Diode Voltage (Note 2)
Reverse Recovery Time
V
T = 25 C, I
J
= 3.5A, V = 0V (Figure 13)
GS
-
-
-
-
-
2.5
V
ns
µC
-
SD
SD
o
t
T = 150 C, I
J
= 3.5A, dI /dt = 100A/µs
200
1.0
-
-
-
-
rr
SD
SD
SD
= 3.5A, dI /dt = 100A/µs
o
Reverse Recovery Charge
Forward Turn-On Time
Q
T = 150 C, I
RR
ON
J
SD
t
Intrinsic Turn-On Time is Negligible. Turn-On
Speed is Substantially Controlled by L + L
S
D
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
o
4. V
= 5V, starting T = 25 C, L = 2.3mH, R = 25Ω, peak I = 3.5A. See Figures 15, 16.
J G AS
DD
Typical Performance Curves Unless Otherwise Specified
1.2
5
1.0
0.8
0.6
0.4
0.2
0
4
3
2
1
0
25
50
75
T , CASE TEMPERATURE ( C)
C
100
150
125
0
50
100
o
150
o
T
, CASE TEMPERATURE ( C)
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
0.5
0.2
P
DM
0.1
0.1
0.05
t
1
0.02
0.01
t
2
SINGLE PULSE
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R
+ T
J
DM
θJC
θJC C
0.01
10
-5
-4
10
-3
10
-2
10
-1
10
1
10
t , RECTANGULAR PULSE DURATION (s)
1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
IRFF110 Rev. A
IRFF110
Typical Performance Curves Unless Otherwise Specified (Continued)
30.0
8.0
80µs PULSE TEST
V
= 10V
GS
= 9V
V
GS
V
= 8V
GS
10µs
10.0
6.4
4.8
100µs
V
= 7V
= 6V
GS
1ms
1.0
0.1
3.2
1.6
0
V
GS
OPERATION IN THIS
AREA LIMITED
10ms
V
= 5V
= 4V
BY r
GS
DS(ON)
100ms
DC
V
GS
0
10
20
30
40
50
1
10
100
200
V
, DRAIN SOURCE VOLTAGE (V)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
DS
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
8.0
8.0
80µs PULSE TEST
V
= 10V
V
> I
x r
DS(ON)MAX
GS
DS D(ON)
o
125 C
80µs PULSE TEST
V
= 9V
GS
6.4
4.8
3.2
1.6
0
6.4
4.8
3.2
1.6
0
o
25 C
V
= 8V
= 7V
GS
V
GS
o
-55 C
V
= 6V
GS
V
= 5V
= 4V
GS
V
GS
0
2.0
3.0
4.0
5.0
1.0
0
2
4
6
8
10
V
, DRAIN TO SOURCE VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
2.0
1.5
1.0
2.50
2.00
1.50
1.00
0.50
0
2µs PULSE TEST
V
= 10V
GS
= 1.5A
I
D
V
= 10V
GS
V
= 20V
GS
0.5
0
0
5
15
20
-40
0
40
80
120
10
I , DRAIN CURRENT (A)
o
T , JUNCTION TEMPERATURE ( C)
D
J
FIGURE 8. DRAINTO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAINTO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
IRFF110 Rev. A
IRFF110
Typical Performance Curves Unless Otherwise Specified (Continued)
1.25
1.15
1.05
0.95
0.85
0.75
500
400
300
200
100
0
I
= 250µA
D
V
= 0V, f = 1MHz
GS
C
C
C
= C
+ C
ISS
GS
GD
= C
GD
RSS
OSS
≈ C
+ C
GD
DS
C
ISS
C
OSS
C
RSS
1
10
20
, DRAIN TO SOURCE VOLTAGE (V)
DS
30
40
50
-40
0
40
80
120
o
T , JUNCTION TEMPERATURE ( C)
V
J
FIGURE 10. NORMALIZED DRAINTO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
4.0
10
V
> I
D(ON)
x r
DS(ON)MAX
DS
80µs PULSE TEST
3.2
2.4
1.6
0.8
0
o
150 C
o
25 C
o
-55 C
o
1.0
0.1
25 C
o
125 C
0
1.6
3.2
4.8
6.4
8.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
I
, DRAIN CURRENT (A)
V , SOURCE TO DRAIN VOLTAGE (V)
SD
D
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
I
= 3.5A
D
V
= 50V
DS
15
10
5
V
= 20V
DS
V
= 80V
DS
0
0
2
4
6
8
10
Q
,TOTAL GATE CHARGE (nC)
g(TOT)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2001 Fairchild Semiconductor Corporation
IRFF110 Rev. A
IRFF110
Test Circuits and Waveforms
V
DS
BV
DSS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
R
REQUIRED PEAK I
G
AS
V
DD
-
DUT
V
GS
t
0
P
I
AS
0V
t
AV
0.01Ω
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
t
t
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
r
V
R
L
DS
90%
90%
+
V
DD
10%
10%
R
G
0
0
-
DUT
90%
50%
V
GS
50%
PULSE WIDTH
10%
V
GS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
V
DS
(ISOLATED
SUPPLY)
CURRENT
REGULATOR
V
DD
Q
SAME TYPE
AS DUT
g(TOT)
V
GS
12V
BATTERY
0.2µF
Q
gd
50kΩ
0.3µF
Q
gs
D
S
V
DS
G
DUT
0
I
G(REF)
0
V
I
DS
G(REF)
I
CURRENT
SAMPLING
RESISTOR
I
CURRENT
G
D
SAMPLING
RESISTOR
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
©2001 Fairchild Semiconductor Corporation
IRFF110 Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
PACMAN™
POP™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
Star* Power™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
FAST
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
UltraFET™
VCX™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TOANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOTASSUMEANY LIABILITYARISING OUT OF THEAPPLICATION OR USE OFANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H
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