HUF75344G3 [FAIRCHILD]
75A, 55V, 0.008 Ohm, N-Channel UltraFET Power MOSFETs; 75A ， 55V ， 0.008 Ohm的N通道UltraFET功率MOSFET
| 型号： | HUF75344G3 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 75A, 55V, 0.008 Ohm, N-Channel UltraFET Power MOSFETs |
| 文件： | 总10页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUF75344G3, HUF75344P3, HUF75344S3S
Data Sheet
December 2001
75A, 55V, 0.008 Ohm, N-Channel UltraFET
Power MOSFETs
Features
• 75A, 55V
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET process. This
• Simulation Models
®
- Temperature Compensated PSPICE and SABER™
Models
®
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
- Thermal Impedance PSPICE and SABER Models
Available on the web at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type TA75344.
D
Ordering Information
PART NUMBER
PACKAGE
BRAND
75344G
G
HUF75344G3
TO-247
HUF75344P3
TO-220AB
TO-263AB
75344P
75344S
S
HUF75344S3S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75344S3ST.
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
GATE
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(TAB)
JEDEC TO-263AB
DRAIN
(FLANGE)
GATE
SOURCE
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
HUF75344G3, HUF75344P3, HUF75344S3S
o
Absolute Maximum Ratings
T
= 25 C, Unless Otherwise Specified
C
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . V
55
55
V
V
V
DSS
DGR
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . V
GS
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
75
Figure 4
Figure 6
285
A
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.90
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T , T
-55 to 175
C
J
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
o
o
1. T = 25 C to 150 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250µA, V
= 0V (Figure 11)
55
-
-
-
-
-
-
V
DSS
D
GS
GS
GS
I
V
V
V
= 50V, V
= 45V, V
= ±20V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
-
GSS
V
V
= V , I = 250µA (Figure 10)
2
-
-
4
V
GS(TH)
GS
DS
D
r
I
= 75A, V
= 10V (Figure 9)
0.0065 0.008
Ω
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
R
R
(Figure 3)
TO-247
-
-
-
-
-
-
0.52
30
C/W
θJC
o
C/W
θJA
o
TO-220, TO-263
62
C/W
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
GS
t
V
R
R
= 30V, I
75A,
= 10V,
-
-
-
-
-
-
-
16
112
37
28
-
195
ns
ns
ns
ns
ns
ns
ON
DD
D
= 0.4Ω, V
L
GS
Turn-On Delay Time
Rise Time
t
-
d(ON)
= 3.0Ω
GS
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
100
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
DD
= 30V,
75A,
-
-
-
-
-
175
90
210
108
7.0
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
I
D
Gate Charge at 10V
Q
g(10)
g(TH)
R
= 0.4Ω
L
Threshold Gate Charge
Q
5.9
14
I
= 1.0mA
g(REF)
(Figure 13)
Gate to Source Gate Charge
Reverse Transfer Capacitance
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
39
-
C
V
= 25V, V
GS
= 0V,
-
-
-
3200
1170
310
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
HUF75344G3, HUF75344P3, HUF75344S3S
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
105
UNITS
V
V
I
I
I
= 75A
-
-
-
-
-
-
SD
SD
SD
SD
t
= 75A, dI /dt = 100A/µs
SD
ns
rr
Reverse Recovered Charge
Q
= 75A, dI /dt = 100A/µs
210
nC
RR
SD
Typical Performance Curves
1.2
80
60
40
20
0
1.0
0.8
0.6
0.4
0.2
0
25
50
75
100
125
150
175
0
25
50
75
100
125
o
150
175
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
x Z
x R
+ T
θJC C
J
DM
θJC
SINGLE PULSE
0.01
-5
10
-4
-3
10
-2
-1
10
0
1
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
HUF75344G3, HUF75344P3, HUF75344S3S
Typical Performance Curves (Continued)
2000
1000
o
T
C
= 25 C
FOR TEMPERATURES
ABOVE 25 C DERATE PEAK
o
CURRENT AS FOLLOWS:
175 - T
150
C
I = I
25
V
= 20V
GS
V
= 10V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
50
-5
-4
10
-3
10
-2
10
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
1000
1000
100
10
If R = 0
T
= MAX RATED
J
t
= (L)(I )/(1.3*RATED BV
- V
)
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
DD
o
T
= 25 C
C
t
AV
- V ) +1]
DD
AS
DSS
100µs
100
o
STARTING T = 25 C
J
1ms
o
STARTING T = 150 C
J
OPERATION IN THIS
AREA MAY BE
10ms
LIMITED BY r
DS(ON)
V
= 55V
DSS(MAX)
10
0.01
1
0.1
1
10
1
10
100
200
t
, TIME IN AVALANCHE (ms)
AV
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
150
120
90
60
30
0
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 20V
GS
V
= 10V
GS
V
= 15V
DD
120
90
60
30
0
V
= 7V
GS
V
= 6V
GS
V
= 5V
GS
o
25 C
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
-55 C
o
T
= 25 C
3
C
0
1
2
4
0
1.5
3
4.5
6
7.5
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
V
, GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
HUF75344G3, HUF75344P3, HUF75344S3S
Typical Performance Curves (Continued)
2.5
2.0
1.5
1.0
0.5
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= V , I = 250µA
DS
GS
D
V
= 10V, I = 75A
GS
D
1.0
0.8
0.6
0.4
-80
-80
-40
0
40
80
120
160
200
200
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1.2
4500
V
= 0V, f = 1MHz
GS
I
= 250µA
D
C
C
C
= C
+ C
ISS
GS
= C
GD
RSS
OSS
GD
C
ISS
≈
C
+ C
GD
DS
1.1
1.0
0.9
3000
C
OSS
1500
C
RSS
0
-80
-40
0
40
80
120
160
200
0
10
20
, DRAIN TO SOURCE VOLTAGE (V)
DS
30
40
50
60
o
T , JUNCTION TEMPERATURE ( C)
V
J
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
V
= 30V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
I
= 75A
= 55A
= 35A
= 20A
D
D
D
D
0
25
50
Q , GATE CHARGE (nC)
75
100
g
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
HUF75344G3, HUF75344P3, HUF75344S3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
-
V
DD
V
= 10V
V
GS
GS
DUT
V
= 2V
GS
I
0
G(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
HUF75344G3, HUF75344P3, HUF75344S3S
PSPICE Electrical Model
.SUBCKT HUF75344P3 2 1 3 ;
rev 3 Feb 1999
CA 12 8 4.9e-9
CB 15 14 4.75e-9
CIN 6 8 2.85e-9
LDRAIN
DPLCAP
5
DRAIN
2
10
RLDRAIN
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC1
DBREAK
51
+
RSLC2
5
51
ESLC
11
+
-
50
EBREAK 11 7 17 18 59.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
-
17
DBODY
RDRAIN
6
8
EBREAK 18
ESG
-
EVTHRES
+
16
21
+
-
EVTEMP 20 6 18 22 1
19
8
MWEAK
LGATE
EVTEMP
+
RGATE
GATE
1
6
-
18
22
MMED
IT 8 17 1
9
20
MSTRO
8
RLGATE
LDRAIN 2 5 1e-9
LGATE 1 9 2.6e-9
LSOURCE 3 7 1.1e-9
LSOURCE
CIN
SOURCE
3
7
KGATE LSOURCE LGATE 0.0085
RSOURCE
RLSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S2A
S2B
RBREAK
12
15
13
14
13
17
18
8
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.94e-3
RGATE 9 20 0.36
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
-
S1B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*400),3))}
.MODEL DBODYMOD D (IS = 2.95e-12 RS = 2.6e-3 TRS1 = 1.05e-3 TRS2 = 5.0e-7 CJO = 5.19e-9 TT = 5.9e-8 M = 0.55)
.MODEL DBREAKMOD D (RS = 1.65e-1 IKF = 30 TRS1 = 1.15e-4 TRS2 = 2.27e-6)
.MODEL DPLCAPMOD D (CJO = 5.40e-9 IS = 1e-30 N=1 M = 0.88 )
.MODEL MMEDMOD NMOS (VTO = 3.29 KP = 5.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.36)
.MODEL MSTROMOD NMOS (VTO = 3.83 KP = 123 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.90 KP =0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL RBREAKMOD RES (TC1 = 1.15e-3 TC2 = 2.0e-7)
.MODEL RDRAINMOD RES (TC1 = 1.37e-2 TC2 = 3.85e-5)
.MODEL RSLCMOD RES (TC1 = 1.45e-4 TC2 = 2.11e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -3.7e-3 TC2 = -1.6e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.4e-3 TC2 = 7e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.9 VOFF= -3.9)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.9 VOFF= -6.9)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.99 VOFF= 2.39)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.39 VOFF= -2.99)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
HUF75344G3, HUF75344P3, HUF75344S3S
SABER Electrical Model
REV 3 February 1999
template huf75344p3 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 2.95e-12, cjo = 5.19e-9, tt = 5.90e-8, m = 0.55)
d..model dbreakmod = ()
LDRAIN
RLDRAIN
RDBODY
DPLCAP
5
DRAIN
2
d..model dplcapmod = (cjo = 5.40e-9, is = 1e-30, n = 1, m = 0.88)
m..model mmedmod = (type=_n, vto = 3.29, kp = 5.5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.83, kp = 123, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.90, kp = 0.04, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.9, voff = -3.9)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.9, voff = -6.9)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2.99, voff = 2.39)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.39, voff = -2.99)
10
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
ISCL
50
-
c.ca n12 n8 = 4.9e-9
c.cb n15 n14 = 4.75e-9
71
RDRAIN
6
8
ESG
c.cin n6 n8 = 2.85e-9
EVTHRES
+
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
+
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
DBODY
RGATE
GATE
1
6
-
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
-
RLGATE
i.it n8 n17 = 1
LSOURCE
CIN
SOURCE
3
7
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.6e-9
l.lsource n3 n7 = 1.1e-9
RSOURCE
RLSOURCE
k.kl i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085
S1A
S2A
14
13
RBREAK
12
15
13
17
18
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
8
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = 2e-7
res.rdbody n71 n5 = 2.6e-3, tc1 = 1.05e-3, tc2 = 5e-7
res.rdbreak n72 n5 = 1.65e-1, tc1 = 1.15e-4, tc2 = 2.27e-6
res.rdrain n50 n16 = 1.94e-3, tc1 = 1.37e-2, tc2 = 3.85e-5
res.rgate n9 n20 = 0.36
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
res.rldrain n2 n5 = 10
RVTHRES
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e-6, tc1 = 1.45e-4, tc2 = 2.11e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.5e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 7e-7
res.rvthres n22 n8 = 1, tc1 = -3.7e-3, tc2 = -1.6e-5
spe.ebreak n11 n7 n17 n18 = 59.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/400))** 3))
}
}
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
HUF75344G3, HUF75344P3, HUF75344S3S
SPICE Thermal Model
JUNCTION
th
REV 5 February 1999
HUF75344
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM1 th 6 5.0e-3
CTHERM2 6 5 1.0e-2
CTHERM3 5 4 1.3e-2
CTHERM4 4 3 1.5e-2
CTHERM5 3 2 2.2e-2
CTHERM6 2 tl 8.5e-2
6
RTHERM1 th 6 6.0e-4
RTHERM2 6 5 3.5e-3
RTHERM3 5 4 2.5e-2
RTHERM4 4 3 4.8e-2
RTHERM5 3 2 1.6e-1
RTHERM6 2 tl 1.8e-1
5
SABER Thermal Model
SABER thermal model HUF75344
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-3
ctherm.ctherm2 6 5 = 1.0e-2
ctherm.ctherm3 5 4 = 1.3e-2
ctherm.ctherm4 4 3 = 1.5e-2
ctherm.ctherm5 3 2 = 2.2e-2
ctherm.ctherm6 2 tl = 8.5e-2
rtherm.rtherm1 th 6 = 6.0e-4
rtherm.rtherm2 6 5 = 3.5e-3
rtherm.rtherm3 5 4 = 2.5e-2
rtherm.rtherm4 4 3 = 4.8e-2
rtherm.rtherm5 3 2 = 1.6e-1
rtherm.rtherm6 2 tl = 1.8e-1
}
tl
CASE
©2001 Fairchild Semiconductor Corporation
HUF75344G3, HUF75344P3, HUF75344S3S Rev. B1
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SuperSOT™-6
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SyncFET™
FASTr™
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E2CMOSTM
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FACT Quiet Series™
FAST â
POP™
HiSeC™
Power247™
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I2C™
ISOPLANAR™
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2. A critical component is any component of a life
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be reasonably expected to cause the failure of the life
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
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The datasheet is printed for reference information only.
Rev. H7
相关型号：
HUF75344G3_NL
Power Field-Effect Transistor, 75A I(D), 55V, 0.008ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-247, TO-247, 3 PIN
FAIRCHILD
HUF75344S3
Power Field-Effect Transistor, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA
FAIRCHILD
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