HCPL-3700SD [FAIRCHILD]
AC/DC TO LOGIC INTERFACE OPTOCOUPLER; AC / DC到逻辑接口光电耦合器
| 型号： | HCPL-3700SD |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | AC/DC TO LOGIC INTERFACE OPTOCOUPLER |
| 文件： | 总11页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
DESCRIPTION
The HCPL-3700 voltage/current threshold detection optocoupler consists of an
AlGaAs LED connected to a threshold sensing input buffer IC which are optically
coupled to a high gain darlington output. The input buffer chip is capable of con-
trolling threshold levels over a wide range of input voltages with a single resistor.
The output is TTL and CMOS compatible.
8
1
FEATURES
•
•
•
•
AC or DC input
Programmable sense voltage
Logic level compatibility
Threshold guaranteed over temperature
(0°C to 70°C)
Optoplanar™ construction for high
common mode immunity
UL recognized (file # E90700)
TRUTH TABLE
(Positive Logic)
8
8
Input
Output
•
•
1
1
H
L
L
H
APPLICATIONS
A 0.1 µF bypass capacitor
must be connected between
pins 8 and 5.
•
•
•
•
•
•
Low voltage detection
5 V to 240 V AC/DC voltage sensing
Relay contact monitor
Current sensing
AC
DC+
DC-
AC
1
2
3
4
8
7
6
5
VCC
NC
Microprocessor Interface
Industrial controls
RX
AC/DC
POWER
LOGIC
HCPL-3700
VO
GND
GND 1
GND 2
ABSOLUTE MAXIMUM RATINGS (No derating required up to 70°C)
Parameter
Symbol
Value
Units
Storage Temperature
Operating Temperature
Lead Solder Temperature
T
-55 to +125
-40 to +85
°C
°C
°C
STG
T
OPR
T
260 for 10 sec
50 (MAX)
SOL
EMITTER
Average
Surge
Input Current
3 ms, 120 Hz Pulse Rate
10 µs, 120 Hz Pulse Rate
I
140 (MAX)
500 (MAX)
-0.5 (MIN)
230 (MAX)
305 (MAX)
mA
IN
Transient
Input Voltage (Pins 2-3)
Input Power Dissipation
Total Package Power Dissipation
DETECTOR
V
P
V
IN
(Note 1)
mW
mW
IN
(Note 2)
P
T
Output Current (Average)
Supply Voltage (Pins 8-5)
Output Voltage (Pins 6-5)
Output Power Dissipation
(Note 3)
I
30 (MAX)
-0.5 to 20
-0.5 to 20
210 (MAX)
mA
V
O
V
CC
V
V
O
(Note 4)
P
mW
O
© 2003 Fairchild Semiconductor Corporation
Page 1 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
ELECTRICAL CHARACTERISTICS (T = 0°C to 70°C Unless otherwise specified)
A
Parameter
Test Conditions Symbol
, V = 4.5 V)
Min
Typ
Max
Unit
(V = V
I
TH+
1.96
1.00
2.4
1.2
3.11
1.62
mA
mA
IN
TH+ CC
Input Threshold Current
(V = 0.4 V, I ≥ 4.2 mA) (Note 5)
I
TH-
O
O
(V = V - V , Pins 1 & 4 Open)
IN
2
3
(V = 4.5 V, V = 0.4 V)
V
TH+
3.35
2.01
3.8
2.5
4.05
2.86
V
V
CC
O
(Note 5) (I ≥ 4.2 mA)
DC
(Pins 2,3)
O
(V = V - V , Pins 1 & 4 Open)
IN
2
3
(V = 4.5 V, V = 2.4 V)
V
TH-
CC
O
(Note 5) (I ≥ 100 µA)
O
Input
Threshold
Voltage
|V = V - V |
IN
1
4
(Pins 2 & 3 Open)
(V = 4.5 V, V = 0.4 V)
V
4.23
2.87
5.0
3.7
5.50
4.20
V
V
TH+
CC
O
(Note 5) (I ≥ 4.2 mA)
AC
O
(Pins 1,4)
|V = |V - V |
IN
1
4
(Pins 2 & 3 Open)
(V = 4.5 V, V = 2.4 V)
V
TH-
CC
O
(Note 5) (I ≤ 100 µA)
O
(I
= I
- I
)
)
I
1.2
1.3
mA
V
HYS
TH+ TH-
HYS
Hysteresis
(V
= V
- V
V
HYS
HYS
TH+
TH-
(V
(V
= V - V , V = GND)
2 3 3
IHC1
(I = 10 mA, Pins 1 & 4
V
5.4
6.1
6.3
7.0
6.6
V
V
IN
IHC1
Connected to Pin 3)
(V
= |V - V |)
1 4
IHC2
(|I | = 10 mA)
V
V
7.3
IN
IHC2
Input Clamp Voltage
(Pins 2 & 3 Open)
= V - V , V = GND)
IHC3
2
3
3
12.5
-0.75
3.7
13.4
V
V
IHC3
(I = 15 mA; Pins 1 & 4 Open)
IN
(V
= V - V , V = GND)
2 3 3
ILC
V
ILC
(I = -10 mA)
IN
(V = V - V = 5.0 V)
IN
2
3
Input Current
I
3.0
4.4
mA
IN
(Pins 1 & 4 Open)
(I = 3 mA)
V
V
0.65
0.65
V
V
Bridge Diode
Forward Voltage
IN
D1,2
(I = 3 mA)
IN
D3,4
(V = 4.5 V; I = 4.2 mA)
CC
OL
Logic Low Output Voltage
Logic High Output Current
Logic Low Supply Current
Logic High Supply Current
Input Capacitance
V
0.04
0.4
100
4
V
OL
(Note 5)
(Note 5) (V = V = 18 V)
I
µA
mA
µA
pF
OH
CC
OH
(V - V = 5.0 V; V = Open)
2
3
O
I
1.0
0.01
50
CCL
CCH
(V = 5 V)
CC
(V = 18 V; V = Open)
I
4
CC
O
(f = 1 MHz; V = 0V)
IN
C
IN
(Pins 2 & 3, Pins 1 & 4 Open)
© 2003 Fairchild Semiconductor Corporation
Page 2 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Units
Supply Voltage
V
2
0
0
18
70
4
V
CC
Operating Temperature
Operating Frequency
T
°C
A
f
kHz
SWITCHING CHARACTERISTICS (T = 25°C, V = 5 V Unless otherwise specified)
A
CC
AC Characteristics
Test Conditions Symbol
Min
Typ
Max
Unit
Propagation Delay Time
(to Output Low Level)
(R = 4.7 kΩ, C = 30 pF)
L L
T
6.0
15
µs
µs
PHL
PLH
(Note 6)
Propagation Delay Time
(to Output High Level)
(R = 4.7 kΩ, C = 30 pF)
L
L
T
25.0
40
(Note 6)
Output Rise Time (10-90%)
Output Fall Time (90-10%)
(R = 4.7 kΩ, C = 30 pF)
t
45
µs
µs
L
L
r
(R = 4.7 kΩ, C = 30 pF)
t
0.5
L
L
f
(I = 0 mA, R = 4.7 kΩ)
IN
L
Common Mode Transient Immunity
(at Output High Level)
(V
= 2.0 V, V
= 1400 V)
|CM |
4000
600
V/µs
V/µs
O min
CM
H
(Notes 7,8)
(I = 3.11 mA,R = 4.7 kΩ)
N
L
Common Mode Transient Immunity
(at Output Low Level)
(V
= 0.8 V, V
= 140 V)
|CM |
L
O max
CM
(Notes 7,8)
PACKAGE CHARACTERISTICS (T = 0°C to 70°C Unless otherwise specified)
A
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Unit
(Relative humidity < 50%)
Withstand Insulation Voltage
(T = 25°C, t = 1 min)
V
2500
V
RMS
A
ISO
(Notes 9,10)
12
Resistance (input to output)
Capacitance (input to output)
(Note 9) (V = 500 Vdc)
R
C
10
Ω
IO
I-O
(f = 1 MHz, V = 0 Vdc)
0.6
pF
IO
I-O
© 2003 Fairchild Semiconductor Corporation
Page 3 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
NOTES
1. Derate linearly above 70°C free-air temperature at a rate of 1.8 mW/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 2.5 mW/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 1.9 mW/°C.
5. Logic low output level at pin 6 occurs when V ≥V
and when V >V
once V exceeds V
. Logic high output level at pin
IN
TH+
IN
TH-
IN
TH+
6 occurs when V ≤V
and when V <V
once V decreases below V
.
IN
TH-
IN
TH+
IN
TH-
6. T
propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 µs rise time) to the 1.5 V
PHL
level on the leading edge of the output pulse.T
propagation delay is measured on the trailing edges of the input and output
PLH
pulse. (Refer to Fig. 9)
7. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV /dt on the leading edge of the
cm
common mode pulse signal V , to assure that the output will remain in a logic high state (i.e., V >2.0 V). Common mode
CM
O
transient immunity in logic low level is the maximum tolerable (negative) dV /dt on the trailing edge of the common mode
cm
pulse signal, V , to assure that the output will remain in a logic low state (i.e., V <0.8 V). (Refer to Fig.10)
CM
O
8. In applications where dV /dt may exceed 50,000 V/µs (Such as static discharge), a series resistor, R , should be included to
cm
CC
protect the detector chip from destructive surge currents. The recommended value for R is 240 V per volt of allowable drop
CC
in V (between pin 8 and V ) with a minimum value of 240 Ω.
CC
CC
9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
10. The 2500 V /1 min. capability is validated by a 3.0 kV /1 sec. dielectric voltage withstand test.
RMS
RMS
11. AC voltage is instantaneous voltage for V
& V
.
TH+
TH-
12. All typicals at T = 25°C, V = 5 V unless otherwise specified.
A
CC
© 2003 Fairchild Semiconductor Corporation
Page 4 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
TYPICAL PERFORMANCE CURVES
Fig. 1 Logic Low Supply Current vs. Operating Supply Voltage
Fig. 2 Input Current vs. Input Voltage
4.0
50
DC (Pins 1,2 shorted together
pins 3,4 shorted together)
45
40
35
30
25
20
15
10
5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
DC (Pins 1 & 4 Open)
0
AC (pins 2 & 3 Open)
-5
-10
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
V
- OPERATING SUPPLY VOLTAGE (V)
V
- INPUT VOLTAGE (V)
CC
IN
Fig. 4 Current Threshold/Voltage Threshold
vs.Temperature
Fig. 3 Input Current/Low Level Output Voltage
vs.Temperature
4.2
3.2
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
120
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
110
100
90
80
70
60
50
40
30
20
10
0
VTH+
ITH+
IIN
VIN = 5.0 V
(PINS 2 and 3)
VCC = 5.0 V
VOL
VCC = 5.0 V
VTH-
ITH-
IOL = 4.2 mA
-40
-20
0
25
45
65
85
-40
-20
0
25
45
65
85
T
- TEMPERATURE (°C)
T
A
- TEMPERATURE (°C)
A
Fig. 5 Propagation Delay vs.Temperature
Fig. 6 Rise and Fall Time vs.Temperature
70
100
90
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
60
50
40
30
20
10
0
Tf
TPLH
TPHL
Tr
-60
-40
-20
0
20
40
60
80
100
-40
-20
0
25
45
65
85
T
- TEMPERATURE (°C)
T
A
- TEMPERATURE (°C)
A
© 2003 Fairchild Semiconductor Corporation
Page 5 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
Fig. 7 Logic High Supply Current
vs.Temperature
Fig. 8 External Threshold Characteristics V+/V- vs. Rx
300
1000
100
10
V- (AC)
V
V
IN
= 18 V
V+ (AC)
CC
250
200
= OPEN
= 0 mA
O
I
V+ (DC)
150
100
V- (DC)
50
0
1
-60
0
40
80
120
160
200
240
-40
-20
0
20
40
60
80
100
R
- EXTERNAL SERIES RESISTOR (KΩ)
T
- TEMPERATURE (°C)
X
A
© 2003 Fairchild Semiconductor Corporation
Page 6 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
+5V
5V
1
2
3
4
AC
VCC
8
7
6
5
2.5V
0V
Input
(VIN
)
Pulse
.1uf
bypass
RL
DC+
DC-
AC
Generator
tr = 5ns
ZO= 50Ω
tPHL
tPLH
Output
(VO
VO
)
VO
Output
(VO
90%
10%
90%
GND
)
1.5 V
VOL
10%
tf
tr
VIN
Pulse Amplitude = 50 V
Pulse Width = 1 ms
f = 100 Hz
T = Tf = 1.0 µs (10 - 90%)
r
Fig. 9. Switching Test Circuit
V
CMH
IIN
RCC*
V
CML
+5V
1
2
3
4
AC
VCC
8
7
6
5
A
B
.1uf
bypass
RL
DC+
DC-
AC
VCM
5V
5V
Output
VO
(VO
)
VFF
GND
VO
CMH
CL**
Switching Pos. (A)
IIN = 0 mA
VO (Min)
VCM
-
+
* SEE NOTE 8
Pulse Gen
VO (Max)
** CL IS 30 pF, WHICH INCLUDES PROBE
AND STRAY WIRING CAPACITANCE
Switching Pos. (B)
IIN = 3.11 mA
VO
VOL
CML
Fig. 10.Test Circuit for Common Mode Transient Immunity and Typical Waveforms
© 2003 Fairchild Semiconductor Corporation
Page 7 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
Package Dimensions (Through Hole)
Package Dimensions (Surface Mount)
0.390 (9.91)
0.370 (9.40)
PIN 1
ID.
PIN 1
ID.
0.270 (6.86)
0.250 (6.35)
0.270 (6.86)
0.250 (6.35)
0.390 (9.91)
0.370 (9.40)
0.300 (7.62)
TYP
0.070 (1.78)
0.045 (1.14)
0.070 (1.78)
0.045 (1.14)
0.020 (0.51)
MIN
0.020 (0.51) MIN
0.200 (5.08)
0.140 (3.55)
0.016 (0.41)
0.008 (0.20)
0.154 (3.90)
0.120 (3.05)
0.045 [1.14]
0.022 (0.56)
0.016 (0.41)
0.022 (0.56)
0.016 (0.41)
15° MAX
0.315 (8.00)
MIN
0.016 (0.40)
0.008 (0.20)
0.100 (2.54)
TYP
0.300 (7.62)
TYP
0.100 (2.54) TYP
0.405 (10.30)
MIN
Lead Coplanarity : 0.004 (0.10) MAX
NOTE
All dimensions are in inches (millimeters)
Package Dimensions (0.4"Lead Spacing)
PIN 1
ID.
0.270 (6.86)
0.250 (6.35)
0.390 (9.91)
0.370 (9.40)
0.070 (1.78)
0.045 (1.14)
0.004 (0.10) MIN
0.200 (5.08)
0.140 (3.55)
0.154 (3.90)
0.120 (3.05)
0.022 (0.56)
0.016 (0.41)
0° to 15°
0.016 (0.40)
0.008 (0.20)
0.400 (10.16)
TYP
0.100 (2.54) TYP
© 2003 Fairchild Semiconductor Corporation
Page 8 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
ORDERING INFORMATION
Order
Option
Entry
Description
Identifier
S
SD
W
.S
.SD
.W
Surface Mount Lead Bend
Surface Mount; Tape and reel
0.4” Lead Spacing
MARKING INFORMATION
1
2
3700
6
V XX YY T1
5
3
4
Definitions
1
2
Fairchild logo
Device number
VDE mark (Note: Only appears on parts ordered with VDE
option – See order entry table)
3
4
5
6
Two digit year code, e.g., ‘03’
Two digit work week ranging from ‘01’ to ‘53’
Assembly package code
© 2003 Fairchild Semiconductor Corporation
Page 9 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
QT Carrier Tape Specifications (“D”Taping Orientation)
12.0 0.1
4.0 0.1
Ø1.55 0.05
1.75 0.10
4.90 0.20
0.30 0.05
4.0 0.1
7.5 0.1
16.0 0.3
10.30 0.20
13.2 0.2
Ø1.6 0.1
0.1 MAX
10.30 0.20
User Direction of Feed
Reflow Profile
300
215C, 10–30 s
250
200
150
100
50
225C peak
Time above 183C, 60–150 sec
Ramp up = 3C/sec
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Time (Minute)
• Peak reflow temperature: 225C (package surface temperature)
• Time of temperature higher than 183C for 60–150 seconds
• One time soldering reflow is recommended
© 2003 Fairchild Semiconductor Corporation
Page 10 of 11
11/8/04
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
© 2003 Fairchild Semiconductor Corporation
Page 11 of 11
11/8/04
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