FSUSB30MUX_12 [FAIRCHILD]
Low-Power, Two-Port, High-Speed USB 2.0 (480Mbps) Switch; 低功耗双端口，高速USB 2.0 （ 480Mbps的）开关
| 型号： | FSUSB30MUX_12 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low-Power, Two-Port, High-Speed USB 2.0 (480Mbps) Switch |
| 文件： | 总18页 (文件大小：739K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Click to see this datasheet
in Simplified Chinese!
February 2012
FSUSB30
Low-Power, Two-Port, High-Speed USB 2.0 (480Mbps)
Switch
Features
Description
?
?
?
Low On Capacitance: 3.7pF (Typical)
Low On Resistance: 6.5 (Typical)
The FSUSB30 is a low-power, two-port, high-speed USB
2.0 switch. Configured as a double-pole double-throw
(DPDT) switch, it is optimized for switching between two
high-speed (480Mbps) sources or a Hi-Speed and Full-
Speed (12Mbps) source. The FSUSB30 is compatible
with the requirements of USB2.0 and features an
extremely low on capacitance (CON) of 3.7pF. The wide
bandwidth of this device (720MHz), exceeds the band-
width needed to pass the third harmonic, resulting in sig-
nals with minimum edge and phase distortion. Superior
channel-to-channel crosstalk minimizes interference.
Low Power Consumption: 1µA (Maximum)
– 10µA Maximum ICCT over an Expanded Control
Voltage Range (VIN = 2.6V, VCC = 4.3V)
?
?
?
Wide -3dB Bandwidth, >720MHz
8KV ESD Protection
Power-Off Protection when VCC = 0V; D+/D- Pins can
Tolerate up to 5.5V
?
Packaged in:
– 10-lead MicroPak™ (1.6 x 2.1mm)
– 14-lead DQFN
– 10-lead MSOP
The FSUSB30 contains special circuitry on the D+/D-
pins which allows the device to withstand an overvoltage
condition when powered off. This device is also designed
to minimize current consumption even when the control
voltage applied to the S pin, is lower than the supply volt-
age (VCC). This feature is especially valuable to ultra-
portable applications such as cell phones, allowing for
direct interface with the general purpose I/Os of the
baseband processor. Other applications include switch-
ing and connector sharing in portable cell phones, PDAs,
digital cameras, printers, and notebook computers.
– 10-lead UMLP (1.4 x 1.8mm)
Applications
?
Cell phone, PDA, Digital Camera, and Notebook LCD
Monitor, TV, and Set-top Box
Related Application Notes
?
AN-6022 Using the FSUSB30 / FSUSB31 to Comply
with USB 2.0 Fault Condition Requirements
Ordering Information
Order
Package ProductCode
Number
Number
Top Mark
Package Description
FSUSB30L10X
MAC010A
FJ
10-Lead MicroPak, 1.6 x 2.1mm
14-Terminal Depopulated Quad Very-Thin Flat Pack
No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
FSUSB30BQX
MLP014A
USB30
10-Lead Molded Small Outline Package (MSOP), JEDEC MO-
187, 3.0mm Wide
FSUSB30MUX
FSUSB30UMX
MUA10A
MLP010A
FSUSB30
GJ
10-Lead, Quad, Ultrathin, MLP (UMLP) 1.4 x 1.8mm
FSUSB30
VCC
1D+
1D–
D+
D–
USB2.0
Controller
USB
Set Top Box
Connector
(STB) CPU
or
DSP
Processor
2D+
2D–
DVR or
Mass Storage
Controller
Control
S
OE
Figure 1. Typical Application
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.7
www.fairchildsemi.com
Connection Diagrams
Analog Symbol
Pad Assignments for MicroPak
HSD1+
HSD2+
D+
D–
9
8
2
7
3
6
HSD1–
HSD2–
VCC 10
1
5
4
GND
S
Control
OE
(Top View)
Pin Descriptions
Pad Assignments for DQFN
NC VCC
Pin Name
Description
Bus Switch Enable
Select Input
OE
1
14
S
D+, D, HSDn+, HSDn
NC
2
3
4
5
6
13
12
11
10
9
S
HSD1+
NC
OE
Data Ports
HSD1–
NC
No Connect
HSD2+
D+
HSD2–
D–
Truth Table
7
8
S
Function
OE
GND NC
(Top Through View)
X
HIGH
LOW
LOW
Disconnect
LOW
HIGH
D+, D = HSD1n
D+, D = HSD2n
Pin Assignment for MSOP
1
10
S
VCC
HSD1+
2
3
4
9
8
7
OE
HSD2+
D+
HSD1–
HSD2–
D–
5
6
GND
(Top Through View)
Pad Assignments for µMLP
7
1
6
2
5
4
3
8
9
D–
OE
VCC
GND
D+
10
Sel
(Top Through View)
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
Parameter
Minimum
-0.5
Maximum
+5.5
Unit
V
VCC
Supply Voltage
VCNTRL DC Input Voltage(1)
-0.5
VCC
V
HSDnX
0.5
VCC
V
VSW
DC Switch Voltage(1)
D+,D- when VCC > 0
D+,D- when VCC = 0
0.5
VCC
V
-0.50
-50
VCC
V
IIK
DC Input Diode Current
DC Output Current
mA
mA
°C
kV
kV
IOUT
TSTG
50
+150
8
Storage Temperature
-65
All Pins
ESD
Human Body Model
I/O to GND
8
Note:
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.(2)
Symbol
VCC
Parameter
Minimum
Maximum
4.3
Unit
V
Supply Voltage
3.0
0
VIN
Control Input Voltage
VCC
V
VSW
TA
Switch Input Voltage
0
VCC
V
Operating Temperature
Thermal Resistance, 10 MicroPak
-40
+85
°C
JA
250
°C/W
Note:
2. Control input must be held HIGH or LOW and it must not float.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSUSB30 Rev. 1.1.6
3
DC Electrical Characteristics
All typical values are at 25°C unless otherwise specified.
TA = 40°C to +85°C
VCC (V)
Symbol
VIK
Parameter
Clamp Diode Voltage
Input Voltage HIGH
Conditions
IIN = -18mA
Unit
Min. Typ. Max.
3.0
-1.2
V
V
3.0 to 3.6 1.3
VIH
4.3
3.0 to 3.6
4.3
1.7
V
0.5
0.7
1.0
2.0
V
VIL
Input Voltage LOW
V
IIN
Control Input Leakage
OFF State Leakage
VSW = 0.0V to VCC
4.3
-1.0
-2.0
µA
µA
IOZ
0 Dn, HSD1n, HSD2n VCC
4.3
Power OFF Leakage
Current (D+, D–)
IOFF
VSW = 0V to 4.3V, VCC = 0V
0
-2.0
2.0
µA
VSW = 0.4V, ION = -8mA
SW = 0V, IO = 30mA at 25°C
3.0
3.6
3.0
6.5
10.0
7.0
RON
Switch On Resistance(3)
V
(4)
RON
Delta RON
VSW = 0.4V, ION = -8mA
0.35
2.0
VSW = 0.0V - 1.0V,
ION = -8mA
R
ON Flatness RON Flatness(3)
3.0
4.3
4.3
VCNTRL = 0.0V or VCC
IOUT = 0
,
ICC
Quiescent Supply Current
1.0
µA
µA
Increase in ICC Current
per Control Voltage
ICCT
VCNTRL (control input) = 2.6V
10.0
Notes:
3. Measured by the voltage drop between Dn, HSD1n, HSD2n pins at the indicated current through the switch.
On resistance is determined by the lower of the voltage on the two ports.
4.Guaranteed by characterization.
AC Electrical Characteristics
All typical values are for VCC = 3.3V at 25°C unless otherwise specified.
TA = 40°C to +85°C
Figure
Number
VCC (V)
Symbol
Parameter
Conditions
Unit
Min. Typ. Max.
Turn-On Time S,
OE to Output
HD1 , HD2 = 0.8V,
n n
t
3.0 to 3.6
3.0 to 3.6
3.3
13
12
30
25
ns
ns
ns
ns
dB
dB
Figure 9
Figure 9
ON
R = 50, C = 5pF
L
L
Turn-Off Time S,
OE to Output
HD1 , HD2 = 0.8V,
n n
t
OFF
R = 50, C = 5pF
L
L
Figure 7
Figure 8
(4)
t
Propagation Delay
R = 50, C = 5pF
0.25
PD
L
L
R = 50, C = 5pF,
L
L
t
Break-Before-Make
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
2.0
6.5
Figure 10
Figure 13
Figure 14
BBM
V
= 0.8V
IN
Off Isolation
(Non-Adjacent)
O
f = 240MHz, R = 50
-30
-45
IRR
T
Non-Adjacent Channel
Crosstalk
Xtalk
BW
R = 50, f = 240MHz
T
R = 50, C = 0pF
720
550
T
L
3dB Bandwidth
3.0 to 3.6
MHz Figure 12
R = 50, C = 5pF
T
L
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
4
USB Hi-Speed Related AC Electrical Characteristics
TA = 40°C to +85°C
Figure
Number
VCC (V)
3.0 to 3.6
3.0 to 3.6
Symbol
Parameter
Conditions
Units
Min. Typ. Max.
Channel-to-Channel
Figure 7
Figure 11
t
R = 50, C = 5pF
50
ps
(5)
SK(O)
L
L
Skew
Skew of Opposite
Transitions of the
Figure 7
Figure 11
t
R = 50, C = 5pF
20
ps
ps
SK(P)
L
L
(5)
Same Output
R = 50, C = 5pF,
L
L
(5)
t
Total Jitter
t
= t = 500ps at 480 Mbps 3.0 to 3.6
200
J
R
F
15
(PRBS = 2 1)
Note:
5. Guaranteed by characterization.
Capacitance
TA = 40°C to +85°C
Figure
Number
Symbol
Parameter
Conditions
Units
Min.
Typ.
1.5
Max.
C
Control Pin Input Capacitance
V
V
V
= 0V
pF
pF
pF
Figure 16
Figure 15
Figure 16
IN
CC
CC
CC
C
D1 , D2 , Dn On Capacitance
= 3.3, OE = 0V
and OE = 3.3
3.7
ON
n
n
C
D1 , D2 Off Capacitance
2.5
OFF
n
n
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
5
Typical Characteristics
Frequency Response
0
-1
-2
-3
-4
-5
-6
-7
-8
1
10
100
1000
10000
Frequency (MHz)
C
L = 0pF, VCC = 3.3V
Figure 2. Gain vs. Frequency
Frequency Response
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
1
10
100
1000
Frequency (MHz)
Figure 3. Off Isolation
Frequency Response
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
1
10
100
1000
VCC = 3.3V
Frequency (MHz)
Figure 4. Crosstalk
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
6
Test Diagrams
VON
IDn(OFF)
NC
HSDn
VIN
A
Dn
VIN
ION
GND
Select
GND
Select
VS = 0 to VCC
RON = VON / ION
GND
VS = 0 or VCC
Each switch port is tested separately.
Figure 5. On Resistance
Figure 6. Off Leakage
tFALL = 500ps
tRISE = 500ps
800mV
HSDn
D+, D–
VIN
90%
50%
90%
50%
Input: HSDn+,
VOUT
RL
CL
HSDn–
400mV
RS
GND
10%
10%
GND
VSel
GND
VOH
Output: D+, D–
50%
50%
RL, RS, and CL are functions of the application environment
(see AC Electrical tables for specific values).
VOL
tPLH
tPHL
CL includes test fixture and stray capacitance.
Figure 7. AC Test Circuit Load
Figure 8. Switch Propagation Delay Waveforms
tFALL = 2.5ns
tRISE = 2.5ns
VCC
90%
/2
90%
Input – S, OE
V
V
/2
CC
CC
10%
10%
GND
VOH
90%
90%
Output – VOUT
VOL
tON
tOFF
Figure 9. Turn-On / Turn-Off Waveform
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
7
VCC
VCC
HSDn
HSDn
VO
VOUT
CL*
VCC
0V
D+, D–
Control
Input
50%
RL
tR = tF = 2.5ns (10–90%)
S
VOUT
Control
Input
GND
0.9 x VOUT
tD
*CL includes test fixture and stray capacitance.
Figure 10. Break-Before-Make (tBBM
)
tFALL = 500ps
tRISE = 500ps
800mV
90%
50%
90%
50%
Input: D+, D–
10%
10%
400mV
t
FALL = 500ps
tRISE = 500ps
800mV
VOH
Output1: HSD1+
HSD1–
90%
50%
90%
50%
50%
50%
Input: HSDn+
HSDn–
VOL
10%
10%
tPLH1
tPHL1
400mV
VOH
VOH
50%
50%
50%
50%
Output1: D2+, D2–
Output: D+, D–
VOL
VOL
tPLH
SK(P) = | tPHL – tPLH
Pulse Skew, TSK(P)
tPHL
tPLH2
tPHL2
T
|
T
SK(O) = | tPLH1 – tPLH2 | or | tPHL1 – tPHL2
|
Output Skew, TSK(OUT)
Figure 11. Switch Skew Tests
Network Analyzer
FSUSB30
RS
VIN
VS
GND
GND
V
Sel
GND
VOUT
RT
GND
RS and RT are functions of the application environment
(See AC Electrical Tables for specific values).
GND
Figure 12. Bandwidth
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
8
Network Analyzer
FSUSB30
RS
VIN
VS
GND
GND
RT
GND
V
Sel
GND
GND
VOUT
RT
GND
OFF-Isolation = 20 Log (VOUT /VIN
)
Figure 13. Channel Off Isolation
NC
Network Analyzer
FSUSB30
RS
VIN
VS
GND
GND
V
Sel
RT
GND
GND
RT
VOUT
GND
RS and RT are functions of the application environment
(50, 75 or 100Ω)
GND
Crosstalk = 20 Log (VOUT / VIN)
Figure 14. Non-Adjacent Channel-to-Channel Crosstalk
FSUSB30
FSUSB30
D1n, D2n
Dn
Dn
Capacitance
Meter
S
S
Capacitance
VSel = 0 or VCC
Meter
VSel = 0 or VCC
f = 240MHz
f = 240MHz
D1n, D2n
Figure 15. Channel On Capacitance
Figure 16. Channel Off Capacitance
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
9
Application Guidance: Meeting USB 2.0 Vbus Short Requirements
In section 7.1.1 of the USB 2.0 specification, it notes that
USB devices must be able to withstand a Vbus short to
D+ or D- when the USB devices is either powered off or
powered on. The FSUSB30 can be successfully config-
ured to meet both these requirements.
Power-On Protection
The USB 2.0 specification also notes that the USB
device should be capable of withstanding a Vbus short
during transmission of data. Fairchild recommends add-
ing a 100 series resister between the switch VCC pin
and supply rail to protect against this case. This modifi-
cation works by limiting current flow back into the VCC
rail during the over-voltage event so current remains
within the safe operating range. In this application, the
switch passes the full 5.25V input signal through to the
selected output, while maintaining specified off isolation
on the un-selected pins.
Power-Off Protection
For a Vbus short circuit, the switch is expected to with-
stand such a condition for at least 24 hours. The
FSUSB30 has specially designed circuitry which pre-
vents unintended signal bleed through as well as guar-
anteed system reliability during a power-down, over-
voltage condition. The protection has been added to the
common pins (D+, D-).
VCC= 3.6 V
100 Ohms
HSD+
HSD+
D+ = 5.25V
D- = 5.25V
FSUSB30
HSD-
HSD-
Figure 17. Adding 100 resistor in series with the VCC supply allows the FSUSB30 to withstand a
Vbus short when powered up
For more information, see Applications Note AN-6022 Using the FSUSB30 to Comply with USB 2.0 Fault
Condition Requirements at www.fairchildsemi.com
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
10
Tape and Reel Specifications
Tape Format for DQFN
Package
Designator
Tape
Section
Number
Cavities
Cavity
Status
Cover Tape
Status
Leader (Start End)
Carrier
125 (typ)
2500/3000
75 (typ)
Empty
Filled
Sealed
Sealed
Sealed
BQX
Trailer (Hub End)
Empty
Tape Dimensions
Dimenions are in millimeters unless otherwise specified.
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
11
Reel Dimensions for DQFN
Dimensions are in inches (millimeters) unless otherwise specified.
Tape Size
A
B
C
D
N
W1
W2
13.0
(330)
0.059
(1.50)
0.512
(13.00)
0.795
(20.20)
7.008
(178)
0.488
(12.4)
0.724
(18.4)
(12mm)
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
12
Tape Dimensions for MSOP
Dimensions are in inches (millimeters) unless otherwise specified.
Reel Dimensions for MSOP
Dimensions are in inches (millimeters) unless otherwise specified
Tape Size
A
B
C
D
N
W1
W2
W3
13
(330)
0.059
(1.5)
0.512
(13)
0.795
(20.2)
7.008
(178)
0.448
(12.4)
0.724
(18.4)
0.468-0.606
(11.9 -15.4)
(12mm)
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.7
www.fairchildsemi.com
13
Physical Dimensions
0.10 C
2.10
A
2X
1.62
B
KEEPOUT ZONE, NO TRACES
OR VIAS ALLOWED
(0.11)
0.56
1.12
1.60
PIN1 IDENT IS
2X LONGER THAN
OTHER LINES
0.10 C
10X
(0.35)
(0.25)
2X
10X
0.50
TOP VIEW
RECOMMENDED LAND PATTERN
0.55 MAX
0.05 C
0.05 C
0.05
0.00
(0.20)
C
0.35
0.25
SIDE VIEW
(0.15)
D
DETAIL A
(0.36)
0.35
0.25
0.65
0.55
0.35
0.25
DETAIL A 2X SCALE
1
4
0.56
NOTES:
10
5
A. PACKAGE CONFORMS TO JEDEC
REGISTRATION MO-255, VARIATION UABD .
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. PRESENCE OF CENTER PAD IS PACKAGE
SUPPLIER DEPENDENT. IF PRESENT IT
IS NOT INTENDED TO BE SOLDERED AND
HAS A BLACK OXIDE FINISH.
(0.29)
0.35
6
9
9X
0.25
0.50
0.25
0.15
9X
1.62
0.10
0.05
C
C
A B
ALL FEATURES
E. DRAWING FILENAME: MKT-MAC10Arev5.
BOTTOM VIEW
Figure 17. 10-Lead MicroPak, 1.6 x 2.1mm
For tape and reel specifications, visit Fairchild’s website: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.7
www.fairchildsemi.com
14
Physical Dimensions
Figure 18. 14-Terminal De-populated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner with-
out notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain
the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
15
Physical Dimensions
Figure 19. 10-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.6
www.fairchildsemi.com
16
Physical Dimensions
(9X)
0.563
1.70
0.15 C
2X
1.40
A
B
0.663
1
2.10
1.80
PIN#1 IDENT
0.40
0.15 C
0.225
(10X)
TOP VIEW
2X
RECOMMENDED
LAND PATTERN
0.55 MAX.
0.152
0.10 C
0.08 C
9X
0.45
1.45
0.55
0.40
SEATING
PLANE
C
0.05
SIDE VIEW
1.85
0.35
(9X)
0.45
0.225
(10X)
3
OPTIONAL MINIMIAL
TOE LAND PATTERN
0.40
6
DETAIL A
1
NOTES:
PIN#1 IDENT
A. PACKAGE DOES NOT FULLY CONFORM TO
0.15
0.25
10
JEDEC STANDARD.
(10X)
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
0.10 C A B
0.05 C
BOTTOM VIEW
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP10Arev3.
0.55
0.45
0.10
0.10
0.10
DETAIL A
SCALE : 2X
PACKAGE
EDGE
LEAD
LEAD
OPTION 2
SCALE : 2X
OPTION 1
SCALE : 2X
Figure 20. 10-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 1.4 x 1.8mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specif-
ically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.7
www.fairchildsemi.com
17
© 2006 Fairchild Semiconductor Corporation
FSUSB30 Rev. 1.1.7
www.fairchildsemi.com
18
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