FST3126MTC [FAIRCHILD]
Quad Bus Switch; 四总线开关
| 型号： | FST3126MTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Quad Bus Switch |
| 文件： | 总6页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1997
Revised December 1999
FST3126
Quad Bus Switch
General Description
Features
The Fairchild Switch FST3126 provides four high-speed
CMOS TTL-compatible bus switches. The low on resis-
tance of the switch allows inputs to be connected to out-
puts without adding propagation delay or generating
additional ground bounce noise.
■ 4Ω switch connection between two ports.
■ Minimal propagation delay through the switch.
■ Low lCC
.
■ Zero bounce in flow-through mode.
■ Control inputs compatible with TTL level.
The device is organized as four 1-bit switches with sepa-
rate OE inputs. When OE is HIGH, the switch is ON and
Port A is connected to Port B. When OE is LOW, the switch
is OPEN and a high-impedance state exists between the
two ports.
Ordering Code:
Order Number
FST3126M
Package Number
M14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
FST3126QSC
FST3126MTC
MQA16
MTC14
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagrams
Pin Assignment for SOIC and TSSOP
Pin Assignment for QSOP
Pin Descriptions
Truth Table
Pin Name
Description
Inputs
Inputs/Outputs
OE1, OE2, OE3, OE4 Bus Switch Enables
OE
L
A,B
Z
1A, 2A, 3A, 4A
1B, 2B, 3B, 4B
NC
Bus A
Bus B
H
A = B
Not Connected
© 1999 Fairchild Semiconductor Corporation
DS500044
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
Supply Voltage (VCC
)
−0.5V to +7.0V
−0.5V to +7.0V
−0.5V to +7.0V
−50mA
DC Switch Voltage (VS)
Power Supply Operating (VCC)
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
DC Input Voltage (VIN) (Note 2)
DC Input Diode Current (lIK) VIN<0V
DC Output (IOUT) Sink Current
Input Voltage (VIN
)
Output Voltage (VOUT
)
128mA
Input Rise and Fall Time (tr, tf)
Switch Control Input
DC VCC/GND Current (ICC/IGND
)
+/− 100mA
0nS/V to 5nS/V
0nS/V to DC
Storage Temperature Range (TSTG
)
−65°C to +150 °C
Switch I/O
Free Air Operating Temperature (TA)
−40 °C to +85 °C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused control inputs must be held high or low. They may not float.
DC Electrical Characteristics
T
A = −40 °C to +85 °C
VCC
(V)
Symbol
Parameter
Units
Conditions
Typ
Min
Max
(Note 4)
VIK
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 5)
4.5
4.0–5.5
4.0–5.5
5.5
−1.2
V
V
IIN = −18mA
VIH
VIL
II
2.0
0.8
±1.0
±1.0
7
V
µA
µA
Ω
0≤ VIN ≤5.5V
0 ≤A, B ≤VCC
IOZ
RON
5.5
4.5
4
4
VIN = 0V, IIN = 64mA
VIN = 0V, IIN = 30mA
VIN = 2.4V, IIN = 15mA
VIN = 2.4V, IIN = 15mA
VIN = VCC or GND,
4.5
7
Ω
4.5
8
15
20
3
Ω
4.0
11
Ω
ICC
Quiescent Supply Current
Increase in ICC per Input
5.5
µA
I
OUT = 0
∆ICC
5.5
2.5
mA
One input at 3.4V.
Other inputs at VCC or GND
Note 4: Typical values are at VCC = 5.0V and TA = +25°C
Note 5: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
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2
AC Electrical Characteristics
TA = −40 °C to +85 °C,
CL = 50pF, RU = RD = 500Ω
Symbol
Parameter
Units
Conditions
Figure No.
V
CC = 4.5 − 5.5V CC = 4.0V
V
Min
Max
0.25
4.5
Min
Max
0.25
5.0
t
PHL,tPLH
Prop Delay Bus to Bus (Note 6)
Output Enable Time
VI=OPEN
Figure 1
Figure 2
ns
ns
tPZH, tPZL
1.0
1.5
VI = 7V for tPZL
Figure 1
Figure 2
VI = OPEN for tPZH
VI = 7V for tPLZ
tPHZ, tPLZ
Output Disable Time
5.7
6.2
ns
Figure 1
Figure 2
VI = OPEN for tPHZ
Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 7)
Symbol
CIN
CI/O
Parameter
Typ
Max
Units
Conditions
Control Pin Input Capacitance
Input/Output Capacitance
3
5
pF
pF
V
CC = 5.0V
CC = 5.0V, OE = 0V
V
Note 7: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0MHz, tW = 500ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
Package Number MQA16
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
5
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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