FSB50550US [FAIRCHILD]
Smart Power Module (SPM?); 智能功率模块（ SPM® ）
| 型号： | FSB50550US |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Smart Power Module (SPM?) |
| 文件： | 总8页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2009
FSB50550US
Smart Power Module (SPM )
®
Features
General Description
FSB50550US is a tiny smart power module (SPM®) based on
FRFET technology as a compact inverter solution for small
power motor drive applications such as fan motors and water
suppliers. It is composed of 6 fast-recovery MOSFET (FRFET),
and 3 half-bridge HVICs for FRFET gate driving. FSB50550US
provides low electromagnetic interference (EMI) characteristics
with optimized switching speed. Moreover, since it employs
FRFET as a power switch, it has much better ruggedness and
larger safe operation area (SOA) than that of an IGBT-based
power module or one-chip solution. The package is optimized
for the thermal performance and compactness for the use in the
built-in motor application and any other application where the
assembly space is concerned. FSB50550US is the most
solution for the compact inverter providing the energy efficiency,
compactness, and low electromagnetic interference.
•
•
500V RDS(on)=1.4Ω(max) 3-phase FRFET inverter including
high voltage integrated circuit (HVIC)
3 divided negative dc-link terminals for inverter current sens-
ing applications
•
•
•
•
•
•
HVIC for gate driving and undervoltage protection
3/5V CMOS/TTL compatible, active-high interface
Optimized for low electromagnetic interference
Isolation voltage rating of 1500Vrms for 1min.
Surface mounted device package
Moisture Sensitive Level (MSL) 3
Absolute Maximum Ratings
Symbol
Parameter
Conditions
Rating
Units
DC Link Input Voltage,
VPN
500
V
Drain-source Voltage of each FRFET
Each FRFET Drain Current, Continuous
Each FRFET Drain Current, Continuous
Each FRFET Drain Current, Peak
Maximum Power Dissipation
Control Supply Voltage
ID25
ID80
IDP
PD
TC = 25°C
TC = 80°C
2.0
A
A
1.5
TC = 25°C, PW < 100μs
5
A
TC = 25°C, Each FRFET
14.5
20
W
V
VCC
VBS
VIN
TJ
Applied between VCC and COM
Applied between VB(U)-U, VB(V)-V, VB(W)-W
Applied between IN and COM
High-side Bias Voltage
20
V
Input Signal Voltage
-0.3 ~ VCC+0.3
-40 ~ 150
V
Operating Junction Temperature
°C
TSTG
RθJC
Storage Temperature
-50 ~ 150
8.6
°C
Each FRFET under inverter operating con-
dition (Note 1)
Junction to Case Thermal Resistance
°C/W
60Hz, Sinusoidal, 1 minute, Connection
pins to heatsink
VISO
Isolation Voltage
1500
Vrms
©2009 Fairchild Semiconductor Corporation
FSB50550US Rev. A
1
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Pin Descriptions
Pin Number
Pin Name
Pin Description
1
2
COM
VB(U)
VCC(U)
IN(UH)
IN(UL)
VS(U)
VB(V)
VCC(V)
IN(VH)
IN(VL)
VS(V)
VB(W)
VCC(W)
IN(WH)
IN(WL)
VS(W)
P
IC Common Supply Ground
Bias Voltage for U Phase High Side FRFET Driving
Bias Voltage for U Phase IC and Low Side FRFET Driving
Signal Input for U Phase High-side
3
4
5
Signal Input for U Phase Low-side
6
Bias Voltage Ground for U Phase High Side FRFET Driving
Bias Voltage for V Phase High Side FRFET Driving
Bias Voltage for V Phase IC and Low Side FRFET Driving
Signal Input for V Phase High-side
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Signal Input for V Phase Low-side
Bias Voltage Ground for V Phase High Side FRFET Driving
Bias Voltage for W Phase High Side FRFET Driving
Bias Voltage for W Phase IC and Low Side FRFET Driving
Signal Input for W Phase High-side
Signal Input for W Phase Low-side
Bias Voltage Ground for W Phase High Side FRFET Driving
Positive DC–Link Input
U
Output for U Phase
NU
Negative DC–Link Input for U Phase
NV
Negative DC–Link Input for V Phase
V
Output for V Phase
NW
Negative DC–Link Input for W Phase
W
Output for W Phase
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN(UH)
(5) IN(UL)
(17) P
(18) U
VCC
HIN
VB
HO
VS
LO
LIN
COM
(6) VS(U)
(7) VB(V)
(19) NU
(20) NV
(8) VCC(V)
(9) IN(VH)
(10) IN(VL)
VCC
HIN
VB
HO
VS
LO
(21) V
LIN
COM
(11) VS(V)
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
VCC
HIN
VB
HO
VS
LO
(22) NW
(23) W
LIN
COM
(16) VS(W)
Note:
®
Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM . External connections should be made as indicated in Fig-
ure 2 and 5.
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
2
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FSB50550US Rev. A
Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified)
Inverter Part (Each FRFET Unless Otherwise Specified)
Symbol
Parameter
Conditions
Min Typ Max Units
Drain-Source Breakdown
Voltage
BVDSS
VIN= 0V, ID = 250μA (Note 2)
500
-
0.53
-
-
V
V
ΔBVDSS
ΔTJ
/
Breakdown Voltage Tem-
perature Coefficient
ID = 250μA, Referenced to 25°C
VIN= 0V, VDS = 500V
-
-
-
-
-
Zero Gate Voltage
Drain Current
IDSS
RDS(on)
VSD
250
1.4
1.2
μA
Ω
Static Drain-Source
On-Resistance
VCC = VBS = 15V, VIN = 5V, ID = 1.2A
VCC = VBS = 15V, VIN = 0V, ID = -1.2A
1.0
-
Drain-Source Diode
Forward Voltage
V
tON
tOFF
trr
-
-
-
-
-
600
500
100
60
-
-
-
-
-
ns
ns
ns
μJ
μJ
VPN = 300V, VCC = VBS = 15V, ID = 1.2A
VIN = 0V ↔ 5V
Inductive load L=3mH
Switching Times
High- and low-side FRFET switching
EON
EOFF
(Note 3)
10
VPN = 400V, VCC = VBS = 15V, ID = IDP, VDS=BVDSS
TJ = 150°C
High- and low-side FRFET switching (Note 4)
,
Reverse-bias Safe Oper-
ating Area
RBSOA
Full Square
Control Part (Each HVIC Unless Otherwise Specified)
Symbol
Parameter
Conditions
Min Typ Max Units
IQCC
Quiescent VCC Current
VCC=15V, VIN=0V Applied between VCC and COM
-
-
160
μA
Applied between VB(U)-U,
VBS=15V, VIN=0V
IQBS
Quiescent VBS Current
-
-
100
μA
VB(V)-V, VB(W)-W
UVCCD
UVCCR
UVBSD
UVBSR
VIH
VCC Undervoltage Protection Detection Level
VCC Undervoltage Protection Reset Level
VBS Undervoltage Protection Detection Level
VBS Undervoltage Protection Reset Level
7.4
8.0
7.4
8.0
3.0
-
8.0
8.9
8.0
8.9
-
9.4
9.8
9.4
9.8
-
V
V
Low-side Undervoltage
Protection (Figure 6)
V
High-side Undervoltage
Protection (Figure 7)
V
ON Threshold Voltage
OFF Threshold Voltage
Logic High Level
Applied between IN and COM
Logic Low Level
V
VIL
-
0.8
20
2
V
IIH
VIN = 5V
-
10
-
μA
μA
Input Bias Current
Applied between IN and COM
VIN = 0V
IIL
-
Note:
1. For the measurement point of case temperature T , please refer to Figure 3 in page 4.
C
®
2. BV
is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM . V should be sufficiently less than this value considering the
PN
DSS
effect of the stray inductance so that V should not exceed BV
in any case.
DS
DSS
3.
t
and t
include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
OFF
ON
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5.
4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 5 for the RBSOA test cir-
cuit that is same as the switching test circuit.
Package Marking & Ordering Information
Device Marking
Device
Package
Reel Size
Packing Type
Quantity
FSB50550US
FSB50550US
SPM23-BD
330mm
Tape & reel
450
3
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FSB50550US Rev. A
Recommended Operating Conditions
Value
Symbol
Parameter
Conditions
Units
Min.
-
Typ. Max.
VPN
VCC
VBS
Supply Voltage
Applied between P and N
300
15
15
-
400
16.5
16.5
VCC
V
V
V
V
V
Control Supply Voltage
High-side Bias Voltage
Applied between VCC and COM
13.5
13.5
3.0
0
Applied between VB and output(U, V, W)
VIN(ON) Input ON Threshold Voltage
VIN(OFF) Input OFF Threshold Voltage
Applied between IN and COM
-
0.6
Blanking Time for Preventing
Arm-short
tdead
VCC=VBS=13.5 ~ 16.5V, TJ ≤ 150°C
TJ ≤ 150°C
1.0
-
-
-
-
μs
fPWM
PWM Switching Frequency
15
kHz
These values depend on PWM
control algorithm
R2
15-V Line
HIN
LIN
Output
Note
P
VDC
R1
D1
0
0
Z
Both FRFET Off
Low-side FRFET On
High-side FRFET On
Shoot-through
VCC
HIN
VB
HO
VS
LO
Inverter
Output
R5
0
1
1
0
0
VDC
Micom
LIN
C3
C5
COM
R3
1
1
Forbidden
Z
N
Open
Open
Same as (0, 0)
One-Leg Diagram of SPM
C2
C1
10μF
* Example of bootstrap paramters:
C1 = C2 = 1μF ceramic capacitor,
R1 = 56Ω, R2 = 20Ω
Note:
(1) It is recommended the bootstrap diode D to have soft and fast recovery characteristics with 600-V rating
1
(2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
®
(3) RC coupling(R and C ) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM is compatible with
5
5
standard CMOS or LSTTL outptus.
(4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C , C
1
2
and C should have good high-frequency characteristics to absorb high-frequency ripple current.
3
Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters
14.50mm
3.80mm
Case Temperature(Tc)
Detecting Point
MOSFET
Note:
®
®
Attach the thermocouple on top of the heatsink-side of SPM (between SPM and heatsink if applied) to get the correct temperature measurement.
Figure 3. Case Temperature Measurement
4
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FSB50550US Rev. A
VIN
VIN
Irr
120% of ID
100% of ID
VDS
ID
10% of ID
ID
VDS
tON
trr
tOFF
(a) Turn-on
(b) Turn-off
Figure 4. Switching Time Definition
REH
VCC
ID
RBS
VCC
HIN
VB
HO
VS
LO
L
VDC
LIN
+
VDS
-
COM
CBS
One-leg Diagram of SPM
Figure 5. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
Input Signal
UV Protection
RESET
DETECTION
RESET
Status
UVCCR
Low-side Supply, VCC
UVCCD
MOSFET Current
Figure 6. Undervoltage Protection (Low-side)
Input Signal
UV Protection
Status
RESET
DETECTION
RESET
UVBSR
High-side Supply, VBS
UVBSD
MOSFET Current
Figure 7. Undervoltage Protection (High-side)
5
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FSB50550US Rev. A
R2
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN(UH)
(5) IN(UL)
R1
R5
(17) P
(18) U
VCC
HIN
VB
HO
VS
LO
LIN
C3
VDC
C5
R1
C2
C2
C2
C1
C1
C1
COM
(6) VS(U)
(7) VB(V)
(19) NU
(20) NV
(8) VCC(V)
(9) IN(VH)
(10) IN(VL)
VCC
HIN
VB
HO
VS
LO
(21) V
M
LIN
COM
(11) VS(V)
R1
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
(22) NW
(23) W
VCC
HIN
VB
HO
VS
LO
LIN
COM
(16) VS(W)
R4
For 3-phase current sensing and protection
15-V
Supply
C4
R3
Figure 8. Example of Application Circuit
6
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FSB50550US Rev. A
Detailed Package Outline Drawings
Max 1.00
0.60±0.10
(1.165)
15*1.778=26.67±0.30
15*1.778=26.67
13.34±0.30
13.34±0.30
#1
#16
#1
#16
1.30
4.43
2.48
#17
#23
12.23±0.30
13.13±0.30
7.80
15.60
29.00±0.20
LAND PATTERN RECOMMENDATIONS
2x3.90=7.80±0.30
(2.275)
4x3.90=15.60±0.30
1.95
17.00±0.20
0.60±0.10
Max 1.00
(2.50)
GAGE PLANE
1.50±0.20
SEATING PLANE
7
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FSB50550US Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be
an exhaustive list of all such trademarks.
ACEx®
Across the board. Around the world.™ GTO™
GlobalOptoisolator™
Power247®
SyncFET™
PowerEdge™
PowerSaver™
PowerTrench®
Programmable Active Droop™
QFET®
TCM™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
CTL™
HiSeC™
i-Lo™
The Power Franchise®
™
tm
ImpliedDisconnect™
IntelliMAX™
ISOPLANAR™
MICROCOUPLER™
MicroPak™
MICROWIRE™
MSX™
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TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyWire™
TruTranslation™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
ScalarPump™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
Current Transfer Logic™
DOME™
E2CMOS™
EcoSPARK®
EnSigna™
MSXPro™
OCX™
FACT Quiet Series™
FACT®
OCXPro™
OPTOLOGIC®
OPTOPLANAR®
PACMAN™
POP™
UniFET™
VCX™
Wire™
FAST®
FASTr™
FPS™
FRFET®
Power220®
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF
THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE
UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF
FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE
PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in significant injury to the user.
2.
A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be pub-
lished at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been discontin-
ued by Fairchild semiconductor. The datasheet is printed for reference infor-
mation only.
Rev. I15
8
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FSB50550US Rev. A
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