FQD9N08LTF_技术文档

December 2000

TM

QFET

FQD9N08L / FQU9N08L

80V LOGIC N-Channel MOSFET

General Description

Features

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

•

7.4A, 80V, R

Low gate charge ( typical 4.7 nC)

Low Crss ( typical 16 pF)

Fast switching

100% avalanche tested

= 0.21Ω @V = 10 V

DS(on) GS

This advanced technology is especially tailored to minimize

on-state

resistance,

provide

superior

switching

performance, and withstand a high energy pulse in the

avalanche and commutation modes. These devices are

well suited for low voltage applications such as automotive,

high efficiency switching for DC/DC converters, and DC

motor control.

Improved dv/dt capability

175°C maximum junction temperature rating

Low level gate drive requirements allowing

direct operation from logic drives

D

!

D

"

! "

"

!

G

"

I-PAK

FQU Series

D-PAK

FQD Series

G

S

G

D

!

S

Absolute Maximum Ratings

T = 25°C unless otherwise noted

C

Symbol

Parameter

FQD9N08L / FQU9N08L

Units

V

I

Drain-Source Voltage

80

7.4

DSS

- Continuous (T = 25°C)

Drain Current

A

D

C

- Continuous (T = 100°C)

4.68

29.6

± 20

55

A

C

I

(Note 1)

Drain Current

- Pulsed

A

DM

V

E

I

Gate-Source Voltage

V

GSS

AS

(Note 2)

(Note 1)

(Note 3)

Single Pulsed Avalanche Energy

Avalanche Current

mJ

A

7.4

AR

E

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

2.5

mJ

V/ns

W

AR

dv/dt

6.5

Power Dissipation (T = 25°C) *

2.5

P

A

D

Power Dissipation (T = 25°C)

25

W

C

- Derate above 25°C

Operating and Storage Temperature Range

0.2

W/°C

°C

T , T

-55 to +150

J

STG

Maximum lead temperature for soldering purposes,

1/8” from case for 5 seconds

T

300

°C

L

Thermal Characteristics

Symbol

Parameter

Typ

--

Max

5.0

50

Units

°C/W

R

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient *

Thermal Resistance, Junction-to-Ambient

θJC

θJA

--

110

* When mounted on the minimum pad size recommended (PCB Mount)

Rev. A2, December 2000

Electrical Characteristics

T = 25°C unless otherwise noted

C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

BV

V

= 0 V, I = 250 µA

GS D

Drain-Source Breakdown Voltage

80

--

V

DSS

∆BV

Breakdown Voltage Temperature

Coefficient

DSS

J

I

= 250 µA, Referenced to 25°C

0.08

V/°C

D

/

I

∆T

V

= 80 V, V = 0 V

--

1

µA

nA

DSS

DS

GS

Zero Gate Voltage Drain Current

= 64 V, T = 125°C

10

DS

GS

C

I

= 20 V, V = 0 V

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

100

-100

GSSF

DS

= -20 V, V = 0 V

GSSR

DS

On Characteristics

V

= V , I = 250 µA

Gate Threshold Voltage

1.0

--

2.0

V

Ω

S

GS(th)

DS

GS

D

= 10 V, I = 3.7 A

R

Static Drain-Source

On-Resistance

0.15

0.17

0.21

0.23

GS

D

DS(on)

= 5 V, I = 3.7 A

D

g

= 25 V, I = 3.7 A

(Note 4)

Forward Transconductance

--

4.8

--

FS

DS

D

Dynamic Characteristics

C

Input Capacitance

--

215

70

280

90

pF

iss

V

= 25 V, V = 0 V,

GS

DS

Output Capacitance

oss

rss

f = 1.0 MHz

Reverse Transfer Capacitance

16

20

Switching Characteristics

t

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

--

6.5

180

13

23

370

35

70

6.1

--

ns

d(on)

V

= 40 V, I = 9.3 A,

DD

D

r

R

= 25 Ω

G

ns

d(off)

f

(Note 4, 5)

30

ns

Q

4.7

1.2

2.8

nC

g

V

= 64 V, I = 9.3 A,

DS

D

= 5 V

gs

gd

GS

--

Drain-Source Diode Characteristics and Maximum Ratings

I

Maximum Continuous Drain-Source Diode Forward Current

--

7.4

29.6

1.5

--

A

S

I

Maximum Pulsed Drain-Source Diode Forward Current

SM

V

t

V

= 0 V, I = 7.4 A

Drain-Source Diode Forward Voltage

Reverse Recovery Time

--

V

SD

GS

S

= 0 V, I = 9.3 A,

54

80

ns

nC

rr

GS

S

(Note 4)

dI / dt = 100 A/µs

Q

Reverse Recovery Charge

--

F

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 1.38mH, I = 7.4A, V = 25V, R = 25 Ω, Starting T = 25°C

AS

DD

G

J

3. I ≤ 9.3A, di/dt ≤ 300A/µs, V ≤ BV

Starting T = 25°C

SD

DD

DSS,

J

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Rev. A2, December 2000

Typical Characteristics

V_GS

Top :

10.0 V

8.0 V

6.0 V

5.0 V

4.5 V

4.0 V

3.5 V

10¹

Bottom: 3.0 V

℃

150

10⁰

℃

25

℃

-55

※

Notes :

※

Notes :

μ

1. V_DS= 25V

1. 250 s Pulse Test

2. T_C= 25

μ

2. 250 s Pulse Test

℃

-1

10

-1

10⁰

10¹

0

2

4

6

8

10

V_GS, Gate-Source Voltage [V]

V_DS, Drain-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

0.8

0.6

0.4

0.2

0.0

10¹

10⁰

10^-1

V_GS= 5V

V_GS= 10V

℃

150

℃

25

※

Notes :

1. V_GS= 0V

※

℃

Note : T = 25

μ

2. 250 s Pulse Test

J

0

5

10

15

20

25

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

I_D, Drain Current [A]

V_SD, Source-Drain Voltage [V]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

600

500

400

300

200

100

0

12

10

8

C

_iss= C_gs+ C_gd(C_ds= shorted)

C_oss= C_ds+ C_gd

_rss= C_gd

C

V_DS= 40V

V_DS= 64V

※

Notes :

1. V_GS= 0 V

2. f = 1 MHz

6

C

iss

C_oss

4

2

C

rss

※

Note : I_D= 9.3A

0

10^-1

10⁰

10¹

0

1

2

3

4

5

6

7

8

9

Q_G, Total Gate Charge [nC]

V_DS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

Rev. A2, December 2000

Typical Characteristics (Continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.2

1.1

1.0

※Notes :

1. V_GS= 0 V

2. I_D= 250 μA

0.9

※

Notes :

1. V_GS= 5 V

2. I_D= 3.7 A

0.8

-100

-50

0

50

100

150

200

-100

-50

0

50

100

150

200

T_J, Junction Temperature [^oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

Figure 8. On-Resistance Variation

vs. Temperature

8

6

4

2

0

10²

10¹

10⁰

Operation in This Area

is Limited by R _DS(on)

100 µs

1 ms

10 ms

DC

※

Notes :

1. T_C= 25 ^o

2. T_J= 150 ^o

C

3. Single Pulse

-1

10

10⁰

10¹

10²

25

50

75

100

125

150

℃

T_C, Case Temperature [

]

V_DS, Drain-Source Voltage [V]

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current

vs. Case Temperature

D = 0 .5

※

N o te s

1 . Z _θ_{J C}(t)

2 . D u ty F a c to r, D = t₁/t₂

:

0 .2

1 0 ⁰

℃

/W M a x.

=

5 .0

0 .1

3 . T _{J M}

-

T _C

=

P _D

* Z _θ_{J C}(t)

M

0 .0 5

P_DM

0 .0 2

0 .0 1

t₁

1 0^-1

s in g le p u ls e

t₂

1 0 ^-5

1 0^-4

1 0 ^-3

1 0 ^-2

1 0 ^-1

1 0 ⁰

1 0 ¹

t₁, S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11. Transient Thermal Response Curve

Rev. A2, December 2000

Gate Charge Test Circuit & Waveform

V_GS

Same Type

50KΩ

as DUT

Q_g

12V

200nF

5V

300nF

V_DS

V_GS

Q_gs

Q_gd

DUT

3mA

Charge

Resistive Switching Test Circuit & Waveforms

R_L

V_DS

90%

V_DS

V_DD

V_GS

R_G

10%

V_GS

DUT

5V

t_d(on)

t_r

t_d(off)

t_f

t _on

t _off

Unclamped Inductive Switching Test Circuit & Waveforms

BV_DSS

--------------------

BV_DSS- V_DD

L

1

2

----

E_AS

=

LI_AS

V_DS

I_D

BV_DSS

I_AS

R_G

V_DD

I_D(t)

V_DD

V_DS(t)

DUT

10V

t _p

Time

Rev. A2, December 2000

Peak Diode Recovery dv/dt Test Circuit & Waveforms

+

DUT

V_DS

_

I _SD

L

Driver

R_G

Same Type

as DUT

V_DD

V_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

Gate Pulse Width

--------------------------

V_GS

D =

Gate Pulse Period

10V

( Driver )

I_FM, Body Diode Forward Current

I _SD

di/dt

( DUT )

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_SD

V_DS

( DUT )

V_DD

Body Diode

Forward Voltage Drop

Rev. A2, December 2000

Package Dimensions

DPAK

6.60 ±0.20

5.34 ±0.30

2.30 ±0.10

0.50 ±0.10

(0.50)

(4.34)

(0.50)

MAX0.96

0.76 ±0.10

0.50 ±0.10

1.02 ±0.20

2.30 ±0.20

2.30TYP

[2.30±0.20]

6.60 ±0.20

(5.34)

(5.04)

(1.50)

(2XR0.25)

0.76 ±0.10

Rev. A2, December 2000

Package Dimensions ^(Continued)

IPAK

2.30 ±0.20

0.50 ±0.10

6.60 ±0.20

5.34 ±0.20

(0.50)

(4.34)

(0.50)

MAX0.96

0.76 ±0.10

0.50 ±0.10

2.30TYP

[2.30±0.20]

Rev. A2, December 2000

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

ACEx™

HiSeC™

SuperSOT™-8

SyncFET™

TinyLogic™

UHC™

Bottomless™

CoolFET™

CROSSVOLT™

E²CMOS™

FACT™

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench^®

QFET™

VCX™

FACT Quiet Series™

QS™

FAST^®

Quiet Series™

SuperSOT™-3

SuperSOT™-6

FASTr™

GTO™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

INTERNATIONAL.

As used herein:

result in significant injury to the user.

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. A, January 2000

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FQD9N08L


型号：	FQD9N08LTF
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Power Field-Effect Transistor, 7.4A I(D), 80V, 0.23ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, DPAK-3 开关脉冲晶体管
文件：	总11页 (文件大小：576K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FQD9N08LTF [FAIRCHILD]

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