FAN7680N [FAIRCHILD]
PC Power Supply Outputs Monitoring IC; PC电源输出监控IC
| 型号： | FAN7680N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | PC Power Supply Outputs Monitoring IC |
| 文件： | 总16页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN7680
PC Power Supply Outputs Monitoring IC
Features
Description
• PC Power Supply Output Monitor Circuitry
• Few External Components
The FAN7680 is a complete output supervisory circuitry
intended for use in the secondary side of a switched mode
power supply. It provides over voltage protection (OVP),
under voltage protection (UVP), fault protection output
(FPO), remote On/Off (PSON), latch, internal delay circuits
and power good signal generator to monitor and control the
output of the switching power supply system. As for output
control, power good output(PGO) and fault protection out-
put(FPO) are included. It directly senses all the output rails
for OVP and UVP without external dividers. The FAN7680
offers a simple and cost effective solution with minimum
number of external components and greatly reduces PCB
board space for power supply.
• Over Voltage Protection for 3.3V, 5V and 12V(Vcc)
Outputs
• Under Voltage Protection for 3.3V, 5V and 12V(Vcc)
Outputs with Delay Time
• Fault Protection Output with Open Drain Output
• Open Drain Power Good Output
• 300ms Power Good Delay
• 38ms PSON On/Off Debounce
• 73us Debounce
• 2.3ms PSON to FPO Turn Off Delay
• Latch Function Controlled by PSON and Protection
Inputs
8-DIP
Typical Application
1
• PC Power Supply
8-SOP
1
FPO
OVP
The FPO(Fault Protection Output) is a signal which indicates
the system fault condition according to protection signals.
When a fault state is occured, the FPO signal becomes high
and the PGO signal becomes low and the main power is to be
turned off.
The FAN7680 has OVP functions for +3.3V, +5V,
+12V(Vcc) outputs. This block is made up of three compara-
tors with two inputs and resistor dividers. One input of a
comparator is connected to a reference voltage and another
input is connected to a resistor divider.
Normal State; "Low"
Fault State; "High"
UVP
The FAN7680 also has UVP functions for +3.3V, +5V,
+12V(Vcc) outputs. This block is made up of three compara-
tors with two inputs and resistor dividers. One input of a
comparator is connected to a reference voltage and another
input is connected to a resistor divider.
PGO
The power good signal generator provides a signal according
to output voltage conditions of a power supply for safe oper-
ation of a secondary system. The power good output should
be low state before the output voltage is out of regulation at
turn-off of the input power switch.
PSON
Normal State ; "High"
Fault State ; "Low"
The remote on/off(PSON) section is for controlling the
SMPS externally. When a high signal is applied to the PSON
input, the FPO signal becomes a high state and all secondary
outputs are grounded. The remote on/off signal is transferred
with some on/off debounce time.
Rev. 1.0.0
©2003 Fairchild Semiconductor Corporation
FAN7680
Internal Block Diagram
PSON
3.6V
Vref
Vcc
REF.
POR
clr
Delay
2.3ms
CLK
Start-up
CLK
Oscillator
Reset
7
6
5
VCC
VS5
R
L
3
FPO
L
UVP
H
L
R
R
S
H
L
L
L
Debounce
73us
Q
Delay
75ms
clr
VS33
CLK
R
CLK
L
Vcc
L
PGI_O
150uA
L
3.6V
OVP
L
PSON
L
L
Debounce
38ms
4
PSON
CLK
R
Vref
3.6V
H
PSON
L
UVP
L
8
2
PGO
GND
Q
CLK
CLK
R
L
H
H
H
clr
H
Delay
300ms
Debounce
73us
1
PGI
L
L
L
PGI_O
Vref
Typical Applicatin Circuit
5 V s b
P G I
P G O
+ 1 2 V
1
2
3
4
PGI
PGO
8
7
6
5
GND
FPO
VCC
VS5
5 V s b
+ 5 V
PSON VS33
P S O N
+ 3 . 3 V
F A N 7 6 8 0
2
FAN7680
Pin Assignments
1
2
3
4
8
7
6
5
PGI
PGO
VCC
GND
FPO
PSON
VS5
VS33
YWW :Work Week Code
Pin Definitions
Pin Number
Pin Name
I/O
Pin Function Description
1
2
3
4
5
6
7
8
PGI
GND
FPO
PSON
VS33
VS5
I
-
O
I
I
I
Power Good Input
Ground
Low Active Fault Protection Output, Open Drain Output Stage
Remote On/Off Control Input
3.3V Output Voltage Input
5V Output Voltage Input
V
CC
PGO
Supply Voltage and 12V Output Voltage Input
Power Good Output Signal
I
O
3
FAN7680
Absolute Maximum Ratings (Note2,3)
Parameter
Supply Voltage
Supply Current
Symbol
Value
16
1
Unit
V
mA
V
CC
I
CC
V
, VS5
PSON
Input Voltage
8
V
V
VS33, V
PGI
PGO
V
V
8
16
Output Voltage
FPO
Operating Temperature
Storage Temperature
Power Dissipation
T
T
P
-40 ~ +125
-65 ~ +150
1
°C
°C
W
O
S
D
Recommended Operating Conditions (Note2,3)
Characteristic
Symbol
Test Condition
Min.
Typ.
Max.
Unit
Supply Voltage
V
4
15
V
CC
, VS5,
V
PSON
VS33, V
Input Voltage
7
V
PGI
PGO
V
7
V
V
mA
mA
ms
Output Voltage
V
FPO
15
30
10
I
FPO
Output Sink Current
I
PGO
tr
Supply Voltage Rising Time
Note1
1
4
FAN7680
Electrical Characteristics
(V
CC
= 5V, Ta=25°C, unless otherwise specified)
Over Voltage Protection, Under Voltage Protection and FPO
Characteristic
Symbol
Test Condition
Min.
3.9
5.8
13.3
2.55
4.1
8.8
-
Typ.
4.1
6.1
13.8
2.69
4.3
9.3
-
Max.
4.3
6.4
14.3
2.83
4.5
9.8
5
Unit
VS33
OV
Over Voltage Threshold
VS5
V
OV
12V(V
)
CC OV
VS33
UV
UV
Under Voltage Threshold
VS5
V
12V(V
)
CC UV
LKG1
Leakage Current(
)
I
V
= 5V
uA
V
FPO
FPO
Isink=10mA
Isink=30mA
-
-
-
-
0.3
0.7
Low Level Output Voltage(FPO)
V
OLI
PGI and PGO
Characteristic
Symbol
Test Condition
Min.
1.16
-
-
Typ.
1.20
-
-
Max.
1.24
5
Unit
V
uA
V
Input Threshold Voltage(PGI)
Leakage Current(PGO)
Low Level Output Voltage(PGO)
V
PGI
I
V
= 5V
PGO
Isink=10mA
LKG2
V
0.4
OL2
PSON Control
Characteristic
Symbol
Test Condition
= 0V
Min.
Typ.
150
-
-
Max.
-
-
Unit
uA
V
Input Pull-up Current
High-Level Input Voltage
Low-Level Input Voltage
V
-
2.4
-
PSON
1.2
V
Total Device
Characteristic
Supply Current
Symbol
Test Condition
= 5V
PSON
Min.
-
Typ.
-
Max.
1
Unit
mA
I
V
CC
Timing Characteristics
(V =5V, Ta=25°C, unless otherwise specified)
CC
Characteristic
Symbol
Test Condition
Note 4
Min.
25
Typ.
38
Max.
51
Unit
ms
us
Debounce Time(PSON)
Noise Debounce Time
PGO Delay Time(PGI to PGO)
t
b1
t
b2
t
d1
50
200
73
300
100
410
ms
FPO goes low and
Internal UVP Delay Time
t
d2
t
d3
51
75
102
ms
ms
every time PGI > 1.20
PSON Off to FPO Delay Time
t
+1.6
t
+2.3
b1
t
+3.2
b1
b1
Note
1. V
slew rate must be less than 14V/ms.
CC
2. All voltages are measured with respect to the ground pin, unless otherwise specified.
3.The Absolute Maximum Ratings indicate the limits that if exceed, damage to the device may occur. Recommended Operating
Conditions indicate conditions in which the device is functional, but do not guarantee specific performance limits.
4. This parameter, although guaranteed over the Timing Characteristics, is not 100% tested in production.
5
FAN7680
Typical Characteristics
6
5
4
3
2
1
0
6
5
4
3
2
1
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.14
1.16
1.18
1.20
1.22
1.24
PSON (V)
PGI (V)
Figure 1. PSON Threshold Voltage
Figure 2. PGI Threshold Voltage
6
5
4
3
2
1
0
6
5
4
3
2
1
0
2.83
2.79
2.75
2.71
2.67
2.63
2.59
2.55
3.90 3.94 3.98 4.02 4.06 4.10 4.14 4.18 4.22 4.26 4.30
VS33 (V)
VS33 (V)
Figure 3. +3.3V UVP Voltage
Figure 4. +3.3V OVP Voltage
6
6
5
4
3
2
1
0
5
4
3
2
1
0
4.50 4.45 4.40 4.36 4.31 4.26 4.21 4.16 4.12
VS5 (V)
5.80
5.88
5.96
6.04
6.12
6.20
6.28
6.36
VS5 (V)
Figure 5. +5V UVP Voltage
Figure 6. +5V OVP Voltage
6
FAN7680
Typical Characteristics
6
5
4
3
2
1
0
6
5
4
3
2
1
0
9.80
9.60
9.40
9.20
9.00
8.80
13.30
13.50
13.70
13.90
14.10
14.30
14.50
Vcc (V)
Vcc (V)
Figure 7. +12V UVP Voltage
Figure 8. +12V OVP Voltage
7
FAN7680
Timing Chart
1) AC Input ON/OFF - Normal State
AC Input
VCC
Enable
POR
PSON
FPO
tb1
AC Input
Disable
PGI
UVP
Threshold
OUT
PGO
tb2+td1
2) PSON ON/OFF - Normal State
PSON
FPO
PGI
td3
tb1
UVP
Threshold
OUT
PGO
tb1+tb2
tb2+td1
- Vcc : Supply Voltage
- POR : Power On Reset
- PSON : Power Supply On/Off
- FPO : Fault Protection Output
- PGI : Power Good Input
- OUT : Output Voltages
- PGO : Power Goood Output
8
FAN7680
3) Under Voltage at Normal State
Latch
PSON
FPO
PGI
tb1
tb2
UVP
Threshold
UVP
Threshold
OUT
PGO
tb2+td1
4) Under Voltage at AC Input ON
AC Input
Enable
VCC
POR
PSON
FPO
PGI
Latch
tb2+td2
tb1
PGI
UVP
Threshold
Threshold
OUT
PGO
tb2+td1
9
FAN7680
5) Under Voltage at PSON ON/OFF
Latch
PSON
tb2+td2
FPO
PGI
td3
tb1
PGI
UVP
Threshold
Threshold
OUT
PGO
tb1+tb2
tb2+td1
6) Over Voltage at PSON ON/OFF
Latch
PSON
FPO
PGI
tb1
tb2
UVP
Threshold
OVP
OUT
PGO
Threshold
tb2+td1
10
FAN7680
Application Information
Power Good(PGO) and Power Good Delay
A PC power supply is commonly designed to provide the motherboard with a power good signal, which is defined by the com-
puter manufactures. If the +3.3V, +5V, and +12V outputs are above the undervoltage threshold limit, the PC power supply
makes the power good signal high after some delay. At this time the power supply should be able to provide enough power to
assure continuous operation within the specification. Conversely, when one of the +3.3V, +5V, or +12V outputs falls below the
undervoltage threshold or rise above the overvoltage threshold, or when main power has been turned off for a sufficiently long
time so that power supply operation is no longer assured, a PGO signal will be a low state.
The AC input, power good(PGO), remote on/off(PSON), and +3.3V/+5V/+12V supply rails are shown in figure 1.
T1
T5
VAC
PSON
+12VDC
+5VDC
95%
10%
Figure 1. Timing Diagram
+3.3VDC
T3
T2
PGO
T4
T5
Although there is no requirement for specific timing parameters, the following signal timings are recommended :
-T1(Power On Time) : T1 < 500ms
-T2(Rise Time) : 0.1ms ≤ T2 ≤ 20ms
-T3(PGO Delay) : 100ms < T3 <500ms
-T4(PGO Delay Risetime) : T4 ≤ 10ms
-T5(AC Loss to PGO Hold-Up Time) : T5 ≥ 16ms
-T6(Power Down Warning) : T6 ≥ 1ms
Furthermore, motherboards should be designed to comply with the above recommended timing range. If timings other than
these are implemented or required, that information should be clearly specified.
The FAN7680 provides a power good(PGO) signal for the +3.3V, +5V and +12V(Vcc) supply voltage rails and a separate
power good input(PGI). An internal delay circuit is used to generate a 300ms power good delay.
If voltages at PGI(+1.2V), VS33(+3.3V), VS5(+5V), and Vcc(+12V) rise above the undervoltage threshold, the open drain
power good output(PGO) will go high after a delay of 300ms. When the PGI voltage or any of +3.3V, +5V, and +12V rails
drops below the undervoltage threshold, the PGO signal will be disabled immediately.
Power Supply Remote On/Off(PSON) and Fault Protect Output(FPO)
Since the latest personal computer generation focuses on easy turn on and power saving functions, a PC power supply will
require two characteristics. One is a dc power supply remote on/off function; the other is standby voltage to achieve very low
power consumption of the PC power supply. Thus, the main power needs to be shut down.
The power supply remote on/off(PSON) is an active-low signal that turns on all of the main power rails including the +3.3V,
+5V, and +12V power rails. When this signal is held high by the PC motherboard or left open circuited, the signal of the fault
protect output(FPO) also goes high. Thus, the main power rails can not deliver power and are held at 0V.
When the FPO signal is held high due to an fault condition, the fault status will be latched and the outputs of the main power
rails can not deliver power and are held at 0V. Toggling the PSON input signal from low to high will reset the fault protection
latch. During this fault condition only the standby power is not affected.
When the PSON input signal goes from high to low or low to high, the 38ms debounce block will be active to avoid that a
glitch on the PSON input may disable/enable the FPO output. When the PSON is set low, the undervoltage function is disabled
11
FAN7680
during 75ms to avoid turn-on failure. At turn-off, there is an additional delay of 2.3ms from PSON to FPO.
Power should be delivered to the rails only when the PSON signal is held at ground potential, thus the FPO becomes a low
state after a debounce of 38ms. The FPO pin can be connected to +5V(or up to +15V) through a pull-up resistor.
Under Voltage Protection(UVP)
The FAN7680 provides undervoltage protection(UVP) for the +3.3V, +5V, and +12V power rails. When an undervoltage con-
dition appears at one of the VS33(+3.3V), VS5(+5V), or Vcc(+12V) input pins for more than 73us, the PGO goes low and
FPO output goes high. Also, this fault condition will be latched until the PSON is toggled from low to high or the Vcc falls
below a minimum operating voltage.
When the power supply is turned on by the AC input or PSON, an internal UVP delay is 75ms. But at normal state an UVP
delay time is a 73us debounce time. The need for undervoltage protection is often overlooked in off-line switching power sup-
ply system design. But it is very important in battery powered or hand-held equipment since the TTL or CMOS logic often
malfunctions under UVP condition.
Over Voltage Protection(OVP)
The overvoltage protection(OVP) of the FAN7680 monitors +3.3V, +5V, and +12V(the +12V output is sensed via the Vcc
pin). When an overvoltage condition appears at one of the +3.3V, +5V, or +12V input pins for more than 73us, the FPO output
goes high and the PGO goes low. Also, this fault condition will be latched until the PSON is toggled from low to high or Vcc
drops below a minimum operating voltage. During fault conditions, most power supplies have the potential to deliver higher
output voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages to be
high enough to cause internal or external damage to the system. To protect the system under these abnormal conditions, it is
common practice to provide overvoltage protection within the power supply.
Because TTL and CMOS circuits are very vulnerable to overvoltage, it is becoming industry standard to provide overvoltage
protection on all +3.3V, +5V, and +12V outputs. Therefore, not only the +3.3V and +5V rails for the logic circuits on the moth-
erboard need to be protected, but also the +12V peripheral devices such as the hard disk, flopply disk, and CD-ROM players
etc., need to be protected.
12
FAN7680
Mechanical Dimensions
Package
Dimensions in millimeters
8-DIP
13
FAN7680
Mechanical Dimensions
Package
Dimensions in millimeters
8-SOP
14
FAN7680
Ordering Information
Product Number
FAN7680N
Package
8DIP
8SOP
Operating Temperature
-40°C ~ +125°C
FAN7680M
15
FAN7680
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/23/03 0.0m 001
Stock#DSxxxxxxxx
2003 Fairchild Semiconductor Corporation
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