FAN7621_10 [FAIRCHILD]
PFM Controller for Half-Bridge Resonant Converters; PFM控制器半桥谐振转换器
| 型号： | FAN7621_10 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | PFM Controller for Half-Bridge Resonant Converters |
| 文件： | 总17页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2010
FAN7621
PFM Controller for Half-Bridge Resonant Converters
Features
Description
The FAN7621 is a pulse frequency modulation controller
for high-efficiency half-bridge resonant converters.
Offering everything necessary to build a reliable and
robust resonant converter, the FAN7621 simplifies
designs and improves productivity, while improving
performance. The FAN7621 includes a high-side gate-
drive circuit, an accurate current controlled oscillator,
frequency limit circuit, soft-start, and built-in protection
Variable Frequency Control with 50% Duty Cycle
for Half-bridge Resonant Converter Topology
High Efficiency through Zero Voltage Switching (ZVS)
Fixed Dead Time (350ns)
Up to 300kHz Operating Frequency
Pulse Skipping for Frequency Limit (Programmable)
at Light-Load Condition
functions. The high-side gate-drive circuit has
a
Remote On/Off Control Using CON Pin
Protection Functions: Over-Voltage Protection
(OVP), Overload Protection (OLP), Over-Current
Protection (OCP), Abnormal Over-Current Protection
(AOCP), Internal Thermal Shutdown (TSD)
common-mode noise cancellation capability, which
guarantees stable operation with excellent noise
immunity. Using the zero-voltage-switching (ZVS)
technique dramatically reduces the switching losses and
efficiency is significantly improved. The ZVS also
reduces the switching noise noticeably, which allows a
small-sized Electromagnetic Interference (EMI) filter.
Applications
The FAN7621 can be applied to various resonant
converter topologies; such as series resonant, parallel
resonant, and LLC resonant converters.
PDP and LCD TVs
Desktop PCs and Servers
Adapters
Telecom Power Supplies
Video Game Consoles
Related Resources
AN4151 — Half-bridge LLC Resonant Converter Design
using FSFR-series Fairchild Power Switch (FPSTM
)
Ordering Information
Operating Junction
Part Number
Package
Packaging Method
Temperature
FAN7621N
FAN7621SJ
FAN7621SJX
16-Lead, Dual Inline Package (DIP)
16-Lead, Small-Outline Package (SOP)
16-Lead, Small-Outline Package (SOP)
Tube
Tube
-40°C ~ 130°C
Tape & Reel
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
Application Circuit Diagram
D1
Cr
Llk
Np
VO
Ns
Ns
VCC
LVcc
Lm
HVCC
RT
HO
CF RF
D2
CON
CS
CTR
CDL
VIN
KA431
LO
SG
PG
Rsense
Figure 1. Typical Application Circuit (LLC Resonant Half-Bridge Converter)
Block Diagram
LVCC
12
+
LVCC good
VREF
VREF
ICTC
+
8.7 / 9.2V
-
11.3 / 14.5V
-
S
R
Q
HVCC good
Internal
Bias
3 V
1 V
-
+
-Q
ICTC
+
2ICTC
1
3
2
F/F
HVCC
HO
-
2V
+
-
High-Side
Gate Drive
Time
Delay
Level-Shift
350ns
8
6
RT
CTR
Counter (1/4)
LVCC
IOLP
Low-Side
Gate Drive
Time
Delay
Balancing
Delay
-
14
CON
LO
0.4 / 0.6 V
+
350ns
+
Shutdown without delay
OLP
S
Q
5 V
-
R
-Q
LVCC good
+
-1
LV
+
-
CC
50ns Delay
Auto-restart
Protection
Q
S
R
0.9 V
-
23 V
-Q
VAOCP
OVP
TSD
LVCC < 5V
16
10
Latch
Protection
PG
SG
VOCP
0.58 V
-
Delay
1.5µs
+
9
CS
Figure 2. Internal Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
2
Pin Configuration
(1) HVCC
(2) CTR
(3) HO
(4) NC
(5) NC
(6) CON
(7) NC
(8) RT
PG (16)
NC (15)
LO (14)
NC (13)
LVCC (12)
NC (11)
SG (10)
CS (9)
FAN7621
Figure 3. Package Diagram
Pin Definitions
Pin #
Name
HVCC
CTR
HO
Description
1
2
3
4
5
This is the supply voltage of the high-side gate-drive circuit IC.
This is the drain of the low-side MOSFET. Typically, a transformer is connected to this pin.
This is the high-side gate driving signal.
NC
No connection.
NC
No connection.
This pin is for a protection and enabling/disabling the controller. When the voltage of this pin
is above 0.6V, the IC operation is enabled. When the voltage of this pin drops below 0.4V,
gate drive signals for both MOSFETs are disabled. When the voltage of this pin increases
above 5V, protection is triggered.
6
CON
7
8
NC
RT
No connection.
This pin programs the switching frequency. Typically, an opto-coupler is connected to
control the switching frequency for the output voltage regulation.
This pin senses the current flowing through the low-side MOSFET. Typically, negative
voltage is applied on this pin.
9
CS
10
11
12
13
14
15
16
SG
NC
This pin is the control ground.
No connection.
LVCC
NC
This pin is the supply voltage of the control IC.
No connection.
LO
This is the low-side gate driving signal.
NC
No connection.
PG
This pin is the power ground. This pin is connected to the source of the low-side MOSFET.
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.
Symbol
VHO
Parameter
High-Side Gate Driving Voltage
Min.
VCTR-0.3
-0.3
Max.
HVCC
LVCC
25.0
25.0
600.0
LVCC
1.0
Unit
V
VLO
Low-Side Gate Driving Voltage
Low-Side Supply Voltage
LVCC
-0.3
V
V
HVCC to VCTR High-Side VCC Pin to Center Voltage
-0.3
VCTR
VCON
Center Voltage
-0.3
V
Control Pin Input Voltage
Current Sense (CS) Pin Input Voltage
RT Pin Input Voltage
-0.3
V
VCS
-5.0
V
VRT
-0.3
5.0
V
dVCTR/dt
Allowable Center Voltage Slew Rate
50
V/ns
W
W
16-DIP
Total Power Dissipation
16-SOP
Maximum Junction Temperature(1)
1.56
1.13
+150
+130
+150
PD
TJ
°C
°C
Recommended Operating Junction Temperature(1)
-40
-55
TSTG
Storage Temperature Range
Note:
1. The maximum value of the recommended operating junction temperature is limited by thermal shutdown.
Thermal Impedance
Symbol
Parameter
Value
80
Unit
16-DIP
θJA
Junction-to-Ambient Thermal Impedance
ºC/W
16-SOP
110
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
4
Electrical Characteristics
TA=25°C and LVCC=17V unless otherwise specified.
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
Supply Section
ILK
Offset Supply Leakage Current
Quiescent HVCC Supply Current
Quiescent LVCC Supply Current
HVCC=VCTR
50
μA
μA
μA
IQHVCC
IQLVCC
(HVCCUV+) - 0.1V
(LVCCUV+) - 0.1V
50
120
200
100
f
OSC=100kHz, VCON > 0.6V,
5
100
6
8
200
9
mA
μA
Operating HVCC Supply Current
(RMS Value)
CLoad=1nF
IOHVCC
No Switching, VCON < 0.4V
f
OSC=100kHz, VCON > 0.6V,
mA
mA
Operating LVCC Supply Current
(RMS Value)
CLoad=1nF
IOLVCC
No Switching, VCON < 0.4V
2
4
UVLO Section
LVCCUV+ LVCC Supply Under-Voltage Positive Going Threshold (LVCC Start)
LVCCUV- LVCC Supply Under-Voltage Negative Going Threshold (LVCC Stop)
LVCCUVH LVCC Supply Under-Voltage Hysteresis
13.0
10.2
14.5
11.3
3.2
16.0
12.4
V
V
V
V
V
V
HVCCUV+ HVCC Supply Under-Voltage Positive Going Threshold (HVCC Start)
8.2
7.8
9.2
10.2
9.6
HVCC Supply Under-Voltage Negative Going Threshold (HVCC Stop)
HVCCUV-
8.7
HVCCUVH HVCC Supply Under-Voltage Hysteresis
0.5
Oscillator & Feedback Section
VCONDIS
VCONEN
VRT
Control Pin Disable Threshold Voltage
Control Pin Enable Threshold Voltage
V-I Converter Threshold Voltage
Output Oscillation Frequency
Output Duty Cycle
0.36
0.54
1.5
94
0.40
0.60
2.0
100
50
0.44
0.66
2.5
V
V
V
fOSC
106
52
kHz
%
RT=5.2kΩ
DC
48
fSS
Internal Soft-Start Initial Frequency
Internal Soft-Start Time
140
3
kHz
ms
fSS=fOSC+40kHz, RT=5.2kΩ
tSS
2
4
Output Section
Isource
Isink
tr
Peak Sourcing Current
HVCC=17V
HVCC=17V
250
460
360
600
65
mA
mA
ns
Peak Sinking Current
Rising Time
CLoad=1nF, HVCC=17V
tf
Falling Time
35
ns
High Level of High-Side Gate Driving
VHOH
VHOL
VLOH
VLOL
1.0
0.6
1.0
0.6
V
V
V
V
Signal (VHVCC-VHO
)
Low Level of High-Side Gate Driving
Signal
IO=20mA
High Level of High-Side Gate Driving
Signal (VLVCC-VLO
)
Low Level of High-Side Gate Driving
Signal
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
TA=25°C and LVCC=17V unless otherwise specified.
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
Protection Section
IOLP
VOLP
VOVP
VAOCP
tBAO
OLP Delay Current
VCON=4V
3.8
4.5
21
5.0
5.0
6.2
5.5
25
μA
V
OLP Protection Voltage
VCON > 3.5V
LVCC > 21V
LVCC Over-Voltage Protection
AOCP Threshold Voltage
AOCP Blanking Time
23
V
-1.0
-0.9
50
-0.8
V
ns
V
VOCP
tBO
OCP Threshold Voltage
OCP Blanking Time(2)
-0.64
1.0
-0.58
1.5
-0.52
2.0
μs
Delay Time (Low-Side) Detecting from
V
tDA
TSD
ISU
250
130
100
400
150
150
ns
°C
μA
AOCP to Switch Off(2)
Thermal Shutdown Temperature(2)
110
5
Protection Latch Sustain LVCC Supply
Current
LVCC=7.5V
Protection Latch Reset LVCC Supply
Voltage
VPRSET
V
Dead-Time Control Section
DT Dead Time
350
ns
Note:
2. These parameters, although guaranteed, are not tested in production.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7621 • Rev. 1.0.3
6
Typical Performance Characteristics
These characteristic graphs are normalized at TA=25ºC.
1.1
1.05
1
1.1
1.05
1
0.95
0.9
0.95
0.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temp (OC)
Temp (OC)
Figure 4. Low-Side MOSFET Duty Cycle
vs. Temperature
Figure 5. Switching Frequency vs. Temperature
1.1
1.05
1
1.1
1.05
1
0.95
0.9
0.95
0.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temp (OC)
Temp (OC)
Figure 6. High-Side VCC (HVCC) Start vs. Temperature
Figure 7. High-Side VCC (HVCC) Stop vs. Temperature
1.1
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temp (OC)
Temp (OC)
Figure 8. Low-Side VCC (LVCC) Start vs. Temperature
Figure 9. Low-Side VCC (LVCC) Stop vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
7
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA=25ºC.
1.1
1.05
1
1.1
1.05
1
0.95
0.9
0.95
0.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temp (OC)
Temp (OC)
Figure 10. OLP Delay Current vs. Temperature
Figure 11. OLP Protection Voltage vs. Temperature
1.1
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temp (OC)
Temp (OC)
Figure 12. LVCC OVP Voltage vs. Temperature
Figure 13. RT Voltage vs. Temperature
1.1
1.1
1.05
1
1.05
1
0.95
0.9
0.95
0.9
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Temp (OC)
Temp (OC)
Figure 14. CON Pin Enable Voltage vs. Temperature
Figure 15. OCP Voltage vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
8
Functional Description
1. Basic Operation
FAN7621 is designed to drive high-side and low-side
MOSFETs complementarily with 50% duty cycle. A fixed
dead time of 350ns is introduced between consecutive
transitions, as shown in Figure 16.
Gain
1.8
max
f min
f normal
f ISS
f
1.6
1.4
1.2
1.0
0.8
0.6
Dead t ime
High-side
MOSFET
gate drive
Low-side
MOSFET
gate drve
Soft-sta rt
time
Figure 16. MOSFETs Gate Drive Signal
150
60
70
80
90
100
110
120
130
140
Frequency (kHz)
2. Internal Oscillator
Figure 18. Resonant Converter Typical Gain Curve
FAN7621 employs a current-controlled oscillator, as
shown in Figure 17. Internally, the voltage of RT pin is
regulated at 2V and the charging / discharging current
for the oscillator capacitor, CT, is obtained by copying the
current flowing out of RT pin (ICTC) using a current mirror.
Therefore, the switching frequency increases as ICTC
increases.
VCC
LV
CC
HV
CC
RT
Rmax
Rmin
RSS
HO
CTR
LO
ICTC
VREF
+
S
R
Q
CON
CS
3V
1V
-
CSS
-Q
ICTC
+
2ICTC
CT
F/F
-
+
SG
PG
2V
-
Counter
(1/4)
RT
Gate drive
8
Rsense
Figure 19. Frequency Control Circuit
The minimum switching frequency is determined as:
5.2kΩ
Figure 17. Current Controlled Oscillator
f min
=
×100(kHz)
(1)
3. Frequency Setting
Rmin
Figure 18 shows the typical voltage gain curve of a
resonant converter, where the gain is inversely
proportional to the switching frequency in the ZVS
region. The output voltage can be regulated by
modulating the switching frequency. Figure 19 shows the
typical circuit configuration for RT pin, where the opto-
coupler transistor is connected to the RT pin to modulate
the switching frequency.
Assuming the saturation voltage of opto-coupler
transistor is 0.2V, the maximum switching frequency is
determined as:
5.2kΩ 4.68kΩ
f max = (
+
)×100(kHz)
(2)
Rmin
Rmax
To prevent excessive inrush current and overshoot of
output voltage during startup, increase the voltage gain
of the resonant converter progressively. Since the
voltage gain of the resonant converter is inversely
proportional to the switching frequency, the soft-start is
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
9
implemented by sweeping down the switching frequency
from an initial high frequency (fISS) until the output
voltage is established. The soft-start circuit is made by
connecting R-C series network on the RT pin, as shown
in Figure 19. FAN7621 also has an internal soft-start for
3ms to reduce the current overshoot during the initial
cycles, which adds 40kHz to the initial frequency of the
external soft-start circuit, as shown in Figure 20. The
initial frequency of the soft-start is given as:
VCC
LV
CC
HV
CC
RT
Rmax
Rmin
RSS
HO
5.2kΩ 5.2kΩ
CON
f ISS = (
+
)×100+ 40 (kHz)
(3)
CTR
LO
CSS
Rmin
RSS
It is typical to set the initial (soft-start) frequency of two ~
three times the resonant frequency (fO) of the resonant
network.
CS
The soft-start time is three to four times the RC time
constant. The RC time constant is as follows:
SG
PG
(4)
TSS = RSS ⋅CSS
fs
Figure 22. Control Pin Configuration for
Pulse Skipping
f ISS
40kHz
Remote On / Off: When an auxiliary power supply is
used for standby, the main power stage using FAN7621
can be shut down by pulling down the control pin
voltage, as shown in Figure 23. R1 and C1 are used to
ensure soft-start when switching resumes.
Control loop
take over
Main
OP1
Output
time
R1
C1
Figure 20. Frequency Sweeping of Soft-Start
4. Control Pin
The FAN7621 has a control pin for protection, cycle
skipping, and remote on/off. Figure 21 shows the internal
block diagram for control pin.
Main Off
FAN7621
RT
LVCC
IOLP
Aux
Output
Rmin
6
-
CON
0.4 / 0.6V
+
Stop Switching
+
CON
OLP
S
R
Q
5V
-
+
-
-Q
LVCC
OP1
Auto-restart
protection
LVCC good
23V
OVP
Figure 23. Remote On / Off Circuit
Figure 21. Internal Block of Control Pin
5. Protection Circuits
Protection: When the control pin voltage exceeds 5V,
protection is triggered. Detailed applications are
described in the protection section.
The FAN7621 has several self-protective functions, such
as Overload Protection (OLP), Over-Current Protection
(OCP), Abnormal Over-Current Protection (AOCP),
Over-Voltage Protection (OVP), and Thermal Shutdown
(TSD). OLP, OCP, and OVP are auto-restart mode
protections; while AOCP and TSD are latch-mode
protections, as shown in Figure 24.
Pulse Skipping: FAN7621 stops switching when the
control pin voltage drops below 0.4V and resumes
switching when the control pin voltage rises above 0.6V.
To use pulse-skipping, the control pin should be
connected to the opto-coupler collector pin. The
frequency that causes pulse skipping is given as:
5.1
Auto-Restart Mode Protection: Once a fault
condition is detected, switching is terminated and the
MOSFETs remain off. When LVCC falls to the LVCC stop
voltage of 11.3V, the protection is reset. FAN7621
5.2k
4.16k
SKIP
=
+
x100
(kHz
)
(5)
Rmin
Rmax
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
10
resumes normal operation when LVCC reaches the start
voltage of 14.5V.
5.4
Current Sensing Using Resonant Capacitor
Voltage: For high-power applications, current sensing
using a resistor may not be available due to the severe
power dissipation in the resistor. In that case, indirect
current sensing using the resonant capacitor voltage can
be a good alternative because the amplitude of the
resonant capacitor voltage (Vcrp-p) is proportional to the
resonant current in the primary side (Ipp-p) as:
5.2
Latch-Mode Protection: Once this protection is
triggered, switching is terminated and the gate output
signals remain off. The latch is reset only when LVCC is
discharged below 5V.
LV CC
12
p− p
Ip
p− p
(6)
+
VCr
=
LVCC good
Internal
Bias
VREF
2π fsCr
-
11/ 14V
To minimize power dissipation, a capacitive voltage
divider is generally used for capacitor voltage sensing,
as shown in Figure 27.
Shutdown
OCP
Latch
protection
Auto-restart
protection
OLP
AOCP
Q
S
LVCC
S
R
Q
OVP
CDL
-Q
R
HVCC
-Q
LVCC good
CON
TSD
F/F
RT
F/F
20k
LVCC < 5V
HO
Ip
CON
CS
CTR
Figure 24. Protection Blocks
Current Sensing Using Resistor: FAN7621
senses drain current as a negative voltage, as shown in
Figure 25 and Figure 26. Half-wave sensing allows low
power dissipation in the sensing resistor, while full-wave
sensing has less switching noise in the sensing signal.
LO
PG
5.3
SG
CB
Csense
100
Vsense
Cr
Ip
LVCC
HV CC
RT
HO
CDL
CON
VCr
CTR
p-p
VCr
Ids
LO
VCS
CS
SG
PG
pk
sense
p− p
pk
V
V
CB
sense+ CB
Vsense
2
Vsense
=
=VCON
C
Cr
VCS
Rsense
Ids
pk
Vsense
VCON
pk
Vsense
Figure 25. Half-Wave Sensing
Ids
t
=R C
d d
Delay
Figure 27. Current Sensing Using Resonant
Capacitor Voltage
LVCC
VCS
5.5
Over-Current Protection (OCP): When the
HVCC
sensing pin voltage drops below -0.6V, OCP is triggered
and the MOSFETs remain off. This protection has a
shutdown time delay of 1.5µs to prevent premature
shutdown during startup.
RT
HO
CDL
CON
CTR
LO
VCS
5.6
Abnormal Over-Current Protection (AOCP): If
CS
the secondary rectifier diodes are shorted, large current
with extremely high di/dt can flow through the MOSFET
before OCP or OLP is triggered. AOCP is triggered
without shutdown delay when the sensing pin voltage
drops below -0.9V. This protection is latch mode and
reset when LVCC is pulled down below 5V.
SG
PG
Rsense
I ds
Figure 26. Full-Wave Sensing
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
11
5.7
Overload Protection (OLP): Overload is
6.
PCB Layout Guideline
defined as the load current exceeding its normal level
due to an unexpected abnormal event. In this situation,
the protection circuit should trigger to protect the power
supply. However, even when the power supply is in the
normal condition, the overload situation can occur during
the load transition. To avoid premature triggering of
protection, the overload protection circuit should be
designed to trigger only after a specified time to
determine whether it is a transient situation or a true
overload situation. Figure 27 shows a typical overload
protection circuit. By sensing the resonant capacitor
voltage on the control pin, the overload protection can be
implemented. Using RC time constant, shutdown delay
can be also introduced. The voltage obtained on the
control pin is given as:
Duty imbalance problems may occur due to the radiated
noise from main transformer, the inequality of the
secondary-side
leakage
inductances
of
main
transformer, and so on. Among them, it is one of the
dominant reasons that the control components in the
vicinity of RT pin are enclosed by the primary current flow
pattern on PCB layout. The direction of the magnetic
field on the components caused by the primary current
flow is changed when the high-and-low side MOSFET
turns on by turns. The magnetic fields with opposite
direction from each other induce a current through, into,
or out of the RT pin, which makes the turn-on duration of
each MOSFET different. It is strongly recommended to
separate the control components in the vicinity of RT pin
from the primary current flow pattern on PCB layout.
Figure 28 shows an example for the duty-balanced case.
The yellow and blue lines show the primary current flows
when the lower-side and higher-side MOSFETs turns on,
respectively. The primary current does not enclose any
component of controller.
CB
p− p
(7)
VCON
=
VCr
2(CB + Csense
)
p-p
where VCr is the amplitude of the resonant capacitor
voltage.
5.8
Over-Voltage Protection (OVP): When the
It is helpful to reduce the duty imbalance to make the
loop configured between CON pin and opto-coupler as
small as possible, as shown in the red line in Figure 28.
LVCC reaches 23V, OVP is triggered. This protection is
used when auxiliary winding of the transformer to supply
VCC to the controller is utilized.
5.9 Thermal Shutdown (TSD): If the temperature
of the junction exceeds approximately 130°C, the
thermal shutdown triggers.
Figure 28. Example for Duty Balancing
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
12
Typical Application Circuit (Half-Bridge LLC Resonant Converter)
Output Voltage
(Rated Current)
Application
Device
Input Voltage Range
Rated Output Power
390VDC
(340~400VDC
LCD TV
FAN7621
200W
24V-8.3A
)
Features
High efficiency ( >94% at 400VDC input)
Reduced EMI noise through zero-voltage-switching (ZVS)
Enhanced system reliability with various protection functions
Figure 29. Typical Application Circuit
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
13
Typical Application Circuit (Continued)
Usually, LLC resonant converters require large leakage inductance value. To obtain a large leakage inductance,
sectional winding method is used.
Core: EC35 (Ae=106 mm2)
Bobbin: EC35 (Horizontal)
Transformer Model Number: SNX-2468-1
EC35
Np
2
6
13
12
Ns2
Ns1
10
9
Figure 30. Transformer Construction
Pins (S → F)
Wire
Turns
Note
Np
6 → 2
12 → 9
10 → 13
0.08φ×88 (Litz Wire)
0.08φ×234 (Litz Wire)
0.08φ×234 (Litz Wire)
36
4
Ns1
Ns2
Bifilar Winding
Bifilar Winding
4
Pins
2－6
2－6
Specifications
Remark
100kHz, 1V
Primary-Side Inductance (Lp)
550μH ± 10%
110μH ± 10%
Primary-Side Effective Leakage (Lr)
Short one of the secondary windings
For more detailed information regarding the transformer, visit http://www.santronics-usa.com/documents.html or
contact sales@santronics-usa.com or +1-408-734-1878 (Sunnyvale, California USA).
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
14
Physical Dimensions
A
19.68
18.66
9
8
16
6.60
6.09
1
(0.40)
TOP VIEW
0.38 MIN
5.33 MAX
8.13
7.62
3.42
3.17
3.81
2.92
15
0
0.35
0.20
2.54
0.58
0.35
A
1.78
1.14
8.69
17.78
SIDE VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-1994
E) DRAWING FILE NAME: N16EREV1
Figure 31. 16-Lead Dual Inline Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
15
Physical Dimensions
Figure 32. 16-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
16
© 2009 Fairchild Semiconductor Corporation
FAN7621 • Rev. 1.0.3
www.fairchildsemi.com
17
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