FAN7311GX [FAIRCHILD]
LCD Backlight Inverter Drive IC; LCD背光逆变器驱动IC
| 型号： | FAN7311GX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | LCD Backlight Inverter Drive IC |
| 文件： | 总13页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2005
FAN7311
LCD Backlight Inverter Drive IC
Features
Description
The FAN7311 provides all the control functions for a
series parallel resonant converter as well as a pulse width mod-
ulation (PWM) controller to develop a supply voltage. Typical
operating frequency range is between 30kHz and 250kHz,
depending on the CCFL and the transformer's characteristics.
The FAN7311 uses a new patent-pending phase-shift control.
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High-Efficiency Single-Stage Power Conversion
Wide Input Voltage Range : 5V to 25.5V
Back Light Lamp Ballast and Soft Dimming
Reduces Number of Required External Components
Precision Voltage Reference Trimmed to 2%
ZVS Full-Bridge Topology
20-SSOP
Soft Start
PWM Control at Fixed Frequency
Analog and Burst Dimming Function
Programmable Striking Frequency
Open Lamp Protection
1
Open Lamp Regulation
20-Pin SSOP
©2005 Fairchild Semiconductor Corporation
FAN7311 Rev. 1.0.0
1
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Internal Block Diagram
RT
CT
OUTA
OSCILLATOR
Output
Driver
max. 2V
OUTB
PGND
OUTC
min. 0.5V
Output
Control
Logic
-
+
+
6uA
S_S
RT1
Output
Driver
OUTD
MRT1
OLP
Striking
Logic
S_S
1.4uA
EA_OUT
ADIM
UVLO
OLP
OLR
+
-
SET
CLR
VOLP+α
VOLP
Q
S
R
+
-
Error Amp.
Q
UVLO
2.5V 1.5V
EA_IN
2.5V
+
-
Solr
Solr 105uA
Sburst 85uA
2V
2.5VREF
Voltage
Reference
&
Internal
Bias
REF
ENA
VIN
Va+α
max. 2V
min. 0.5V
+
-
BCT
BDIM
AGND
-
Sburst
1.4V
+
VIN
+
-
UVLO
UVLO 5V
2
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FAN7311 Rev. 1.0.0
Pin Assignments
RT1
OUTB
PGND
VIN
CT
BCT
OUTA
OUTC OUTD
RT
16
19
13
20
18
17
15
14
12
11
FAN7311
1
2
6
7
8
9
3
4
5
10
REF
EA_IN
ENA
GND
S_S
OLP
OLR
EA_OUT
ADIM
BDIM
Pin Definitions
No
1
Name
OLP
Function/Description
Open Lamp Protection
Open Lamp Regulation
Enable Input
No
Name
BCT
Function/Description
11
12
13
14
15
16
17
18
19
20
Burst Dimming Timing Capacitor
Timing Resistor
2
OLR
RT
3
ENA
CT
Timing Capacitor
4
S_S
Soft Start
OUTD
OUTC
PGND
VIN
NMOSFET Drive Output D
PMOSFET Drive Output C
Power Ground
5
GND
Analog Ground
6
REF
2.5V Reference Voltage
Analog Dimming Input
Burst Dimming Input
Error Amplifier Input
Error Amplifier Output
7
ADIM
BDIM
EA_IN
EA_OUT
Supply Voltage
8
OUTA
OUTB
RT1
PMOSFET Drive Output A
NMOSFET Drive Output B
Striking Frequency Resistor
9
10
3
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FAN7311 Rev. 1.0.0
Absolute Maximum Ratings
For typical values Ta=25°C, Vcc=12V and for min/max values Ta is the operating ambient temperature range with
-25°C ≤ Ta ≤ 85°C and 5V ≤ Vcc ≤ 25.5V, unless otherwise specified.
Characteristics
Symbol
Value
5 ~ 25.5
-25 ~ 85
-65 ~ 150
112
Unit
V
Supply Voltage
V
CC
Operating Temperature Range
Storage Temperature Range
Thermal Resistance Junction-Air (Note1,2)
Power Dissipation
Topr
Tstg
°C
°C
R
°C/W
W
θJA
Pd
1.1
Note:
1. Thermal resistance test board
Size: 76.2mm * 114.3mm * 1.6mm(1S0P)
JEDEC standard: JESD51-3, JESD51-7
2. Assume no ambient airflow
4
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FAN7311 Rev. 1.0.0
Electrical Characteristics
For typical values Ta=25°C, Vcc=12V and for min/max values Ta is the operating ambient temperature range with
-25°C ≤ Ta ≤ 85°C and 5V ≤ Vcc ≤ 25.5V, unless otherwise specified.
Characteristics
Symbol
Test Condition
Min.
Typ.
Max. Unit
REFERENCE SECTION ( Recommend X7R Capacitor )
Line Regulation
∆Vref
5 ≤ V ≤ 25.5V
-
2
25
mV
V
CC
2.5V Regulation Voltage
V25
-
2.45
2.5
2.55
OSCILLATOR SECTION(MAIN)
Ta = 25°C, Ct = 270pF
108
115
122
Rt = 18k
Oscillation Frequency
fosc
kHz
Ct = 270pF, Rt = 18k
106
115
2.0
0.5
124
CT High Voltage
CT Low Voltage
Vcth
Vctl
-
-
-
-
-
-
V
V
OSCILLATOR SECTION(BURST)
Oscillation Frequency
foscb
Vbcth
Vbctl
Ctb = 10nF, Rt=18k
195
225
2
255
Hz
V
BCT High Voltage
-
-
-
-
-
-
BCT Low Voltage
0.5
V
ERROR AMP SECTION
Open Loop Gain
-
-
80
1.5
2.27
-
-
-
dB
MHz
V
Unit Gain Bandwidth
-
EA_IN = 0V
EA_OUT = 1.5V
EA_OUT = 1.5V
-
-
2.0
-
Feedback Output High Voltage
Output Sink Current
Veh
lsin
2.54
-1
mA
mA
uA
uA
V
Output Source Current
lsur
1
-
-
EA_IN Driving Current On OLR
EA_IN Driving Current On Burst Dimming
Feedback High Voltage On Burst Dimming
Iolr
75
105
85
135
109
Va+0.7
Iburst
Vfbh
-
61
R(EA_IN) = 60kΩ
Va+0.1
Va+0.4
SOFT START SECTION
Soft Start Current
I
S_S=2V
-
4
-
6
5
8
-
uA
V
SS
Soft Start Clamping Voltage
Vssh
PROTECTION SECTION
Open Lamp Protection Voltage 0
Open Lamp Protection Voltage 1
Open Lamp Regulation Voltage
Open Lamp Protection Charging Current
Volp0
Volp1
Volr
Start at open lamp
2.2
1.3
2.5
1.5
2
2.8
1.7
V
V
Normal -> open lamp
-
-
1.75
0.7
2.25
2.1
V
Iolp
1.4
uA
UNDER VOLTAGE LOCK OUT SECTION
Start Threshold Voltage
Start Up Current
Vth
-
-
-
-
-
-
5
V
Ist
Iop
Isb
V
V
V
= Vth-0.2
= 12V
130
1.5
200
180
4
uA
mA
uA
CC
CC
CC
Operating Supply Current
Stand-by Current
= 12V
370
ON/OFF SECTION
On State Input Voltage
Off Stage Input Voltage
Von
Voff
-
-
2
-
-
-
5
V
V
0.7
5
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FAN7311 Rev. 1.0.0
Electrical Characteristics (Continued)
For typical values Ta=25°C, Vcc=12V and for min/max values Ta is the operating ambient temperature range with
-25°C ≤ Ta ≤ 85°C and 5V ≤ Vcc ≤ 25.5V, unless otherwise specified.
Characteristics
Symbol
Test Condition
Min.
Typ.
Max. Unit
OUTPUT SECTION
PMOS Gate High Voltage
PMOS Gate Low Voltage
NMOS Gate Drive Volgate
NMOS Gate Drive Volgate
PMOS Gate Voltage With UVLO Activated
NMOS Gate Voltage With UVLO Activated
Rising Time
Vpdhv
Vphlv
Vndhv
Vndhv
Vpuv
Vnuv
Tr
V
V
V
V
V
V
V
V
= 12V
-
Vcc
-
V
V
CC
CC
CC
CC
CC
CC
CC
CC
= 12V
Vcc-10.5
Vcc-8.5 Vcc-6.5
= 12V
6.5
8.5
0
10.5
-
V
= 12V
-
V
= Vth-0.2
= Vth-0.2
= 12V, Cload=2nF
= 12V, Cload=2nF
Vcc-0.3
-
-
V
-
-
-
-
0.3
500
500
V
200
200
ns
ns
Falling Time
Tf
MAX./MIN OVERLAP
Min. Overlap between diagonal switches
fosc=100KHz
fosc=100KHz
-
-
0
-
-
%
%
Max. Overlap betwwen diagonal switches
100
DELAY TIME
PDR_A/NDR_B
PDR_C/NDR_D
Rt=18k
Rt=18k
-
-
450
450
-
-
ns
ns
6
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FAN7311 Rev. 1.0.0
Function Description
UVLO: The under voltage lockout circuit guarantees stable
operation of the IC’s control circuit by stopping and starting it as
a function of the Vin value. The UVLO circuit turns on the con-
trol circuit when Vin exceeds 5V. When Vin is lower than 5V, the
IC’s standby current is less than 200uA.
ENA: Applying voltage higher than 2V to the ENA pin enables
the operation of the IC. Applying voltage lower than 0.7V to the
ENA pin will disable the operation of the inverter.
Soft start: The soft start function requires that the S_S pin is
connected through a capacitor to GND. A soft start circuit
ensures a gradual increase in the input and output power. The
capacitor connected to the S_S pin determines the rate at which
the duty ratio rises. It is charged by a 6uA current source.
Burst oscillator & burst dimming: The timing capacitors
(BCTs) are charged by the reference current source, which is
formed by the timing resistor (RT). The timing resistor’s voltage
is regulated at 1.25V. The sawtooth waveform charges up to 2V.
Once this voltage is reached, the capacitors begin discharging
down to 0.5V. Next the timing capacitors start charging again
and a new switching cycle begins. The burst dimming frequency
can be programmed by adjusting the Rt and BCT values. The
burst dimming frequency can be calculated as shown below.
3.75
f
= ----------------------------------
burst
64 R BC
T
T
To avoid visible flicker, the burst dimming frequency should be
greater than 120Hz.
Main oscillator: The timing capacitors (CTs) are charged by the
reference current source, which is formed by the timing resistor
(RT). The timing resistor’s voltage is regulated at 1.25V. The
sawtooth waveform charges up to 2V. Once this voltage is
reached, the capacitors begin discharging down to 0.5V. Next,
the timing capacitors start charging again and a new switching
cycle begins. The main frequency can be programmed by
adjusting the Rt and CT values. The main frequency can be cal-
culated as shown below.
What does the following sentence mean? Please rewrite.To
compare the input of BDIM pin with the 0.5~2V triangular wave
of burst oscillator makes the PWM pulse for burst dimming. The
PWM pulse controls EA_OUT’s voltage by summing 85uA into
the EA_IN pin.
19
f
= ------------------------------
op
32 R
C
T
T
7
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FAN7311 Rev. 1.0.0
VIN
8.5V
8.5V
VIN
8.5V
8.5V
Open lamp regulation & open lamp protection: It is neces-
sary to suspend power stage operation if an open lamp occurs,
because the power stage has high gain. When a voltage higher
than 2V is applied to the OLR pin, the part enters regulation
mode and controls the EA_OUT voltage. This limits the lamp
voltage by summing 105uA into the feedback node. At the same
time, the OLP capacitor, connected to the OLP pin, is charged
by the 1.4uA internal current source. Once it reaches 2.5V, the
IC enters shut down where all the output is high.
Output Drives: The four output drives are designed so that
switches A and B, C and D never turn on simultaneously. The
OUTA-OUTB pair is intended to drive one half-bridge in the
external power stage. The OUTC-OUTD pair will drive the other
half-bridge.
8
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FAN7311 Rev. 1.0.0
Timing Diagram
The FAN7311 uses the improved phase-shift control full-bridge to drive CCFL. As a result, the temperature difference between the left
and the right leg is almost zero. The detail timing is shown below.
EA_OUT
CT
SYNC
T
T1
POUT A
NOUT B
POUT C
NOUT D
9
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FAN7311 Rev. 1.0.0
Typical Application Circuits
VCC
C25
100u
C27
1u
IC1 FAN7311
RT
C22
1u
R6 120k
C8
R25
10k
R26
10k
OLP
RT1
OUTB
OUTA
VIN
0
0.1u
0
0
0
OUTB
OUTA
OLR
R24
10k
ENA
ENA
C28
10n
M1
C7
0
0
0
S_S
0
0
TX1
FDS8958A
C1 1u
C2
C6 1u
10u
GND
REF
PGND
OUTC
OUTD
CT
0
M2
FDS8958A
REF
REF
OUTC
1u
R2
OUTD
ADIM
BDIM
EA_IN
EA_OUT
R4
56k
22k
C5 220p
CCFL
0
0
DIM(0~3.3V)
C10
15p
R5 27k
C4 4.7n
C21
10n
R3
20k
RT
0
0
OLP1
C3
0
0
BCT
0
0
OLR
FB
4.7n
R8
RT
R15
2k
D4
BAV99
D6
BAV99
R16
1.5k
C14
20n
FB
100k
R9
8.2k
0
0
0
0
0
OLR
R14
100k
C16
2.2n
OLP1
0
0
OLP
R1
330k
R22
10k
Q1
KST2222
D11
D1N4148
C9
1u
C19
2.2n
D1
D1N4148
0
0
10
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FAN7311 Rev. 1.0.0
Mechanical Dimensions
Package
Dimensions in millimeters
20-SSOP
11
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FAN7311 Rev. 1.0.0
Ordering Information
Product number
FAN7311G
Package
Operating Temperature
20-SSOP
-25°C ~ 85°C
FAN7311GX
12
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FAN7311 Rev. 1.0.0
13
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FAN7311 Rev. 1.0.0
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